drivers/net/wireless/realtek/rtlwifi/rtl8723be/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2014  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "reg.h"
  34 #include "def.h"
  35 #include "phy.h"
  36 #include "../rtl8723com/phy_common.h"
  37 #include "dm.h"
  38 #include "../rtl8723com/dm_common.h"
  39 #include "fw.h"
  40 #include "../rtl8723com/fw_common.h"
  41 #include "led.h"
  42 #include "hw.h"
  43 #include "../pwrseqcmd.h"
  44 #include "pwrseq.h"
  45 #include "../btcoexist/rtl_btc.h"
  46
  47 #define LLT_CONFIG      5
  48
  49 static void _rtl8723be_return_beacon_queue_skb(struct ieee80211_hw *hw)
  50 {
  51         struct rtl_priv *rtlpriv = rtl_priv(hw);
  52         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  53         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  54         unsigned long flags;
  55
  56         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  57         while (skb_queue_len(&ring->queue)) {
  58                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  59                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  60
  61                 pci_unmap_single(rtlpci->pdev,
  62                                  rtlpriv->cfg->ops->get_desc(
  63                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
  64                                  skb->len, PCI_DMA_TODEVICE);
  65                 kfree_skb(skb);
  66                 ring->idx = (ring->idx + 1) % ring->entries;
  67         }
  68         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
  69 }
  70
  71 static void _rtl8723be_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  72                                         u8 set_bits, u8 clear_bits)
  73 {
  74         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  75         struct rtl_priv *rtlpriv = rtl_priv(hw);
  76
  77         rtlpci->reg_bcn_ctrl_val |= set_bits;
  78         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  79
  80         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
  81 }
  82
  83 static void _rtl8723be_stop_tx_beacon(struct ieee80211_hw *hw)
  84 {
  85         struct rtl_priv *rtlpriv = rtl_priv(hw);
  86         u8 tmp1byte;
  87
  88         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  89         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  90         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  91         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  92         tmp1byte &= ~(BIT(0));
  93         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  94 }
  95
  96 static void _rtl8723be_resume_tx_beacon(struct ieee80211_hw *hw)
  97 {
  98         struct rtl_priv *rtlpriv = rtl_priv(hw);
  99         u8 tmp1byte;
 100
 101         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 102         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
 103         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
 104         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
 105         tmp1byte |= BIT(1);
 106         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
 107 }
 108
 109 static void _rtl8723be_enable_bcn_sub_func(struct ieee80211_hw *hw)
 110 {
 111         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(1));
 112 }
 113
 114 static void _rtl8723be_disable_bcn_sub_func(struct ieee80211_hw *hw)
 115 {
 116         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(1), 0);
 117 }
 118
 119 static void _rtl8723be_set_fw_clock_on(struct ieee80211_hw *hw, u8 rpwm_val,
 120                                        bool b_need_turn_off_ckk)
 121 {
 122         struct rtl_priv *rtlpriv = rtl_priv(hw);
 123         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 124         bool b_support_remote_wake_up;
 125         u32 count = 0, isr_regaddr, content;
 126         bool b_schedule_timer = b_need_turn_off_ckk;
 127         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 128                                       (u8 *)(&b_support_remote_wake_up));
 129
 130         if (!rtlhal->fw_ready)
 131                 return;
 132         if (!rtlpriv->psc.fw_current_inpsmode)
 133                 return;
 134
 135         while (1) {
 136                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 137                 if (rtlhal->fw_clk_change_in_progress) {
 138                         while (rtlhal->fw_clk_change_in_progress) {
 139                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 140                                 count++;
 141                                 udelay(100);
 142                                 if (count > 1000)
 143                                         return;
 144                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 145                         }
 146                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 147                 } else {
 148                         rtlhal->fw_clk_change_in_progress = false;
 149                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 150                         break;
 151                 }
 152         }
 153
 154         if (IS_IN_LOW_POWER_STATE(rtlhal->fw_ps_state)) {
 155                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM,
 156                                               (u8 *)(&rpwm_val));
 157                 if (FW_PS_IS_ACK(rpwm_val)) {
 158                         isr_regaddr = REG_HISR;
 159                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 160                         while (!(content & IMR_CPWM) && (count < 500)) {
 161                                 udelay(50);
 162                                 count++;
 163                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 164                         }
 165
 166                         if (content & IMR_CPWM) {
 167                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 168                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON;
 169                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 170                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 171                                          rtlhal->fw_ps_state);
 172                         }
 173                 }
 174
 175                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 176                 rtlhal->fw_clk_change_in_progress = false;
 177                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 178                 if (b_schedule_timer)
 179                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 180                                   jiffies + MSECS(10));
 181         } else  {
 182                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 183                 rtlhal->fw_clk_change_in_progress = false;
 184                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 185         }
 186 }
 187
 188 static void _rtl8723be_set_fw_clock_off(struct ieee80211_hw *hw, u8 rpwm_val)
 189 {
 190         struct rtl_priv *rtlpriv = rtl_priv(hw);
 191         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 192         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 193         struct rtl8192_tx_ring *ring;
 194         enum rf_pwrstate rtstate;
 195         bool b_schedule_timer = false;
 196         u8 queue;
 197
 198         if (!rtlhal->fw_ready)
 199                 return;
 200         if (!rtlpriv->psc.fw_current_inpsmode)
 201                 return;
 202         if (!rtlhal->allow_sw_to_change_hwclc)
 203                 return;
 204         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 205         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 206                 return;
 207
 208         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 209                 ring = &rtlpci->tx_ring[queue];
 210                 if (skb_queue_len(&ring->queue)) {
 211                         b_schedule_timer = true;
 212                         break;
 213                 }
 214         }
 215
 216         if (b_schedule_timer) {
 217                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 218                           jiffies + MSECS(10));
 219                 return;
 220         }
 221
 222         if (FW_PS_STATE(rtlhal->fw_ps_state) != FW_PS_STATE_RF_OFF_LOW_PWR) {
 223                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 224                 if (!rtlhal->fw_clk_change_in_progress) {
 225                         rtlhal->fw_clk_change_in_progress = true;
 226                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 227                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 228                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 229                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 230                                                       (u8 *)(&rpwm_val));
 231                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 232                         rtlhal->fw_clk_change_in_progress = false;
 233                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 234                 } else {
 235                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 236                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 237                                   jiffies + MSECS(10));
 238                 }
 239         }
 240
 241 }
 242
 243 static void _rtl8723be_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 244 {
 245         u8 rpwm_val = 0;
 246         rpwm_val |= (FW_PS_STATE_RF_OFF | FW_PS_ACK);
 247         _rtl8723be_set_fw_clock_on(hw, rpwm_val, true);
 248 }
 249
 250 static void _rtl8723be_fwlps_leave(struct ieee80211_hw *hw)
 251 {
 252         struct rtl_priv *rtlpriv = rtl_priv(hw);
 253         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 254         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 255         bool fw_current_inps = false;
 256         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 257
 258         if (ppsc->low_power_enable) {
 259                 rpwm_val = (FW_PS_STATE_ALL_ON | FW_PS_ACK);/* RF on */
 260                 _rtl8723be_set_fw_clock_on(hw, rpwm_val, false);
 261                 rtlhal->allow_sw_to_change_hwclc = false;
 262                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 263                                               (u8 *)(&fw_pwrmode));
 264                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 265                                               (u8 *)(&fw_current_inps));
 266         } else {
 267                 rpwm_val = FW_PS_STATE_ALL_ON;  /* RF on */
 268                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 269                                               (u8 *)(&rpwm_val));
 270                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 271                                               (u8 *)(&fw_pwrmode));
 272                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 273                                               (u8 *)(&fw_current_inps));
 274         }
 275
 276 }
 277
 278 static void _rtl8723be_fwlps_enter(struct ieee80211_hw *hw)
 279 {
 280         struct rtl_priv *rtlpriv = rtl_priv(hw);
 281         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 282         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 283         bool fw_current_inps = true;
 284         u8 rpwm_val;
 285
 286         if (ppsc->low_power_enable) {
 287                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR;  /* RF off */
 288                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 289                                               (u8 *)(&fw_current_inps));
 290                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 291                                               (u8 *)(&ppsc->fwctrl_psmode));
 292                 rtlhal->allow_sw_to_change_hwclc = true;
 293                 _rtl8723be_set_fw_clock_off(hw, rpwm_val);
 294         } else {
 295                 rpwm_val = FW_PS_STATE_RF_OFF;  /* RF off */
 296                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 297                                               (u8 *)(&fw_current_inps));
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 299                                               (u8 *)(&ppsc->fwctrl_psmode));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 301                                               (u8 *)(&rpwm_val));
 302         }
 303
 304 }
 305
 306 void rtl8723be_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 307 {
 308         struct rtl_priv *rtlpriv = rtl_priv(hw);
 309         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 310         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 311
 312         switch (variable) {
 313         case HW_VAR_RCR:
 314                 *((u32 *)(val)) = rtlpci->receive_config;
 315                 break;
 316         case HW_VAR_RF_STATE:
 317                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 318                 break;
 319         case HW_VAR_FWLPS_RF_ON:{
 320                 enum rf_pwrstate rfState;
 321                 u32 val_rcr;
 322
 323                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
 324                                               (u8 *)(&rfState));
 325                 if (rfState == ERFOFF) {
 326                         *((bool *)(val)) = true;
 327                 } else {
 328                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 329                         val_rcr &= 0x00070000;
 330                         if (val_rcr)
 331                                 *((bool *)(val)) = false;
 332                         else
 333                                 *((bool *)(val)) = true;
 334                 }
 335                 }
 336                 break;
 337         case HW_VAR_FW_PSMODE_STATUS:
 338                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 339                 break;
 340         case HW_VAR_CORRECT_TSF:{
 341                 u64 tsf;
 342                 u32 *ptsf_low = (u32 *)&tsf;
 343                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 344
 345                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 346                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 347
 348                 *((u64 *)(val)) = tsf;
 349                 }
 350                 break;
 351         case HAL_DEF_WOWLAN:
 352                 break;
 353         default:
 354                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 355                          "switch case %#x not processed\n", variable);
 356                 break;
 357         }
 358 }
 359
 360 static void _rtl8723be_download_rsvd_page(struct ieee80211_hw *hw)
 361 {
 362         struct rtl_priv *rtlpriv = rtl_priv(hw);
 363         u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 364         u8 count = 0, dlbcn_count = 0;
 365         bool b_recover = false;
 366
 367         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 368         rtl_write_byte(rtlpriv, REG_CR + 1,
 369                        (tmp_regcr | BIT(0)));
 370
 371         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 372         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
 373
 374         tmp_reg422 = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
 375         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422 & (~BIT(6)));
 376         if (tmp_reg422 & BIT(6))
 377                 b_recover = true;
 378
 379         do {
 380                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 381                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2,
 382                                (bcnvalid_reg | BIT(0)));
 383                 _rtl8723be_return_beacon_queue_skb(hw);
 384
 385                 rtl8723be_set_fw_rsvdpagepkt(hw, 0);
 386                 bcnvalid_reg = rtl_read_byte(rtlpriv, REG_TDECTRL + 2);
 387                 count = 0;
 388                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 389                         count++;
 390                         udelay(10);
 391                         bcnvalid_reg = rtl_read_byte(rtlpriv,
 392                                                      REG_TDECTRL + 2);
 393                 }
 394                 dlbcn_count++;
 395         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 396
 397         if (bcnvalid_reg & BIT(0))
 398                 rtl_write_byte(rtlpriv, REG_TDECTRL + 2, BIT(0));
 399
 400         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 401         _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
 402
 403         if (b_recover)
 404                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp_reg422);
 405
 406         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 407         rtl_write_byte(rtlpriv, REG_CR + 1, (tmp_regcr & ~(BIT(0))));
 408 }
 409
 410 void rtl8723be_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 411 {
 412         struct rtl_priv *rtlpriv = rtl_priv(hw);
 413         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 414         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 415         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 416         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 417         u8 idx;
 418
 419         switch (variable) {
 420         case HW_VAR_ETHER_ADDR:
 421                 for (idx = 0; idx < ETH_ALEN; idx++)
 422                         rtl_write_byte(rtlpriv, (REG_MACID + idx), val[idx]);
 423                 break;
 424         case HW_VAR_BASIC_RATE:{
 425                 u16 b_rate_cfg = ((u16 *)val)[0];
 426                 u8 rate_index = 0;
 427                 b_rate_cfg = b_rate_cfg & 0x15f;
 428                 b_rate_cfg |= 0x01;
 429                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 430                 rtl_write_byte(rtlpriv, REG_RRSR + 1, (b_rate_cfg >> 8) & 0xff);
 431                 while (b_rate_cfg > 0x1) {
 432                         b_rate_cfg = (b_rate_cfg >> 1);
 433                         rate_index++;
 434                 }
 435                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, rate_index);
 436                 }
 437                 break;
 438         case HW_VAR_BSSID:
 439                 for (idx = 0; idx < ETH_ALEN; idx++)
 440                         rtl_write_byte(rtlpriv, (REG_BSSID + idx), val[idx]);
 441
 442                 break;
 443         case HW_VAR_SIFS:
 444                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 445                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 446
 447                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 448                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 449
 450                 if (!mac->ht_enable)
 451                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM, 0x0e0e);
 452                 else
 453                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 454                                        *((u16 *)val));
 455                 break;
 456         case HW_VAR_SLOT_TIME:{
 457                 u8 e_aci;
 458
 459                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 460                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 461
 462                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 463
 464                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 465                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 466                                                       (u8 *)(&e_aci));
 467                 }
 468                 }
 469                 break;
 470         case HW_VAR_ACK_PREAMBLE:{
 471                 u8 reg_tmp;
 472                 u8 short_preamble = (bool)(*(u8 *)val);
 473                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL + 2);
 474                 if (short_preamble) {
 475                         reg_tmp |= 0x02;
 476                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 477                 } else {
 478                         reg_tmp &= 0xFD;
 479                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL + 2, reg_tmp);
 480                 }
 481                 }
 482                 break;
 483         case HW_VAR_WPA_CONFIG:
 484                 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
 485                 break;
 486         case HW_VAR_AMPDU_MIN_SPACE:{
 487                 u8 min_spacing_to_set;
 488                 u8 sec_min_space;
 489
 490                 min_spacing_to_set = *((u8 *)val);
 491                 if (min_spacing_to_set <= 7) {
 492                         sec_min_space = 0;
 493
 494                         if (min_spacing_to_set < sec_min_space)
 495                                 min_spacing_to_set = sec_min_space;
 496
 497                         mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
 498                                               min_spacing_to_set);
 499
 500                         *val = min_spacing_to_set;
 501
 502                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 503                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 504                                   mac->min_space_cfg);
 505
 506                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 507                                        mac->min_space_cfg);
 508                 }
 509                 }
 510                 break;
 511         case HW_VAR_SHORTGI_DENSITY:{
 512                 u8 density_to_set;
 513
 514                 density_to_set = *((u8 *)val);
 515                 mac->min_space_cfg |= (density_to_set << 3);
 516
 517                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 518                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 519                           mac->min_space_cfg);
 520
 521                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 522                                mac->min_space_cfg);
 523                 }
 524                 break;
 525         case HW_VAR_AMPDU_FACTOR:{
 526                 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
 527                 u8 factor_toset;
 528                 u8 *p_regtoset = NULL;
 529                 u8 index = 0;
 530
 531                 p_regtoset = regtoset_normal;
 532
 533                 factor_toset = *((u8 *)val);
 534                 if (factor_toset <= 3) {
 535                         factor_toset = (1 << (factor_toset + 2));
 536                         if (factor_toset > 0xf)
 537                                 factor_toset = 0xf;
 538
 539                         for (index = 0; index < 4; index++) {
 540                                 if ((p_regtoset[index] & 0xf0) >
 541                                     (factor_toset << 4))
 542                                         p_regtoset[index] =
 543                                                 (p_regtoset[index] & 0x0f) |
 544                                                 (factor_toset << 4);
 545
 546                                 if ((p_regtoset[index] & 0x0f) > factor_toset)
 547                                         p_regtoset[index] =
 548                                                 (p_regtoset[index] & 0xf0) |
 549                                                 (factor_toset);
 550
 551                                 rtl_write_byte(rtlpriv,
 552                                                (REG_AGGLEN_LMT + index),
 553                                                p_regtoset[index]);
 554
 555                         }
 556
 557                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 558                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 559                                   factor_toset);
 560                 }
 561                 }
 562                 break;
 563         case HW_VAR_AC_PARAM:{
 564                 u8 e_aci = *((u8 *)val);
 565                 rtl8723_dm_init_edca_turbo(hw);
 566
 567                 if (rtlpci->acm_method != EACMWAY2_SW)
 568                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
 569                                                       (u8 *)(&e_aci));
 570                 }
 571                 break;
 572         case HW_VAR_ACM_CTRL:{
 573                 u8 e_aci = *((u8 *)val);
 574                 union aci_aifsn *p_aci_aifsn =
 575                                 (union aci_aifsn *)(&(mac->ac[0].aifs));
 576                 u8 acm = p_aci_aifsn->f.acm;
 577                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 578
 579                 acm_ctrl =
 580                     acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 581
 582                 if (acm) {
 583                         switch (e_aci) {
 584                         case AC0_BE:
 585                                 acm_ctrl |= ACMHW_BEQEN;
 586                                 break;
 587                         case AC2_VI:
 588                                 acm_ctrl |= ACMHW_VIQEN;
 589                                 break;
 590                         case AC3_VO:
 591                                 acm_ctrl |= ACMHW_VOQEN;
 592                                 break;
 593                         default:
 594                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 595                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 596                                          acm);
 597                                 break;
 598                         }
 599                 } else {
 600                         switch (e_aci) {
 601                         case AC0_BE:
 602                                 acm_ctrl &= (~ACMHW_BEQEN);
 603                                 break;
 604                         case AC2_VI:
 605                                 acm_ctrl &= (~ACMHW_VIQEN);
 606                                 break;
 607                         case AC3_VO:
 608                                 acm_ctrl &= (~ACMHW_VOQEN);
 609                                 break;
 610                         default:
 611                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 612                                          "switch case %#x not processed\n",
 613                                          e_aci);
 614                                 break;
 615                         }
 616                 }
 617
 618                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 619                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 620                          acm_ctrl);
 621                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 622                 }
 623                 break;
 624         case HW_VAR_RCR:
 625                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 626                 rtlpci->receive_config = ((u32 *)(val))[0];
 627                 break;
 628         case HW_VAR_RETRY_LIMIT:{
 629                 u8 retry_limit = ((u8 *)(val))[0];
 630
 631                 rtl_write_word(rtlpriv, REG_RL,
 632                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 633                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 634                 }
 635                 break;
 636         case HW_VAR_DUAL_TSF_RST:
 637                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 638                 break;
 639         case HW_VAR_EFUSE_BYTES:
 640                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 641                 break;
 642         case HW_VAR_EFUSE_USAGE:
 643                 rtlefuse->efuse_usedpercentage = *((u8 *)val);
 644                 break;
 645         case HW_VAR_IO_CMD:
 646                 rtl8723be_phy_set_io_cmd(hw, (*(enum io_type *)val));
 647                 break;
 648         case HW_VAR_SET_RPWM:{
 649                 u8 rpwm_val;
 650
 651                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 652                 udelay(1);
 653
 654                 if (rpwm_val & BIT(7)) {
 655                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, (*(u8 *)val));
 656                 } else {
 657                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
 658                                        ((*(u8 *)val) | BIT(7)));
 659                 }
 660                 }
 661                 break;
 662         case HW_VAR_H2C_FW_PWRMODE:
 663                 rtl8723be_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
 664                 break;
 665         case HW_VAR_FW_PSMODE_STATUS:
 666                 ppsc->fw_current_inpsmode = *((bool *)val);
 667                 break;
 668         case HW_VAR_RESUME_CLK_ON:
 669                 _rtl8723be_set_fw_ps_rf_on(hw);
 670                 break;
 671         case HW_VAR_FW_LPS_ACTION:{
 672                 bool b_enter_fwlps = *((bool *)val);
 673
 674                 if (b_enter_fwlps)
 675                         _rtl8723be_fwlps_enter(hw);
 676                 else
 677                         _rtl8723be_fwlps_leave(hw);
 678                 }
 679                 break;
 680         case HW_VAR_H2C_FW_JOINBSSRPT:{
 681                 u8 mstatus = (*(u8 *)val);
 682
 683                 if (mstatus == RT_MEDIA_CONNECT) {
 684                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID, NULL);
 685                         _rtl8723be_download_rsvd_page(hw);
 686                 }
 687                 rtl8723be_set_fw_media_status_rpt_cmd(hw, mstatus);
 688                 }
 689                 break;
 690         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 691                 rtl8723be_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
 692                 break;
 693         case HW_VAR_AID:{
 694                 u16 u2btmp;
 695                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 696                 u2btmp &= 0xC000;
 697                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
 698                                (u2btmp | mac->assoc_id));
 699                 }
 700                 break;
 701         case HW_VAR_CORRECT_TSF:{
 702                 u8 btype_ibss = ((u8 *)(val))[0];
 703
 704                 if (btype_ibss)
 705                         _rtl8723be_stop_tx_beacon(hw);
 706
 707                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(3));
 708
 709                 rtl_write_dword(rtlpriv, REG_TSFTR,
 710                                 (u32) (mac->tsf & 0xffffffff));
 711                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 712                                 (u32) ((mac->tsf >> 32) & 0xffffffff));
 713
 714                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
 715
 716                 if (btype_ibss)
 717                         _rtl8723be_resume_tx_beacon(hw);
 718                 }
 719                 break;
 720         case HW_VAR_KEEP_ALIVE:{
 721                 u8 array[2];
 722                 array[0] = 0xff;
 723                 array[1] = *((u8 *)val);
 724                 rtl8723be_fill_h2c_cmd(hw, H2C_8723B_KEEP_ALIVE_CTRL, 2, array);
 725                 }
 726                 break;
 727         default:
 728                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 729                          "switch case %#x not processed\n", variable);
 730                 break;
 731         }
 732 }
 733
 734 static bool _rtl8723be_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 735 {
 736         struct rtl_priv *rtlpriv = rtl_priv(hw);
 737         bool status = true;
 738         long count = 0;
 739         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 740                     _LLT_OP(_LLT_WRITE_ACCESS);
 741
 742         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 743
 744         do {
 745                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 746                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 747                         break;
 748
 749                 if (count > POLLING_LLT_THRESHOLD) {
 750                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 751                                  "Failed to polling write LLT done at address %d!\n",
 752                                  address);
 753                         status = false;
 754                         break;
 755                 }
 756         } while (++count);
 757
 758         return status;
 759 }
 760
 761 static bool _rtl8723be_llt_table_init(struct ieee80211_hw *hw)
 762 {
 763         struct rtl_priv *rtlpriv = rtl_priv(hw);
 764         unsigned short i;
 765         u8 txpktbuf_bndy;
 766         u8 maxPage;
 767         bool status;
 768
 769         maxPage = 255;
 770         txpktbuf_bndy = 245;
 771
 772         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
 773                         (0x27FF0000 | txpktbuf_bndy));
 774         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 775
 776         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 777         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 778
 779         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 780         rtl_write_byte(rtlpriv, REG_PBP, 0x31);
 781         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 782
 783         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 784                 status = _rtl8723be_llt_write(hw, i, i + 1);
 785                 if (!status)
 786                         return status;
 787         }
 788
 789         status = _rtl8723be_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 790
 791         if (!status)
 792                 return status;
 793
 794         for (i = txpktbuf_bndy; i < maxPage; i++) {
 795                 status = _rtl8723be_llt_write(hw, i, (i + 1));
 796                 if (!status)
 797                         return status;
 798         }
 799
 800         status = _rtl8723be_llt_write(hw, maxPage, txpktbuf_bndy);
 801         if (!status)
 802                 return status;
 803
 804         rtl_write_dword(rtlpriv, REG_RQPN, 0x80e40808);
 805         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x00);
 806
 807         return true;
 808 }
 809
 810 static void _rtl8723be_gen_refresh_led_state(struct ieee80211_hw *hw)
 811 {
 812         struct rtl_priv *rtlpriv = rtl_priv(hw);
 813         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
 814         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 815         struct rtl_led *pled0 = &(pcipriv->ledctl.sw_led0);
 816
 817         if (rtlpriv->rtlhal.up_first_time)
 818                 return;
 819
 820         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 821                 rtl8723be_sw_led_on(hw, pled0);
 822         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 823                 rtl8723be_sw_led_on(hw, pled0);
 824         else
 825                 rtl8723be_sw_led_off(hw, pled0);
 826 }
 827
 828 static bool _rtl8723be_init_mac(struct ieee80211_hw *hw)
 829 {
 830         struct rtl_priv *rtlpriv = rtl_priv(hw);
 831         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 832         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 833         unsigned char bytetmp;
 834         unsigned short wordtmp;
 835
 836         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 837
 838         /*Auto Power Down to CHIP-off State*/
 839         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 840         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 841
 842         /* HW Power on sequence */
 843         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 844                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 845                                       RTL8723_NIC_ENABLE_FLOW)) {
 846                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 847                          "init MAC Fail as power on failure\n");
 848                 return false;
 849         }
 850
 851         bytetmp = rtl_read_byte(rtlpriv, REG_MULTI_FUNC_CTRL);
 852         rtl_write_byte(rtlpriv, REG_MULTI_FUNC_CTRL, bytetmp | BIT(3));
 853
 854         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 855         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 856
 857         bytetmp = rtl_read_byte(rtlpriv, REG_CR);
 858         bytetmp = 0xff;
 859         rtl_write_byte(rtlpriv, REG_CR, bytetmp);
 860         mdelay(2);
 861
 862         bytetmp = rtl_read_byte(rtlpriv, REG_HWSEQ_CTRL);
 863         bytetmp |= 0x7f;
 864         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, bytetmp);
 865         mdelay(2);
 866
 867         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CFG + 3);
 868         if (bytetmp & BIT(0)) {
 869                 bytetmp = rtl_read_byte(rtlpriv, 0x7c);
 870                 rtl_write_byte(rtlpriv, 0x7c, bytetmp | BIT(6));
 871         }
 872
 873         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 874         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp | BIT(3));
 875         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG + 1);
 876         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG + 1, bytetmp & (~BIT(4)));
 877
 878         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 879
 880         if (!rtlhal->mac_func_enable) {
 881                 if (_rtl8723be_llt_table_init(hw) == false)
 882                         return false;
 883         }
 884
 885         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 886         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 887
 888         /* Enable FW Beamformer Interrupt */
 889         bytetmp = rtl_read_byte(rtlpriv, REG_FWIMR + 3);
 890         rtl_write_byte(rtlpriv, REG_FWIMR + 3, bytetmp | BIT(6));
 891
 892         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 893         wordtmp &= 0xf;
 894         wordtmp |= 0xF5B1;
 895         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 896
 897         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
 898         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 899         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
 900         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 901
 902         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 903                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 904                         DMA_BIT_MASK(32));
 905         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 906                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 907                         DMA_BIT_MASK(32));
 908         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 909                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 910         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 911                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 912         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 913                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 914         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 915                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 916         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 917                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 918                         DMA_BIT_MASK(32));
 919         rtl_write_dword(rtlpriv, REG_RX_DESA,
 920                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 921                         DMA_BIT_MASK(32));
 922
 923         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 3);
 924         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, bytetmp | 0x77);
 925
 926         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 927
 928         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 929
 930         rtl_write_byte(rtlpriv, REG_SECONDARY_CCA_CTRL, 0x3);
 931
 932         /* <20130114, Kordan> The following setting is
 933          * only for DPDT and Fixed board type.
 934          * TODO:  A better solution is configure it
 935          * according EFUSE during the run-time.
 936          */
 937         rtl_set_bbreg(hw, 0x64, BIT(20), 0x0);/* 0x66[4]=0 */
 938         rtl_set_bbreg(hw, 0x64, BIT(24), 0x0);/* 0x66[8]=0 */
 939         rtl_set_bbreg(hw, 0x40, BIT(4), 0x0)/* 0x40[4]=0 */;
 940         rtl_set_bbreg(hw, 0x40, BIT(3), 0x1)/* 0x40[3]=1 */;
 941         rtl_set_bbreg(hw, 0x4C, BIT(24) | BIT(23), 0x2)/* 0x4C[24:23]=10 */;
 942         rtl_set_bbreg(hw, 0x944, BIT(1) | BIT(0), 0x3)/* 0x944[1:0]=11 */;
 943         rtl_set_bbreg(hw, 0x930, MASKBYTE0, 0x77)/* 0x930[7:0]=77 */;
 944         rtl_set_bbreg(hw, 0x38, BIT(11), 0x1)/* 0x38[11]=1 */;
 945
 946         bytetmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
 947         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, bytetmp & (~BIT(2)));
 948
 949         _rtl8723be_gen_refresh_led_state(hw);
 950         return true;
 951 }
 952
 953 static void _rtl8723be_hw_configure(struct ieee80211_hw *hw)
 954 {
 955         struct rtl_priv *rtlpriv = rtl_priv(hw);
 956         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 957         u32 reg_rrsr;
 958
 959         reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 960         /* Init value for RRSR. */
 961         rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
 962
 963         /* ARFB table 9 for 11ac 5G 2SS */
 964         rtl_write_dword(rtlpriv, REG_ARFR0 + 4, 0xfffff000);
 965
 966         /* ARFB table 10 for 11ac 5G 1SS */
 967         rtl_write_dword(rtlpriv, REG_ARFR1 + 4, 0x003ff000);
 968
 969         /* CF-End setting. */
 970         rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F00);
 971
 972         /* 0x456 = 0x70, sugguested by Zhilin */
 973         rtl_write_byte(rtlpriv, REG_AMPDU_MAX_TIME, 0x70);
 974
 975         /* Set retry limit */
 976         rtl_write_word(rtlpriv, REG_RL, 0x0707);
 977
 978         /* Set Data / Response auto rate fallack retry count */
 979         rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
 980         rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
 981         rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
 982         rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
 983
 984         rtlpci->reg_bcn_ctrl_val = 0x1d;
 985         rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
 986
 987         /* TBTT prohibit hold time. Suggested by designer TimChen. */
 988         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff); /* 8 ms */
 989
 990         rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0040);
 991
 992         /*For Rx TP. Suggested by SD1 Richard. Added by tynli. 2010.04.12.*/
 993         rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
 994
 995         rtl_write_byte(rtlpriv, REG_HT_SINGLE_AMPDU, 0x80);
 996
 997         rtl_write_byte(rtlpriv, REG_RX_PKT_LIMIT, 0x20);
 998
 999         rtl_write_byte(rtlpriv, REG_MAX_AGGR_NUM, 0x1F);
1000 }
1001
1002 static u8 _rtl8723be_dbi_read(struct rtl_priv *rtlpriv, u16 addr)
1003 {
1004         u16 read_addr = addr & 0xfffc;
1005         u8 ret = 0, tmp = 0, count = 0;
1006
1007         rtl_write_word(rtlpriv, REG_DBI_ADDR, read_addr);
1008         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x2);
1009         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1010         count = 0;
1011         while (tmp && count < 20) {
1012                 udelay(10);
1013                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1014                 count++;
1015         }
1016         if (0 == tmp) {
1017                 read_addr = REG_DBI_RDATA + addr % 4;
1018                 ret = rtl_read_byte(rtlpriv, read_addr);
1019         }
1020
1021         return ret;
1022 }
1023
1024 static void _rtl8723be_dbi_write(struct rtl_priv *rtlpriv, u16 addr, u8 data)
1025 {
1026         u8 tmp = 0, count = 0;
1027         u16 write_addr = 0, remainder = addr % 4;
1028
1029         /* Write DBI 1Byte Data */
1030         write_addr = REG_DBI_WDATA + remainder;
1031         rtl_write_byte(rtlpriv, write_addr, data);
1032
1033         /* Write DBI 2Byte Address & Write Enable */
1034         write_addr = (addr & 0xfffc) | (BIT(0) << (remainder + 12));
1035         rtl_write_word(rtlpriv, REG_DBI_ADDR, write_addr);
1036
1037         /* Write DBI Write Flag */
1038         rtl_write_byte(rtlpriv, REG_DBI_FLAG, 0x1);
1039
1040         tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1041         count = 0;
1042         while (tmp && count < 20) {
1043                 udelay(10);
1044                 tmp = rtl_read_byte(rtlpriv, REG_DBI_FLAG);
1045                 count++;
1046         }
1047 }
1048
1049 static u16 _rtl8723be_mdio_read(struct rtl_priv *rtlpriv, u8 addr)
1050 {
1051         u16 ret = 0;
1052         u8 tmp = 0, count = 0;
1053
1054         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(6));
1055         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1056         count = 0;
1057         while (tmp && count < 20) {
1058                 udelay(10);
1059                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(6);
1060                 count++;
1061         }
1062
1063         if (0 == tmp)
1064                 ret = rtl_read_word(rtlpriv, REG_MDIO_RDATA);
1065
1066         return ret;
1067 }
1068
1069 static void _rtl8723be_mdio_write(struct rtl_priv *rtlpriv, u8 addr, u16 data)
1070 {
1071         u8 tmp = 0, count = 0;
1072
1073         rtl_write_word(rtlpriv, REG_MDIO_WDATA, data);
1074         rtl_write_byte(rtlpriv, REG_MDIO_CTL, addr | BIT(5));
1075         tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1076         count = 0;
1077         while (tmp && count < 20) {
1078                 udelay(10);
1079                 tmp = rtl_read_byte(rtlpriv, REG_MDIO_CTL) & BIT(5);
1080                 count++;
1081         }
1082 }
1083
1084 static void _rtl8723be_enable_aspm_back_door(struct ieee80211_hw *hw)
1085 {
1086         struct rtl_priv *rtlpriv = rtl_priv(hw);
1087         u8 tmp8 = 0;
1088         u16 tmp16 = 0;
1089
1090         /* <Roger_Notes> Overwrite following ePHY parameter for
1091          * some platform compatibility issue,
1092          * especially when CLKReq is enabled, 2012.11.09.
1093          */
1094         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x01);
1095         if (tmp16 != 0x0663)
1096                 _rtl8723be_mdio_write(rtlpriv, 0x01, 0x0663);
1097
1098         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x04);
1099         if (tmp16 != 0x7544)
1100                 _rtl8723be_mdio_write(rtlpriv, 0x04, 0x7544);
1101
1102         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x06);
1103         if (tmp16 != 0xB880)
1104                 _rtl8723be_mdio_write(rtlpriv, 0x06, 0xB880);
1105
1106         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x07);
1107         if (tmp16 != 0x4000)
1108                 _rtl8723be_mdio_write(rtlpriv, 0x07, 0x4000);
1109
1110         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x08);
1111         if (tmp16 != 0x9003)
1112                 _rtl8723be_mdio_write(rtlpriv, 0x08, 0x9003);
1113
1114         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x09);
1115         if (tmp16 != 0x0D03)
1116                 _rtl8723be_mdio_write(rtlpriv, 0x09, 0x0D03);
1117
1118         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0A);
1119         if (tmp16 != 0x4037)
1120                 _rtl8723be_mdio_write(rtlpriv, 0x0A, 0x4037);
1121
1122         tmp16 = _rtl8723be_mdio_read(rtlpriv, 0x0B);
1123         if (tmp16 != 0x0070)
1124                 _rtl8723be_mdio_write(rtlpriv, 0x0B, 0x0070);
1125
1126         /* Configuration Space offset 0x70f BIT7 is used to control L0S */
1127         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x70f);
1128         _rtl8723be_dbi_write(rtlpriv, 0x70f, tmp8 | BIT(7) |
1129                              ASPM_L1_LATENCY << 3);
1130
1131         /* Configuration Space offset 0x719 Bit3 is for L1
1132          * BIT4 is for clock request
1133          */
1134         tmp8 = _rtl8723be_dbi_read(rtlpriv, 0x719);
1135         _rtl8723be_dbi_write(rtlpriv, 0x719, tmp8 | BIT(3) | BIT(4));
1136 }
1137
1138 void rtl8723be_enable_hw_security_config(struct ieee80211_hw *hw)
1139 {
1140         struct rtl_priv *rtlpriv = rtl_priv(hw);
1141         u8 sec_reg_value;
1142
1143         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1144                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1145                   rtlpriv->sec.pairwise_enc_algorithm,
1146                   rtlpriv->sec.group_enc_algorithm);
1147
1148         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1149                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1150                          "not open hw encryption\n");
1151                 return;
1152         }
1153
1154         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1155
1156         if (rtlpriv->sec.use_defaultkey) {
1157                 sec_reg_value |= SCR_TXUSEDK;
1158                 sec_reg_value |= SCR_RXUSEDK;
1159         }
1160
1161         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1162
1163         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1164
1165         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1166                  "The SECR-value %x\n", sec_reg_value);
1167
1168         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1169 }
1170
1171 static void _rtl8723be_poweroff_adapter(struct ieee80211_hw *hw)
1172 {
1173         struct rtl_priv *rtlpriv = rtl_priv(hw);
1174         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1175         u8 u1b_tmp;
1176
1177         rtlhal->mac_func_enable = false;
1178         /* Combo (PCIe + USB) Card and PCIe-MF Card */
1179         /* 1. Run LPS WL RFOFF flow */
1180         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1181                                  PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1182
1183         /* 2. 0x1F[7:0] = 0 */
1184         /* turn off RF */
1185         /* rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00); */
1186         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1187             rtlhal->fw_ready) {
1188                 rtl8723be_firmware_selfreset(hw);
1189         }
1190
1191         /* Reset MCU. Suggested by Filen. */
1192         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1193         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1194
1195         /* g.   MCUFWDL 0x80[1:0]=0      */
1196         /* reset MCU ready status */
1197         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1198
1199         /* HW card disable configuration. */
1200         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1201                                  PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1202
1203         /* Reset MCU IO Wrapper */
1204         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1205         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1206         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1207         rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1208
1209         /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1210         /* lock ISO/CLK/Power control register */
1211         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1212 }
1213
1214 static bool _rtl8723be_check_pcie_dma_hang(struct rtl_priv *rtlpriv)
1215 {
1216         u8 tmp;
1217
1218         /* write reg 0x350 Bit[26]=1. Enable debug port. */
1219         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1220         if (!(tmp & BIT(2))) {
1221                 rtl_write_byte(rtlpriv, REG_DBI_CTRL + 3, (tmp | BIT(2)));
1222                 mdelay(100); /* Suggested by DD Justin_tsai. */
1223         }
1224
1225         /* read reg 0x350 Bit[25] if 1 : RX hang
1226          * read reg 0x350 Bit[24] if 1 : TX hang
1227          */
1228         tmp = rtl_read_byte(rtlpriv, REG_DBI_CTRL + 3);
1229         if ((tmp & BIT(0)) || (tmp & BIT(1))) {
1230                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1231                          "CheckPcieDMAHang8723BE(): true!!\n");
1232                 return true;
1233         }
1234         return false;
1235 }
1236
1237 static void _rtl8723be_reset_pcie_interface_dma(struct rtl_priv *rtlpriv,
1238                                                 bool mac_power_on)
1239 {
1240         u8 tmp;
1241         bool release_mac_rx_pause;
1242         u8 backup_pcie_dma_pause;
1243
1244         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1245                  "ResetPcieInterfaceDMA8723BE()\n");
1246
1247         /* Revise Note: Follow the document "PCIe RX DMA Hang Reset Flow_v03"
1248          * released by SD1 Alan.
1249          * 2013.05.07, by tynli.
1250          */
1251
1252         /* 1. disable register write lock
1253          *      write 0x1C bit[1:0] = 2'h0
1254          *      write 0xCC bit[2] = 1'b1
1255          */
1256         tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL);
1257         tmp &= ~(BIT(1) | BIT(0));
1258         rtl_write_byte(rtlpriv, REG_RSV_CTRL, tmp);
1259         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1260         tmp |= BIT(2);
1261         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1262
1263         /* 2. Check and pause TRX DMA
1264          *      write 0x284 bit[18] = 1'b1
1265          *      write 0x301 = 0xFF
1266          */
1267         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1268         if (tmp & BIT(2)) {
1269                 /* Already pause before the function for another purpose. */
1270                 release_mac_rx_pause = false;
1271         } else {
1272                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, (tmp | BIT(2)));
1273                 release_mac_rx_pause = true;
1274         }
1275
1276         backup_pcie_dma_pause = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG + 1);
1277         if (backup_pcie_dma_pause != 0xFF)
1278                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFF);
1279
1280         if (mac_power_on) {
1281                 /* 3. reset TRX function
1282                  *      write 0x100 = 0x00
1283                  */
1284                 rtl_write_byte(rtlpriv, REG_CR, 0);
1285         }
1286
1287         /* 4. Reset PCIe DMA
1288          *      write 0x003 bit[0] = 0
1289          */
1290         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1291         tmp &= ~(BIT(0));
1292         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1293
1294         /* 5. Enable PCIe DMA
1295          *      write 0x003 bit[0] = 1
1296          */
1297         tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1298         tmp |= BIT(0);
1299         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmp);
1300
1301         if (mac_power_on) {
1302                 /* 6. enable TRX function
1303                  *      write 0x100 = 0xFF
1304                  */
1305                 rtl_write_byte(rtlpriv, REG_CR, 0xFF);
1306
1307                 /* We should init LLT & RQPN and
1308                  * prepare Tx/Rx descrptor address later
1309                  * because MAC function is reset.
1310                  */
1311         }
1312
1313         /* 7. Restore PCIe autoload down bit
1314          *      write 0xF8 bit[17] = 1'b1
1315          */
1316         tmp = rtl_read_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2);
1317         tmp |= BIT(1);
1318         rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL + 2, tmp);
1319
1320         /* In MAC power on state, BB and RF maybe in ON state,
1321          * if we release TRx DMA here
1322          * it will cause packets to be started to Tx/Rx,
1323          * so we release Tx/Rx DMA later.
1324          */
1325         if (!mac_power_on) {
1326                 /* 8. release TRX DMA
1327                  *      write 0x284 bit[18] = 1'b0
1328                  *      write 0x301 = 0x00
1329                  */
1330                 if (release_mac_rx_pause) {
1331                         tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1332                         rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL,
1333                                        (tmp & (~BIT(2))));
1334                 }
1335                 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1,
1336                                backup_pcie_dma_pause);
1337         }
1338
1339         /* 9. lock system register
1340          *      write 0xCC bit[2] = 1'b0
1341          */
1342         tmp = rtl_read_byte(rtlpriv, REG_PMC_DBG_CTRL2);
1343         tmp &= ~(BIT(2));
1344         rtl_write_byte(rtlpriv, REG_PMC_DBG_CTRL2, tmp);
1345 }
1346
1347 int rtl8723be_hw_init(struct ieee80211_hw *hw)
1348 {
1349         struct rtl_priv *rtlpriv = rtl_priv(hw);
1350         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1351         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1352         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1353         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1354         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1355         bool rtstatus = true;
1356         int err;
1357         u8 tmp_u1b;
1358         unsigned long flags;
1359
1360         /* reenable interrupts to not interfere with other devices */
1361         local_save_flags(flags);
1362         local_irq_enable();
1363
1364         rtlhal->fw_ready = false;
1365         rtlpriv->rtlhal.being_init_adapter = true;
1366         rtlpriv->intf_ops->disable_aspm(hw);
1367
1368         tmp_u1b = rtl_read_byte(rtlpriv, REG_CR);
1369         if (tmp_u1b != 0 && tmp_u1b != 0xea) {
1370                 rtlhal->mac_func_enable = true;
1371         } else {
1372                 rtlhal->mac_func_enable = false;
1373                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON;
1374         }
1375
1376         if (_rtl8723be_check_pcie_dma_hang(rtlpriv)) {
1377                 _rtl8723be_reset_pcie_interface_dma(rtlpriv,
1378                                                     rtlhal->mac_func_enable);
1379                 rtlhal->mac_func_enable = false;
1380         }
1381         if (rtlhal->mac_func_enable) {
1382                 _rtl8723be_poweroff_adapter(hw);
1383                 rtlhal->mac_func_enable = false;
1384         }
1385         rtstatus = _rtl8723be_init_mac(hw);
1386         if (!rtstatus) {
1387                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
1388                 err = 1;
1389                 goto exit;
1390         }
1391
1392         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CFG);
1393         rtl_write_byte(rtlpriv, REG_SYS_CFG, tmp_u1b & 0x7F);
1394
1395         err = rtl8723_download_fw(hw, true, FW_8723B_POLLING_TIMEOUT_COUNT);
1396         if (err) {
1397                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1398                          "Failed to download FW. Init HW without FW now..\n");
1399                 err = 1;
1400                 goto exit;
1401         }
1402         rtlhal->fw_ready = true;
1403
1404         rtlhal->last_hmeboxnum = 0;
1405         rtl8723be_phy_mac_config(hw);
1406         /* because last function modify RCR, so we update
1407          * rcr var here, or TP will unstable for receive_config
1408          * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
1409          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1410          */
1411         rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
1412         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1413         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1414
1415         rtl8723be_phy_bb_config(hw);
1416         rtl8723be_phy_rf_config(hw);
1417
1418         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1419                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1420         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1421                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1422         rtlphy->rfreg_chnlval[0] &= 0xFFF03FF;
1423         rtlphy->rfreg_chnlval[0] |= (BIT(10) | BIT(11));
1424
1425         _rtl8723be_hw_configure(hw);
1426         rtlhal->mac_func_enable = true;
1427         rtl_cam_reset_all_entry(hw);
1428         rtl8723be_enable_hw_security_config(hw);
1429
1430         ppsc->rfpwr_state = ERFON;
1431
1432         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1433         _rtl8723be_enable_aspm_back_door(hw);
1434         rtlpriv->intf_ops->enable_aspm(hw);
1435
1436         rtl8723be_bt_hw_init(hw);
1437
1438         if (ppsc->rfpwr_state == ERFON) {
1439                 rtl8723be_phy_set_rfpath_switch(hw, 1);
1440                 /* when use 1ant NIC, iqk will disturb BT music
1441                  * root cause is not clear now, is something
1442                  * related with 'mdelay' and Reg[0x948]
1443                  */
1444                 if (rtlpriv->btcoexist.btc_info.ant_num == ANT_X2 ||
1445                     !rtlpriv->cfg->ops->get_btc_status()) {
1446                         rtl8723be_phy_iq_calibrate(hw, false);
1447                         rtlphy->iqk_initialized = true;
1448                 }
1449                 rtl8723be_dm_check_txpower_tracking(hw);
1450                 rtl8723be_phy_lc_calibrate(hw);
1451         }
1452         rtl_write_byte(rtlpriv, REG_NAV_UPPER, ((30000 + 127) / 128));
1453
1454         /* Release Rx DMA. */
1455         tmp_u1b = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1456         if (tmp_u1b & BIT(2)) {
1457                 /* Release Rx DMA if needed */
1458                 tmp_u1b &= (~BIT(2));
1459                 rtl_write_byte(rtlpriv, REG_RXDMA_CONTROL, tmp_u1b);
1460         }
1461         /* Release Tx/Rx PCIE DMA. */
1462         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0);
1463
1464         rtl8723be_dm_init(hw);
1465 exit:
1466         local_irq_restore(flags);
1467         rtlpriv->rtlhal.being_init_adapter = false;
1468         return err;
1469 }
1470
1471 static enum version_8723e _rtl8723be_read_chip_version(struct ieee80211_hw *hw)
1472 {
1473         struct rtl_priv *rtlpriv = rtl_priv(hw);
1474         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1475         enum version_8723e version = VERSION_UNKNOWN;
1476         u32 value32;
1477
1478         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG1);
1479         if ((value32 & (CHIP_8723B)) != CHIP_8723B)
1480                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "unknown chip version\n");
1481         else
1482                 version = (enum version_8723e)CHIP_8723B;
1483
1484         rtlphy->rf_type = RF_1T1R;
1485
1486         /* treat rtl8723be chip as  MP version in default */
1487         version = (enum version_8723e)(version | NORMAL_CHIP);
1488
1489         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1490         /* cut version */
1491         version |= (enum version_8723e)(value32 & CHIP_VER_RTL_MASK);
1492         /* Manufacture */
1493         if (((value32 & EXT_VENDOR_ID) >> 18) == 0x01)
1494                 version = (enum version_8723e)(version | CHIP_VENDOR_SMIC);
1495
1496         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1497                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1498                   "RF_2T2R" : "RF_1T1R");
1499
1500         return version;
1501 }
1502
1503 static int _rtl8723be_set_media_status(struct ieee80211_hw *hw,
1504                                        enum nl80211_iftype type)
1505 {
1506         struct rtl_priv *rtlpriv = rtl_priv(hw);
1507         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1508         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1509         u8 mode = MSR_NOLINK;
1510
1511         switch (type) {
1512         case NL80211_IFTYPE_UNSPECIFIED:
1513                 mode = MSR_NOLINK;
1514                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1515                          "Set Network type to NO LINK!\n");
1516                 break;
1517         case NL80211_IFTYPE_ADHOC:
1518         case NL80211_IFTYPE_MESH_POINT:
1519                 mode = MSR_ADHOC;
1520                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1521                          "Set Network type to Ad Hoc!\n");
1522                 break;
1523         case NL80211_IFTYPE_STATION:
1524                 mode = MSR_INFRA;
1525                 ledaction = LED_CTL_LINK;
1526                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1527                          "Set Network type to STA!\n");
1528                 break;
1529         case NL80211_IFTYPE_AP:
1530                 mode = MSR_AP;
1531                 ledaction = LED_CTL_LINK;
1532                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1533                          "Set Network type to AP!\n");
1534                 break;
1535         default:
1536                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1537                          "Network type %d not support!\n", type);
1538                 return 1;
1539         }
1540
1541         /* MSR_INFRA == Link in infrastructure network;
1542          * MSR_ADHOC == Link in ad hoc network;
1543          * Therefore, check link state is necessary.
1544          *
1545          * MSR_AP == AP mode; link state is not cared here.
1546          */
1547         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1548                 mode = MSR_NOLINK;
1549                 ledaction = LED_CTL_NO_LINK;
1550         }
1551
1552         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1553                 _rtl8723be_stop_tx_beacon(hw);
1554                 _rtl8723be_enable_bcn_sub_func(hw);
1555         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1556                 _rtl8723be_resume_tx_beacon(hw);
1557                 _rtl8723be_disable_bcn_sub_func(hw);
1558         } else {
1559                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1560                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1561                          mode);
1562         }
1563
1564         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1565         rtlpriv->cfg->ops->led_control(hw, ledaction);
1566         if (mode == MSR_AP)
1567                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1568         else
1569                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1570         return 0;
1571 }
1572
1573 void rtl8723be_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1574 {
1575         struct rtl_priv *rtlpriv = rtl_priv(hw);
1576         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1577         u32 reg_rcr = rtlpci->receive_config;
1578
1579         if (rtlpriv->psc.rfpwr_state != ERFON)
1580                 return;
1581
1582         if (check_bssid) {
1583                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1584                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1585                                               (u8 *)(&reg_rcr));
1586                 _rtl8723be_set_bcn_ctrl_reg(hw, 0, BIT(4));
1587         } else if (!check_bssid) {
1588                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1589                 _rtl8723be_set_bcn_ctrl_reg(hw, BIT(4), 0);
1590                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1591                                               (u8 *)(&reg_rcr));
1592         }
1593
1594 }
1595
1596 int rtl8723be_set_network_type(struct ieee80211_hw *hw,
1597                                enum nl80211_iftype type)
1598 {
1599         struct rtl_priv *rtlpriv = rtl_priv(hw);
1600
1601         if (_rtl8723be_set_media_status(hw, type))
1602                 return -EOPNOTSUPP;
1603
1604         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1605                 if (type != NL80211_IFTYPE_AP)
1606                         rtl8723be_set_check_bssid(hw, true);
1607         } else {
1608                 rtl8723be_set_check_bssid(hw, false);
1609         }
1610
1611         return 0;
1612 }
1613
1614 /* don't set REG_EDCA_BE_PARAM here
1615  * because mac80211 will send pkt when scan
1616  */
1617 void rtl8723be_set_qos(struct ieee80211_hw *hw, int aci)
1618 {
1619         struct rtl_priv *rtlpriv = rtl_priv(hw);
1620
1621         rtl8723_dm_init_edca_turbo(hw);
1622         switch (aci) {
1623         case AC1_BK:
1624                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1625                 break;
1626         case AC0_BE:
1627                 break;
1628         case AC2_VI:
1629                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1630                 break;
1631         case AC3_VO:
1632                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1633                 break;
1634         default:
1635                 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1636                 break;
1637         }
1638 }
1639
1640 void rtl8723be_enable_interrupt(struct ieee80211_hw *hw)
1641 {
1642         struct rtl_priv *rtlpriv = rtl_priv(hw);
1643         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1644
1645         rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1646         rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1647         rtlpci->irq_enabled = true;
1648
1649         /*enable system interrupt*/
1650         rtl_write_dword(rtlpriv, REG_HSIMR, rtlpci->sys_irq_mask & 0xFFFFFFFF);
1651 }
1652
1653 void rtl8723be_disable_interrupt(struct ieee80211_hw *hw)
1654 {
1655         struct rtl_priv *rtlpriv = rtl_priv(hw);
1656         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1657
1658         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1659         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1660         rtlpci->irq_enabled = false;
1661         /*synchronize_irq(rtlpci->pdev->irq);*/
1662 }
1663
1664 void rtl8723be_card_disable(struct ieee80211_hw *hw)
1665 {
1666         struct rtl_priv *rtlpriv = rtl_priv(hw);
1667         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1668         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1669         enum nl80211_iftype opmode;
1670
1671         mac->link_state = MAC80211_NOLINK;
1672         opmode = NL80211_IFTYPE_UNSPECIFIED;
1673         _rtl8723be_set_media_status(hw, opmode);
1674         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1675             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1676                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1677         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1678         _rtl8723be_poweroff_adapter(hw);
1679
1680         /* after power off we should do iqk again */
1681         rtlpriv->phy.iqk_initialized = false;
1682 }
1683
1684 void rtl8723be_interrupt_recognized(struct ieee80211_hw *hw,
1685                                     u32 *p_inta, u32 *p_intb)
1686 {
1687         struct rtl_priv *rtlpriv = rtl_priv(hw);
1688         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1689
1690         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1691         rtl_write_dword(rtlpriv, ISR, *p_inta);
1692
1693         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) &
1694                                         rtlpci->irq_mask[1];
1695         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1696 }
1697
1698 void rtl8723be_set_beacon_related_registers(struct ieee80211_hw *hw)
1699 {
1700         struct rtl_priv *rtlpriv = rtl_priv(hw);
1701         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1702         u16 bcn_interval, atim_window;
1703
1704         bcn_interval = mac->beacon_interval;
1705         atim_window = 2;        /*FIX MERGE */
1706         rtl8723be_disable_interrupt(hw);
1707         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1708         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1709         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1710         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1711         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1712         rtl_write_byte(rtlpriv, 0x606, 0x30);
1713         rtl8723be_enable_interrupt(hw);
1714 }
1715
1716 void rtl8723be_set_beacon_interval(struct ieee80211_hw *hw)
1717 {
1718         struct rtl_priv *rtlpriv = rtl_priv(hw);
1719         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1720         u16 bcn_interval = mac->beacon_interval;
1721
1722         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1723                  "beacon_interval:%d\n", bcn_interval);
1724         rtl8723be_disable_interrupt(hw);
1725         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1726         rtl8723be_enable_interrupt(hw);
1727 }
1728
1729 void rtl8723be_update_interrupt_mask(struct ieee80211_hw *hw,
1730                                    u32 add_msr, u32 rm_msr)
1731 {
1732         struct rtl_priv *rtlpriv = rtl_priv(hw);
1733         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1734
1735         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1736                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1737
1738         if (add_msr)
1739                 rtlpci->irq_mask[0] |= add_msr;
1740         if (rm_msr)
1741                 rtlpci->irq_mask[0] &= (~rm_msr);
1742         rtl8723be_disable_interrupt(hw);
1743         rtl8723be_enable_interrupt(hw);
1744 }
1745
1746 static u8 _rtl8723be_get_chnl_group(u8 chnl)
1747 {
1748         u8 group;
1749
1750         if (chnl < 3)
1751                 group = 0;
1752         else if (chnl < 9)
1753                 group = 1;
1754         else
1755                 group = 2;
1756         return group;
1757 }
1758
1759 static void _rtl8723be_read_power_value_fromprom(struct ieee80211_hw *hw,
1760                                         struct txpower_info_2g *pw2g,
1761                                         struct txpower_info_5g *pw5g,
1762                                         bool autoload_fail, u8 *hwinfo)
1763 {
1764         struct rtl_priv *rtlpriv = rtl_priv(hw);
1765         u32 path, addr = EEPROM_TX_PWR_INX, group, cnt = 0;
1766
1767         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1768                  "hal_ReadPowerValueFromPROM8723BE(): PROMContent[0x%x]=0x%x\n",
1769                  (addr + 1), hwinfo[addr + 1]);
1770         if (0xFF == hwinfo[addr + 1])  /*YJ,add,120316*/
1771                 autoload_fail = true;
1772
1773         if (autoload_fail) {
1774                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1775                          "auto load fail : Use Default value!\n");
1776                 for (path = 0; path < MAX_RF_PATH; path++) {
1777                         /* 2.4G default value */
1778                         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1779                                 pw2g->index_cck_base[path][group] = 0x2D;
1780                                 pw2g->index_bw40_base[path][group] = 0x2D;
1781                         }
1782                         for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1783                                 if (cnt == 0) {
1784                                         pw2g->bw20_diff[path][0] = 0x02;
1785                                         pw2g->ofdm_diff[path][0] = 0x04;
1786                                 } else {
1787                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1788                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1789                                         pw2g->cck_diff[path][cnt] = 0xFE;
1790                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1791                                 }
1792                         }
1793                 }
1794                 return;
1795         }
1796
1797         for (path = 0; path < MAX_RF_PATH; path++) {
1798                 /*2.4G default value*/
1799                 for (group = 0; group < MAX_CHNL_GROUP_24G; group++) {
1800                         pw2g->index_cck_base[path][group] = hwinfo[addr++];
1801                         if (pw2g->index_cck_base[path][group] == 0xFF)
1802                                 pw2g->index_cck_base[path][group] = 0x2D;
1803
1804                 }
1805                 for (group = 0; group < MAX_CHNL_GROUP_24G - 1; group++) {
1806                         pw2g->index_bw40_base[path][group] = hwinfo[addr++];
1807                         if (pw2g->index_bw40_base[path][group] == 0xFF)
1808                                 pw2g->index_bw40_base[path][group] = 0x2D;
1809                 }
1810                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1811                         if (cnt == 0) {
1812                                 pw2g->bw40_diff[path][cnt] = 0;
1813                                 if (hwinfo[addr] == 0xFF) {
1814                                         pw2g->bw20_diff[path][cnt] = 0x02;
1815                                 } else {
1816                                         pw2g->bw20_diff[path][cnt] =
1817                                                 (hwinfo[addr] & 0xf0) >> 4;
1818                                         /*bit sign number to 8 bit sign number*/
1819                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1820                                                 pw2g->bw20_diff[path][cnt] |=
1821                                                                           0xF0;
1822                                 }
1823
1824                                 if (hwinfo[addr] == 0xFF) {
1825                                         pw2g->ofdm_diff[path][cnt] = 0x04;
1826                                 } else {
1827                                         pw2g->ofdm_diff[path][cnt] =
1828                                                         (hwinfo[addr] & 0x0f);
1829                                         /*bit sign number to 8 bit sign number*/
1830                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1831                                                 pw2g->ofdm_diff[path][cnt] |=
1832                                                                           0xF0;
1833                                 }
1834                                 pw2g->cck_diff[path][cnt] = 0;
1835                                 addr++;
1836                         } else {
1837                                 if (hwinfo[addr] == 0xFF) {
1838                                         pw2g->bw40_diff[path][cnt] = 0xFE;
1839                                 } else {
1840                                         pw2g->bw40_diff[path][cnt] =
1841                                                 (hwinfo[addr] & 0xf0) >> 4;
1842                                         if (pw2g->bw40_diff[path][cnt] & BIT(3))
1843                                                 pw2g->bw40_diff[path][cnt] |=
1844                                                                           0xF0;
1845                                 }
1846
1847                                 if (hwinfo[addr] == 0xFF) {
1848                                         pw2g->bw20_diff[path][cnt] = 0xFE;
1849                                 } else {
1850                                         pw2g->bw20_diff[path][cnt] =
1851                                                         (hwinfo[addr] & 0x0f);
1852                                         if (pw2g->bw20_diff[path][cnt] & BIT(3))
1853                                                 pw2g->bw20_diff[path][cnt] |=
1854                                                                           0xF0;
1855                                 }
1856                                 addr++;
1857
1858                                 if (hwinfo[addr] == 0xFF) {
1859                                         pw2g->ofdm_diff[path][cnt] = 0xFE;
1860                                 } else {
1861                                         pw2g->ofdm_diff[path][cnt] =
1862                                                 (hwinfo[addr] & 0xf0) >> 4;
1863                                         if (pw2g->ofdm_diff[path][cnt] & BIT(3))
1864                                                 pw2g->ofdm_diff[path][cnt] |=
1865                                                                           0xF0;
1866                                 }
1867
1868                                 if (hwinfo[addr] == 0xFF)
1869                                         pw2g->cck_diff[path][cnt] = 0xFE;
1870                                 else {
1871                                         pw2g->cck_diff[path][cnt] =
1872                                                         (hwinfo[addr] & 0x0f);
1873                                         if (pw2g->cck_diff[path][cnt] & BIT(3))
1874                                                 pw2g->cck_diff[path][cnt] |=
1875                                                                          0xF0;
1876                                 }
1877                                 addr++;
1878                         }
1879                 }
1880
1881                 /*5G default value*/
1882                 for (group = 0; group < MAX_CHNL_GROUP_5G; group++) {
1883                         pw5g->index_bw40_base[path][group] = hwinfo[addr++];
1884                         if (pw5g->index_bw40_base[path][group] == 0xFF)
1885                                 pw5g->index_bw40_base[path][group] = 0xFE;
1886                 }
1887
1888                 for (cnt = 0; cnt < MAX_TX_COUNT; cnt++) {
1889                         if (cnt == 0) {
1890                                 pw5g->bw40_diff[path][cnt] = 0;
1891
1892                                 if (hwinfo[addr] == 0xFF) {
1893                                         pw5g->bw20_diff[path][cnt] = 0;
1894                                 } else {
1895                                         pw5g->bw20_diff[path][0] =
1896                                                 (hwinfo[addr] & 0xf0) >> 4;
1897                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1898                                                 pw5g->bw20_diff[path][cnt] |=
1899                                                                           0xF0;
1900                                 }
1901
1902                                 if (hwinfo[addr] == 0xFF)
1903                                         pw5g->ofdm_diff[path][cnt] = 0x04;
1904                                 else {
1905                                         pw5g->ofdm_diff[path][0] =
1906                                                         (hwinfo[addr] & 0x0f);
1907                                         if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1908                                                 pw5g->ofdm_diff[path][cnt] |=
1909                                                                           0xF0;
1910                                 }
1911                                 addr++;
1912                         } else {
1913                                 if (hwinfo[addr] == 0xFF) {
1914                                         pw5g->bw40_diff[path][cnt] = 0xFE;
1915                                 } else {
1916                                         pw5g->bw40_diff[path][cnt] =
1917                                                 (hwinfo[addr] & 0xf0) >> 4;
1918                                         if (pw5g->bw40_diff[path][cnt] & BIT(3))
1919                                                 pw5g->bw40_diff[path][cnt] |= 0xF0;
1920                                 }
1921
1922                                 if (hwinfo[addr] == 0xFF) {
1923                                         pw5g->bw20_diff[path][cnt] = 0xFE;
1924                                 } else {
1925                                         pw5g->bw20_diff[path][cnt] =
1926                                                         (hwinfo[addr] & 0x0f);
1927                                         if (pw5g->bw20_diff[path][cnt] & BIT(3))
1928                                                 pw5g->bw20_diff[path][cnt] |= 0xF0;
1929                                 }
1930                                 addr++;
1931                         }
1932                 }
1933
1934                 if (hwinfo[addr] == 0xFF) {
1935                         pw5g->ofdm_diff[path][1] = 0xFE;
1936                         pw5g->ofdm_diff[path][2] = 0xFE;
1937                 } else {
1938                         pw5g->ofdm_diff[path][1] = (hwinfo[addr] & 0xf0) >> 4;
1939                         pw5g->ofdm_diff[path][2] = (hwinfo[addr] & 0x0f);
1940                 }
1941                 addr++;
1942
1943                 if (hwinfo[addr] == 0xFF)
1944                         pw5g->ofdm_diff[path][3] = 0xFE;
1945                 else
1946                         pw5g->ofdm_diff[path][3] = (hwinfo[addr] & 0x0f);
1947                 addr++;
1948
1949                 for (cnt = 1; cnt < MAX_TX_COUNT; cnt++) {
1950                         if (pw5g->ofdm_diff[path][cnt] == 0xFF)
1951                                 pw5g->ofdm_diff[path][cnt] = 0xFE;
1952                         else if (pw5g->ofdm_diff[path][cnt] & BIT(3))
1953                                 pw5g->ofdm_diff[path][cnt] |= 0xF0;
1954                 }
1955         }
1956 }
1957
1958 static void _rtl8723be_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1959                                                    bool autoload_fail,
1960                                                    u8 *hwinfo)
1961 {
1962         struct rtl_priv *rtlpriv = rtl_priv(hw);
1963         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1964         struct txpower_info_2g pw2g;
1965         struct txpower_info_5g pw5g;
1966         u8 rf_path, index;
1967         u8 i;
1968
1969         _rtl8723be_read_power_value_fromprom(hw, &pw2g, &pw5g, autoload_fail,
1970                                              hwinfo);
1971
1972         for (rf_path = 0; rf_path < 2; rf_path++) {
1973                 for (i = 0; i < 14; i++) {
1974                         index = _rtl8723be_get_chnl_group(i+1);
1975
1976                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1977                                         pw2g.index_cck_base[rf_path][index];
1978                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1979                                         pw2g.index_bw40_base[rf_path][index];
1980                 }
1981                 for (i = 0; i < MAX_TX_COUNT; i++) {
1982                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1983                                                 pw2g.bw20_diff[rf_path][i];
1984                         rtlefuse->txpwr_ht40diff[rf_path][i] =
1985                                                 pw2g.bw40_diff[rf_path][i];
1986                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1987                                                 pw2g.ofdm_diff[rf_path][i];
1988                 }
1989
1990                 for (i = 0; i < 14; i++) {
1991                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1992                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1993                                 rf_path, i,
1994                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1995                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1996                 }
1997         }
1998
1999         if (!autoload_fail)
2000                 rtlefuse->eeprom_thermalmeter =
2001                                         hwinfo[EEPROM_THERMAL_METER_88E];
2002         else
2003                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2004
2005         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
2006                 rtlefuse->apk_thermalmeterignore = true;
2007                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
2008         }
2009
2010         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
2011         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2012                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
2013
2014         if (!autoload_fail) {
2015                 rtlefuse->eeprom_regulatory =
2016                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
2017                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
2018                         rtlefuse->eeprom_regulatory = 0;
2019         } else {
2020                 rtlefuse->eeprom_regulatory = 0;
2021         }
2022         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
2023                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
2024 }
2025
2026 static void _rtl8723be_read_adapter_info(struct ieee80211_hw *hw,
2027                                          bool pseudo_test)
2028 {
2029         struct rtl_priv *rtlpriv = rtl_priv(hw);
2030         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2031         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2032         int params[] = {RTL8723BE_EEPROM_ID, EEPROM_VID, EEPROM_DID,
2033                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
2034                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
2035                         COUNTRY_CODE_WORLD_WIDE_13};
2036         u8 *hwinfo;
2037         int i;
2038         bool is_toshiba_smid1 = false;
2039         bool is_toshiba_smid2 = false;
2040         bool is_samsung_smid = false;
2041         bool is_lenovo_smid = false;
2042         u16 toshiba_smid1[] = {
2043                 0x6151, 0x6152, 0x6154, 0x6155, 0x6177, 0x6178, 0x6179, 0x6180,
2044                 0x7151, 0x7152, 0x7154, 0x7155, 0x7177, 0x7178, 0x7179, 0x7180,
2045                 0x8151, 0x8152, 0x8154, 0x8155, 0x8181, 0x8182, 0x8184, 0x8185,
2046                 0x9151, 0x9152, 0x9154, 0x9155, 0x9181, 0x9182, 0x9184, 0x9185
2047         };
2048         u16 toshiba_smid2[] = {
2049                 0x6181, 0x6184, 0x6185, 0x7181, 0x7182, 0x7184, 0x7185, 0x8181,
2050                 0x8182, 0x8184, 0x8185, 0x9181, 0x9182, 0x9184, 0x9185
2051         };
2052         u16 samsung_smid[] = {
2053                 0x6191, 0x6192, 0x6193, 0x7191, 0x7192, 0x7193, 0x8191, 0x8192,
2054                 0x8193, 0x9191, 0x9192, 0x9193
2055         };
2056         u16 lenovo_smid[] = {
2057                 0x8195, 0x9195, 0x7194, 0x8200, 0x8201, 0x8202, 0x9199, 0x9200
2058         };
2059
2060         if (pseudo_test) {
2061                 /* needs to be added */
2062                 return;
2063         }
2064
2065         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
2066         if (!hwinfo)
2067                 return;
2068
2069         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
2070                 goto exit;
2071
2072         /*parse xtal*/
2073         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_8723BE];
2074         if (rtlefuse->crystalcap == 0xFF)
2075                 rtlefuse->crystalcap = 0x20;
2076
2077         _rtl8723be_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
2078                                                hwinfo);
2079
2080         rtl8723be_read_bt_coexist_info_from_hwpg(hw,
2081                                                  rtlefuse->autoload_failflag,
2082                                                  hwinfo);
2083
2084         /* set channel plan from efuse */
2085         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
2086
2087         if (rtlhal->oem_id == RT_CID_DEFAULT) {
2088                 /* Does this one have a Toshiba SMID from group 1? */
2089                 for (i = 0; i < sizeof(toshiba_smid1) / sizeof(u16); i++) {
2090                         if (rtlefuse->eeprom_smid == toshiba_smid1[i]) {
2091                                 is_toshiba_smid1 = true;
2092                                 break;
2093                         }
2094                 }
2095                 /* Does this one have a Toshiba SMID from group 2? */
2096                 for (i = 0; i < sizeof(toshiba_smid2) / sizeof(u16); i++) {
2097                         if (rtlefuse->eeprom_smid == toshiba_smid2[i]) {
2098                                 is_toshiba_smid2 = true;
2099                                 break;
2100                         }
2101                 }
2102                 /* Does this one have a Samsung SMID? */
2103                 for (i = 0; i < sizeof(samsung_smid) / sizeof(u16); i++) {
2104                         if (rtlefuse->eeprom_smid == samsung_smid[i]) {
2105                                 is_samsung_smid = true;
2106                                 break;
2107                         }
2108                 }
2109                 /* Does this one have a Lenovo SMID? */
2110                 for (i = 0; i < sizeof(lenovo_smid) / sizeof(u16); i++) {
2111                         if (rtlefuse->eeprom_smid == lenovo_smid[i]) {
2112                                 is_lenovo_smid = true;
2113                                 break;
2114                         }
2115                 }
2116                 switch (rtlefuse->eeprom_oemid) {
2117                 case EEPROM_CID_DEFAULT:
2118                         if (rtlefuse->eeprom_did == 0x8176) {
2119                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2120                                     is_toshiba_smid1) {
2121                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2122                                 } else if (rtlefuse->eeprom_svid == 0x1025) {
2123                                         rtlhal->oem_id = RT_CID_819X_ACER;
2124                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2125                                            is_samsung_smid) {
2126                                         rtlhal->oem_id = RT_CID_819X_SAMSUNG;
2127                                 } else if (rtlefuse->eeprom_svid == 0x10EC &&
2128                                            is_lenovo_smid) {
2129                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
2130                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2131                                             rtlefuse->eeprom_smid == 0x8197) ||
2132                                            (rtlefuse->eeprom_svid == 0x10EC &&
2133                                             rtlefuse->eeprom_smid == 0x9196)) {
2134                                         rtlhal->oem_id = RT_CID_819X_CLEVO;
2135                                 } else if ((rtlefuse->eeprom_svid == 0x1028 &&
2136                                             rtlefuse->eeprom_smid == 0x8194) ||
2137                                            (rtlefuse->eeprom_svid == 0x1028 &&
2138                                             rtlefuse->eeprom_smid == 0x8198) ||
2139                                            (rtlefuse->eeprom_svid == 0x1028 &&
2140                                             rtlefuse->eeprom_smid == 0x9197) ||
2141                                            (rtlefuse->eeprom_svid == 0x1028 &&
2142                                             rtlefuse->eeprom_smid == 0x9198)) {
2143                                         rtlhal->oem_id = RT_CID_819X_DELL;
2144                                 } else if ((rtlefuse->eeprom_svid == 0x103C &&
2145                                             rtlefuse->eeprom_smid == 0x1629)) {
2146                                         rtlhal->oem_id = RT_CID_819X_HP;
2147                                 } else if ((rtlefuse->eeprom_svid == 0x1A32 &&
2148                                            rtlefuse->eeprom_smid == 0x2315)) {
2149                                         rtlhal->oem_id = RT_CID_819X_QMI;
2150                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
2151                                            rtlefuse->eeprom_smid == 0x8203)) {
2152                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2153                                 } else if ((rtlefuse->eeprom_svid == 0x1043 &&
2154                                            rtlefuse->eeprom_smid == 0x84B5)) {
2155                                         rtlhal->oem_id = RT_CID_819X_EDIMAX_ASUS;
2156                                 } else {
2157                                         rtlhal->oem_id = RT_CID_DEFAULT;
2158                                 }
2159                         } else if (rtlefuse->eeprom_did == 0x8178) {
2160                                 if (rtlefuse->eeprom_svid == 0x10EC &&
2161                                     is_toshiba_smid2)
2162                                         rtlhal->oem_id = RT_CID_TOSHIBA;
2163                                 else if (rtlefuse->eeprom_svid == 0x1025)
2164                                         rtlhal->oem_id = RT_CID_819X_ACER;
2165                                 else if ((rtlefuse->eeprom_svid == 0x10EC &&
2166                                           rtlefuse->eeprom_smid == 0x8186))
2167                                         rtlhal->oem_id = RT_CID_819X_PRONETS;
2168                                 else if ((rtlefuse->eeprom_svid == 0x1043 &&
2169                                           rtlefuse->eeprom_smid == 0x84B6))
2170                                         rtlhal->oem_id =
2171                                                         RT_CID_819X_EDIMAX_ASUS;
2172                                 else
2173                                         rtlhal->oem_id = RT_CID_DEFAULT;
2174                         } else {
2175                                         rtlhal->oem_id = RT_CID_DEFAULT;
2176                         }
2177                         break;
2178                 case EEPROM_CID_TOSHIBA:
2179                         rtlhal->oem_id = RT_CID_TOSHIBA;
2180                         break;
2181                 case EEPROM_CID_CCX:
2182                         rtlhal->oem_id = RT_CID_CCX;
2183                         break;
2184                 case EEPROM_CID_QMI:
2185                         rtlhal->oem_id = RT_CID_819X_QMI;
2186                         break;
2187                 case EEPROM_CID_WHQL:
2188                         break;
2189                 default:
2190                         rtlhal->oem_id = RT_CID_DEFAULT;
2191                         break;
2192                 }
2193         }
2194 exit:
2195         kfree(hwinfo);
2196 }
2197
2198 static void _rtl8723be_hal_customized_behavior(struct ieee80211_hw *hw)
2199 {
2200         struct rtl_priv *rtlpriv = rtl_priv(hw);
2201         struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2202         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2203
2204         pcipriv->ledctl.led_opendrain = true;
2205         switch (rtlhal->oem_id) {
2206         case RT_CID_819X_HP:
2207                 pcipriv->ledctl.led_opendrain = true;
2208                 break;
2209         case RT_CID_819X_LENOVO:
2210         case RT_CID_DEFAULT:
2211         case RT_CID_TOSHIBA:
2212         case RT_CID_CCX:
2213         case RT_CID_819X_ACER:
2214         case RT_CID_WHQL:
2215         default:
2216                 break;
2217         }
2218         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2219                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
2220 }
2221
2222 void rtl8723be_read_eeprom_info(struct ieee80211_hw *hw)
2223 {
2224         struct rtl_priv *rtlpriv = rtl_priv(hw);
2225         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2226         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2227         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2228         u8 tmp_u1b;
2229
2230         rtlhal->version = _rtl8723be_read_chip_version(hw);
2231         if (get_rf_type(rtlphy) == RF_1T1R)
2232                 rtlpriv->dm.rfpath_rxenable[0] = true;
2233         else
2234                 rtlpriv->dm.rfpath_rxenable[0] =
2235                     rtlpriv->dm.rfpath_rxenable[1] = true;
2236         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
2237                  rtlhal->version);
2238         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
2239         if (tmp_u1b & BIT(4)) {
2240                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2241                 rtlefuse->epromtype = EEPROM_93C46;
2242         } else {
2243                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2244                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2245         }
2246         if (tmp_u1b & BIT(5)) {
2247                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2248                 rtlefuse->autoload_failflag = false;
2249                 _rtl8723be_read_adapter_info(hw, false);
2250         } else {
2251                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2252         }
2253         _rtl8723be_hal_customized_behavior(hw);
2254 }
2255
2256 static u8 _rtl8723be_mrate_idx_to_arfr_id(struct ieee80211_hw *hw,
2257                                           u8 rate_index)
2258 {
2259         u8 ret = 0;
2260         switch (rate_index) {
2261         case RATR_INX_WIRELESS_NGB:
2262                 ret = 1;
2263                 break;
2264         case RATR_INX_WIRELESS_N:
2265         case RATR_INX_WIRELESS_NG:
2266                 ret = 5;
2267                 break;
2268         case RATR_INX_WIRELESS_NB:
2269                 ret = 3;
2270                 break;
2271         case RATR_INX_WIRELESS_GB:
2272                 ret = 6;
2273                 break;
2274         case RATR_INX_WIRELESS_G:
2275                 ret = 7;
2276                 break;
2277         case RATR_INX_WIRELESS_B:
2278                 ret = 8;
2279                 break;
2280         default:
2281                 ret = 0;
2282                 break;
2283         }
2284         return ret;
2285 }
2286
2287 static void rtl8723be_update_hal_rate_mask(struct ieee80211_hw *hw,
2288                                            struct ieee80211_sta *sta,
2289                                            u8 rssi_level)
2290 {
2291         struct rtl_priv *rtlpriv = rtl_priv(hw);
2292         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2293         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2294         struct rtl_sta_info *sta_entry = NULL;
2295         u32 ratr_bitmap;
2296         u8 ratr_index;
2297         u8 curtxbw_40mhz = (sta->ht_cap.cap &
2298                               IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
2299         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2300                                 1 : 0;
2301         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2302                                 1 : 0;
2303         enum wireless_mode wirelessmode = 0;
2304         bool shortgi = false;
2305         u8 rate_mask[7];
2306         u8 macid = 0;
2307
2308         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2309         wirelessmode = sta_entry->wireless_mode;
2310         if (mac->opmode == NL80211_IFTYPE_STATION ||
2311             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2312                 curtxbw_40mhz = mac->bw_40;
2313         else if (mac->opmode == NL80211_IFTYPE_AP ||
2314                  mac->opmode == NL80211_IFTYPE_ADHOC)
2315                 macid = sta->aid + 1;
2316
2317         ratr_bitmap = sta->supp_rates[0];
2318
2319         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2320                 ratr_bitmap = 0xfff;
2321
2322         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2323                         sta->ht_cap.mcs.rx_mask[0] << 12);
2324         switch (wirelessmode) {
2325         case WIRELESS_MODE_B:
2326                 ratr_index = RATR_INX_WIRELESS_B;
2327                 if (ratr_bitmap & 0x0000000c)
2328                         ratr_bitmap &= 0x0000000d;
2329                 else
2330                         ratr_bitmap &= 0x0000000f;
2331                 break;
2332         case WIRELESS_MODE_G:
2333                 ratr_index = RATR_INX_WIRELESS_GB;
2334
2335                 if (rssi_level == 1)
2336                         ratr_bitmap &= 0x00000f00;
2337                 else if (rssi_level == 2)
2338                         ratr_bitmap &= 0x00000ff0;
2339                 else
2340                         ratr_bitmap &= 0x00000ff5;
2341                 break;
2342         case WIRELESS_MODE_N_24G:
2343         case WIRELESS_MODE_N_5G:
2344                 ratr_index = RATR_INX_WIRELESS_NGB;
2345                 if (rtlphy->rf_type == RF_1T1R) {
2346                         if (curtxbw_40mhz) {
2347                                 if (rssi_level == 1)
2348                                         ratr_bitmap &= 0x000f0000;
2349                                 else if (rssi_level == 2)
2350                                         ratr_bitmap &= 0x000ff000;
2351                                 else
2352                                         ratr_bitmap &= 0x000ff015;
2353                         } else {
2354                                 if (rssi_level == 1)
2355                                         ratr_bitmap &= 0x000f0000;
2356                                 else if (rssi_level == 2)
2357                                         ratr_bitmap &= 0x000ff000;
2358                                 else
2359                                         ratr_bitmap &= 0x000ff005;
2360                         }
2361                 } else {
2362                         if (curtxbw_40mhz) {
2363                                 if (rssi_level == 1)
2364                                         ratr_bitmap &= 0x0f8f0000;
2365                                 else if (rssi_level == 2)
2366                                         ratr_bitmap &= 0x0f8ff000;
2367                                 else
2368                                         ratr_bitmap &= 0x0f8ff015;
2369                         } else {
2370                                 if (rssi_level == 1)
2371                                         ratr_bitmap &= 0x0f8f0000;
2372                                 else if (rssi_level == 2)
2373                                         ratr_bitmap &= 0x0f8ff000;
2374                                 else
2375                                         ratr_bitmap &= 0x0f8ff005;
2376                         }
2377                 }
2378                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2379                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2380                         if (macid == 0)
2381                                 shortgi = true;
2382                         else if (macid == 1)
2383                                 shortgi = false;
2384                 }
2385                 break;
2386         default:
2387                 ratr_index = RATR_INX_WIRELESS_NGB;
2388
2389                 if (rtlphy->rf_type == RF_1T2R)
2390                         ratr_bitmap &= 0x000ff0ff;
2391                 else
2392                         ratr_bitmap &= 0x0f0ff0ff;
2393                 break;
2394         }
2395
2396         sta_entry->ratr_index = ratr_index;
2397
2398         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2399                  "ratr_bitmap :%x\n", ratr_bitmap);
2400         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2401                                        (ratr_index << 28);
2402         rate_mask[0] = macid;
2403         rate_mask[1] = _rtl8723be_mrate_idx_to_arfr_id(hw, ratr_index) |
2404                                                       (shortgi ? 0x80 : 0x00);
2405         rate_mask[2] = curtxbw_40mhz;
2406
2407         rate_mask[3] = (u8)(ratr_bitmap & 0x000000ff);
2408         rate_mask[4] = (u8)((ratr_bitmap & 0x0000ff00) >> 8);
2409         rate_mask[5] = (u8)((ratr_bitmap & 0x00ff0000) >> 16);
2410         rate_mask[6] = (u8)((ratr_bitmap & 0xff000000) >> 24);
2411
2412         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2413                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x:%x:%x\n",
2414                  ratr_index, ratr_bitmap,
2415                  rate_mask[0], rate_mask[1],
2416                  rate_mask[2], rate_mask[3],
2417                  rate_mask[4], rate_mask[5],
2418                  rate_mask[6]);
2419         rtl8723be_fill_h2c_cmd(hw, H2C_8723B_RA_MASK, 7, rate_mask);
2420         _rtl8723be_set_bcn_ctrl_reg(hw, BIT(3), 0);
2421 }
2422
2423 void rtl8723be_update_hal_rate_tbl(struct ieee80211_hw *hw,
2424                                    struct ieee80211_sta *sta,
2425                                    u8 rssi_level)
2426 {
2427         struct rtl_priv *rtlpriv = rtl_priv(hw);
2428         if (rtlpriv->dm.useramask)
2429                 rtl8723be_update_hal_rate_mask(hw, sta, rssi_level);
2430 }
2431
2432 void rtl8723be_update_channel_access_setting(struct ieee80211_hw *hw)
2433 {
2434         struct rtl_priv *rtlpriv = rtl_priv(hw);
2435         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2436         u16 sifs_timer;
2437
2438         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2439         if (!mac->ht_enable)
2440                 sifs_timer = 0x0a0a;
2441         else
2442                 sifs_timer = 0x0e0e;
2443         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2444 }
2445
2446 bool rtl8723be_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2447 {
2448         struct rtl_priv *rtlpriv = rtl_priv(hw);
2449         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2450         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2451         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2452         u8 u1tmp;
2453         bool b_actuallyset = false;
2454
2455         if (rtlpriv->rtlhal.being_init_adapter)
2456                 return false;
2457
2458         if (ppsc->swrf_processing)
2459                 return false;
2460
2461         spin_lock(&rtlpriv->locks.rf_ps_lock);
2462         if (ppsc->rfchange_inprogress) {
2463                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2464                 return false;
2465         } else {
2466                 ppsc->rfchange_inprogress = true;
2467                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2468         }
2469
2470         cur_rfstate = ppsc->rfpwr_state;
2471
2472         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2473                        rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2) & ~(BIT(1)));
2474
2475         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2476
2477         if (rtlphy->polarity_ctl)
2478                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2479         else
2480                 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2481
2482         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2483                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2484                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2485
2486                 e_rfpowerstate_toset = ERFON;
2487                 ppsc->hwradiooff = false;
2488                 b_actuallyset = true;
2489         } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2490                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2491                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2492
2493                 e_rfpowerstate_toset = ERFOFF;
2494                 ppsc->hwradiooff = true;
2495                 b_actuallyset = true;
2496         }
2497
2498         if (b_actuallyset) {
2499                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2500                 ppsc->rfchange_inprogress = false;
2501                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2502         } else {
2503                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2504                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2505
2506                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2507                 ppsc->rfchange_inprogress = false;
2508                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2509         }
2510
2511         *valid = 1;
2512         return !ppsc->hwradiooff;
2513
2514 }
2515
2516 void rtl8723be_set_key(struct ieee80211_hw *hw, u32 key_index,
2517                        u8 *p_macaddr, bool is_group, u8 enc_algo,
2518                        bool is_wepkey, bool clear_all)
2519 {
2520         struct rtl_priv *rtlpriv = rtl_priv(hw);
2521         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2522         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2523         u8 *macaddr = p_macaddr;
2524         u32 entry_id = 0;
2525         bool is_pairwise = false;
2526
2527         static u8 cam_const_addr[4][6] = {
2528                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2529                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2530                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2531                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2532         };
2533         static u8 cam_const_broad[] = {
2534                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2535         };
2536
2537         if (clear_all) {
2538                 u8 idx = 0;
2539                 u8 cam_offset = 0;
2540                 u8 clear_number = 5;
2541
2542                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2543
2544                 for (idx = 0; idx < clear_number; idx++) {
2545                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2546                         rtl_cam_empty_entry(hw, cam_offset + idx);
2547
2548                         if (idx < 5) {
2549                                 memset(rtlpriv->sec.key_buf[idx], 0,
2550                                        MAX_KEY_LEN);
2551                                 rtlpriv->sec.key_len[idx] = 0;
2552                         }
2553                 }
2554
2555         } else {
2556                 switch (enc_algo) {
2557                 case WEP40_ENCRYPTION:
2558                         enc_algo = CAM_WEP40;
2559                         break;
2560                 case WEP104_ENCRYPTION:
2561                         enc_algo = CAM_WEP104;
2562                         break;
2563                 case TKIP_ENCRYPTION:
2564                         enc_algo = CAM_TKIP;
2565                         break;
2566                 case AESCCMP_ENCRYPTION:
2567                         enc_algo = CAM_AES;
2568                         break;
2569                 default:
2570                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
2571                                  "switch case %#x not processed\n", enc_algo);
2572                         enc_algo = CAM_TKIP;
2573                         break;
2574                 }
2575
2576                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2577                         macaddr = cam_const_addr[key_index];
2578                         entry_id = key_index;
2579                 } else {
2580                         if (is_group) {
2581                                 macaddr = cam_const_broad;
2582                                 entry_id = key_index;
2583                         } else {
2584                                 if (mac->opmode == NL80211_IFTYPE_AP) {
2585                                         entry_id = rtl_cam_get_free_entry(hw,
2586                                                                 p_macaddr);
2587                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2588                                                 RT_TRACE(rtlpriv, COMP_SEC,
2589                                                          DBG_EMERG,
2590                                                          "Can not find free hw security cam entry\n");
2591                                                 return;
2592                                         }
2593                                 } else {
2594                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2595                                 }
2596
2597                                 key_index = PAIRWISE_KEYIDX;
2598                                 is_pairwise = true;
2599                         }
2600                 }
2601
2602                 if (rtlpriv->sec.key_len[key_index] == 0) {
2603                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2604                                  "delete one entry, entry_id is %d\n",
2605                                   entry_id);
2606                         if (mac->opmode == NL80211_IFTYPE_AP)
2607                                 rtl_cam_del_entry(hw, p_macaddr);
2608                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2609                 } else {
2610                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2611                                  "add one entry\n");
2612                         if (is_pairwise) {
2613                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2614                                          "set Pairwiase key\n");
2615
2616                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2617                                                entry_id, enc_algo,
2618                                                CAM_CONFIG_NO_USEDK,
2619                                                rtlpriv->sec.key_buf[key_index]);
2620                         } else {
2621                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2622                                          "set group key\n");
2623
2624                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2625                                         rtl_cam_add_one_entry(hw,
2626                                                 rtlefuse->dev_addr,
2627                                                 PAIRWISE_KEYIDX,
2628                                                 CAM_PAIRWISE_KEY_POSITION,
2629                                                 enc_algo,
2630                                                 CAM_CONFIG_NO_USEDK,
2631                                                 rtlpriv->sec.key_buf
2632                                                 [entry_id]);
2633                                 }
2634
2635                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2636                                                 entry_id, enc_algo,
2637                                                 CAM_CONFIG_NO_USEDK,
2638                                                 rtlpriv->sec.key_buf[entry_id]);
2639                         }
2640                 }
2641         }
2642 }
2643
2644 void rtl8723be_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2645                                               bool auto_load_fail, u8 *hwinfo)
2646 {
2647         struct rtl_priv *rtlpriv = rtl_priv(hw);
2648         struct rtl_mod_params *mod_params = rtlpriv->cfg->mod_params;
2649         u8 value;
2650         u32 tmpu_32;
2651
2652         if (!auto_load_fail) {
2653                 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2654                 if (tmpu_32 & BIT(18))
2655                         rtlpriv->btcoexist.btc_info.btcoexist = 1;
2656                 else
2657                         rtlpriv->btcoexist.btc_info.btcoexist = 0;
2658                 value = hwinfo[EEPROM_RF_BT_SETTING_8723B];
2659                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2660                 rtlpriv->btcoexist.btc_info.ant_num = (value & 0x1);
2661         } else {
2662                 rtlpriv->btcoexist.btc_info.btcoexist = 0;
2663                 rtlpriv->btcoexist.btc_info.bt_type = BT_RTL8723B;
2664                 rtlpriv->btcoexist.btc_info.ant_num = ANT_X2;
2665         }
2666
2667         /* override ant_num / ant_path */
2668         if (mod_params->ant_sel)
2669                 rtlpriv->btcoexist.btc_info.ant_num =
2670                         (mod_params->ant_sel == 1 ? ANT_X2 : ANT_X1);
2671 }
2672
2673 void rtl8723be_bt_reg_init(struct ieee80211_hw *hw)
2674 {
2675         struct rtl_priv *rtlpriv = rtl_priv(hw);
2676
2677         /* 0:Low, 1:High, 2:From Efuse. */
2678         rtlpriv->btcoexist.reg_bt_iso = 2;
2679         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2680         rtlpriv->btcoexist.reg_bt_sco = 3;
2681         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2682         rtlpriv->btcoexist.reg_bt_sco = 0;
2683 }
2684
2685 void rtl8723be_bt_hw_init(struct ieee80211_hw *hw)
2686 {
2687         struct rtl_priv *rtlpriv = rtl_priv(hw);
2688
2689         if (rtlpriv->cfg->ops->get_btc_status())
2690                 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2691
2692 }
2693
2694 void rtl8723be_suspend(struct ieee80211_hw *hw)
2695 {
2696 }
2697
2698 void rtl8723be_resume(struct ieee80211_hw *hw)
2699 {
2700 }