1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
35 #include "../rtl8723com/phy_common.h"
37 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
38 enum radio_path rfpath, u32 offset,
40 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
41 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
42 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
44 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
46 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
47 u8 channel, u8 *stage, u8 *step,
49 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
50 enum wireless_mode wirelessmode,
52 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw);
53 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw);
55 u32 rtl8723e_phy_query_rf_reg(struct ieee80211_hw *hw,
56 enum radio_path rfpath,
57 u32 regaddr, u32 bitmask)
59 struct rtl_priv *rtlpriv = rtl_priv(hw);
60 u32 original_value = 0, readback_value, bitshift;
61 struct rtl_phy *rtlphy = &rtlpriv->phy;
64 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
65 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
66 regaddr, rfpath, bitmask);
68 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
70 if (rtlphy->rf_mode != RF_OP_BY_FW) {
71 original_value = rtl8723_phy_rf_serial_read(hw,
75 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
76 readback_value = (original_value & bitmask) >> bitshift;
78 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
80 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
81 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
82 regaddr, rfpath, bitmask, original_value);
84 return readback_value;
87 void rtl8723e_phy_set_rf_reg(struct ieee80211_hw *hw,
88 enum radio_path rfpath,
89 u32 regaddr, u32 bitmask, u32 data)
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
92 struct rtl_phy *rtlphy = &rtlpriv->phy;
93 u32 original_value = 0, bitshift;
96 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
97 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
98 regaddr, bitmask, data, rfpath);
100 spin_lock_irqsave(&rtlpriv->locks.rf_lock, flags);
102 if (rtlphy->rf_mode != RF_OP_BY_FW) {
103 if (bitmask != RFREG_OFFSET_MASK) {
104 original_value = rtl8723_phy_rf_serial_read(hw,
107 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
109 ((original_value & (~bitmask)) |
113 rtl8723_phy_rf_serial_write(hw, rfpath, regaddr, data);
115 if (bitmask != RFREG_OFFSET_MASK) {
116 bitshift = rtl8723_phy_calculate_bit_shift(bitmask);
118 ((original_value & (~bitmask)) |
121 _rtl8723e_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
124 spin_unlock_irqrestore(&rtlpriv->locks.rf_lock, flags);
126 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
127 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
128 regaddr, bitmask, data, rfpath);
132 static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
133 enum radio_path rfpath, u32 offset,
136 RT_ASSERT(false, "deprecated!\n");
139 static void _rtl8723e_phy_bb_config_1t(struct ieee80211_hw *hw)
141 rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
142 rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
143 rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
144 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
145 rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
146 rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
147 rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
148 rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
149 rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
150 rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
153 bool rtl8723e_phy_mac_config(struct ieee80211_hw *hw)
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 bool rtstatus = _rtl8723e_phy_config_mac_with_headerfile(hw);
157 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
161 bool rtl8723e_phy_bb_config(struct ieee80211_hw *hw)
163 bool rtstatus = true;
164 struct rtl_priv *rtlpriv = rtl_priv(hw);
166 u8 b_reg_hwparafile = 1;
168 rtl8723_phy_init_bb_rf_reg_def(hw);
171 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_PLL_CTRL);
173 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, (tmpu1b|BIT(1)));
175 /* 2. 0x29[7:0] = 0xFF */
176 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL+1, 0xff);
179 /* 3. 0x02[1:0] = 2b'11 */
180 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
181 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
182 (tmpu1b | FEN_BB_GLB_RSTN | FEN_BBRSTB));
185 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+1);
186 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+1, (tmpu1b & (~BIT(6))));
188 /* 5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09. */
189 tmpu1b = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2);
190 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, (tmpu1b & (~BIT(4))));
192 /* 6. 0x1f[7:0] = 0x07 */
193 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x07);
195 if (b_reg_hwparafile == 1)
196 rtstatus = _rtl8723e_phy_bb8192c_config_parafile(hw);
200 bool rtl8723e_phy_rf_config(struct ieee80211_hw *hw)
202 return rtl8723e_phy_rf6052_config(hw);
205 static bool _rtl8723e_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
207 struct rtl_priv *rtlpriv = rtl_priv(hw);
208 struct rtl_phy *rtlphy = &rtlpriv->phy;
209 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
212 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "\n");
213 rtstatus = _rtl8723e_phy_config_bb_with_headerfile(hw,
214 BASEBAND_CONFIG_PHY_REG);
215 if (rtstatus != true) {
216 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
220 if (rtlphy->rf_type == RF_1T2R) {
221 _rtl8723e_phy_bb_config_1t(hw);
222 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
224 if (rtlefuse->autoload_failflag == false) {
225 rtlphy->pwrgroup_cnt = 0;
226 rtstatus = _rtl8723e_phy_config_bb_with_pgheaderfile(hw,
227 BASEBAND_CONFIG_PHY_REG);
229 if (rtstatus != true) {
230 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
234 _rtl8723e_phy_config_bb_with_headerfile(hw, BASEBAND_CONFIG_AGC_TAB);
235 if (rtstatus != true) {
236 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
239 rtlphy->cck_high_power = (bool) (rtl_get_bbreg(hw,
240 RFPGA0_XA_HSSIPARAMETER2,
246 static bool _rtl8723e_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
248 struct rtl_priv *rtlpriv = rtl_priv(hw);
253 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl723MACPHY_Array\n");
254 arraylength = RTL8723E_MACARRAYLENGTH;
255 ptrarray = RTL8723EMAC_ARRAY;
257 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
258 "Img:RTL8192CEMAC_2T_ARRAY\n");
259 for (i = 0; i < arraylength; i = i + 2)
260 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
264 static bool _rtl8723e_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
268 u32 *phy_regarray_table;
269 u32 *agctab_array_table;
270 u16 phy_reg_arraylen, agctab_arraylen;
271 struct rtl_priv *rtlpriv = rtl_priv(hw);
273 agctab_arraylen = RTL8723E_AGCTAB_1TARRAYLENGTH;
274 agctab_array_table = RTL8723EAGCTAB_1TARRAY;
275 phy_reg_arraylen = RTL8723E_PHY_REG_1TARRAY_LENGTH;
276 phy_regarray_table = RTL8723EPHY_REG_1TARRAY;
277 if (configtype == BASEBAND_CONFIG_PHY_REG) {
278 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
279 if (phy_regarray_table[i] == 0xfe)
281 else if (phy_regarray_table[i] == 0xfd)
283 else if (phy_regarray_table[i] == 0xfc)
285 else if (phy_regarray_table[i] == 0xfb)
287 else if (phy_regarray_table[i] == 0xfa)
289 else if (phy_regarray_table[i] == 0xf9)
291 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
292 phy_regarray_table[i + 1]);
294 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
295 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
296 phy_regarray_table[i],
297 phy_regarray_table[i + 1]);
299 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
300 for (i = 0; i < agctab_arraylen; i = i + 2) {
301 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
302 agctab_array_table[i + 1]);
304 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
305 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
306 agctab_array_table[i],
307 agctab_array_table[i + 1]);
313 static void store_pwrindex_diffrate_offset(struct ieee80211_hw *hw,
314 u32 regaddr, u32 bitmask,
317 struct rtl_priv *rtlpriv = rtl_priv(hw);
318 struct rtl_phy *rtlphy = &rtlpriv->phy;
320 if (regaddr == RTXAGC_A_RATE18_06) {
321 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
323 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
324 "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
325 rtlphy->pwrgroup_cnt,
326 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
329 if (regaddr == RTXAGC_A_RATE54_24) {
330 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
332 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
333 "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
334 rtlphy->pwrgroup_cnt,
335 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
338 if (regaddr == RTXAGC_A_CCK1_MCS32) {
339 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
341 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
342 "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
343 rtlphy->pwrgroup_cnt,
344 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
347 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
348 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
350 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
351 "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
352 rtlphy->pwrgroup_cnt,
353 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
356 if (regaddr == RTXAGC_A_MCS03_MCS00) {
357 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
359 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
360 "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
361 rtlphy->pwrgroup_cnt,
362 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
365 if (regaddr == RTXAGC_A_MCS07_MCS04) {
366 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
368 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
369 "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
370 rtlphy->pwrgroup_cnt,
371 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
374 if (regaddr == RTXAGC_A_MCS11_MCS08) {
375 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
377 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
378 "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
379 rtlphy->pwrgroup_cnt,
380 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
383 if (regaddr == RTXAGC_A_MCS15_MCS12) {
384 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
386 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
387 "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
388 rtlphy->pwrgroup_cnt,
389 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
392 if (regaddr == RTXAGC_B_RATE18_06) {
393 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
395 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
396 "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
397 rtlphy->pwrgroup_cnt,
398 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
401 if (regaddr == RTXAGC_B_RATE54_24) {
402 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
404 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
405 "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
406 rtlphy->pwrgroup_cnt,
407 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
410 if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
411 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
414 "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
415 rtlphy->pwrgroup_cnt,
416 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
419 if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
420 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
422 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
423 "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
424 rtlphy->pwrgroup_cnt,
425 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
428 if (regaddr == RTXAGC_B_MCS03_MCS00) {
429 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
431 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
432 "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
433 rtlphy->pwrgroup_cnt,
434 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
437 if (regaddr == RTXAGC_B_MCS07_MCS04) {
438 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
440 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
441 "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
442 rtlphy->pwrgroup_cnt,
443 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
446 if (regaddr == RTXAGC_B_MCS11_MCS08) {
447 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
449 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
450 "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
451 rtlphy->pwrgroup_cnt,
452 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
455 if (regaddr == RTXAGC_B_MCS15_MCS12) {
456 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
459 "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
460 rtlphy->pwrgroup_cnt,
461 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
464 rtlphy->pwrgroup_cnt++;
468 static bool _rtl8723e_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
471 struct rtl_priv *rtlpriv = rtl_priv(hw);
473 u32 *phy_regarray_table_pg;
474 u16 phy_regarray_pg_len;
476 phy_regarray_pg_len = RTL8723E_PHY_REG_ARRAY_PGLENGTH;
477 phy_regarray_table_pg = RTL8723EPHY_REG_ARRAY_PG;
479 if (configtype == BASEBAND_CONFIG_PHY_REG) {
480 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
481 if (phy_regarray_table_pg[i] == 0xfe)
483 else if (phy_regarray_table_pg[i] == 0xfd)
485 else if (phy_regarray_table_pg[i] == 0xfc)
487 else if (phy_regarray_table_pg[i] == 0xfb)
489 else if (phy_regarray_table_pg[i] == 0xfa)
491 else if (phy_regarray_table_pg[i] == 0xf9)
494 store_pwrindex_diffrate_offset(hw,
495 phy_regarray_table_pg[i],
496 phy_regarray_table_pg[i + 1],
497 phy_regarray_table_pg[i + 2]);
500 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
501 "configtype != BaseBand_Config_PHY_REG\n");
506 bool rtl8723e_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
507 enum radio_path rfpath)
510 bool rtstatus = true;
511 u32 *radioa_array_table;
512 u32 *radiob_array_table;
513 u16 radioa_arraylen, radiob_arraylen;
515 radioa_arraylen = RTL8723ERADIOA_1TARRAYLENGTH;
516 radioa_array_table = RTL8723E_RADIOA_1TARRAY;
517 radiob_arraylen = RTL8723E_RADIOB_1TARRAYLENGTH;
518 radiob_array_table = RTL8723E_RADIOB_1TARRAY;
524 for (i = 0; i < radioa_arraylen; i = i + 2) {
525 if (radioa_array_table[i] == 0xfe) {
527 } else if (radioa_array_table[i] == 0xfd) {
529 } else if (radioa_array_table[i] == 0xfc) {
531 } else if (radioa_array_table[i] == 0xfb) {
533 } else if (radioa_array_table[i] == 0xfa) {
535 } else if (radioa_array_table[i] == 0xf9) {
538 rtl_set_rfreg(hw, rfpath, radioa_array_table[i],
540 radioa_array_table[i + 1]);
553 void rtl8723e_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
555 struct rtl_priv *rtlpriv = rtl_priv(hw);
556 struct rtl_phy *rtlphy = &rtlpriv->phy;
558 rtlphy->default_initialgain[0] =
559 (u8) rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
560 rtlphy->default_initialgain[1] =
561 (u8) rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
562 rtlphy->default_initialgain[2] =
563 (u8) rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
564 rtlphy->default_initialgain[3] =
565 (u8) rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
567 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
568 "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
569 rtlphy->default_initialgain[0],
570 rtlphy->default_initialgain[1],
571 rtlphy->default_initialgain[2],
572 rtlphy->default_initialgain[3]);
574 rtlphy->framesync = (u8) rtl_get_bbreg(hw,
575 ROFDM0_RXDETECTOR3, MASKBYTE0);
576 rtlphy->framesync_c34 = rtl_get_bbreg(hw,
577 ROFDM0_RXDETECTOR2, MASKDWORD);
579 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
580 "Default framesync (0x%x) = 0x%x\n",
581 ROFDM0_RXDETECTOR3, rtlphy->framesync);
584 void rtl8723e_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
586 struct rtl_priv *rtlpriv = rtl_priv(hw);
587 struct rtl_phy *rtlphy = &rtlpriv->phy;
588 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
592 txpwr_level = rtlphy->cur_cck_txpwridx;
593 txpwr_dbm = rtl8723_phy_txpwr_idx_to_dbm(hw,
594 WIRELESS_MODE_B, txpwr_level);
595 txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
596 rtlefuse->legacy_ht_txpowerdiff;
597 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
599 txpwr_level) > txpwr_dbm)
601 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
603 txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
604 if (rtl8723_phy_txpwr_idx_to_dbm(hw,
606 txpwr_level) > txpwr_dbm)
608 rtl8723_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
610 *powerlevel = txpwr_dbm;
613 static void _rtl8723e_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
614 u8 *cckpowerlevel, u8 *ofdmpowerlevel)
616 struct rtl_priv *rtlpriv = rtl_priv(hw);
617 struct rtl_phy *rtlphy = &rtlpriv->phy;
618 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
619 u8 index = (channel - 1);
621 cckpowerlevel[RF90_PATH_A] =
622 rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
623 cckpowerlevel[RF90_PATH_B] =
624 rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
625 if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
626 ofdmpowerlevel[RF90_PATH_A] =
627 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
628 ofdmpowerlevel[RF90_PATH_B] =
629 rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
630 } else if (get_rf_type(rtlphy) == RF_2T2R) {
631 ofdmpowerlevel[RF90_PATH_A] =
632 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
633 ofdmpowerlevel[RF90_PATH_B] =
634 rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
638 static void _rtl8723e_ccxpower_index_check(struct ieee80211_hw *hw,
639 u8 channel, u8 *cckpowerlevel,
642 struct rtl_priv *rtlpriv = rtl_priv(hw);
643 struct rtl_phy *rtlphy = &rtlpriv->phy;
645 rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
646 rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
650 void rtl8723e_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
652 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
653 u8 cckpowerlevel[2], ofdmpowerlevel[2];
655 if (rtlefuse->txpwr_fromeprom == false)
657 _rtl8723e_get_txpower_index(hw, channel,
658 &cckpowerlevel[0], &ofdmpowerlevel[0]);
659 _rtl8723e_ccxpower_index_check(hw,
660 channel, &cckpowerlevel[0],
662 rtl8723e_phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
663 rtl8723e_phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0], channel);
666 bool rtl8723e_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
668 struct rtl_priv *rtlpriv = rtl_priv(hw);
669 struct rtl_phy *rtlphy = &rtlpriv->phy;
670 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
673 u8 ccktxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
676 u8 ofdmtxpwridx = _rtl8723e_phy_dbm_to_txpwr_idx(hw,
679 if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
680 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
683 RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
684 "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
685 power_indbm, ccktxpwridx, ofdmtxpwridx);
686 for (idx = 0; idx < 14; idx++) {
687 for (rf_path = 0; rf_path < 2; rf_path++) {
688 rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
689 rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
691 rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
695 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
699 static u8 _rtl8723e_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
700 enum wireless_mode wirelessmode,
706 switch (wirelessmode) {
707 case WIRELESS_MODE_B:
710 case WIRELESS_MODE_G:
711 case WIRELESS_MODE_N_24G:
719 if ((power_indbm - offset) > 0)
720 txpwridx = (u8)((power_indbm - offset) * 2);
724 if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
725 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
730 void rtl8723e_phy_scan_operation_backup(struct ieee80211_hw *hw, u8 operation)
732 struct rtl_priv *rtlpriv = rtl_priv(hw);
733 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
736 if (!is_hal_stop(rtlhal)) {
738 case SCAN_OPT_BACKUP_BAND0:
739 iotype = IO_CMD_PAUSE_BAND0_DM_BY_SCAN;
740 rtlpriv->cfg->ops->set_hw_reg(hw,
745 case SCAN_OPT_RESTORE:
746 iotype = IO_CMD_RESUME_DM_BY_SCAN;
747 rtlpriv->cfg->ops->set_hw_reg(hw,
752 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
753 "Unknown Scan Backup operation.\n");
759 void rtl8723e_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
761 struct rtl_priv *rtlpriv = rtl_priv(hw);
762 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
763 struct rtl_phy *rtlphy = &rtlpriv->phy;
764 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
768 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
769 "Switch to %s bandwidth\n",
770 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
773 if (is_hal_stop(rtlhal)) {
774 rtlphy->set_bwmode_inprogress = false;
778 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
779 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
781 switch (rtlphy->current_chan_bw) {
782 case HT_CHANNEL_WIDTH_20:
783 reg_bw_opmode |= BW_OPMODE_20MHZ;
784 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
786 case HT_CHANNEL_WIDTH_20_40:
787 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
788 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
790 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
791 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
794 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
795 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
799 switch (rtlphy->current_chan_bw) {
800 case HT_CHANNEL_WIDTH_20:
801 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
802 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
803 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
805 case HT_CHANNEL_WIDTH_20_40:
806 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
807 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
809 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
810 (mac->cur_40_prime_sc >> 1));
811 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
812 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
814 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
815 (mac->cur_40_prime_sc ==
816 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
819 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
820 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
823 rtl8723e_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
824 rtlphy->set_bwmode_inprogress = false;
825 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
828 void rtl8723e_phy_set_bw_mode(struct ieee80211_hw *hw,
829 enum nl80211_channel_type ch_type)
831 struct rtl_priv *rtlpriv = rtl_priv(hw);
832 struct rtl_phy *rtlphy = &rtlpriv->phy;
833 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
834 u8 tmp_bw = rtlphy->current_chan_bw;
836 if (rtlphy->set_bwmode_inprogress)
838 rtlphy->set_bwmode_inprogress = true;
839 if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
840 rtl8723e_phy_set_bw_mode_callback(hw);
842 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
843 "false driver sleep or unload\n");
844 rtlphy->set_bwmode_inprogress = false;
845 rtlphy->current_chan_bw = tmp_bw;
849 void rtl8723e_phy_sw_chnl_callback(struct ieee80211_hw *hw)
851 struct rtl_priv *rtlpriv = rtl_priv(hw);
852 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
853 struct rtl_phy *rtlphy = &rtlpriv->phy;
856 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
857 "switch to channel%d\n", rtlphy->current_channel);
858 if (is_hal_stop(rtlhal))
861 if (!rtlphy->sw_chnl_inprogress)
863 if (!_rtl8723e_phy_sw_chnl_step_by_step
864 (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
865 &rtlphy->sw_chnl_step, &delay)) {
871 rtlphy->sw_chnl_inprogress = false;
875 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
878 u8 rtl8723e_phy_sw_chnl(struct ieee80211_hw *hw)
880 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 struct rtl_phy *rtlphy = &rtlpriv->phy;
882 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
884 if (rtlphy->sw_chnl_inprogress)
886 if (rtlphy->set_bwmode_inprogress)
888 RT_ASSERT((rtlphy->current_channel <= 14),
889 "WIRELESS_MODE_G but channel>14");
890 rtlphy->sw_chnl_inprogress = true;
891 rtlphy->sw_chnl_stage = 0;
892 rtlphy->sw_chnl_step = 0;
893 if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
894 rtl8723e_phy_sw_chnl_callback(hw);
895 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
896 "sw_chnl_inprogress false schedule workitem\n");
897 rtlphy->sw_chnl_inprogress = false;
899 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
900 "sw_chnl_inprogress false driver sleep or unload\n");
901 rtlphy->sw_chnl_inprogress = false;
906 static void _rtl8723e_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
908 struct rtl_priv *rtlpriv = rtl_priv(hw);
909 struct rtl_phy *rtlphy = &rtlpriv->phy;
910 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
912 if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
913 if (channel == 6 && rtlphy->current_chan_bw ==
915 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
918 u32 backuprf0x1a = (u32)rtl_get_rfreg(hw,
919 RF90_PATH_A, RF_RX_G1,
921 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
922 MASKDWORD, backuprf0x1a);
927 static bool _rtl8723e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
928 u8 channel, u8 *stage, u8 *step,
931 struct rtl_priv *rtlpriv = rtl_priv(hw);
932 struct rtl_phy *rtlphy = &rtlpriv->phy;
933 struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
935 struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
936 u32 postcommoncmdcnt;
937 struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
939 struct swchnlcmd *currentcmd = NULL;
941 u8 num_total_rfpath = rtlphy->num_total_rfpath;
944 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
946 CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
947 rtl8723_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
948 MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
950 postcommoncmdcnt = 0;
952 rtl8723_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
953 MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
957 RT_ASSERT((channel >= 1 && channel <= 14),
958 "illegal channel for Zebra: %d\n", channel);
960 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
961 MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
962 RF_CHNLBW, channel, 10);
964 rtl8723_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
965 MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
971 currentcmd = &precommoncmd[*step];
974 currentcmd = &rfdependcmd[*step];
977 currentcmd = &postcommoncmd[*step];
980 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
981 "Invalid 'stage' = %d, Check it!\n", *stage);
985 if (currentcmd->cmdid == CMDID_END) {
995 switch (currentcmd->cmdid) {
996 case CMDID_SET_TXPOWEROWER_LEVEL:
997 rtl8723e_phy_set_txpower_level(hw, channel);
999 case CMDID_WRITEPORT_ULONG:
1000 rtl_write_dword(rtlpriv, currentcmd->para1,
1003 case CMDID_WRITEPORT_USHORT:
1004 rtl_write_word(rtlpriv, currentcmd->para1,
1005 (u16) currentcmd->para2);
1007 case CMDID_WRITEPORT_UCHAR:
1008 rtl_write_byte(rtlpriv, currentcmd->para1,
1009 (u8) currentcmd->para2);
1011 case CMDID_RF_WRITEREG:
1012 for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
1013 rtlphy->rfreg_chnlval[rfpath] =
1014 ((rtlphy->rfreg_chnlval[rfpath] &
1015 0xfffffc00) | currentcmd->para2);
1017 rtl_set_rfreg(hw, (enum radio_path)rfpath,
1020 rtlphy->rfreg_chnlval[rfpath]);
1022 _rtl8723e_phy_sw_rf_seting(hw, channel);
1025 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1026 "switch case %#x not processed\n",
1034 (*delay) = currentcmd->msdelay;
1039 static u8 _rtl8723e_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
1041 u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
1044 rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
1045 rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
1046 rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
1047 rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
1048 config_pathb ? 0x28160202 : 0x28160502);
1051 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
1052 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
1053 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
1054 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
1057 rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
1058 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
1059 rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
1061 mdelay(IQK_DELAY_TIME);
1063 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1064 reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
1065 reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
1066 reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
1068 if (!(reg_eac & BIT(28)) &&
1069 (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
1070 (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
1075 if (!(reg_eac & BIT(27)) &&
1076 (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
1077 (((reg_eac & 0x03FF0000) >> 16) != 0x36))
1082 static u8 _rtl8723e_phy_path_b_iqk(struct ieee80211_hw *hw)
1084 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1087 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
1088 rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
1089 mdelay(IQK_DELAY_TIME);
1090 reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
1091 reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
1092 reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
1093 reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
1094 reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
1096 if (!(reg_eac & BIT(31)) &&
1097 (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
1098 (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
1102 if (!(reg_eac & BIT(30)) &&
1103 (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
1104 (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
1109 static bool _rtl8723e_phy_simularity_compare(struct ieee80211_hw *hw,
1110 long result[][8], u8 c1, u8 c2)
1112 u32 i, j, diff, simularity_bitmap, bound;
1114 u8 final_candidate[2] = { 0xFF, 0xFF };
1115 bool bresult = true;
1119 simularity_bitmap = 0;
1121 for (i = 0; i < bound; i++) {
1122 diff = (result[c1][i] > result[c2][i]) ?
1123 (result[c1][i] - result[c2][i]) :
1124 (result[c2][i] - result[c1][i]);
1126 if (diff > MAX_TOLERANCE) {
1127 if ((i == 2 || i == 6) && !simularity_bitmap) {
1128 if (result[c1][i] + result[c1][i + 1] == 0)
1129 final_candidate[(i / 4)] = c2;
1130 else if (result[c2][i] + result[c2][i + 1] == 0)
1131 final_candidate[(i / 4)] = c1;
1133 simularity_bitmap = simularity_bitmap |
1137 simularity_bitmap | (1 << i);
1141 if (simularity_bitmap == 0) {
1142 for (i = 0; i < (bound / 4); i++) {
1143 if (final_candidate[i] != 0xFF) {
1144 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1146 result[final_candidate[i]][j];
1151 } else if (!(simularity_bitmap & 0x0F)) {
1152 for (i = 0; i < 4; i++)
1153 result[3][i] = result[c1][i];
1161 static void _rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw,
1162 long result[][8], u8 t, bool is2t)
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 struct rtl_phy *rtlphy = &rtlpriv->phy;
1167 u8 patha_ok, pathb_ok;
1168 u32 adda_reg[IQK_ADDA_REG_NUM] = {
1169 0x85c, 0xe6c, 0xe70, 0xe74,
1170 0xe78, 0xe7c, 0xe80, 0xe84,
1171 0xe88, 0xe8c, 0xed0, 0xed4,
1172 0xed8, 0xedc, 0xee0, 0xeec
1175 u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1176 0x522, 0x550, 0x551, 0x040
1179 const u32 retrycount = 2;
1184 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1186 rtl8723_save_adda_registers(hw, adda_reg,
1187 rtlphy->adda_backup, 16);
1188 rtl8723_phy_save_mac_registers(hw, iqk_mac_reg,
1189 rtlphy->iqk_mac_backup);
1191 rtl8723_phy_path_adda_on(hw, adda_reg, true, is2t);
1193 rtlphy->rfpi_enable = (u8) rtl_get_bbreg(hw,
1194 RFPGA0_XA_HSSIPARAMETER1,
1198 if (!rtlphy->rfpi_enable)
1199 rtl8723_phy_pi_mode_switch(hw, true);
1201 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1202 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1203 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1205 rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1206 rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1207 rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1209 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1210 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1212 rtl8723_phy_mac_setting_calibration(hw, iqk_mac_reg,
1213 rtlphy->iqk_mac_backup);
1214 rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1216 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1217 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1218 rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1219 rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1220 for (i = 0; i < retrycount; i++) {
1221 patha_ok = _rtl8723e_phy_path_a_iqk(hw, is2t);
1222 if (patha_ok == 0x03) {
1223 result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1225 result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1227 result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1229 result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1232 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1234 result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1235 MASKDWORD) & 0x3FF0000) >>
1238 (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1243 rtl8723_phy_path_a_standby(hw);
1244 rtl8723_phy_path_adda_on(hw, adda_reg, false, is2t);
1245 for (i = 0; i < retrycount; i++) {
1246 pathb_ok = _rtl8723e_phy_path_b_iqk(hw);
1247 if (pathb_ok == 0x03) {
1248 result[t][4] = (rtl_get_bbreg(hw,
1253 (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1256 (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1259 (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1262 } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1263 result[t][4] = (rtl_get_bbreg(hw,
1268 result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1272 rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1273 rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1274 rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1275 rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1276 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1278 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1280 if (!rtlphy->rfpi_enable)
1281 rtl8723_phy_pi_mode_switch(hw, false);
1282 rtl8723_phy_reload_adda_registers(hw, adda_reg,
1283 rtlphy->adda_backup, 16);
1284 rtl8723_phy_reload_mac_registers(hw, iqk_mac_reg,
1285 rtlphy->iqk_mac_backup);
1289 static void _rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
1292 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
1293 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
1297 if ((tmpreg & 0x70) != 0)
1298 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
1300 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1302 if ((tmpreg & 0x70) != 0) {
1303 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
1306 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
1309 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
1310 (rf_a_mode & 0x8FFFF) | 0x10000);
1313 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1314 (rf_b_mode & 0x8FFFF) | 0x10000);
1316 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
1318 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
1322 if ((tmpreg & 0x70) != 0) {
1323 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
1324 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
1327 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
1330 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1334 static void _rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1335 bool bmain, bool is2t)
1337 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1339 if (is_hal_stop(rtlhal)) {
1340 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1341 rtl_set_bbreg(hw, RFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1345 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1346 BIT(5) | BIT(6), 0x1);
1348 rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1349 BIT(5) | BIT(6), 0x2);
1352 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1354 rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1360 #undef IQK_ADDA_REG_NUM
1361 #undef IQK_DELAY_TIME
1363 void rtl8723e_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1365 struct rtl_priv *rtlpriv = rtl_priv(hw);
1366 struct rtl_phy *rtlphy = &rtlpriv->phy;
1369 u8 i, final_candidate;
1370 bool b_patha_ok, b_pathb_ok;
1371 long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1372 reg_ecc, reg_tmp = 0;
1373 bool is12simular, is13simular, is23simular;
1374 u32 iqk_bb_reg[10] = {
1375 ROFDM0_XARXIQIMBALANCE,
1376 ROFDM0_XBRXIQIMBALANCE,
1377 ROFDM0_ECCATHRESHOLD,
1378 ROFDM0_AGCRSSITABLE,
1379 ROFDM0_XATXIQIMBALANCE,
1380 ROFDM0_XBTXIQIMBALANCE,
1381 ROFDM0_XCTXIQIMBALANCE,
1388 rtl8723_phy_reload_adda_registers(hw,
1390 rtlphy->iqk_bb_backup, 10);
1393 for (i = 0; i < 8; i++) {
1399 final_candidate = 0xff;
1402 is12simular = false;
1403 is23simular = false;
1404 is13simular = false;
1405 for (i = 0; i < 3; i++) {
1406 _rtl8723e_phy_iq_calibrate(hw, result, i, false);
1409 _rtl8723e_phy_simularity_compare(hw, result, 0, 1);
1411 final_candidate = 0;
1417 _rtl8723e_phy_simularity_compare(hw, result, 0, 2);
1419 final_candidate = 0;
1423 _rtl8723e_phy_simularity_compare(hw, result, 1, 2);
1425 final_candidate = 1;
1427 for (i = 0; i < 8; i++)
1428 reg_tmp += result[3][i];
1431 final_candidate = 3;
1433 final_candidate = 0xFF;
1437 for (i = 0; i < 4; i++) {
1438 reg_e94 = result[i][0];
1439 reg_e9c = result[i][1];
1440 reg_ea4 = result[i][2];
1441 reg_eac = result[i][3];
1442 reg_eb4 = result[i][4];
1443 reg_ebc = result[i][5];
1444 reg_ec4 = result[i][6];
1445 reg_ecc = result[i][7];
1447 if (final_candidate != 0xff) {
1448 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1449 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1450 reg_ea4 = result[final_candidate][2];
1451 reg_eac = result[final_candidate][3];
1452 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1453 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1454 reg_ec4 = result[final_candidate][6];
1455 reg_ecc = result[final_candidate][7];
1459 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1460 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1463 rtl8723_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1466 rtl8723_save_adda_registers(hw, iqk_bb_reg,
1467 rtlphy->iqk_bb_backup, 10);
1470 void rtl8723e_phy_lc_calibrate(struct ieee80211_hw *hw)
1472 _rtl8723e_phy_lc_calibrate(hw, false);
1475 void rtl8723e_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1477 _rtl8723e_phy_set_rfpath_switch(hw, bmain, false);
1480 bool rtl8723e_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1482 struct rtl_priv *rtlpriv = rtl_priv(hw);
1483 struct rtl_phy *rtlphy = &rtlpriv->phy;
1484 bool postprocessing = false;
1486 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1487 "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1488 iotype, rtlphy->set_io_inprogress);
1491 case IO_CMD_RESUME_DM_BY_SCAN:
1492 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1493 "[IO CMD] Resume DM after scan.\n");
1494 postprocessing = true;
1496 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1497 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1498 "[IO CMD] Pause DM before scan.\n");
1499 postprocessing = true;
1502 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1503 "switch case %#x not processed\n", iotype);
1507 if (postprocessing && !rtlphy->set_io_inprogress) {
1508 rtlphy->set_io_inprogress = true;
1509 rtlphy->current_io_type = iotype;
1513 rtl8723e_phy_set_io(hw);
1514 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1518 static void rtl8723e_phy_set_io(struct ieee80211_hw *hw)
1520 struct rtl_priv *rtlpriv = rtl_priv(hw);
1521 struct rtl_phy *rtlphy = &rtlpriv->phy;
1522 struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1524 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1525 "--->Cmd(%#x), set_io_inprogress(%d)\n",
1526 rtlphy->current_io_type, rtlphy->set_io_inprogress);
1527 switch (rtlphy->current_io_type) {
1528 case IO_CMD_RESUME_DM_BY_SCAN:
1529 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1530 rtl8723e_dm_write_dig(hw);
1531 rtl8723e_phy_set_txpower_level(hw, rtlphy->current_channel);
1533 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1534 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1535 dm_digtable->cur_igvalue = 0x17;
1536 rtl8723e_dm_write_dig(hw);
1539 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1540 "switch case %#x not processed\n",
1541 rtlphy->current_io_type);
1544 rtlphy->set_io_inprogress = false;
1545 RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1546 "(%#x)\n", rtlphy->current_io_type);
1549 static void rtl8723e_phy_set_rf_on(struct ieee80211_hw *hw)
1551 struct rtl_priv *rtlpriv = rtl_priv(hw);
1553 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1554 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1555 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1556 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1557 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1558 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1561 static void _rtl8723e_phy_set_rf_sleep(struct ieee80211_hw *hw)
1565 struct rtl_priv *rtlpriv = rtl_priv(hw);
1567 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1568 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1569 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1570 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1571 while (u4b_tmp != 0 && delay > 0) {
1572 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1573 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1574 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1575 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1579 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1580 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1581 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1582 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1583 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1584 "Switch RF timeout !!!.\n");
1587 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1588 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1591 static bool _rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1592 enum rf_pwrstate rfpwr_state)
1594 struct rtl_priv *rtlpriv = rtl_priv(hw);
1595 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1596 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1597 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1598 bool bresult = true;
1600 struct rtl8192_tx_ring *ring = NULL;
1602 switch (rfpwr_state) {
1604 if ((ppsc->rfpwr_state == ERFOFF) &&
1605 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
1607 u32 initializecount = 0;
1611 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1612 "IPS Set eRf nic enable\n");
1613 rtstatus = rtl_ps_enable_nic(hw);
1614 } while (!rtstatus && (initializecount < 10));
1615 RT_CLEAR_PS_LEVEL(ppsc,
1616 RT_RF_OFF_LEVL_HALT_NIC);
1618 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1619 "Set ERFON sleeped:%d ms\n",
1620 jiffies_to_msecs(jiffies -
1622 last_sleep_jiffies));
1623 ppsc->last_awake_jiffies = jiffies;
1624 rtl8723e_phy_set_rf_on(hw);
1626 if (mac->link_state == MAC80211_LINKED) {
1627 rtlpriv->cfg->ops->led_control(hw,
1630 rtlpriv->cfg->ops->led_control(hw,
1635 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
1636 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1637 "IPS Set eRf nic disable\n");
1638 rtl_ps_disable_nic(hw);
1639 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1641 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
1642 rtlpriv->cfg->ops->led_control(hw,
1645 rtlpriv->cfg->ops->led_control(hw,
1651 if (ppsc->rfpwr_state == ERFOFF)
1653 for (queue_id = 0, i = 0;
1654 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
1655 ring = &pcipriv->dev.tx_ring[queue_id];
1656 if (queue_id == BEACON_QUEUE ||
1657 skb_queue_len(&ring->queue) == 0) {
1661 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1662 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
1664 skb_queue_len(&ring->queue));
1669 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
1670 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1671 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
1672 MAX_DOZE_WAITING_TIMES_9x,
1674 skb_queue_len(&ring->queue));
1678 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
1679 "Set ERFSLEEP awaked:%d ms\n",
1680 jiffies_to_msecs(jiffies -
1681 ppsc->last_awake_jiffies));
1682 ppsc->last_sleep_jiffies = jiffies;
1683 _rtl8723e_phy_set_rf_sleep(hw);
1686 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1687 "switch case %#x not processed\n", rfpwr_state);
1692 ppsc->rfpwr_state = rfpwr_state;
1696 bool rtl8723e_phy_set_rf_power_state(struct ieee80211_hw *hw,
1697 enum rf_pwrstate rfpwr_state)
1699 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1701 bool bresult = false;
1703 if (rfpwr_state == ppsc->rfpwr_state)
1705 bresult = _rtl8723e_phy_set_rf_power_state(hw, rfpwr_state);