1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL8723E_DM_H__
27 #define __RTL8723E_DM_H__
29 #define HAL_DM_DIG_DISABLE BIT(0)
30 #define HAL_DM_HIPWR_DISABLE BIT(1)
32 #define OFDM_TABLE_LENGTH 37
33 #define CCK_TABLE_LENGTH 33
35 #define OFDM_TABLE_SIZE 37
36 #define CCK_TABLE_SIZE 33
38 #define BW_AUTO_SWITCH_HIGH_LOW 25
39 #define BW_AUTO_SWITCH_LOW_HIGH 30
41 #define DM_DIG_FA_UPPER 0x32
42 #define DM_DIG_FA_LOWER 0x20
43 #define DM_DIG_FA_TH0 0x20
44 #define DM_DIG_FA_TH1 0x100
45 #define DM_DIG_FA_TH2 0x200
47 #define RXPATHSELECTION_SS_TH_LOW 30
48 #define RXPATHSELECTION_DIFF_TH 18
50 #define DM_RATR_STA_INIT 0
51 #define DM_RATR_STA_HIGH 1
52 #define DM_RATR_STA_MIDDLE 2
53 #define DM_RATR_STA_LOW 3
55 #define CTS2SELF_THVAL 30
60 #define TXHIGHPWRLEVEL_NORMAL 0
61 #define TXHIGHPWRLEVEL_LEVEL1 1
62 #define TXHIGHPWRLEVEL_LEVEL2 2
63 #define TXHIGHPWRLEVEL_BT1 3
64 #define TXHIGHPWRLEVEL_BT2 4
66 #define DM_TYPE_BYFW 0
67 #define DM_TYPE_BYDRIVER 1
69 #define TX_POWER_NEAR_FIELD_THRESH_LVL2 74
70 #define TX_POWER_NEAR_FIELD_THRESH_LVL1 67
77 long trying_threshold;
83 enum tag_dynamic_init_gain_operation_type_definition {
84 DIG_TYPE_THRESH_HIGH = 0,
85 DIG_TYPE_THRESH_LOW = 1,
87 DIG_TYPE_RX_GAIN_MIN = 3,
88 DIG_TYPE_RX_GAIN_MAX = 4,
106 enum dm_sw_ant_switch_e {
112 #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
113 #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
114 #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
115 #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
116 #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
117 #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
119 (((struct rtl_priv *)(_priv))->mac80211.opmode == \
120 NL80211_IFTYPE_ADHOC) ? \
121 (((struct rtl_priv *)(_priv))->dm.entry_min_undec_sm_pwdb) : \
122 (((struct rtl_priv *)(_priv))->dm.undec_sm_pwdb) \
125 void rtl8723e_dm_init(struct ieee80211_hw *hw);
126 void rtl8723e_dm_watchdog(struct ieee80211_hw *hw);
127 void rtl8723e_dm_write_dig(struct ieee80211_hw *hw);
128 void rtl8723e_dm_check_txpower_tracking(struct ieee80211_hw *hw);
129 void rtl8723e_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
130 void rtl8723e_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
131 void rtl8723e_dm_bt_coexist(struct ieee80211_hw *hw);