drivers/net/wireless/realtek/rtlwifi/rtl8192se/sw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../core.h"
  28 #include "../base.h"
  29 #include "../pci.h"
  30 #include "reg.h"
  31 #include "def.h"
  32 #include "phy.h"
  33 #include "dm.h"
  34 #include "fw.h"
  35 #include "hw.h"
  36 #include "sw.h"
  37 #include "trx.h"
  38 #include "led.h"
  39
  40 #include <linux/module.h>
  41
  42 static void rtl92s_init_aspm_vars(struct ieee80211_hw *hw)
  43 {
  44         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  45
  46         /*close ASPM for AMD defaultly */
  47         rtlpci->const_amdpci_aspm = 0;
  48
  49         /* ASPM PS mode.
  50          * 0 - Disable ASPM,
  51          * 1 - Enable ASPM without Clock Req,
  52          * 2 - Enable ASPM with Clock Req,
  53          * 3 - Alwyas Enable ASPM with Clock Req,
  54          * 4 - Always Enable ASPM without Clock Req.
  55          * set defult to RTL8192CE:3 RTL8192E:2
  56          * */
  57         rtlpci->const_pci_aspm = 2;
  58
  59         /*Setting for PCI-E device */
  60         rtlpci->const_devicepci_aspm_setting = 0x03;
  61
  62         /*Setting for PCI-E bridge */
  63         rtlpci->const_hostpci_aspm_setting = 0x02;
  64
  65         /* In Hw/Sw Radio Off situation.
  66          * 0 - Default,
  67          * 1 - From ASPM setting without low Mac Pwr,
  68          * 2 - From ASPM setting with low Mac Pwr,
  69          * 3 - Bus D3
  70          * set default to RTL8192CE:0 RTL8192SE:2
  71          */
  72         rtlpci->const_hwsw_rfoff_d3 = 2;
  73
  74         /* This setting works for those device with
  75          * backdoor ASPM setting such as EPHY setting.
  76          * 0 - Not support ASPM,
  77          * 1 - Support ASPM,
  78          * 2 - According to chipset.
  79          */
  80         rtlpci->const_support_pciaspm = 2;
  81 }
  82
  83 static void rtl92se_fw_cb(const struct firmware *firmware, void *context)
  84 {
  85         struct ieee80211_hw *hw = context;
  86         struct rtl_priv *rtlpriv = rtl_priv(hw);
  87         struct rt_firmware *pfirmware = NULL;
  88         char *fw_name = "/*(DEBLOBBED)*/";
  89
  90         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
  91                          "Firmware callback routine entered!\n");
  92         complete(&rtlpriv->firmware_loading_complete);
  93         if (!firmware) {
  94                 pr_err("Firmware %s not available\n", fw_name);
  95                 rtlpriv->max_fw_size = 0;
  96                 return;
  97         }
  98         if (firmware->size > rtlpriv->max_fw_size) {
  99                 pr_err("Firmware is too big!\n");
 100                 rtlpriv->max_fw_size = 0;
 101                 release_firmware(firmware);
 102                 return;
 103         }
 104         pfirmware = (struct rt_firmware *)rtlpriv->rtlhal.pfirmware;
 105         memcpy(pfirmware->sz_fw_tmpbuffer, firmware->data, firmware->size);
 106         pfirmware->sz_fw_tmpbufferlen = firmware->size;
 107         release_firmware(firmware);
 108 }
 109
 110 static int rtl92s_init_sw_vars(struct ieee80211_hw *hw)
 111 {
 112         struct rtl_priv *rtlpriv = rtl_priv(hw);
 113         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 114         int err = 0;
 115         u16 earlyrxthreshold = 7;
 116         char *fw_name = "/*(DEBLOBBED)*/";
 117
 118         rtlpriv->dm.dm_initialgain_enable = true;
 119         rtlpriv->dm.dm_flag = 0;
 120         rtlpriv->dm.disable_framebursting = false;
 121         rtlpriv->dm.thermalvalue = 0;
 122         rtlpriv->dm.useramask = true;
 123
 124         /* compatible 5G band 91se just 2.4G band & smsp */
 125         rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
 126         rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
 127         rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
 128
 129         rtlpci->transmit_config = 0;
 130
 131         rtlpci->receive_config =
 132                         RCR_APPFCS |
 133                         RCR_APWRMGT |
 134                         /*RCR_ADD3 |*/
 135                         RCR_AMF |
 136                         RCR_ADF |
 137                         RCR_APP_MIC |
 138                         RCR_APP_ICV |
 139                         RCR_AICV |
 140                         /* Accept ICV error, CRC32 Error */
 141                         RCR_ACRC32 |
 142                         RCR_AB |
 143                         /* Accept Broadcast, Multicast */
 144                         RCR_AM  |
 145                         /* Accept Physical match */
 146                         RCR_APM |
 147                         /* Accept Destination Address packets */
 148                         /*RCR_AAP |*/
 149                         RCR_APP_PHYST_STAFF |
 150                         /* Accept PHY status */
 151                         RCR_APP_PHYST_RXFF |
 152                         (earlyrxthreshold << RCR_FIFO_OFFSET);
 153
 154         rtlpci->irq_mask[0] = (u32)
 155                         (IMR_ROK |
 156                         IMR_VODOK |
 157                         IMR_VIDOK |
 158                         IMR_BEDOK |
 159                         IMR_BKDOK |
 160                         IMR_HCCADOK |
 161                         IMR_MGNTDOK |
 162                         IMR_COMDOK |
 163                         IMR_HIGHDOK |
 164                         IMR_BDOK |
 165                         IMR_RXCMDOK |
 166                         /*IMR_TIMEOUT0 |*/
 167                         IMR_RDU |
 168                         IMR_RXFOVW      |
 169                         IMR_BCNINT
 170                         /*| IMR_TXFOVW*/
 171                         /*| IMR_TBDOK |
 172                         IMR_TBDER*/);
 173
 174         rtlpci->irq_mask[1] = (u32) 0;
 175
 176         rtlpci->shortretry_limit = 0x30;
 177         rtlpci->longretry_limit = 0x30;
 178
 179         rtlpci->first_init = true;
 180
 181         /* for LPS & IPS */
 182         rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
 183         rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
 184         rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
 185         rtlpriv->cfg->mod_params->sw_crypto =
 186                 rtlpriv->cfg->mod_params->sw_crypto;
 187         if (!rtlpriv->psc.inactiveps)
 188                 pr_info("Power Save off (module option)\n");
 189         if (!rtlpriv->psc.fwctrl_lps)
 190                 pr_info("FW Power Save off (module option)\n");
 191         rtlpriv->psc.reg_fwctrl_lps = 3;
 192         rtlpriv->psc.reg_max_lps_awakeintvl = 5;
 193         /* for ASPM, you can close aspm through
 194          * set const_support_pciaspm = 0 */
 195         rtl92s_init_aspm_vars(hw);
 196
 197         if (rtlpriv->psc.reg_fwctrl_lps == 1)
 198                 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
 199         else if (rtlpriv->psc.reg_fwctrl_lps == 2)
 200                 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
 201         else if (rtlpriv->psc.reg_fwctrl_lps == 3)
 202                 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
 203
 204         /* for firmware buf */
 205         rtlpriv->rtlhal.pfirmware = vzalloc(sizeof(struct rt_firmware));
 206         if (!rtlpriv->rtlhal.pfirmware)
 207                 return 1;
 208
 209         rtlpriv->max_fw_size = RTL8190_MAX_FIRMWARE_CODE_SIZE*2 +
 210                                sizeof(struct fw_hdr);
 211         pr_info("Driver for Realtek RTL8192SE/RTL8191SE\n"
 212                 "Loading firmware %s\n", fw_name);
 213         /* request fw */
 214         err = reject_firmware_nowait(THIS_MODULE, 1, fw_name,
 215                                       rtlpriv->io.dev, GFP_KERNEL, hw,
 216                                       rtl92se_fw_cb);
 217         if (err) {
 218                 pr_err("Failed to request firmware!\n");
 219                 vfree(rtlpriv->rtlhal.pfirmware);
 220                 rtlpriv->rtlhal.pfirmware = NULL;
 221                 return 1;
 222         }
 223
 224         return err;
 225 }
 226
 227 static void rtl92s_deinit_sw_vars(struct ieee80211_hw *hw)
 228 {
 229         struct rtl_priv *rtlpriv = rtl_priv(hw);
 230
 231         if (rtlpriv->rtlhal.pfirmware) {
 232                 vfree(rtlpriv->rtlhal.pfirmware);
 233                 rtlpriv->rtlhal.pfirmware = NULL;
 234         }
 235 }
 236
 237 static bool rtl92se_is_tx_desc_closed(struct ieee80211_hw *hw, u8 hw_queue,
 238                                       u16 index)
 239 {
 240         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 241         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
 242         u8 *entry = (u8 *)(&ring->desc[ring->idx]);
 243         u8 own = (u8)rtl92se_get_desc(entry, true, HW_DESC_OWN);
 244
 245         if (own)
 246                 return false;
 247         return true;
 248 }
 249
 250 static struct rtl_hal_ops rtl8192se_hal_ops = {
 251         .init_sw_vars = rtl92s_init_sw_vars,
 252         .deinit_sw_vars = rtl92s_deinit_sw_vars,
 253         .read_eeprom_info = rtl92se_read_eeprom_info,
 254         .interrupt_recognized = rtl92se_interrupt_recognized,
 255         .hw_init = rtl92se_hw_init,
 256         .hw_disable = rtl92se_card_disable,
 257         .hw_suspend = rtl92se_suspend,
 258         .hw_resume = rtl92se_resume,
 259         .enable_interrupt = rtl92se_enable_interrupt,
 260         .disable_interrupt = rtl92se_disable_interrupt,
 261         .set_network_type = rtl92se_set_network_type,
 262         .set_chk_bssid = rtl92se_set_check_bssid,
 263         .set_qos = rtl92se_set_qos,
 264         .set_bcn_reg = rtl92se_set_beacon_related_registers,
 265         .set_bcn_intv = rtl92se_set_beacon_interval,
 266         .update_interrupt_mask = rtl92se_update_interrupt_mask,
 267         .get_hw_reg = rtl92se_get_hw_reg,
 268         .set_hw_reg = rtl92se_set_hw_reg,
 269         .update_rate_tbl = rtl92se_update_hal_rate_tbl,
 270         .fill_tx_desc = rtl92se_tx_fill_desc,
 271         .fill_tx_cmddesc = rtl92se_tx_fill_cmddesc,
 272         .query_rx_desc = rtl92se_rx_query_desc,
 273         .set_channel_access = rtl92se_update_channel_access_setting,
 274         .radio_onoff_checking = rtl92se_gpio_radio_on_off_checking,
 275         .set_bw_mode = rtl92s_phy_set_bw_mode,
 276         .switch_channel = rtl92s_phy_sw_chnl,
 277         .dm_watchdog = rtl92s_dm_watchdog,
 278         .scan_operation_backup = rtl92s_phy_scan_operation_backup,
 279         .set_rf_power_state = rtl92s_phy_set_rf_power_state,
 280         .led_control = rtl92se_led_control,
 281         .set_desc = rtl92se_set_desc,
 282         .get_desc = rtl92se_get_desc,
 283         .is_tx_desc_closed = rtl92se_is_tx_desc_closed,
 284         .tx_polling = rtl92se_tx_polling,
 285         .enable_hw_sec = rtl92se_enable_hw_security_config,
 286         .set_key = rtl92se_set_key,
 287         .init_sw_leds = rtl92se_init_sw_leds,
 288         .get_bbreg = rtl92s_phy_query_bb_reg,
 289         .set_bbreg = rtl92s_phy_set_bb_reg,
 290         .get_rfreg = rtl92s_phy_query_rf_reg,
 291         .set_rfreg = rtl92s_phy_set_rf_reg,
 292         .get_btc_status = rtl_btc_status_false,
 293 };
 294
 295 static struct rtl_mod_params rtl92se_mod_params = {
 296         .sw_crypto = false,
 297         .inactiveps = true,
 298         .swctrl_lps = true,
 299         .fwctrl_lps = false,
 300         .debug_level = 0,
 301         .debug_mask = 0,
 302 };
 303
 304 /* Because memory R/W bursting will cause system hang/crash
 305  * for 92se, so we don't read back after every write action */
 306 static const struct rtl_hal_cfg rtl92se_hal_cfg = {
 307         .bar_id = 1,
 308         .write_readback = false,
 309         .name = "rtl92s_pci",
 310         .ops = &rtl8192se_hal_ops,
 311         .mod_params = &rtl92se_mod_params,
 312
 313         .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
 314         .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
 315         .maps[SYS_CLK] = SYS_CLKR,
 316         .maps[MAC_RCR_AM] = RCR_AM,
 317         .maps[MAC_RCR_AB] = RCR_AB,
 318         .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
 319         .maps[MAC_RCR_ACF] = RCR_ACF,
 320         .maps[MAC_RCR_AAP] = RCR_AAP,
 321         .maps[MAC_HIMR] = INTA_MASK,
 322         .maps[MAC_HIMRE] = INTA_MASK + 4,
 323
 324         .maps[EFUSE_TEST] = REG_EFUSE_TEST,
 325         .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
 326         .maps[EFUSE_CLK] = REG_EFUSE_CLK,
 327         .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
 328         .maps[EFUSE_PWC_EV12V] = 0, /* nouse for 8192se */
 329         .maps[EFUSE_FEN_ELDR] = 0, /* nouse for 8192se */
 330         .maps[EFUSE_LOADER_CLK_EN] = 0,/* nouse for 8192se */
 331         .maps[EFUSE_ANA8M] = EFUSE_ANA8M,
 332         .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE_92S,
 333         .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
 334         .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
 335         .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
 336
 337         .maps[RWCAM] = REG_RWCAM,
 338         .maps[WCAMI] = REG_WCAMI,
 339         .maps[RCAMO] = REG_RCAMO,
 340         .maps[CAMDBG] = REG_CAMDBG,
 341         .maps[SECR] = REG_SECR,
 342         .maps[SEC_CAM_NONE] = CAM_NONE,
 343         .maps[SEC_CAM_WEP40] = CAM_WEP40,
 344         .maps[SEC_CAM_TKIP] = CAM_TKIP,
 345         .maps[SEC_CAM_AES] = CAM_AES,
 346         .maps[SEC_CAM_WEP104] = CAM_WEP104,
 347
 348         .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
 349         .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
 350         .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
 351         .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
 352         .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
 353         .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
 354         .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
 355         .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
 356         .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
 357         .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
 358         .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
 359         .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
 360         .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
 361         .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
 362         .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
 363         .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
 364
 365         .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
 366         .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
 367         .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
 368         .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
 369         .maps[RTL_IMR_RDU] = IMR_RDU,
 370         .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
 371         .maps[RTL_IMR_BDOK] = IMR_BDOK,
 372         .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
 373         .maps[RTL_IMR_TBDER] = IMR_TBDER,
 374         .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
 375         .maps[RTL_IMR_COMDOK] = IMR_COMDOK,
 376         .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
 377         .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
 378         .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
 379         .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
 380         .maps[RTL_IMR_VODOK] = IMR_VODOK,
 381         .maps[RTL_IMR_ROK] = IMR_ROK,
 382         .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
 383
 384         .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
 385         .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
 386         .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
 387         .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
 388         .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
 389         .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
 390         .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
 391         .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
 392         .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
 393         .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
 394         .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
 395         .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
 396
 397         .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
 398         .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
 399 };
 400
 401 static const struct pci_device_id rtl92se_pci_ids[] = {
 402         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8192, rtl92se_hal_cfg)},
 403         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8171, rtl92se_hal_cfg)},
 404         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8172, rtl92se_hal_cfg)},
 405         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8173, rtl92se_hal_cfg)},
 406         {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8174, rtl92se_hal_cfg)},
 407         {},
 408 };
 409
 410 MODULE_DEVICE_TABLE(pci, rtl92se_pci_ids);
 411
 412 MODULE_AUTHOR("lizhaoming       <chaoming_li@realsil.com.cn>");
 413 MODULE_AUTHOR("Realtek WlanFAE  <wlanfae@realtek.com>");
 414 MODULE_AUTHOR("Larry Finger     <Larry.Finger@lwfinger.net>");
 415 MODULE_LICENSE("GPL");
 416 MODULE_DESCRIPTION("Realtek 8192S/8191S 802.11n PCI wireless");
 417 /*(DEBLOBBED)*/
 418
 419 module_param_named(swenc, rtl92se_mod_params.sw_crypto, bool, 0444);
 420 module_param_named(debug_level, rtl92se_mod_params.debug_level, int, 0644);
 421 module_param_named(debug_mask, rtl92se_mod_params.debug_mask, ullong, 0644);
 422 module_param_named(ips, rtl92se_mod_params.inactiveps, bool, 0444);
 423 module_param_named(swlps, rtl92se_mod_params.swctrl_lps, bool, 0444);
 424 module_param_named(fwlps, rtl92se_mod_params.fwctrl_lps, bool, 0444);
 425 MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
 426 MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
 427 MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
 428 MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
 429 MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
 430 MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
 431
 432 static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
 433
 434 static struct pci_driver rtl92se_driver = {
 435         .name = KBUILD_MODNAME,
 436         .id_table = rtl92se_pci_ids,
 437         .probe = rtl_pci_probe,
 438         .remove = rtl_pci_disconnect,
 439         .driver.pm = &rtlwifi_pm_ops,
 440 };
 441
 442 module_pci_driver(rtl92se_driver);