1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
25 #ifndef __REALTEK_92S_REG_H__
26 #define __REALTEK_92S_REG_H__
28 /* 1. System Configuration Registers */
29 #define REG_SYS_ISO_CTRL 0x0000
30 #define REG_SYS_FUNC_EN 0x0002
31 #define PMC_FSM 0x0004
32 #define SYS_CLKR 0x0008
33 #define EPROM_CMD 0x000A
35 #define AFE_MISC 0x0010
36 #define SPS0_CTRL 0x0011
37 #define SPS1_CTRL 0x0018
38 #define RF_CTRL 0x001F
39 #define LDOA15_CTRL 0x0020
40 #define LDOV12D_CTRL 0x0021
41 #define LDOHCI12_CTRL 0x0022
42 #define LDO_USB_SDIO 0x0023
43 #define LPLDO_CTRL 0x0024
44 #define AFE_XTAL_CTRL 0x0026
45 #define AFE_PLL_CTRL 0x0028
46 #define REG_EFUSE_CTRL 0x0030
47 #define REG_EFUSE_TEST 0x0034
48 #define PWR_DATA 0x0038
49 #define DBG_PORT 0x003A
50 #define DPS_TIMER 0x003C
51 #define RCLK_MON 0x003E
53 /* 2. Command Control Registers */
55 #define TXPAUSE 0x0042
56 #define LBKMD_SEL 0x0043
60 #define SYSF_CFG 0x004D
61 #define RX_PKY_LIMIT 0x004E
62 #define MBIDCTRL 0x004F
64 /* 3. MACID Setting Registers */
66 #define MACIDR0 0x0050
67 #define MACIDR4 0x0054
71 #define MBIDCAMCONTENT 0x0068
72 #define MBIDCAMCFG 0x0070
73 #define BUILDTIME 0x0074
74 #define BUILDUSER 0x0078
79 /* 4. Timing Control Registers */
81 #define SLOT_TIME 0x0089
83 #define SIFS_CCK 0x008C
84 #define SIFS_OFDM 0x008E
85 #define PIFS_TIME 0x0090
86 #define ACK_TIMEOUT 0x0091
88 #define BCN_INTERVAL 0x0094
89 #define ATIMWND 0x0096
90 #define BCN_DRV_EARLY_INT 0x0098
91 #define BCN_DMATIME 0x009A
92 #define BCN_ERR_THRESH 0x009C
94 #define RSVD_MAC_TUNE_US 0x009E
96 /* 5. FIFO Control Registers */
107 #define RQPN10 0x00A9
108 #define LD_RQPN 0x00AB
109 #define RXFF_BNDY 0x00AC
110 #define RXRPT_BNDY 0x00B0
111 #define TXPKTBUF_PGBNDY 0x00B4
113 #define RXDRVINFO_SZ 0x00B6
114 #define TXFF_STATUS 0x00B7
115 #define RXFF_STATUS 0x00B8
116 #define TXFF_EMPTY_TH 0x00B9
117 #define SDIO_RX_BLKSZ 0x00BC
119 #define RXPKT_NUM 0x00BE
120 #define C2HCMD_UDT_SIZE 0x00C0
121 #define C2HCMD_UDT_ADDR 0x00C2
122 #define FIFOPAGE1 0x00C4
123 #define FIFOPAGE2 0x00C8
124 #define FIFOPAGE3 0x00CC
125 #define FIFOPAGE4 0x00D0
126 #define FIFOPAGE5 0x00D4
127 #define FW_RSVD_PG_CRTL 0x00D8
128 #define RXDMA_AGG_PG_TH 0x00D9
129 #define TXDESC_MSK 0x00DC
130 #define TXRPTFF_RDPTR 0x00E0
131 #define TXRPTFF_WTPTR 0x00E4
132 #define C2HFF_RDPTR 0x00E8
133 #define C2HFF_WTPTR 0x00EC
134 #define RXFF0_RDPTR 0x00F0
135 #define RXFF0_WTPTR 0x00F4
136 #define RXFF1_RDPTR 0x00F8
137 #define RXFF1_WTPTR 0x00FC
138 #define RXRPT0_RDPTR 0x0100
139 #define RXRPT0_WTPTR 0x0104
140 #define RXRPT1_RDPTR 0x0108
141 #define RXRPT1_WTPTR 0x010C
142 #define RX0_UDT_SIZE 0x0110
143 #define RX1PKTNUM 0x0114
144 #define RXFILTERMAP 0x0116
145 #define RXFILTERMAP_GP1 0x0118
146 #define RXFILTERMAP_GP2 0x011A
147 #define RXFILTERMAP_GP3 0x011C
148 #define BCNQ_CTRL 0x0120
149 #define MGTQ_CTRL 0x0124
150 #define HIQ_CTRL 0x0128
151 #define VOTID7_CTRL 0x012c
152 #define VOTID6_CTRL 0x0130
153 #define VITID5_CTRL 0x0134
154 #define VITID4_CTRL 0x0138
155 #define BETID3_CTRL 0x013c
156 #define BETID0_CTRL 0x0140
157 #define BKTID2_CTRL 0x0144
158 #define BKTID1_CTRL 0x0148
159 #define CMDQ_CTRL 0x014c
160 #define TXPKT_NUM_CTRL 0x0150
161 #define TXQ_PGADD 0x0152
162 #define TXFF_PG_NUM 0x0154
163 #define TRXDMA_STATUS 0x0156
165 /* 6. Adaptive Control Registers */
166 #define INIMCS_SEL 0x0160
167 #define TX_RATE_REG INIMCS_SEL
168 #define INIRTSMCS_SEL 0x0180
178 #define AGGLEN_LMT_H 0x01A7
179 #define AGGLEN_LMT_L 0x01A8
180 #define DARFRC 0x01B0
181 #define RARFRC 0x01B8
182 #define MCS_TXAGC 0x01C0
183 #define CCK_TXAGC 0x01C8
185 /* 7. EDCA Setting Registers */
186 #define EDCAPARA_VO 0x01D0
187 #define EDCAPARA_VI 0x01D4
188 #define EDCAPARA_BE 0x01D8
189 #define EDCAPARA_BK 0x01DC
190 #define BCNTCFG 0x01E0
192 #define ACMAVG 0x01E4
193 #define AcmHwCtrl 0x01E7
194 #define VO_ADMTM 0x01E8
195 #define VI_ADMTM 0x01EC
196 #define BE_ADMTM 0x01F0
197 #define RETRY_LIMIT 0x01F4
198 #define SG_RATE 0x01F6
200 /* 8. WMAC, BA and CCX related Register. */
201 #define NAV_CTRL 0x0200
202 #define BW_OPMODE 0x0203
203 #define BACAMCMD 0x0204
204 #define BACAMCONTENT 0x0208
206 /* the 0x2xx register WMAC definition */
209 #define HWPC_RX_CTRL 0x0218
213 #define CLM_RESULT 0x0227
214 #define NHM_RPI_CNT 0x0228
215 #define RXERR_RPT 0x0230
216 #define NAV_PROT_LEN 0x0234
217 #define CFEND_TH 0x0236
218 #define AMPDU_MIN_SPACE 0x0237
219 #define TXOP_STALL_CTRL 0x0238
221 /* 9. Security Control Registers */
222 #define REG_RWCAM 0x0240
223 #define REG_WCAMI 0x0244
224 #define REG_RCAMO 0x0248
225 #define REG_CAMDBG 0x024C
226 #define REG_SECR 0x0250
228 /* 10. Power Save Control Registers */
229 #define WOW_CTRL 0x0260
230 #define PSSTATUS 0x0261
231 #define PSSWITCH 0x0262
232 #define MIMOPS_WAIT_PERIOD 0x0263
233 #define LPNAV_CTRL 0x0264
241 #define FW_RPT_REG 0x02c4
243 /* 11. General Purpose Registers */
244 #define PSTIME 0x02E0
245 #define TIMER0 0x02E4
246 #define TIMER1 0x02E8
247 #define GPIO_IN_SE 0x02EC
248 #define GPIO_IO_SEL 0x02EE
249 #define MAC_PINMUX_CFG 0x02F1
250 #define LEDCFG 0x02F2
251 #define PHY_REG 0x02F3
252 #define PHY_REG_DATA 0x02F4
253 #define REG_EFUSE_CLK 0x02F8
255 /* 12. Host Interrupt Status Registers */
256 #define INTA_MASK 0x0300
259 /* 13. Test Mode and Debug Control Registers */
260 #define DBG_PORT_SWITCH 0x003A
263 #define CPUINST 0x0318
264 #define CPUCAUSE 0x031C
265 #define LBUS_ERR_ADDR 0x0320
266 #define LBUS_ERR_CMD 0x0324
267 #define LBUS_ERR_DATA_L 0x0328
268 #define LBUS_ERR_DATA_H 0x032C
269 #define LX_EXCEPTION_ADDR 0x0330
270 #define WDG_CTRL 0x0334
271 #define INTMTU 0x0338
273 #define FDLOCKTURN0 0x033C
274 #define FDLOCKTURN1 0x033D
275 #define TRXPKTBUF_DBG_DATA 0x0340
276 #define TRXPKTBUF_DBG_CTRL 0x0348
278 #define CBUS_ERR_ADDR 0x0350
279 #define CBUS_ERR_CMD 0x0354
280 #define CBUS_ERR_DATA_L 0x0358
281 #define CBUS_ERR_DATA_H 0x035C
282 #define USB_SIE_INTF_ADDR 0x0360
283 #define USB_SIE_INTF_WD 0x0361
284 #define USB_SIE_INTF_RD 0x0362
285 #define USB_SIE_INTF_CTRL 0x0363
286 #define LBUS_MON_ADDR 0x0364
287 #define LBUS_ADDR_MASK 0x0368
289 /* Boundary is 0x37F */
291 /* 14. PCIE config register */
292 #define TP_POLL 0x0500
293 #define PM_CTRL 0x0502
307 #define DBI_WDATA 0x0540
308 #define DBI_RDATA 0x0544
309 #define DBI_CTRL 0x0548
310 #define MDIO_DATA 0x0550
311 #define MDIO_CTRL 0x0554
312 #define PCI_RPWM 0x0561
313 #define PCI_CPWM 0x0563
315 /* Config register (Offset 0x800-) */
316 #define PHY_CCA 0x803
318 /* Min Spacing related settings. */
319 #define MAX_MSS_DENSITY_2T 0x13
320 #define MAX_MSS_DENSITY_1T 0x0A
322 /* Rx DMA Control related settings */
323 #define RXDMA_AGG_EN BIT(7)
325 #define RPWM PCI_RPWM
327 /* Regsiter Bit and Content definition */
329 #define ISO_MD2PP BIT(0)
330 #define ISO_PA2PCIE BIT(3)
331 #define ISO_PLL2MD BIT(4)
332 #define ISO_PWC_DV2RP BIT(11)
333 #define ISO_PWC_RV2RP BIT(12)
336 #define FEN_MREGEN BIT(15)
337 #define FEN_DCORE BIT(11)
338 #define FEN_CPUEN BIT(10)
340 #define PAD_HWPD_IDN BIT(22)
342 #define SYS_CLKSEL_80M BIT(0)
343 #define SYS_PS_CLKSEL BIT(1)
344 #define SYS_CPU_CLKSEL BIT(2)
345 #define SYS_MAC_CLK_EN BIT(11)
346 #define SYS_SWHW_SEL BIT(14)
347 #define SYS_FWHW_SEL BIT(15)
349 #define CmdEEPROM_En BIT(5)
350 #define CmdEERPOMSEL BIT(4)
351 #define Cmd9346CR_9356SEL BIT(4)
353 #define AFE_MBEN BIT(1)
354 #define AFE_BGEN BIT(0)
356 #define SPS1_SWEN BIT(1)
357 #define SPS1_LDEN BIT(0)
360 #define RF_RSTB BIT(1)
361 #define RF_SDMRSTB BIT(2)
363 #define LDA15_EN BIT(0)
365 #define LDV12_EN BIT(0)
366 #define LDV12_SDBY BIT(1)
368 #define XTAL_GATE_AFE BIT(10)
370 #define APLL_EN BIT(0)
372 #define AFR_CardBEn BIT(0)
373 #define AFR_CLKRUN_SEL BIT(1)
374 #define AFR_FuncRegEn BIT(2)
376 #define APSDOFF_STATUS BIT(15)
377 #define APSDOFF BIT(14)
378 #define BBRSTN BIT(13)
379 #define BB_GLB_RSTN BIT(12)
380 #define SCHEDULE_EN BIT(10)
381 #define MACRXEN BIT(9)
382 #define MACTXEN BIT(8)
383 #define DDMA_EN BIT(7)
384 #define FW2HW_EN BIT(6)
385 #define RXDMA_EN BIT(5)
386 #define TXDMA_EN BIT(4)
387 #define HCI_RXDMA_EN BIT(3)
388 #define HCI_TXDMA_EN BIT(2)
390 #define StopHCCA BIT(6)
391 #define StopHigh BIT(5)
392 #define StopMgt BIT(4)
393 #define StopVO BIT(3)
394 #define StopVI BIT(2)
395 #define StopBE BIT(1)
396 #define StopBK BIT(0)
398 #define LBK_NORMAL 0x00
399 #define LBK_MAC_LB (BIT(0) | BIT(1) | BIT(3))
400 #define LBK_MAC_DLB (BIT(0) | BIT(1))
401 #define LBK_DMA_LB (BIT(0) | BIT(1) | BIT(2))
403 #define TCP_OFDL_EN BIT(25)
404 #define HWPC_TX_EN BIT(24)
405 #define TXDMAPRE2FULL BIT(23)
406 #define DISCW BIT(20)
407 #define TCRICV BIT(19)
408 #define CfendForm BIT(17)
409 #define TCRCRC BIT(16)
410 #define FAKE_IMEM_EN BIT(15)
411 #define TSFRST BIT(9)
413 #define FWALLRDY (BIT(0) | BIT(1) | BIT(2) | \
414 BIT(3) | BIT(4) | BIT(5) | \
417 #define BASECHG BIT(6)
419 #define DMEM_CODE_DONE BIT(4)
420 #define EXT_IMEM_CHK_RPT BIT(3)
421 #define EXT_IMEM_CODE_DONE BIT(2)
422 #define IMEM_CHK_RPT BIT(1)
423 #define IMEM_CODE_DONE BIT(0)
424 #define EMEM_CODE_DONE BIT(2)
425 #define EMEM_CHK_RPT BIT(3)
426 #define IMEM_RDY BIT(5)
427 #define LOAD_FW_READY (IMEM_CODE_DONE | \
435 #define TCR_TSFEN BIT(8)
436 #define TCR_TSFRST BIT(9)
437 #define TCR_FAKE_IMEM_EN BIT(15)
438 #define TCR_CRC BIT(16)
439 #define TCR_ICV BIT(19)
440 #define TCR_DISCW BIT(20)
441 #define TCR_HWPC_TX_EN BIT(24)
442 #define TCR_TCP_OFDL_EN BIT(25)
443 #define TXDMA_INIT_VALUE (IMEM_CHK_RPT | \
446 #define RCR_APPFCS BIT(31)
447 #define RCR_DIS_ENC_2BYTE BIT(30)
448 #define RCR_DIS_AES_2BYTE BIT(29)
449 #define RCR_HTC_LOC_CTRL BIT(28)
450 #define RCR_ENMBID BIT(27)
451 #define RCR_RX_TCPOFDL_EN BIT(26)
452 #define RCR_APP_PHYST_RXFF BIT(25)
453 #define RCR_APP_PHYST_STAFF BIT(24)
454 #define RCR_CBSSID BIT(23)
455 #define RCR_APWRMGT BIT(22)
456 #define RCR_ADD3 BIT(21)
457 #define RCR_AMF BIT(20)
458 #define RCR_ACF BIT(19)
459 #define RCR_ADF BIT(18)
460 #define RCR_APP_MIC BIT(17)
461 #define RCR_APP_ICV BIT(16)
462 #define RCR_RXFTH BIT(13)
463 #define RCR_AICV BIT(12)
464 #define RCR_RXDESC_LK_EN BIT(11)
465 #define RCR_APP_BA_SSN BIT(6)
466 #define RCR_ACRC32 BIT(5)
467 #define RCR_RXSHFT_EN BIT(4)
468 #define RCR_AB BIT(3)
469 #define RCR_AM BIT(2)
470 #define RCR_APM BIT(1)
471 #define RCR_AAP BIT(0)
472 #define RCR_MXDMA_OFFSET 8
473 #define RCR_FIFO_OFFSET 13
476 #define MSR_LINK_MASK ((1 << 0) | (1 << 1))
477 #define MSR_LINK_MANAGED 2
478 #define MSR_LINK_NONE 0
479 #define MSR_LINK_SHIFT 0
480 #define MSR_LINK_ADHOC 1
481 #define MSR_LINK_MASTER 3
482 #define MSR_NOLINK 0x00
483 #define MSR_ADHOC 0x01
484 #define MSR_INFRA 0x02
487 #define ENUART BIT(7)
488 #define ENJTAG BIT(3)
489 #define BTMODE (BIT(2) | BIT(1))
492 #define ENMBID BIT(7)
493 #define BCNUM (BIT(6) | BIT(5) | BIT(4))
495 #define USTIME_EDCA 0xFF00
496 #define USTIME_TSF 0x00FF
498 #define SIFS_TRX 0xFF00
499 #define SIFS_CTX 0x00FF
501 #define ENSWBCN BIT(15)
502 #define DRVERLY_TU 0x0FF0
503 #define DRVERLY_US 0x000F
504 #define BCN_TCFG_CW_SHIFT 8
505 #define BCN_TCFG_IFS 0
507 #define RRSR_RSC_OFFSET 21
508 #define RRSR_SHORT_OFFSET 23
509 #define RRSR_RSC_BW_40M 0x600000
510 #define RRSR_RSC_UPSUBCHNL 0x400000
511 #define RRSR_RSC_LOWSUBCHNL 0x200000
512 #define RRSR_SHORT 0x800000
513 #define RRSR_1M BIT(0)
514 #define RRSR_2M BIT(1)
515 #define RRSR_5_5M BIT(2)
516 #define RRSR_11M BIT(3)
517 #define RRSR_6M BIT(4)
518 #define RRSR_9M BIT(5)
519 #define RRSR_12M BIT(6)
520 #define RRSR_18M BIT(7)
521 #define RRSR_24M BIT(8)
522 #define RRSR_36M BIT(9)
523 #define RRSR_48M BIT(10)
524 #define RRSR_54M BIT(11)
525 #define RRSR_MCS0 BIT(12)
526 #define RRSR_MCS1 BIT(13)
527 #define RRSR_MCS2 BIT(14)
528 #define RRSR_MCS3 BIT(15)
529 #define RRSR_MCS4 BIT(16)
530 #define RRSR_MCS5 BIT(17)
531 #define RRSR_MCS6 BIT(18)
532 #define RRSR_MCS7 BIT(19)
533 #define BRSR_AckShortPmb BIT(23)
535 #define RATR_1M 0x00000001
536 #define RATR_2M 0x00000002
537 #define RATR_55M 0x00000004
538 #define RATR_11M 0x00000008
539 #define RATR_6M 0x00000010
540 #define RATR_9M 0x00000020
541 #define RATR_12M 0x00000040
542 #define RATR_18M 0x00000080
543 #define RATR_24M 0x00000100
544 #define RATR_36M 0x00000200
545 #define RATR_48M 0x00000400
546 #define RATR_54M 0x00000800
547 #define RATR_MCS0 0x00001000
548 #define RATR_MCS1 0x00002000
549 #define RATR_MCS2 0x00004000
550 #define RATR_MCS3 0x00008000
551 #define RATR_MCS4 0x00010000
552 #define RATR_MCS5 0x00020000
553 #define RATR_MCS6 0x00040000
554 #define RATR_MCS7 0x00080000
555 #define RATR_MCS8 0x00100000
556 #define RATR_MCS9 0x00200000
557 #define RATR_MCS10 0x00400000
558 #define RATR_MCS11 0x00800000
559 #define RATR_MCS12 0x01000000
560 #define RATR_MCS13 0x02000000
561 #define RATR_MCS14 0x04000000
562 #define RATR_MCS15 0x08000000
564 #define RATE_ALL_CCK (RATR_1M | RATR_2M | \
566 #define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | \
567 RATR_12M | RATR_18M | \
568 RATR_24M | RATR_36M | \
570 #define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | \
571 RATR_MCS2 | RATR_MCS3 | \
572 RATR_MCS4 | RATR_MCS5 | \
573 RATR_MCS6 | RATR_MCS7)
574 #define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | \
575 RATR_MCS10 | RATR_MCS11 | \
576 RATR_MCS12 | RATR_MCS13 | \
577 RATR_MCS14 | RATR_MCS15)
579 #define AC_PARAM_TXOP_LIMIT_OFFSET 16
580 #define AC_PARAM_ECW_MAX_OFFSET 12
581 #define AC_PARAM_ECW_MIN_OFFSET 8
582 #define AC_PARAM_AIFS_OFFSET 0
584 #define AcmHw_HwEn BIT(0)
585 #define AcmHw_BeqEn BIT(1)
586 #define AcmHw_ViqEn BIT(2)
587 #define AcmHw_VoqEn BIT(3)
588 #define AcmHw_BeqStatus BIT(4)
589 #define AcmHw_ViqStatus BIT(5)
590 #define AcmHw_VoqStatus BIT(6)
592 #define RETRY_LIMIT_SHORT_SHIFT 8
593 #define RETRY_LIMIT_LONG_SHIFT 0
595 #define NAV_UPPER_EN BIT(16)
596 #define NAV_UPPER 0xFF00
597 #define NAV_RTSRST 0xFF
599 #define BW_OPMODE_20MHZ BIT(2)
600 #define BW_OPMODE_5G BIT(1)
601 #define BW_OPMODE_11J BIT(0)
603 #define RXERR_RPT_RST BIT(27)
604 #define RXERR_OFDM_PPDU 0
605 #define RXERR_OFDM_FALSE_ALARM 1
606 #define RXERR_OFDM_MPDU_OK 2
607 #define RXERR_OFDM_MPDU_FAIL 3
608 #define RXERR_CCK_PPDU 4
609 #define RXERR_CCK_FALSE_ALARM 5
610 #define RXERR_CCK_MPDU_OK 6
611 #define RXERR_CCK_MPDU_FAIL 7
612 #define RXERR_HT_PPDU 8
613 #define RXERR_HT_FALSE_ALARM 9
614 #define RXERR_HT_MPDU_TOTAL 10
615 #define RXERR_HT_MPDU_OK 11
616 #define RXERR_HT_MPDU_FAIL 12
617 #define RXERR_RX_FULL_DROP 15
619 #define SCR_TXUSEDK BIT(0)
620 #define SCR_RXUSEDK BIT(1)
621 #define SCR_TXENCENABLE BIT(2)
622 #define SCR_RXENCENABLE BIT(3)
623 #define SCR_SKBYA2 BIT(4)
624 #define SCR_NOSKMC BIT(5)
626 #define CAM_VALID BIT(15)
627 #define CAM_NOTVALID 0x0000
628 #define CAM_USEDK BIT(5)
631 #define CAM_WEP40 0x01
632 #define CAM_TKIP 0x02
634 #define CAM_WEP104 0x05
636 #define TOTAL_CAM_ENTRY 32
637 #define HALF_CAM_ENTRY 16
639 #define CAM_WRITE BIT(16)
640 #define CAM_READ 0x00000000
641 #define CAM_POLLINIG BIT(31)
643 #define WOW_PMEN BIT(0)
644 #define WOW_WOMEN BIT(1)
645 #define WOW_MAGIC BIT(2)
646 #define WOW_UWF BIT(3)
648 #define GPIOMUX_EN BIT(3)
649 #define GPIOSEL_GPIO 0
650 #define GPIOSEL_PHYDBG 1
652 #define GPIOSEL_WLANDBG 3
653 #define GPIOSEL_GPIO_MASK (~(BIT(0)|BIT(1)))
655 #define HST_RDBUSY BIT(0)
656 #define CPU_WTBUSY BIT(1)
658 #define IMR8190_DISABLED 0x0
659 #define IMR_CPUERR BIT(5)
660 #define IMR_ATIMEND BIT(4)
661 #define IMR_TBDOK BIT(3)
662 #define IMR_TBDER BIT(2)
663 #define IMR_BCNDMAINT8 BIT(1)
664 #define IMR_BCNDMAINT7 BIT(0)
665 #define IMR_BCNDMAINT6 BIT(31)
666 #define IMR_BCNDMAINT5 BIT(30)
667 #define IMR_BCNDMAINT4 BIT(29)
668 #define IMR_BCNDMAINT3 BIT(28)
669 #define IMR_BCNDMAINT2 BIT(27)
670 #define IMR_BCNDMAINT1 BIT(26)
671 #define IMR_BCNDOK8 BIT(25)
672 #define IMR_BCNDOK7 BIT(24)
673 #define IMR_BCNDOK6 BIT(23)
674 #define IMR_BCNDOK5 BIT(22)
675 #define IMR_BCNDOK4 BIT(21)
676 #define IMR_BCNDOK3 BIT(20)
677 #define IMR_BCNDOK2 BIT(19)
678 #define IMR_BCNDOK1 BIT(18)
679 #define IMR_TIMEOUT2 BIT(17)
680 #define IMR_TIMEOUT1 BIT(16)
681 #define IMR_TXFOVW BIT(15)
682 #define IMR_PSTIMEOUT BIT(14)
683 #define IMR_BCNINT BIT(13)
684 #define IMR_RXFOVW BIT(12)
685 #define IMR_RDU BIT(11)
686 #define IMR_RXCMDOK BIT(10)
687 #define IMR_BDOK BIT(9)
688 #define IMR_HIGHDOK BIT(8)
689 #define IMR_COMDOK BIT(7)
690 #define IMR_MGNTDOK BIT(6)
691 #define IMR_HCCADOK BIT(5)
692 #define IMR_BKDOK BIT(4)
693 #define IMR_BEDOK BIT(3)
694 #define IMR_VIDOK BIT(2)
695 #define IMR_VODOK BIT(1)
696 #define IMR_ROK BIT(0)
698 #define TPPOLL_BKQ BIT(0)
699 #define TPPOLL_BEQ BIT(1)
700 #define TPPOLL_VIQ BIT(2)
701 #define TPPOLL_VOQ BIT(3)
702 #define TPPOLL_BQ BIT(4)
703 #define TPPOLL_CQ BIT(5)
704 #define TPPOLL_MQ BIT(6)
705 #define TPPOLL_HQ BIT(7)
706 #define TPPOLL_HCCAQ BIT(8)
707 #define TPPOLL_STOPBK BIT(9)
708 #define TPPOLL_STOPBE BIT(10)
709 #define TPPOLL_STOPVI BIT(11)
710 #define TPPOLL_STOPVO BIT(12)
711 #define TPPOLL_STOPMGT BIT(13)
712 #define TPPOLL_STOPHIGH BIT(14)
713 #define TPPOLL_STOPHCCA BIT(15)
714 #define TPPOLL_SHIFT 8
716 #define CCX_CMD_CLM_ENABLE BIT(0)
717 #define CCX_CMD_NHM_ENABLE BIT(1)
718 #define CCX_CMD_FUNCTION_ENABLE BIT(8)
719 #define CCX_CMD_IGNORE_CCA BIT(9)
720 #define CCX_CMD_IGNORE_TXON BIT(10)
721 #define CCX_CLM_RESULT_READY BIT(16)
722 #define CCX_NHM_RESULT_READY BIT(16)
723 #define CCX_CMD_RESET 0x0
726 #define HWSET_MAX_SIZE_92S 128
727 #define EFUSE_MAX_SECTION 16
728 #define EFUSE_REAL_CONTENT_LEN 512
729 #define EFUSE_OOB_PROTECT_BYTES 15
731 #define RTL8190_EEPROM_ID 0x8129
732 #define EEPROM_HPON 0x02
733 #define EEPROM_CLK 0x06
734 #define EEPROM_TESTR 0x08
736 #define EEPROM_VID 0x0A
737 #define EEPROM_DID 0x0C
738 #define EEPROM_SVID 0x0E
739 #define EEPROM_SMID 0x10
741 #define EEPROM_MAC_ADDR 0x12
742 #define EEPROM_NODE_ADDRESS_BYTE_0 0x12
744 #define EEPROM_PWDIFF 0x54
746 #define EEPROM_TXPOWERBASE 0x50
747 #define EEPROM_TX_PWR_INDEX_RANGE 28
749 #define EEPROM_TX_PWR_HT20_DIFF 0x62
750 #define DEFAULT_HT20_TXPWR_DIFF 2
751 #define EEPROM_TX_PWR_OFDM_DIFF 0x65
753 #define EEPROM_TXPWRGROUP 0x67
754 #define EEPROM_REGULATORY 0x6D
756 #define TX_PWR_SAFETY_CHK 0x6D
757 #define EEPROM_TXPWINDEX_CCK_24G 0x5D
758 #define EEPROM_TXPWINDEX_OFDM_24G 0x6B
759 #define EEPROM_HT2T_CH1_A 0x6c
760 #define EEPROM_HT2T_CH7_A 0x6d
761 #define EEPROM_HT2T_CH13_A 0x6e
762 #define EEPROM_HT2T_CH1_B 0x6f
763 #define EEPROM_HT2T_CH7_B 0x70
764 #define EEPROM_HT2T_CH13_B 0x71
766 #define EEPROM_TSSI_A 0x74
767 #define EEPROM_TSSI_B 0x75
769 #define EEPROM_RFIND_POWERDIFF 0x76
770 #define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3
772 #define EEPROM_THERMALMETER 0x77
773 #define EEPROM_BLUETOOTH_COEXIST 0x78
774 #define EEPROM_BLUETOOTH_TYPE 0x4f
776 #define EEPROM_OPTIONAL 0x78
777 #define EEPROM_WOWLAN 0x78
779 #define EEPROM_CRYSTALCAP 0x79
780 #define EEPROM_CHANNELPLAN 0x7B
781 #define EEPROM_VERSION 0x7C
782 #define EEPROM_CUSTOMID 0x7A
783 #define EEPROM_BOARDTYPE 0x7E
785 #define EEPROM_CHANNEL_PLAN_FCC 0x0
786 #define EEPROM_CHANNEL_PLAN_IC 0x1
787 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
788 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
789 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
790 #define EEPROM_CHANNEL_PLAN_MKK 0x5
791 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
792 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
793 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
794 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
795 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
796 #define EEPROM_CHANNEL_PLAN_NCC 0xB
797 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
799 #define FW_DIG_DISABLE 0xfd00cc00
800 #define FW_DIG_ENABLE 0xfd000000
801 #define FW_DIG_HALT 0xfd000001
802 #define FW_DIG_RESUME 0xfd000002
803 #define FW_HIGH_PWR_DISABLE 0xfd000008
804 #define FW_HIGH_PWR_ENABLE 0xfd000009
805 #define FW_ADD_A2_ENTRY 0xfd000016
806 #define FW_TXPWR_TRACK_ENABLE 0xfd000017
807 #define FW_TXPWR_TRACK_DISABLE 0xfd000018
808 #define FW_TXPWR_TRACK_THERMAL 0xfd000019
809 #define FW_TXANT_SWITCH_ENABLE 0xfd000023
810 #define FW_TXANT_SWITCH_DISABLE 0xfd000024
811 #define FW_RA_INIT 0xfd000026
812 #define FW_CTRL_DM_BY_DRIVER 0Xfd00002a
813 #define FW_RA_IOT_BG_COMB 0xfd000030
814 #define FW_RA_IOT_N_COMB 0xfd000031
815 #define FW_RA_REFRESH 0xfd0000a0
816 #define FW_RA_UPDATE_MASK 0xfd0000a2
817 #define FW_RA_DISABLE 0xfd0000a4
818 #define FW_RA_ACTIVE 0xfd0000a6
819 #define FW_RA_DISABLE_RSSI_MASK 0xfd0000ac
820 #define FW_RA_ENABLE_RSSI_MASK 0xfd0000ad
821 #define FW_RA_RESET 0xfd0000af
822 #define FW_DM_DISABLE 0xfd00aa00
823 #define FW_IQK_ENABLE 0xf0000020
824 #define FW_IQK_SUCCESS 0x0000dddd
825 #define FW_IQK_FAIL 0x0000ffff
826 #define FW_OP_FAILURE 0xffffffff
827 #define FW_TX_FEEDBACK_NONE 0xfb000000
828 #define FW_TX_FEEDBACK_DTM_ENABLE (FW_TX_FEEDBACK_NONE | 0x1)
829 #define FW_TX_FEEDBACK_CCX_ENABL (FW_TX_FEEDBACK_NONE | 0x2)
830 #define FW_BB_RESET_ENABLE 0xff00000d
831 #define FW_BB_RESET_DISABLE 0xff00000e
832 #define FW_CCA_CHK_ENABLE 0xff000011
833 #define FW_CCK_RESET_CNT 0xff000013
834 #define FW_LPS_ENTER 0xfe000010
835 #define FW_LPS_LEAVE 0xfe000011
836 #define FW_INDIRECT_READ 0xf2000000
837 #define FW_INDIRECT_WRITE 0xf2000001
838 #define FW_CHAN_SET 0xf3000001
841 #define RCR_9356SEL BIT(6)
842 #define TCR_LRL_OFFSET 0
843 #define TCR_SRL_OFFSET 8
844 #define TCR_MXDMA_OFFSET 21
845 #define TCR_SAT BIT(24)
846 #define RCR_MXDMA_OFFSET 8
847 #define RCR_FIFO_OFFSET 13
848 #define RCR_OnlyErlPkt BIT(31)
850 #define RETRYCTR 0xDE
852 #define CPU_GEN_SYSTEM_RESET 0x00000001
854 #define CCX_COMMAND_REG 0x890
855 #define CLM_PERIOD_REG 0x894
856 #define NHM_PERIOD_REG 0x896
858 #define NHM_THRESHOLD0 0x898
859 #define NHM_THRESHOLD1 0x899
860 #define NHM_THRESHOLD2 0x89A
861 #define NHM_THRESHOLD3 0x89B
862 #define NHM_THRESHOLD4 0x89C
863 #define NHM_THRESHOLD5 0x89D
864 #define NHM_THRESHOLD6 0x89E
865 #define CLM_RESULT_REG 0x8D0
866 #define NHM_RESULT_REG 0x8D4
867 #define NHM_RPI_COUNTER0 0x8D8
868 #define NHM_RPI_COUNTER1 0x8D9
869 #define NHM_RPI_COUNTER2 0x8DA
870 #define NHM_RPI_COUNTER3 0x8DB
871 #define NHM_RPI_COUNTER4 0x8DC
872 #define NHM_RPI_COUNTER5 0x8DD
873 #define NHM_RPI_COUNTER6 0x8DE
874 #define NHM_RPI_COUNTER7 0x8DF
876 #define HAL_8192S_HW_GPIO_OFF_BIT BIT(3)
877 #define HAL_8192S_HW_GPIO_OFF_MASK 0xF7
878 #define HAL_8192S_HW_GPIO_WPS_BIT BIT(4)
880 #define RPMAC_RESET 0x100
881 #define RPMAC_TXSTART 0x104
882 #define RPMAC_TXLEGACYSIG 0x108
883 #define RPMAC_TXHTSIG1 0x10c
884 #define RPMAC_TXHTSIG2 0x110
885 #define RPMAC_PHYDEBUG 0x114
886 #define RPMAC_TXPACKETNNM 0x118
887 #define RPMAC_TXIDLE 0x11c
888 #define RPMAC_TXMACHEADER0 0x120
889 #define RPMAC_TXMACHEADER1 0x124
890 #define RPMAC_TXMACHEADER2 0x128
891 #define RPMAC_TXMACHEADER3 0x12c
892 #define RPMAC_TXMACHEADER4 0x130
893 #define RPMAC_TXMACHEADER5 0x134
894 #define RPMAC_TXDATATYPE 0x138
895 #define RPMAC_TXRANDOMSEED 0x13c
896 #define RPMAC_CCKPLCPPREAMBLE 0x140
897 #define RPMAC_CCKPLCPHEADER 0x144
898 #define RPMAC_CCKCRC16 0x148
899 #define RPMAC_OFDMRXCRC32OK 0x170
900 #define RPMAC_OFDMRXCRC32ER 0x174
901 #define RPMAC_OFDMRXPARITYER 0x178
902 #define RPMAC_OFDMRXCRC8ER 0x17c
903 #define RPMAC_CCKCRXRC16ER 0x180
904 #define RPMAC_CCKCRXRC32ER 0x184
905 #define RPMAC_CCKCRXRC32OK 0x188
906 #define RPMAC_TXSTATUS 0x18c
908 #define RF_BB_CMD_ADDR 0x02c0
909 #define RF_BB_CMD_DATA 0x02c4
911 #define RFPGA0_RFMOD 0x800
913 #define RFPGA0_TXINFO 0x804
914 #define RFPGA0_PSDFUNCTION 0x808
916 #define RFPGA0_TXGAINSTAGE 0x80c
918 #define RFPGA0_RFTIMING1 0x810
919 #define RFPGA0_RFTIMING2 0x814
920 #define RFPGA0_XA_HSSIPARAMETER1 0x820
921 #define RFPGA0_XA_HSSIPARAMETER2 0x824
922 #define RFPGA0_XB_HSSIPARAMETER1 0x828
923 #define RFPGA0_XB_HSSIPARAMETER2 0x82c
924 #define RFPGA0_XC_HSSIPARAMETER1 0x830
925 #define RFPGA0_XC_HSSIPARAMETER2 0x834
926 #define RFPGA0_XD_HSSIPARAMETER1 0x838
927 #define RFPGA0_XD_HSSIPARAMETER2 0x83c
928 #define RFPGA0_XA_LSSIPARAMETER 0x840
929 #define RFPGA0_XB_LSSIPARAMETER 0x844
930 #define RFPGA0_XC_LSSIPARAMETER 0x848
931 #define RFPGA0_XD_LSSIPARAMETER 0x84c
933 #define RFPGA0_RFWAKEUP_PARAMETER 0x850
934 #define RFPGA0_RFSLEEPUP_PARAMETER 0x854
936 #define RFPGA0_XAB_SWITCHCONTROL 0x858
937 #define RFPGA0_XCD_SWITCHCONTROL 0x85c
939 #define RFPGA0_XA_RFINTERFACEOE 0x860
940 #define RFPGA0_XB_RFINTERFACEOE 0x864
941 #define RFPGA0_XC_RFINTERFACEOE 0x868
942 #define RFPGA0_XD_RFINTERFACEOE 0x86c
944 #define RFPGA0_XAB_RFINTERFACESW 0x870
945 #define RFPGA0_XCD_RFINTERFACESW 0x874
947 #define RFPGA0_XAB_RFPARAMETER 0x878
948 #define RFPGA0_XCD_RFPARAMETER 0x87c
950 #define RFPGA0_ANALOGPARAMETER1 0x880
951 #define RFPGA0_ANALOGPARAMETER2 0x884
952 #define RFPGA0_ANALOGPARAMETER3 0x888
953 #define RFPGA0_ANALOGPARAMETER4 0x88c
955 #define RFPGA0_XA_LSSIREADBACK 0x8a0
956 #define RFPGA0_XB_LSSIREADBACK 0x8a4
957 #define RFPGA0_XC_LSSIREADBACK 0x8a8
958 #define RFPGA0_XD_LSSIREADBACK 0x8ac
960 #define RFPGA0_PSDREPORT 0x8b4
961 #define TRANSCEIVERA_HSPI_READBACK 0x8b8
962 #define TRANSCEIVERB_HSPI_READBACK 0x8bc
963 #define RFPGA0_XAB_RFINTERFACERB 0x8e0
964 #define RFPGA0_XCD_RFINTERFACERB 0x8e4
965 #define RFPGA1_RFMOD 0x900
967 #define RFPGA1_TXBLOCK 0x904
968 #define RFPGA1_DEBUGSELECT 0x908
969 #define RFPGA1_TXINFO 0x90c
971 #define RCCK0_SYSTEM 0xa00
973 #define RCCK0_AFESETTING 0xa04
974 #define RCCK0_CCA 0xa08
976 #define RCCK0_RXAGC1 0xa0c
977 #define RCCK0_RXAGC2 0xa10
979 #define RCCK0_RXHP 0xa14
981 #define RCCK0_DSPPARAMETER1 0xa18
982 #define RCCK0_DSPPARAMETER2 0xa1c
984 #define RCCK0_TXFILTER1 0xa20
985 #define RCCK0_TXFILTER2 0xa24
986 #define RCCK0_DEBUGPORT 0xa28
987 #define RCCK0_FALSEALARMREPORT 0xa2c
988 #define RCCK0_TRSSIREPORT 0xa50
989 #define RCCK0_RXREPORT 0xa54
990 #define RCCK0_FACOUNTERLOWER 0xa5c
991 #define RCCK0_FACOUNTERUPPER 0xa58
993 #define ROFDM0_LSTF 0xc00
995 #define ROFDM0_TRXPATHENABLE 0xc04
996 #define ROFDM0_TRMUXPAR 0xc08
997 #define ROFDM0_TRSWISOLATION 0xc0c
999 #define ROFDM0_XARXAFE 0xc10
1000 #define ROFDM0_XARXIQIMBALANCE 0xc14
1001 #define ROFDM0_XBRXAFE 0xc18
1002 #define ROFDM0_XBRXIQIMBALANCE 0xc1c
1003 #define ROFDM0_XCRXAFE 0xc20
1004 #define ROFDM0_XCRXIQIMBALANCE 0xc24
1005 #define ROFDM0_XDRXAFE 0xc28
1006 #define ROFDM0_XDRXIQIMBALANCE 0xc2c
1008 #define ROFDM0_RXDETECTOR1 0xc30
1009 #define ROFDM0_RXDETECTOR2 0xc34
1010 #define ROFDM0_RXDETECTOR3 0xc38
1011 #define ROFDM0_RXDETECTOR4 0xc3c
1013 #define ROFDM0_RXDSP 0xc40
1014 #define ROFDM0_CFO_AND_DAGC 0xc44
1015 #define ROFDM0_CCADROP_THRESHOLD 0xc48
1016 #define ROFDM0_ECCA_THRESHOLD 0xc4c
1018 #define ROFDM0_XAAGCCORE1 0xc50
1019 #define ROFDM0_XAAGCCORE2 0xc54
1020 #define ROFDM0_XBAGCCORE1 0xc58
1021 #define ROFDM0_XBAGCCORE2 0xc5c
1022 #define ROFDM0_XCAGCCORE1 0xc60
1023 #define ROFDM0_XCAGCCORE2 0xc64
1024 #define ROFDM0_XDAGCCORE1 0xc68
1025 #define ROFDM0_XDAGCCORE2 0xc6c
1027 #define ROFDM0_AGCPARAMETER1 0xc70
1028 #define ROFDM0_AGCPARAMETER2 0xc74
1029 #define ROFDM0_AGCRSSITABLE 0xc78
1030 #define ROFDM0_HTSTFAGC 0xc7c
1032 #define ROFDM0_XATXIQIMBALANCE 0xc80
1033 #define ROFDM0_XATXAFE 0xc84
1034 #define ROFDM0_XBTXIQIMBALANCE 0xc88
1035 #define ROFDM0_XBTXAFE 0xc8c
1036 #define ROFDM0_XCTXIQIMBALANCE 0xc90
1037 #define ROFDM0_XCTXAFE 0xc94
1038 #define ROFDM0_XDTXIQIMBALANCE 0xc98
1039 #define ROFDM0_XDTXAFE 0xc9c
1041 #define ROFDM0_RXHP_PARAMETER 0xce0
1042 #define ROFDM0_TXPSEUDO_NOISE_WGT 0xce4
1043 #define ROFDM0_FRAME_SYNC 0xcf0
1044 #define ROFDM0_DFSREPORT 0xcf4
1045 #define ROFDM0_TXCOEFF1 0xca4
1046 #define ROFDM0_TXCOEFF2 0xca8
1047 #define ROFDM0_TXCOEFF3 0xcac
1048 #define ROFDM0_TXCOEFF4 0xcb0
1049 #define ROFDM0_TXCOEFF5 0xcb4
1050 #define ROFDM0_TXCOEFF6 0xcb8
1053 #define ROFDM1_LSTF 0xd00
1054 #define ROFDM1_TRXPATHENABLE 0xd04
1056 #define ROFDM1_CFO 0xd08
1057 #define ROFDM1_CSI1 0xd10
1058 #define ROFDM1_SBD 0xd14
1059 #define ROFDM1_CSI2 0xd18
1060 #define ROFDM1_CFOTRACKING 0xd2c
1061 #define ROFDM1_TRXMESAURE1 0xd34
1062 #define ROFDM1_INTF_DET 0xd3c
1063 #define ROFDM1_PSEUDO_NOISESTATEAB 0xd50
1064 #define ROFDM1_PSEUDO_NOISESTATECD 0xd54
1065 #define ROFDM1_RX_PSEUDO_NOISE_WGT 0xd58
1067 #define ROFDM_PHYCOUNTER1 0xda0
1068 #define ROFDM_PHYCOUNTER2 0xda4
1069 #define ROFDM_PHYCOUNTER3 0xda8
1071 #define ROFDM_SHORT_CFOAB 0xdac
1072 #define ROFDM_SHORT_CFOCD 0xdb0
1073 #define ROFDM_LONG_CFOAB 0xdb4
1074 #define ROFDM_LONG_CFOCD 0xdb8
1075 #define ROFDM_TAIL_CFOAB 0xdbc
1076 #define ROFDM_TAIL_CFOCD 0xdc0
1077 #define ROFDM_PW_MEASURE1 0xdc4
1078 #define ROFDM_PW_MEASURE2 0xdc8
1079 #define ROFDM_BW_REPORT 0xdcc
1080 #define ROFDM_AGC_REPORT 0xdd0
1081 #define ROFDM_RXSNR 0xdd4
1082 #define ROFDM_RXEVMCSI 0xdd8
1083 #define ROFDM_SIG_REPORT 0xddc
1086 #define RTXAGC_RATE18_06 0xe00
1087 #define RTXAGC_RATE54_24 0xe04
1088 #define RTXAGC_CCK_MCS32 0xe08
1089 #define RTXAGC_MCS03_MCS00 0xe10
1090 #define RTXAGC_MCS07_MCS04 0xe14
1091 #define RTXAGC_MCS11_MCS08 0xe18
1092 #define RTXAGC_MCS15_MCS12 0xe1c
1096 #define RF_IQADJ_G1 0x01
1097 #define RF_IQADJ_G2 0x02
1098 #define RF_POW_TRSW 0x05
1099 #define RF_GAIN_RX 0x06
1100 #define RF_GAIN_TX 0x07
1101 #define RF_TXM_IDAC 0x08
1102 #define RF_BS_IQGEN 0x0F
1104 #define RF_MODE1 0x10
1105 #define RF_MODE2 0x11
1106 #define RF_RX_AGC_HP 0x12
1107 #define RF_TX_AGC 0x13
1108 #define RF_BIAS 0x14
1110 #define RF_POW_ABILITY 0x17
1111 #define RF_MODE_AG 0x18
1112 #define RF_CHANNEL 0x18
1113 #define RF_CHNLBW 0x18
1115 #define RF_RX_G1 0x1A
1116 #define RF_RX_G2 0x1B
1117 #define RF_RX_BB2 0x1C
1118 #define RF_RX_BB1 0x1D
1119 #define RF_RCK1 0x1E
1120 #define RF_RCK2 0x1F
1122 #define RF_TX_G1 0x20
1123 #define RF_TX_G2 0x21
1124 #define RF_TX_G3 0x22
1125 #define RF_TX_BB1 0x23
1126 #define RF_T_METER 0x24
1127 #define RF_SYN_G1 0x25
1128 #define RF_SYN_G2 0x26
1129 #define RF_SYN_G3 0x27
1130 #define RF_SYN_G4 0x28
1131 #define RF_SYN_G5 0x29
1132 #define RF_SYN_G6 0x2A
1133 #define RF_SYN_G7 0x2B
1134 #define RF_SYN_G8 0x2C
1136 #define RF_RCK_OS 0x30
1137 #define RF_TXPA_G1 0x31
1138 #define RF_TXPA_G2 0x32
1139 #define RF_TXPA_G3 0x33
1142 #define BCCKEN 0x1000000
1143 #define BOFDMEN 0x2000000
1145 #define BXBTXAGC 0xf00
1146 #define BXCTXAGC 0xf000
1147 #define BXDTXAGC 0xf0000
1149 #define B3WIRE_DATALENGTH 0x800
1150 #define B3WIRE_ADDRESSLENGTH 0x400
1152 #define BRFSI_RFENV 0x10
1154 #define BLSSI_READADDRESS 0x7f800000
1155 #define BLSSI_READEDGE 0x80000000
1156 #define BLSSI_READBACK_DATA 0xfffff
1158 #define BADCLKPHASE 0x4000000
1160 #define BCCK_SIDEBAND 0x10
1162 #define BTX_AGCRATECCK 0x7f00