1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
45 void rtl92se_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
49 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 *((u32 *) (val)) = rtlpci->receive_config;
56 case HW_VAR_RF_STATE: {
57 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
60 case HW_VAR_FW_PSMODE_STATUS: {
61 *((bool *) (val)) = ppsc->fw_current_inpsmode;
64 case HW_VAR_CORRECT_TSF: {
66 u32 *ptsf_low = (u32 *)&tsf;
67 u32 *ptsf_high = ((u32 *)&tsf) + 1;
69 *ptsf_high = rtl_read_dword(rtlpriv, (TSFR + 4));
70 *ptsf_low = rtl_read_dword(rtlpriv, TSFR);
72 *((u64 *) (val)) = tsf;
77 *((bool *)(val)) = rtlpriv->dm.current_mrc_switch;
83 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
84 "switch case %#x not processed\n", variable);
90 void rtl92se_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
95 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
96 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
97 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
100 case HW_VAR_ETHER_ADDR:{
101 rtl_write_dword(rtlpriv, IDR0, ((u32 *)(val))[0]);
102 rtl_write_word(rtlpriv, IDR4, ((u16 *)(val + 4))[0]);
105 case HW_VAR_BASIC_RATE:{
106 u16 rate_cfg = ((u16 *) val)[0];
109 if (rtlhal->version == VERSION_8192S_ACUT)
110 rate_cfg = rate_cfg & 0x150;
112 rate_cfg = rate_cfg & 0x15f;
116 rtl_write_byte(rtlpriv, RRSR, rate_cfg & 0xff);
117 rtl_write_byte(rtlpriv, RRSR + 1,
118 (rate_cfg >> 8) & 0xff);
120 while (rate_cfg > 0x1) {
121 rate_cfg = (rate_cfg >> 1);
124 rtl_write_byte(rtlpriv, INIRTSMCS_SEL, rate_index);
129 rtl_write_dword(rtlpriv, BSSIDR, ((u32 *)(val))[0]);
130 rtl_write_word(rtlpriv, BSSIDR + 4,
131 ((u16 *)(val + 4))[0]);
135 rtl_write_byte(rtlpriv, SIFS_OFDM, val[0]);
136 rtl_write_byte(rtlpriv, SIFS_OFDM + 1, val[1]);
139 case HW_VAR_SLOT_TIME:{
142 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
143 "HW_VAR_SLOT_TIME %x\n", val[0]);
145 rtl_write_byte(rtlpriv, SLOT_TIME, val[0]);
147 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
148 rtlpriv->cfg->ops->set_hw_reg(hw,
154 case HW_VAR_ACK_PREAMBLE:{
156 u8 short_preamble = (bool) (*val);
157 reg_tmp = (mac->cur_40_prime_sc) << 5;
161 rtl_write_byte(rtlpriv, RRSR + 2, reg_tmp);
164 case HW_VAR_AMPDU_MIN_SPACE:{
165 u8 min_spacing_to_set;
168 min_spacing_to_set = *val;
169 if (min_spacing_to_set <= 7) {
170 if (rtlpriv->sec.pairwise_enc_algorithm ==
176 if (min_spacing_to_set < sec_min_space)
177 min_spacing_to_set = sec_min_space;
178 if (min_spacing_to_set > 5)
179 min_spacing_to_set = 5;
182 ((mac->min_space_cfg & 0xf8) |
185 *val = min_spacing_to_set;
187 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
188 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
191 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
196 case HW_VAR_SHORTGI_DENSITY:{
199 density_to_set = *val;
200 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
201 mac->min_space_cfg |= (density_to_set << 3);
203 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
204 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
207 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE,
212 case HW_VAR_AMPDU_FACTOR:{
215 u8 factorlevel[18] = {
216 2, 4, 4, 7, 7, 13, 13,
222 if (factor_toset <= 3) {
223 factor_toset = (1 << (factor_toset + 2));
224 if (factor_toset > 0xf)
227 for (index = 0; index < 17; index++) {
228 if (factorlevel[index] > factor_toset)
233 for (index = 0; index < 8; index++) {
234 regtoset = ((factorlevel[index * 2]) |
237 rtl_write_byte(rtlpriv,
238 AGGLEN_LMT_L + index,
242 regtoset = ((factorlevel[16]) |
243 (factorlevel[17] << 4));
244 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, regtoset);
246 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
247 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
252 case HW_VAR_AC_PARAM:{
254 rtl92s_dm_init_edca_turbo(hw);
256 if (rtlpci->acm_method != EACMWAY2_SW)
257 rtlpriv->cfg->ops->set_hw_reg(hw,
262 case HW_VAR_ACM_CTRL:{
264 union aci_aifsn *p_aci_aifsn = (union aci_aifsn *)(&(
266 u8 acm = p_aci_aifsn->f.acm;
267 u8 acm_ctrl = rtl_read_byte(rtlpriv, AcmHwCtrl);
269 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ?
275 acm_ctrl |= AcmHw_BeqEn;
278 acm_ctrl |= AcmHw_ViqEn;
281 acm_ctrl |= AcmHw_VoqEn;
284 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
285 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
292 acm_ctrl &= (~AcmHw_BeqEn);
295 acm_ctrl &= (~AcmHw_ViqEn);
298 acm_ctrl &= (~AcmHw_VoqEn);
301 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
302 "switch case %#x not processed\n",
308 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
309 "HW_VAR_ACM_CTRL Write 0x%X\n", acm_ctrl);
310 rtl_write_byte(rtlpriv, AcmHwCtrl, acm_ctrl);
314 rtl_write_dword(rtlpriv, RCR, ((u32 *) (val))[0]);
315 rtlpci->receive_config = ((u32 *) (val))[0];
318 case HW_VAR_RETRY_LIMIT:{
319 u8 retry_limit = val[0];
321 rtl_write_word(rtlpriv, RETRY_LIMIT,
322 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
323 retry_limit << RETRY_LIMIT_LONG_SHIFT);
326 case HW_VAR_DUAL_TSF_RST: {
329 case HW_VAR_EFUSE_BYTES: {
330 rtlefuse->efuse_usedbytes = *((u16 *) val);
333 case HW_VAR_EFUSE_USAGE: {
334 rtlefuse->efuse_usedpercentage = *val;
337 case HW_VAR_IO_CMD: {
340 case HW_VAR_WPA_CONFIG: {
341 rtl_write_byte(rtlpriv, REG_SECR, *val);
344 case HW_VAR_SET_RPWM:{
347 case HW_VAR_H2C_FW_PWRMODE:{
350 case HW_VAR_FW_PSMODE_STATUS: {
351 ppsc->fw_current_inpsmode = *((bool *) val);
354 case HW_VAR_H2C_FW_JOINBSSRPT:{
360 case HW_VAR_CORRECT_TSF:{
364 bool bmrc_toset = *((bool *)val);
368 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
370 u1bdata = (u8)rtl_get_bbreg(hw,
371 ROFDM1_TRXPATHENABLE,
373 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
375 ((u1bdata & 0xf0) | 0x03));
376 u1bdata = (u8)rtl_get_bbreg(hw,
377 ROFDM0_TRXPATHENABLE,
379 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
383 /* Update current settings. */
384 rtlpriv->dm.current_mrc_switch = bmrc_toset;
386 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
388 u1bdata = (u8)rtl_get_bbreg(hw,
389 ROFDM1_TRXPATHENABLE,
391 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE,
393 ((u1bdata & 0xf0) | 0x01));
394 u1bdata = (u8)rtl_get_bbreg(hw,
395 ROFDM0_TRXPATHENABLE,
397 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE,
398 MASKBYTE1, (u1bdata & 0xfb));
400 /* Update current settings. */
401 rtlpriv->dm.current_mrc_switch = bmrc_toset;
406 case HW_VAR_FW_LPS_ACTION: {
407 bool enter_fwlps = *((bool *)val);
408 u8 rpwm_val, fw_pwrmode;
409 bool fw_current_inps;
412 rpwm_val = 0x02; /* RF off */
413 fw_current_inps = true;
414 rtlpriv->cfg->ops->set_hw_reg(hw,
415 HW_VAR_FW_PSMODE_STATUS,
416 (u8 *)(&fw_current_inps));
417 rtlpriv->cfg->ops->set_hw_reg(hw,
418 HW_VAR_H2C_FW_PWRMODE,
419 &ppsc->fwctrl_psmode);
421 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
424 rpwm_val = 0x0C; /* RF on */
425 fw_pwrmode = FW_PS_ACTIVE_MODE;
426 fw_current_inps = false;
427 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
429 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
432 rtlpriv->cfg->ops->set_hw_reg(hw,
433 HW_VAR_FW_PSMODE_STATUS,
434 (u8 *)(&fw_current_inps));
438 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
439 "switch case %#x not processed\n", variable);
445 void rtl92se_enable_hw_security_config(struct ieee80211_hw *hw)
447 struct rtl_priv *rtlpriv = rtl_priv(hw);
448 u8 sec_reg_value = 0x0;
450 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
451 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
452 rtlpriv->sec.pairwise_enc_algorithm,
453 rtlpriv->sec.group_enc_algorithm);
455 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
456 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
457 "not open hw encryption\n");
461 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
463 if (rtlpriv->sec.use_defaultkey) {
464 sec_reg_value |= SCR_TXUSEDK;
465 sec_reg_value |= SCR_RXUSEDK;
468 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
471 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
475 static u8 _rtl92se_halset_sysclk(struct ieee80211_hw *hw, u8 data)
477 struct rtl_priv *rtlpriv = rtl_priv(hw);
479 bool bresult = false;
482 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
484 /* Wait the MAC synchronized. */
487 /* Check if it is set ready. */
488 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
489 bresult = ((tmpvalue & BIT(7)) == (data & BIT(7)));
491 if ((data & (BIT(6) | BIT(7))) == false) {
498 tmpvalue = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
499 if ((tmpvalue & BIT(6)))
502 pr_err("wait for BIT(6) return value %x\n", tmpvalue);
518 void rtl8192se_gpiobit3_cfg_inputmode(struct ieee80211_hw *hw)
520 struct rtl_priv *rtlpriv = rtl_priv(hw);
523 /* The following config GPIO function */
524 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
525 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
527 /* config GPIO3 to input */
528 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
529 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
533 static u8 _rtl92se_rf_onoff_detect(struct ieee80211_hw *hw)
535 struct rtl_priv *rtlpriv = rtl_priv(hw);
539 /* The following config GPIO function */
540 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, (GPIOMUX_EN | GPIOSEL_GPIO));
541 u1tmp = rtl_read_byte(rtlpriv, GPIO_IO_SEL);
543 /* config GPIO3 to input */
544 u1tmp &= HAL_8192S_HW_GPIO_OFF_MASK;
545 rtl_write_byte(rtlpriv, GPIO_IO_SEL, u1tmp);
547 /* On some of the platform, driver cannot read correct
548 * value without delay between Write_GPIO_SEL and Read_GPIO_IN */
552 u1tmp = rtl_read_byte(rtlpriv, GPIO_IN_SE);
553 retval = (u1tmp & HAL_8192S_HW_GPIO_OFF_BIT) ? ERFON : ERFOFF;
558 static void _rtl92se_macconfig_before_fwdownload(struct ieee80211_hw *hw)
560 struct rtl_priv *rtlpriv = rtl_priv(hw);
561 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
562 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
569 if (rtlpci->first_init) {
570 /* Reset PCIE Digital */
571 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
573 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
575 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b | BIT(0));
578 /* Switch to SW IO control */
579 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
580 if (tmpu1b & BIT(7)) {
581 tmpu1b &= ~(BIT(6) | BIT(7));
583 /* Set failed, return to prevent hang. */
584 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
588 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
590 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
593 /* Clear FW RPWM for FW control LPS.*/
594 rtl_write_byte(rtlpriv, RPWM, 0x0);
596 /* Reset MAC-IO and CPU and Core Digital BIT(10)/11/15 */
597 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
599 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
600 /* wait for BIT 10/11/15 to pull high automatically!! */
603 rtl_write_byte(rtlpriv, CMDR, 0);
604 rtl_write_byte(rtlpriv, TCR, 0);
606 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
607 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
609 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
611 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
613 /* Enable AFE clock source */
614 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
615 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
618 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
619 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
621 /* Enable AFE Macro Block's Bandgap */
622 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
623 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
626 /* Enable AFE Mbias */
627 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
628 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
631 /* Enable LDOA15 block */
632 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
633 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
635 /* Set Digital Vdd to Retention isolation Path. */
636 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
637 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
639 /* For warm reboot NIC disappera bug. */
640 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
641 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
643 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
645 /* Enable AFE PLL Macro Block */
646 /* We need to delay 100u before enabling PLL. */
648 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
649 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
651 /* for divider reset */
653 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) |
656 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
659 /* Enable MAC 80MHZ clock */
660 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
661 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
664 /* Release isolation AFE PLL & MD */
665 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
667 /* Enable MAC clock */
668 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
669 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
671 /* Enable Core digital and enable IOREG R/W */
672 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
673 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
675 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
676 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b & ~(BIT(7)));
679 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
681 /* Switch the control path. */
682 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
683 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
685 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
686 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
687 if (!_rtl92se_halset_sysclk(hw, tmpu1b))
688 return; /* Set failed, return to prevent hang. */
690 rtl_write_word(rtlpriv, CMDR, 0x07FC);
692 /* MH We must enable the section of code to prevent load IMEM fail. */
693 /* Load MAC register from WMAc temporarily We simulate macreg. */
694 /* txt HW will provide MAC txt later */
695 rtl_write_byte(rtlpriv, 0x6, 0x30);
696 rtl_write_byte(rtlpriv, 0x49, 0xf0);
698 rtl_write_byte(rtlpriv, 0x4b, 0x81);
700 rtl_write_byte(rtlpriv, 0xb5, 0x21);
702 rtl_write_byte(rtlpriv, 0xdc, 0xff);
703 rtl_write_byte(rtlpriv, 0xdd, 0xff);
704 rtl_write_byte(rtlpriv, 0xde, 0xff);
705 rtl_write_byte(rtlpriv, 0xdf, 0xff);
707 rtl_write_byte(rtlpriv, 0x11a, 0x00);
708 rtl_write_byte(rtlpriv, 0x11b, 0x00);
710 for (i = 0; i < 32; i++)
711 rtl_write_byte(rtlpriv, INIMCS_SEL + i, 0x1b);
713 rtl_write_byte(rtlpriv, 0x236, 0xff);
715 rtl_write_byte(rtlpriv, 0x503, 0x22);
717 if (ppsc->support_aspm && !ppsc->support_backdoor)
718 rtl_write_byte(rtlpriv, 0x560, 0x40);
720 rtl_write_byte(rtlpriv, 0x560, 0x00);
722 rtl_write_byte(rtlpriv, DBG_PORT, 0x91);
724 /* Set RX Desc Address */
725 rtl_write_dword(rtlpriv, RDQDA, rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
726 rtl_write_dword(rtlpriv, RCDA, rtlpci->rx_ring[RX_CMD_QUEUE].dma);
728 /* Set TX Desc Address */
729 rtl_write_dword(rtlpriv, TBKDA, rtlpci->tx_ring[BK_QUEUE].dma);
730 rtl_write_dword(rtlpriv, TBEDA, rtlpci->tx_ring[BE_QUEUE].dma);
731 rtl_write_dword(rtlpriv, TVIDA, rtlpci->tx_ring[VI_QUEUE].dma);
732 rtl_write_dword(rtlpriv, TVODA, rtlpci->tx_ring[VO_QUEUE].dma);
733 rtl_write_dword(rtlpriv, TBDA, rtlpci->tx_ring[BEACON_QUEUE].dma);
734 rtl_write_dword(rtlpriv, TCDA, rtlpci->tx_ring[TXCMD_QUEUE].dma);
735 rtl_write_dword(rtlpriv, TMDA, rtlpci->tx_ring[MGNT_QUEUE].dma);
736 rtl_write_dword(rtlpriv, THPDA, rtlpci->tx_ring[HIGH_QUEUE].dma);
737 rtl_write_dword(rtlpriv, HDA, rtlpci->tx_ring[HCCA_QUEUE].dma);
739 rtl_write_word(rtlpriv, CMDR, 0x37FC);
741 /* To make sure that TxDMA can ready to download FW. */
742 /* We should reset TxDMA if IMEM RPT was not ready. */
744 tmpu1b = rtl_read_byte(rtlpriv, TCR);
745 if ((tmpu1b & TXDMA_INIT_VALUE) == TXDMA_INIT_VALUE)
749 } while (pollingcnt--);
751 if (pollingcnt <= 0) {
752 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
753 "Polling TXDMA_INIT_VALUE timeout!! Current TCR(%#x)\n",
755 tmpu1b = rtl_read_byte(rtlpriv, CMDR);
756 rtl_write_byte(rtlpriv, CMDR, tmpu1b & (~TXDMA_EN));
759 rtl_write_byte(rtlpriv, CMDR, tmpu1b | TXDMA_EN);
762 /* After MACIO reset,we must refresh LED state. */
763 if ((ppsc->rfoff_reason == RF_CHANGE_BY_IPS) ||
764 (ppsc->rfoff_reason == 0)) {
765 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
766 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
767 enum rf_pwrstate rfpwr_state_toset;
768 rfpwr_state_toset = _rtl92se_rf_onoff_detect(hw);
770 if (rfpwr_state_toset == ERFON)
771 rtl92se_sw_led_on(hw, pLed0);
775 static void _rtl92se_macconfig_after_fwdownload(struct ieee80211_hw *hw)
777 struct rtl_priv *rtlpriv = rtl_priv(hw);
778 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
779 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
780 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
784 /* 1. System Configure Register (Offset: 0x0000 - 0x003F) */
786 /* 2. Command Control Register (Offset: 0x0040 - 0x004F) */
787 /* Turn on 0x40 Command register */
788 rtl_write_word(rtlpriv, CMDR, (BBRSTN | BB_GLB_RSTN |
789 SCHEDULE_EN | MACRXEN | MACTXEN | DDMA_EN | FW2HW_EN |
790 RXDMA_EN | TXDMA_EN | HCI_RXDMA_EN | HCI_TXDMA_EN));
792 /* Set TCR TX DMA pre 2 FULL enable bit */
793 rtl_write_dword(rtlpriv, TCR, rtl_read_dword(rtlpriv, TCR) |
797 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
799 /* 3. MACID Setting Register (Offset: 0x0050 - 0x007F) */
801 /* 4. Timing Control Register (Offset: 0x0080 - 0x009F) */
802 /* Set CCK/OFDM SIFS */
803 /* CCK SIFS shall always be 10us. */
804 rtl_write_word(rtlpriv, SIFS_CCK, 0x0a0a);
805 rtl_write_word(rtlpriv, SIFS_OFDM, 0x1010);
808 rtl_write_byte(rtlpriv, ACK_TIMEOUT, 0x40);
811 rtl_write_word(rtlpriv, BCN_INTERVAL, 100);
812 rtl_write_word(rtlpriv, ATIMWND, 2);
814 /* 5. FIFO Control Register (Offset: 0x00A0 - 0x015F) */
815 /* 5.1 Initialize Number of Reserved Pages in Firmware Queue */
816 /* Firmware allocate now, associate with FW internal setting.!!! */
818 /* 5.2 Setting TX/RX page size 0/1/2/3/4=64/128/256/512/1024 */
819 /* 5.3 Set driver info, we only accept PHY status now. */
820 /* 5.4 Set RXDMA arbitration to control RXDMA/MAC/FW R/W for RXFIFO */
821 rtl_write_byte(rtlpriv, RXDMA, rtl_read_byte(rtlpriv, RXDMA) | BIT(6));
823 /* 6. Adaptive Control Register (Offset: 0x0160 - 0x01CF) */
824 /* Set RRSR to all legacy rate and HT rate
825 * CCK rate is supported by default.
826 * CCK rate will be filtered out only when associated
827 * AP does not support it.
828 * Only enable ACK rate to OFDM 24M
829 * Disable RRSR for CCK rate in A-Cut */
831 if (rtlhal->version == VERSION_8192S_ACUT)
832 rtl_write_byte(rtlpriv, RRSR, 0xf0);
833 else if (rtlhal->version == VERSION_8192S_BCUT)
834 rtl_write_byte(rtlpriv, RRSR, 0xff);
835 rtl_write_byte(rtlpriv, RRSR + 1, 0x01);
836 rtl_write_byte(rtlpriv, RRSR + 2, 0x00);
838 /* A-Cut IC do not support CCK rate. We forbid ARFR to */
839 /* fallback to CCK rate */
840 for (i = 0; i < 8; i++) {
841 /*Disable RRSR for CCK rate in A-Cut */
842 if (rtlhal->version == VERSION_8192S_ACUT)
843 rtl_write_dword(rtlpriv, ARFR0 + i * 4, 0x1f0ff0f0);
846 /* Different rate use different AMPDU size */
847 /* MCS32/ MCS15_SG use max AMPDU size 15*2=30K */
848 rtl_write_byte(rtlpriv, AGGLEN_LMT_H, 0x0f);
849 /* MCS0/1/2/3 use max AMPDU size 4*2=8K */
850 rtl_write_word(rtlpriv, AGGLEN_LMT_L, 0x7442);
851 /* MCS4/5 use max AMPDU size 8*2=16K 6/7 use 10*2=20K */
852 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 2, 0xddd7);
853 /* MCS8/9 use max AMPDU size 8*2=16K 10/11 use 10*2=20K */
854 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 4, 0xd772);
855 /* MCS12/13/14/15 use max AMPDU size 15*2=30K */
856 rtl_write_word(rtlpriv, AGGLEN_LMT_L + 6, 0xfffd);
858 /* Set Data / Response auto rate fallack retry count */
859 rtl_write_dword(rtlpriv, DARFRC, 0x04010000);
860 rtl_write_dword(rtlpriv, DARFRC + 4, 0x09070605);
861 rtl_write_dword(rtlpriv, RARFRC, 0x04010000);
862 rtl_write_dword(rtlpriv, RARFRC + 4, 0x09070605);
864 /* 7. EDCA Setting Register (Offset: 0x01D0 - 0x01FF) */
865 /* Set all rate to support SG */
866 rtl_write_word(rtlpriv, SG_RATE, 0xFFFF);
868 /* 8. WMAC, BA, and CCX related Register (Offset: 0x0200 - 0x023F) */
869 /* Set NAV protection length */
870 rtl_write_word(rtlpriv, NAV_PROT_LEN, 0x0080);
871 /* CF-END Threshold */
872 rtl_write_byte(rtlpriv, CFEND_TH, 0xFF);
873 /* Set AMPDU minimum space */
874 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, 0x07);
875 /* Set TXOP stall control for several queue/HI/BCN/MGT/ */
876 rtl_write_byte(rtlpriv, TXOP_STALL_CTRL, 0x00);
878 /* 9. Security Control Register (Offset: 0x0240 - 0x025F) */
879 /* 10. Power Save Control Register (Offset: 0x0260 - 0x02DF) */
880 /* 11. General Purpose Register (Offset: 0x02E0 - 0x02FF) */
881 /* 12. Host Interrupt Status Register (Offset: 0x0300 - 0x030F) */
882 /* 13. Test Mode and Debug Control Register (Offset: 0x0310 - 0x034F) */
884 /* 14. Set driver info, we only accept PHY status now. */
885 rtl_write_byte(rtlpriv, RXDRVINFO_SZ, 4);
887 /* 15. For EEPROM R/W Workaround */
888 /* 16. For EFUSE to share REG_SYS_FUNC_EN with EEPROM!!! */
889 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN);
890 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, tmpu2b | BIT(13));
891 tmpu2b = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
892 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, tmpu2b & (~BIT(8)));
895 /* We may R/W EFUSE in EEPROM mode */
896 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
899 tempval = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL + 1);
901 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, tempval);
903 /* Change Program timing */
904 rtl_write_byte(rtlpriv, REG_EFUSE_CTRL + 3, 0x72);
905 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "EFUSE CONFIG OK\n");
908 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
912 static void _rtl92se_hw_configure(struct ieee80211_hw *hw)
914 struct rtl_priv *rtlpriv = rtl_priv(hw);
915 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
916 struct rtl_phy *rtlphy = &(rtlpriv->phy);
917 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
919 u8 reg_bw_opmode = 0;
923 reg_bw_opmode = BW_OPMODE_20MHZ;
924 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
926 regtmp = rtl_read_byte(rtlpriv, INIRTSMCS_SEL);
927 reg_rrsr = ((reg_rrsr & 0x000fffff) << 8) | regtmp;
928 rtl_write_dword(rtlpriv, INIRTSMCS_SEL, reg_rrsr);
929 rtl_write_byte(rtlpriv, BW_OPMODE, reg_bw_opmode);
931 /* Set Retry Limit here */
932 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
933 (u8 *)(&rtlpci->shortretry_limit));
935 rtl_write_byte(rtlpriv, MLT, 0x8f);
937 /* For Min Spacing configuration. */
938 switch (rtlphy->rf_type) {
941 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
945 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
948 rtl_write_byte(rtlpriv, AMPDU_MIN_SPACE, rtlhal->minspace_cfg);
951 int rtl92se_hw_init(struct ieee80211_hw *hw)
953 struct rtl_priv *rtlpriv = rtl_priv(hw);
954 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
955 struct rtl_phy *rtlphy = &(rtlpriv->phy);
956 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
957 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
960 bool rtstatus = true;
964 int wdcapra_add[] = {
965 EDCAPARA_BE, EDCAPARA_BK,
966 EDCAPARA_VI, EDCAPARA_VO};
969 rtlpci->being_init_adapter = true;
971 /* As this function can take a very long time (up to 350 ms)
972 * and can be called with irqs disabled, reenable the irqs
973 * to let the other devices continue being serviced.
975 * It is safe doing so since our own interrupts will only be enabled
976 * in a subsequent step.
978 local_save_flags(flags);
981 rtlpriv->intf_ops->disable_aspm(hw);
983 /* 1. MAC Initialize */
984 /* Before FW download, we have to set some MAC register */
985 _rtl92se_macconfig_before_fwdownload(hw);
987 rtlhal->version = (enum version_8192s)((rtl_read_dword(rtlpriv,
988 PMC_FSM) >> 16) & 0xF);
990 rtl8192se_gpiobit3_cfg_inputmode(hw);
992 /* 2. download firmware */
993 rtstatus = rtl92s_download_fw(hw);
995 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
996 "Failed to download FW. Init HW without FW now... "
997 "Please copy FW into /lib/firmware/rtlwifi\n");
1002 /* After FW download, we have to reset MAC register */
1003 _rtl92se_macconfig_after_fwdownload(hw);
1005 /*Retrieve default FW Cmd IO map. */
1006 rtlhal->fwcmd_iomap = rtl_read_word(rtlpriv, LBUS_MON_ADDR);
1007 rtlhal->fwcmd_ioparam = rtl_read_dword(rtlpriv, LBUS_ADDR_MASK);
1009 /* 3. Initialize MAC/PHY Config by MACPHY_reg.txt */
1010 if (!rtl92s_phy_mac_config(hw)) {
1011 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "MAC Config failed\n");
1016 /* because last function modify RCR, so we update
1017 * rcr var here, or TP will unstable for receive_config
1018 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1019 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1021 rtlpci->receive_config = rtl_read_dword(rtlpriv, RCR);
1022 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1023 rtl_write_dword(rtlpriv, RCR, rtlpci->receive_config);
1025 /* Make sure BB/RF write OK. We should prevent enter IPS. radio off. */
1026 /* We must set flag avoid BB/RF config period later!! */
1027 rtl_write_dword(rtlpriv, CMDR, 0x37FC);
1029 /* 4. Initialize BB After MAC Config PHY_reg.txt, AGC_Tab.txt */
1030 if (!rtl92s_phy_bb_config(hw)) {
1031 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "BB Config failed\n");
1036 /* 5. Initiailze RF RAIO_A.txt RF RAIO_B.txt */
1037 /* Before initalizing RF. We can not use FW to do RF-R/W. */
1039 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1041 /* Before RF-R/W we must execute the IO from Scott's suggestion. */
1042 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, 0xDB);
1043 if (rtlhal->version == VERSION_8192S_ACUT)
1044 rtl_write_byte(rtlpriv, SPS1_CTRL + 3, 0x07);
1046 rtl_write_byte(rtlpriv, RF_CTRL, 0x07);
1048 if (!rtl92s_phy_rf_config(hw)) {
1049 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RF Config failed\n");
1054 /* After read predefined TXT, we must set BB/MAC/RF
1055 * register as our requirement */
1057 rtlphy->rfreg_chnlval[0] = rtl92s_phy_query_rf_reg(hw,
1061 rtlphy->rfreg_chnlval[1] = rtl92s_phy_query_rf_reg(hw,
1066 /*---- Set CCK and OFDM Block "ON"----*/
1067 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1068 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1070 /*3 Set Hardware(Do nothing now) */
1071 _rtl92se_hw_configure(hw);
1073 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1074 /* TX power index for different rate set. */
1075 /* Get original hw reg values */
1076 rtl92s_phy_get_hw_reg_originalvalue(hw);
1077 /* Write correct tx power index */
1078 rtl92s_phy_set_txpower(hw, rtlphy->current_channel);
1080 /* We must set MAC address after firmware download. */
1081 for (i = 0; i < 6; i++)
1082 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1084 /* EEPROM R/W workaround */
1085 tmp_u1b = rtl_read_byte(rtlpriv, MAC_PINMUX_CFG);
1086 rtl_write_byte(rtlpriv, MAC_PINMUX_CFG, tmp_u1b & (~BIT(3)));
1088 rtl_write_byte(rtlpriv, 0x4d, 0x0);
1090 if (hal_get_firmwareversion(rtlpriv) >= 0x49) {
1091 tmp_byte = rtl_read_byte(rtlpriv, FW_RSVD_PG_CRTL) & (~BIT(4));
1092 tmp_byte = tmp_byte | BIT(5);
1093 rtl_write_byte(rtlpriv, FW_RSVD_PG_CRTL, tmp_byte);
1094 rtl_write_dword(rtlpriv, TXDESC_MSK, 0xFFFFCFFF);
1097 /* We enable high power and RA related mechanism after NIC
1099 if (hal_get_firmwareversion(rtlpriv) >= 0x35) {
1100 /* Fw v.53 and later. */
1101 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_INIT);
1102 } else if (hal_get_firmwareversion(rtlpriv) == 0x34) {
1104 rtl_write_dword(rtlpriv, WFM5, FW_RA_INIT);
1105 rtl92s_phy_chk_fwcmd_iodone(hw);
1107 /* Compatible earlier FW version. */
1108 rtl_write_dword(rtlpriv, WFM5, FW_RA_RESET);
1109 rtl92s_phy_chk_fwcmd_iodone(hw);
1110 rtl_write_dword(rtlpriv, WFM5, FW_RA_ACTIVE);
1111 rtl92s_phy_chk_fwcmd_iodone(hw);
1112 rtl_write_dword(rtlpriv, WFM5, FW_RA_REFRESH);
1113 rtl92s_phy_chk_fwcmd_iodone(hw);
1116 /* Add to prevent ASPM bug. */
1117 /* Always enable hst and NIC clock request. */
1118 rtl92s_phy_switch_ephy_parameter(hw);
1121 * 1. Clear all H/W keys.
1122 * 2. Enable H/W encryption/decryption. */
1123 rtl_cam_reset_all_entry(hw);
1124 secr_value |= SCR_TXENCENABLE;
1125 secr_value |= SCR_RXENCENABLE;
1126 secr_value |= SCR_NOSKMC;
1127 rtl_write_byte(rtlpriv, REG_SECR, secr_value);
1129 for (i = 0; i < 4; i++)
1130 rtl_write_dword(rtlpriv, wdcapra_add[i], 0x5e4322);
1132 if (rtlphy->rf_type == RF_1T2R) {
1133 bool mrc2set = true;
1134 /* Turn on B-Path */
1135 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MRC, (u8 *)&mrc2set);
1138 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_ON);
1141 local_irq_restore(flags);
1142 rtlpci->being_init_adapter = false;
1146 void rtl92se_set_mac_addr(struct rtl_io *io, const u8 *addr)
1148 /* This is a stub. */
1151 void rtl92se_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1153 struct rtl_priv *rtlpriv = rtl_priv(hw);
1156 if (rtlpriv->psc.rfpwr_state != ERFON)
1159 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1162 reg_rcr |= (RCR_CBSSID);
1163 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1164 } else if (!check_bssid) {
1165 reg_rcr &= (~RCR_CBSSID);
1166 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1171 static int _rtl92se_set_media_status(struct ieee80211_hw *hw,
1172 enum nl80211_iftype type)
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1177 bt_msr &= ~MSR_LINK_MASK;
1180 case NL80211_IFTYPE_UNSPECIFIED:
1181 bt_msr |= (MSR_LINK_NONE << MSR_LINK_SHIFT);
1182 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1183 "Set Network type to NO LINK!\n");
1185 case NL80211_IFTYPE_ADHOC:
1186 bt_msr |= (MSR_LINK_ADHOC << MSR_LINK_SHIFT);
1187 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1188 "Set Network type to Ad Hoc!\n");
1190 case NL80211_IFTYPE_STATION:
1191 bt_msr |= (MSR_LINK_MANAGED << MSR_LINK_SHIFT);
1192 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1193 "Set Network type to STA!\n");
1195 case NL80211_IFTYPE_AP:
1196 bt_msr |= (MSR_LINK_MASTER << MSR_LINK_SHIFT);
1197 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1198 "Set Network type to AP!\n");
1201 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1202 "Network type %d not supported!\n", type);
1207 if (type != NL80211_IFTYPE_AP &&
1208 rtlpriv->mac80211.link_state < MAC80211_LINKED)
1209 bt_msr = rtl_read_byte(rtlpriv, MSR) & ~MSR_LINK_MASK;
1210 rtl_write_byte(rtlpriv, MSR, bt_msr);
1212 temp = rtl_read_dword(rtlpriv, TCR);
1213 rtl_write_dword(rtlpriv, TCR, temp & (~BIT(8)));
1214 rtl_write_dword(rtlpriv, TCR, temp | BIT(8));
1220 /* HW_VAR_MEDIA_STATUS & HW_VAR_CECHK_BSSID */
1221 int rtl92se_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1223 struct rtl_priv *rtlpriv = rtl_priv(hw);
1225 if (_rtl92se_set_media_status(hw, type))
1228 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1229 if (type != NL80211_IFTYPE_AP)
1230 rtl92se_set_check_bssid(hw, true);
1232 rtl92se_set_check_bssid(hw, false);
1238 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1239 void rtl92se_set_qos(struct ieee80211_hw *hw, int aci)
1241 struct rtl_priv *rtlpriv = rtl_priv(hw);
1242 rtl92s_dm_init_edca_turbo(hw);
1246 rtl_write_dword(rtlpriv, EDCAPARA_BK, 0xa44f);
1249 /* rtl_write_dword(rtlpriv, EDCAPARA_BE, u4b_ac_param); */
1252 rtl_write_dword(rtlpriv, EDCAPARA_VI, 0x5e4322);
1255 rtl_write_dword(rtlpriv, EDCAPARA_VO, 0x2f3222);
1258 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1263 void rtl92se_enable_interrupt(struct ieee80211_hw *hw)
1265 struct rtl_priv *rtlpriv = rtl_priv(hw);
1266 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1268 rtl_write_dword(rtlpriv, INTA_MASK, rtlpci->irq_mask[0]);
1269 /* Support Bit 32-37(Assign as Bit 0-5) interrupt setting now */
1270 rtl_write_dword(rtlpriv, INTA_MASK + 4, rtlpci->irq_mask[1] & 0x3F);
1271 rtlpci->irq_enabled = true;
1274 void rtl92se_disable_interrupt(struct ieee80211_hw *hw)
1276 struct rtl_priv *rtlpriv;
1277 struct rtl_pci *rtlpci;
1279 rtlpriv = rtl_priv(hw);
1280 /* if firmware not available, no interrupts */
1281 if (!rtlpriv || !rtlpriv->max_fw_size)
1283 rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1284 rtl_write_dword(rtlpriv, INTA_MASK, 0);
1285 rtl_write_dword(rtlpriv, INTA_MASK + 4, 0);
1286 rtlpci->irq_enabled = false;
1289 static u8 _rtl92s_set_sysclk(struct ieee80211_hw *hw, u8 data)
1291 struct rtl_priv *rtlpriv = rtl_priv(hw);
1293 bool result = false;
1296 rtl_write_byte(rtlpriv, SYS_CLKR + 1, data);
1298 /* Wait the MAC synchronized. */
1301 /* Check if it is set ready. */
1302 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1303 result = ((tmp & BIT(7)) == (data & BIT(7)));
1305 if ((data & (BIT(6) | BIT(7))) == false) {
1311 tmp = rtl_read_byte(rtlpriv, SYS_CLKR + 1);
1316 pr_err("wait for BIT(6) return value %x\n", tmp);
1332 static void _rtl92s_phy_set_rfhalt(struct ieee80211_hw *hw)
1334 struct rtl_priv *rtlpriv = rtl_priv(hw);
1335 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1336 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1339 if (rtlhal->driver_going2unload)
1340 rtl_write_byte(rtlpriv, 0x560, 0x0);
1342 /* Power save for BB/RF */
1343 u1btmp = rtl_read_byte(rtlpriv, LDOV12D_CTRL);
1345 rtl_write_byte(rtlpriv, LDOV12D_CTRL, u1btmp);
1346 rtl_write_byte(rtlpriv, SPS1_CTRL, 0x0);
1347 rtl_write_byte(rtlpriv, TXPAUSE, 0xFF);
1348 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1350 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1351 rtl_write_byte(rtlpriv, PHY_CCA, 0x0);
1353 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1355 rtl_write_word(rtlpriv, CMDR, 0x77FC);
1357 rtl_write_word(rtlpriv, CMDR, 0x57FC);
1358 rtl_write_word(rtlpriv, CMDR, 0x0000);
1360 if (rtlhal->driver_going2unload) {
1361 u1btmp = rtl_read_byte(rtlpriv, (REG_SYS_FUNC_EN + 1));
1362 u1btmp &= ~(BIT(0));
1363 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, u1btmp);
1366 u1btmp = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1368 /* Add description. After switch control path. register
1369 * after page1 will be invisible. We can not do any IO
1370 * for register>0x40. After resume&MACIO reset, we need
1371 * to remember previous reg content. */
1372 if (u1btmp & BIT(7)) {
1373 u1btmp &= ~(BIT(6) | BIT(7));
1374 if (!_rtl92s_set_sysclk(hw, u1btmp)) {
1375 pr_err("Switch ctrl path fail\n");
1380 /* Power save for MAC */
1381 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS &&
1382 !rtlhal->driver_going2unload) {
1383 /* enable LED function */
1384 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1385 /* SW/HW radio off or halt adapter!! For example S3/S4 */
1387 /* LED function disable. Power range is about 8mA now. */
1388 /* if write 0xF1 disconnet_pci power
1389 * ifconfig wlan0 down power are both high 35:70 */
1390 /* if write oxF9 disconnet_pci power
1391 * ifconfig wlan0 down power are both low 12:45*/
1392 rtl_write_byte(rtlpriv, 0x03, 0xF9);
1395 rtl_write_byte(rtlpriv, SYS_CLKR + 1, 0x70);
1396 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, 0x68);
1397 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x00);
1398 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1399 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, 0x0E);
1400 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1404 static void _rtl92se_gen_refreshledstate(struct ieee80211_hw *hw)
1406 struct rtl_priv *rtlpriv = rtl_priv(hw);
1407 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1408 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1409 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
1411 if (rtlpci->up_first_time == 1)
1414 if (rtlpriv->psc.rfoff_reason == RF_CHANGE_BY_IPS)
1415 rtl92se_sw_led_on(hw, pLed0);
1417 rtl92se_sw_led_off(hw, pLed0);
1421 static void _rtl92se_power_domain_init(struct ieee80211_hw *hw)
1423 struct rtl_priv *rtlpriv = rtl_priv(hw);
1427 rtlpriv->psc.pwrdomain_protect = true;
1429 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1430 if (tmpu1b & BIT(7)) {
1431 tmpu1b &= ~(BIT(6) | BIT(7));
1432 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1433 rtlpriv->psc.pwrdomain_protect = false;
1438 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, 0x0);
1439 rtl_write_byte(rtlpriv, LDOA15_CTRL, 0x34);
1441 /* Reset MAC-IO and CPU and Core Digital BIT10/11/15 */
1442 tmpu1b = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN + 1);
1444 /* If IPS we need to turn LED on. So we not
1445 * not disable BIT 3/7 of reg3. */
1446 if (rtlpriv->psc.rfoff_reason & (RF_CHANGE_BY_IPS | RF_CHANGE_BY_HW))
1451 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, tmpu1b);
1452 /* wait for BIT 10/11/15 to pull high automatically!! */
1455 rtl_write_byte(rtlpriv, CMDR, 0);
1456 rtl_write_byte(rtlpriv, TCR, 0);
1458 /* Data sheet not define 0x562!!! Copy from WMAC!!!!! */
1459 tmpu1b = rtl_read_byte(rtlpriv, 0x562);
1461 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1462 tmpu1b &= ~(BIT(3));
1463 rtl_write_byte(rtlpriv, 0x562, tmpu1b);
1465 /* Enable AFE clock source */
1466 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL);
1467 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL, (tmpu1b | 0x01));
1470 tmpu1b = rtl_read_byte(rtlpriv, AFE_XTAL_CTRL + 1);
1471 rtl_write_byte(rtlpriv, AFE_XTAL_CTRL + 1, (tmpu1b & 0xfb));
1473 /* Enable AFE Macro Block's Bandgap */
1474 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1475 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | BIT(0)));
1478 /* Enable AFE Mbias */
1479 tmpu1b = rtl_read_byte(rtlpriv, AFE_MISC);
1480 rtl_write_byte(rtlpriv, AFE_MISC, (tmpu1b | 0x02));
1483 /* Enable LDOA15 block */
1484 tmpu1b = rtl_read_byte(rtlpriv, LDOA15_CTRL);
1485 rtl_write_byte(rtlpriv, LDOA15_CTRL, (tmpu1b | BIT(0)));
1487 /* Set Digital Vdd to Retention isolation Path. */
1488 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
1489 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, (tmpu2b | BIT(11)));
1492 /* For warm reboot NIC disappera bug. */
1493 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1494 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(13)));
1496 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x68);
1498 /* Enable AFE PLL Macro Block */
1499 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL);
1500 rtl_write_byte(rtlpriv, AFE_PLL_CTRL, (tmpu1b | BIT(0) | BIT(4)));
1501 /* Enable MAC 80MHZ clock */
1502 tmpu1b = rtl_read_byte(rtlpriv, AFE_PLL_CTRL + 1);
1503 rtl_write_byte(rtlpriv, AFE_PLL_CTRL + 1, (tmpu1b | BIT(0)));
1506 /* Release isolation AFE PLL & MD */
1507 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xA6);
1509 /* Enable MAC clock */
1510 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1511 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b | BIT(12) | BIT(11)));
1513 /* Enable Core digital and enable IOREG R/W */
1514 tmpu2b = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1515 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11)));
1517 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (tmpu2b | BIT(11) | BIT(15)));
1519 /* Switch the control path. */
1520 tmpu2b = rtl_read_word(rtlpriv, SYS_CLKR);
1521 rtl_write_word(rtlpriv, SYS_CLKR, (tmpu2b & (~BIT(2))));
1523 tmpu1b = rtl_read_byte(rtlpriv, (SYS_CLKR + 1));
1524 tmpu1b = ((tmpu1b | BIT(7)) & (~BIT(6)));
1525 if (!_rtl92s_set_sysclk(hw, tmpu1b)) {
1526 rtlpriv->psc.pwrdomain_protect = false;
1530 rtl_write_word(rtlpriv, CMDR, 0x37FC);
1532 /* After MACIO reset,we must refresh LED state. */
1533 _rtl92se_gen_refreshledstate(hw);
1535 rtlpriv->psc.pwrdomain_protect = false;
1538 void rtl92se_card_disable(struct ieee80211_hw *hw)
1540 struct rtl_priv *rtlpriv = rtl_priv(hw);
1541 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1542 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1543 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1544 enum nl80211_iftype opmode;
1547 rtlpriv->intf_ops->enable_aspm(hw);
1549 if (rtlpci->driver_is_goingto_unload ||
1550 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1551 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1553 /* we should chnge GPIO to input mode
1554 * this will drop away current about 25mA*/
1555 rtl8192se_gpiobit3_cfg_inputmode(hw);
1557 /* this is very important for ips power save */
1558 while (wait-- >= 10 && rtlpriv->psc.pwrdomain_protect) {
1559 if (rtlpriv->psc.pwrdomain_protect)
1565 mac->link_state = MAC80211_NOLINK;
1566 opmode = NL80211_IFTYPE_UNSPECIFIED;
1567 _rtl92se_set_media_status(hw, opmode);
1569 _rtl92s_phy_set_rfhalt(hw);
1573 void rtl92se_interrupt_recognized(struct ieee80211_hw *hw, u32 *p_inta,
1576 struct rtl_priv *rtlpriv = rtl_priv(hw);
1577 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1579 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1580 rtl_write_dword(rtlpriv, ISR, *p_inta);
1582 *p_intb = rtl_read_dword(rtlpriv, ISR + 4) & rtlpci->irq_mask[1];
1583 rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1586 void rtl92se_set_beacon_related_registers(struct ieee80211_hw *hw)
1588 struct rtl_priv *rtlpriv = rtl_priv(hw);
1589 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1590 u16 bcntime_cfg = 0;
1591 u16 bcn_cw = 6, bcn_ifs = 0xf;
1592 u16 atim_window = 2;
1594 /* ATIM Window (in unit of TU). */
1595 rtl_write_word(rtlpriv, ATIMWND, atim_window);
1597 /* Beacon interval (in unit of TU). */
1598 rtl_write_word(rtlpriv, BCN_INTERVAL, mac->beacon_interval);
1600 /* DrvErlyInt (in unit of TU). (Time to send
1601 * interrupt to notify driver to change
1602 * beacon content) */
1603 rtl_write_word(rtlpriv, BCN_DRV_EARLY_INT, 10 << 4);
1605 /* BcnDMATIM(in unit of us). Indicates the
1606 * time before TBTT to perform beacon queue DMA */
1607 rtl_write_word(rtlpriv, BCN_DMATIME, 256);
1609 /* Force beacon frame transmission even
1610 * after receiving beacon frame from
1611 * other ad hoc STA */
1612 rtl_write_byte(rtlpriv, BCN_ERR_THRESH, 100);
1614 /* Beacon Time Configuration */
1615 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1616 bcntime_cfg |= (bcn_cw << BCN_TCFG_CW_SHIFT);
1618 /* TODO: bcn_ifs may required to be changed on ASIC */
1619 bcntime_cfg |= bcn_ifs << BCN_TCFG_IFS;
1621 /*for beacon changed */
1622 rtl92s_phy_set_beacon_hwreg(hw, mac->beacon_interval);
1625 void rtl92se_set_beacon_interval(struct ieee80211_hw *hw)
1627 struct rtl_priv *rtlpriv = rtl_priv(hw);
1628 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1629 u16 bcn_interval = mac->beacon_interval;
1631 /* Beacon interval (in unit of TU). */
1632 rtl_write_word(rtlpriv, BCN_INTERVAL, bcn_interval);
1633 /* 2008.10.24 added by tynli for beacon changed. */
1634 rtl92s_phy_set_beacon_hwreg(hw, bcn_interval);
1637 void rtl92se_update_interrupt_mask(struct ieee80211_hw *hw,
1638 u32 add_msr, u32 rm_msr)
1640 struct rtl_priv *rtlpriv = rtl_priv(hw);
1641 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1643 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1647 rtlpci->irq_mask[0] |= add_msr;
1650 rtlpci->irq_mask[0] &= (~rm_msr);
1652 rtl92se_disable_interrupt(hw);
1653 rtl92se_enable_interrupt(hw);
1656 static void _rtl8192se_get_IC_Inferiority(struct ieee80211_hw *hw)
1658 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1659 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1662 rtlhal->ic_class = IC_INFERIORITY_A;
1664 /* Only retrieving while using EFUSE. */
1665 if ((rtlefuse->epromtype == EEPROM_BOOT_EFUSE) &&
1666 !rtlefuse->autoload_failflag) {
1667 efuse_id = efuse_read_1byte(hw, EFUSE_IC_ID_OFFSET);
1669 if (efuse_id == 0xfe)
1670 rtlhal->ic_class = IC_INFERIORITY_B;
1674 static void _rtl92se_read_adapter_info(struct ieee80211_hw *hw)
1676 struct rtl_priv *rtlpriv = rtl_priv(hw);
1677 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1678 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1679 struct device *dev = &rtl_pcipriv(hw)->dev.pdev->dev;
1683 u8 hwinfo[HWSET_MAX_SIZE_92S];
1686 switch (rtlefuse->epromtype) {
1687 case EEPROM_BOOT_EFUSE:
1688 rtl_efuse_shadow_map_update(hw);
1692 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1693 "RTL819X Not boot from eeprom, check it !!\n");
1697 dev_warn(dev, "no efuse data\n");
1701 memcpy(hwinfo, &rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1702 HWSET_MAX_SIZE_92S);
1704 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1705 hwinfo, HWSET_MAX_SIZE_92S);
1707 eeprom_id = *((u16 *)&hwinfo[0]);
1708 if (eeprom_id != RTL8190_EEPROM_ID) {
1709 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1710 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1711 rtlefuse->autoload_failflag = true;
1713 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1714 rtlefuse->autoload_failflag = false;
1717 if (rtlefuse->autoload_failflag)
1720 _rtl8192se_get_IC_Inferiority(hw);
1722 /* Read IC Version && Channel Plan */
1723 /* VID, DID SE 0xA-D */
1724 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1725 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1726 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1727 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1728 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1730 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1731 "EEPROMId = 0x%4x\n", eeprom_id);
1732 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1733 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1734 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1735 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1736 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1737 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1738 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1739 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1741 for (i = 0; i < 6; i += 2) {
1742 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1743 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1746 for (i = 0; i < 6; i++)
1747 rtl_write_byte(rtlpriv, MACIDR0 + i, rtlefuse->dev_addr[i]);
1749 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1751 /* Get Tx Power Level by Channel */
1752 /* Read Tx power of Channel 1 ~ 14 from EEPROM. */
1753 /* 92S suupport RF A & B */
1754 for (rf_path = 0; rf_path < 2; rf_path++) {
1755 for (i = 0; i < 3; i++) {
1756 /* Read CCK RF A & B Tx power */
1757 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1758 hwinfo[EEPROM_TXPOWERBASE + rf_path * 3 + i];
1760 /* Read OFDM RF A & B Tx power for 1T */
1761 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1762 hwinfo[EEPROM_TXPOWERBASE + 6 + rf_path * 3 + i];
1764 /* Read OFDM RF A & B Tx power for 2T */
1765 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[rf_path][i]
1766 = hwinfo[EEPROM_TXPOWERBASE + 12 +
1771 for (rf_path = 0; rf_path < 2; rf_path++)
1772 for (i = 0; i < 3; i++)
1773 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1774 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1776 rtlefuse->eeprom_chnlarea_txpwr_cck
1778 for (rf_path = 0; rf_path < 2; rf_path++)
1779 for (i = 0; i < 3; i++)
1780 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1781 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1783 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1785 for (rf_path = 0; rf_path < 2; rf_path++)
1786 for (i = 0; i < 3; i++)
1787 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1788 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1790 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1793 for (rf_path = 0; rf_path < 2; rf_path++) {
1795 /* Assign dedicated channel tx power */
1796 for (i = 0; i < 14; i++) {
1797 /* channel 1~3 use the same Tx Power Level. */
1807 /* Record A & B CCK /OFDM - 1T/2T Channel area
1809 rtlefuse->txpwrlevel_cck[rf_path][i] =
1810 rtlefuse->eeprom_chnlarea_txpwr_cck
1812 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1813 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1815 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1816 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1820 for (i = 0; i < 14; i++) {
1821 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1822 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1824 rtlefuse->txpwrlevel_cck[rf_path][i],
1825 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1826 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1830 for (rf_path = 0; rf_path < 2; rf_path++) {
1831 for (i = 0; i < 3; i++) {
1832 /* Read Power diff limit. */
1833 rtlefuse->eeprom_pwrgroup[rf_path][i] =
1834 hwinfo[EEPROM_TXPWRGROUP + rf_path * 3 + i];
1838 for (rf_path = 0; rf_path < 2; rf_path++) {
1839 /* Fill Pwr group */
1840 for (i = 0; i < 14; i++) {
1851 rtlefuse->pwrgroup_ht20[rf_path][i] =
1852 (rtlefuse->eeprom_pwrgroup[rf_path][index] &
1854 rtlefuse->pwrgroup_ht40[rf_path][i] =
1855 ((rtlefuse->eeprom_pwrgroup[rf_path][index] &
1858 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1859 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1861 rtlefuse->pwrgroup_ht20[rf_path][i]);
1862 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1863 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1865 rtlefuse->pwrgroup_ht40[rf_path][i]);
1869 for (i = 0; i < 14; i++) {
1870 /* Read tx power difference between HT OFDM 20/40 MHZ */
1881 tempval = hwinfo[EEPROM_TX_PWR_HT20_DIFF + index] & 0xff;
1882 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1883 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1884 ((tempval >> 4) & 0xF);
1886 /* Read OFDM<->HT tx power diff */
1897 tempval = hwinfo[EEPROM_TX_PWR_OFDM_DIFF + index] & 0xff;
1898 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] =
1900 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1901 ((tempval >> 4) & 0xF);
1903 tempval = hwinfo[TX_PWR_SAFETY_CHK];
1904 rtlefuse->txpwr_safetyflag = (tempval & 0x01);
1907 rtlefuse->eeprom_regulatory = 0;
1908 if (rtlefuse->eeprom_version >= 2) {
1910 if (rtlefuse->eeprom_version >= 4)
1911 rtlefuse->eeprom_regulatory =
1912 (hwinfo[EEPROM_REGULATORY] & 0x7);
1914 rtlefuse->eeprom_regulatory =
1915 (hwinfo[EEPROM_REGULATORY] & 0x1);
1917 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1918 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1920 for (i = 0; i < 14; i++)
1921 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1922 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1923 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1924 for (i = 0; i < 14; i++)
1925 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1926 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1927 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1928 for (i = 0; i < 14; i++)
1929 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1930 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1931 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1932 for (i = 0; i < 14; i++)
1933 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1934 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1935 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1937 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1938 "TxPwrSafetyFlag = %d\n", rtlefuse->txpwr_safetyflag);
1940 /* Read RF-indication and Tx Power gain
1941 * index diff of legacy to HT OFDM rate. */
1942 tempval = hwinfo[EEPROM_RFIND_POWERDIFF] & 0xff;
1943 rtlefuse->eeprom_txpowerdiff = tempval;
1944 rtlefuse->legacy_httxpowerdiff =
1945 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][0];
1947 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1948 "TxPowerDiff = %#x\n", rtlefuse->eeprom_txpowerdiff);
1950 /* Get TSSI value for each path. */
1951 usvalue = *(u16 *)&hwinfo[EEPROM_TSSI_A];
1952 rtlefuse->eeprom_tssi[RF90_PATH_A] = (u8)((usvalue & 0xff00) >> 8);
1953 usvalue = hwinfo[EEPROM_TSSI_B];
1954 rtlefuse->eeprom_tssi[RF90_PATH_B] = (u8)(usvalue & 0xff);
1956 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1957 rtlefuse->eeprom_tssi[RF90_PATH_A],
1958 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1960 /* Read antenna tx power offset of B/C/D to A from EEPROM */
1961 /* and read ThermalMeter from EEPROM */
1962 tempval = hwinfo[EEPROM_THERMALMETER];
1963 rtlefuse->eeprom_thermalmeter = tempval;
1964 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1965 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1967 /* ThermalMeter, BIT(0)~3 for RFIC1, BIT(4)~7 for RFIC2 */
1968 rtlefuse->thermalmeter[0] = (rtlefuse->eeprom_thermalmeter & 0x1f);
1969 rtlefuse->tssi_13dbm = rtlefuse->eeprom_thermalmeter * 100;
1971 /* Read CrystalCap from EEPROM */
1972 tempval = hwinfo[EEPROM_CRYSTALCAP] >> 4;
1973 rtlefuse->eeprom_crystalcap = tempval;
1974 /* CrystalCap, BIT(12)~15 */
1975 rtlefuse->crystalcap = rtlefuse->eeprom_crystalcap;
1977 /* Read IC Version && Channel Plan */
1978 /* Version ID, Channel plan */
1979 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
1980 rtlefuse->txpwr_fromeprom = true;
1981 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1982 "EEPROM ChannelPlan = 0x%4x\n", rtlefuse->eeprom_channelplan);
1984 /* Read Customer ID or Board Type!!! */
1985 tempval = hwinfo[EEPROM_BOARDTYPE];
1986 /* Change RF type definition */
1988 rtlphy->rf_type = RF_2T2R;
1989 else if (tempval == 1)
1990 rtlphy->rf_type = RF_1T2R;
1991 else if (tempval == 2)
1992 rtlphy->rf_type = RF_1T2R;
1993 else if (tempval == 3)
1994 rtlphy->rf_type = RF_1T1R;
1996 /* 1T2R but 1SS (1x1 receive combining) */
1997 rtlefuse->b1x1_recvcombine = false;
1998 if (rtlphy->rf_type == RF_1T2R) {
1999 tempval = rtl_read_byte(rtlpriv, 0x07);
2000 if (!(tempval & BIT(0))) {
2001 rtlefuse->b1x1_recvcombine = true;
2002 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2003 "RF_TYPE=1T2R but only 1SS\n");
2006 rtlefuse->b1ss_support = rtlefuse->b1x1_recvcombine;
2007 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMID];
2009 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
2010 rtlefuse->eeprom_oemid);
2012 /* set channel paln to world wide 13 */
2013 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
2016 void rtl92se_read_eeprom_info(struct ieee80211_hw *hw)
2018 struct rtl_priv *rtlpriv = rtl_priv(hw);
2019 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2022 tmp_u1b = rtl_read_byte(rtlpriv, EPROM_CMD);
2024 if (tmp_u1b & BIT(4)) {
2025 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
2026 rtlefuse->epromtype = EEPROM_93C46;
2028 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
2029 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
2032 if (tmp_u1b & BIT(5)) {
2033 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
2034 rtlefuse->autoload_failflag = false;
2035 _rtl92se_read_adapter_info(hw);
2037 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
2038 rtlefuse->autoload_failflag = true;
2042 static void rtl92se_update_hal_rate_table(struct ieee80211_hw *hw,
2043 struct ieee80211_sta *sta)
2045 struct rtl_priv *rtlpriv = rtl_priv(hw);
2046 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2047 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2048 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2051 u8 nmode = mac->ht_enable;
2052 u8 mimo_ps = IEEE80211_SMPS_OFF;
2053 u16 shortgi_rate = 0;
2054 u32 tmp_ratr_value = 0;
2055 u8 curtxbw_40mhz = mac->bw_40;
2056 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2058 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2060 enum wireless_mode wirelessmode = mac->mode;
2062 if (rtlhal->current_bandtype == BAND_ON_5G)
2063 ratr_value = sta->supp_rates[1] << 4;
2065 ratr_value = sta->supp_rates[0];
2066 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2068 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2069 sta->ht_cap.mcs.rx_mask[0] << 12);
2070 switch (wirelessmode) {
2071 case WIRELESS_MODE_B:
2072 ratr_value &= 0x0000000D;
2074 case WIRELESS_MODE_G:
2075 ratr_value &= 0x00000FF5;
2077 case WIRELESS_MODE_N_24G:
2078 case WIRELESS_MODE_N_5G:
2080 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2081 ratr_value &= 0x0007F005;
2085 if (get_rf_type(rtlphy) == RF_1T2R ||
2086 get_rf_type(rtlphy) == RF_1T1R) {
2088 ratr_mask = 0x000ff015;
2090 ratr_mask = 0x000ff005;
2093 ratr_mask = 0x0f0ff015;
2095 ratr_mask = 0x0f0ff005;
2098 ratr_value &= ratr_mask;
2102 if (rtlphy->rf_type == RF_1T2R)
2103 ratr_value &= 0x000ff0ff;
2105 ratr_value &= 0x0f0ff0ff;
2110 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2111 ratr_value &= 0x0FFFFFFF;
2112 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2113 ratr_value &= 0x0FFFFFF0;
2115 if (nmode && ((curtxbw_40mhz &&
2116 curshortgi_40mhz) || (!curtxbw_40mhz &&
2117 curshortgi_20mhz))) {
2119 ratr_value |= 0x10000000;
2120 tmp_ratr_value = (ratr_value >> 12);
2122 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2123 if ((1 << shortgi_rate) & tmp_ratr_value)
2127 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2128 (shortgi_rate << 4) | (shortgi_rate);
2130 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2133 rtl_write_dword(rtlpriv, ARFR0 + ratr_index * 4, ratr_value);
2134 if (ratr_value & 0xfffff000)
2135 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_N);
2137 rtl92s_phy_set_fw_cmd(hw, FW_CMD_RA_REFRESH_BG);
2139 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2140 rtl_read_dword(rtlpriv, ARFR0));
2143 static void rtl92se_update_hal_rate_mask(struct ieee80211_hw *hw,
2144 struct ieee80211_sta *sta,
2147 struct rtl_priv *rtlpriv = rtl_priv(hw);
2148 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2149 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2150 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2151 struct rtl_sta_info *sta_entry = NULL;
2154 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2155 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2157 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2159 enum wireless_mode wirelessmode = 0;
2160 bool shortgi = false;
2162 u8 shortgi_rate = 0;
2165 bool bmulticast = false;
2167 u8 mimo_ps = IEEE80211_SMPS_OFF;
2169 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2170 wirelessmode = sta_entry->wireless_mode;
2171 if (mac->opmode == NL80211_IFTYPE_STATION)
2172 curtxbw_40mhz = mac->bw_40;
2173 else if (mac->opmode == NL80211_IFTYPE_AP ||
2174 mac->opmode == NL80211_IFTYPE_ADHOC)
2175 macid = sta->aid + 1;
2177 if (rtlhal->current_bandtype == BAND_ON_5G)
2178 ratr_bitmap = sta->supp_rates[1] << 4;
2180 ratr_bitmap = sta->supp_rates[0];
2181 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2182 ratr_bitmap = 0xfff;
2183 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2184 sta->ht_cap.mcs.rx_mask[0] << 12);
2185 switch (wirelessmode) {
2186 case WIRELESS_MODE_B:
2187 band |= WIRELESS_11B;
2188 ratr_index = RATR_INX_WIRELESS_B;
2189 if (ratr_bitmap & 0x0000000c)
2190 ratr_bitmap &= 0x0000000d;
2192 ratr_bitmap &= 0x0000000f;
2194 case WIRELESS_MODE_G:
2195 band |= (WIRELESS_11G | WIRELESS_11B);
2196 ratr_index = RATR_INX_WIRELESS_GB;
2198 if (rssi_level == 1)
2199 ratr_bitmap &= 0x00000f00;
2200 else if (rssi_level == 2)
2201 ratr_bitmap &= 0x00000ff0;
2203 ratr_bitmap &= 0x00000ff5;
2205 case WIRELESS_MODE_A:
2206 band |= WIRELESS_11A;
2207 ratr_index = RATR_INX_WIRELESS_A;
2208 ratr_bitmap &= 0x00000ff0;
2210 case WIRELESS_MODE_N_24G:
2211 case WIRELESS_MODE_N_5G:
2212 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2213 ratr_index = RATR_INX_WIRELESS_NGB;
2215 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2216 if (rssi_level == 1)
2217 ratr_bitmap &= 0x00070000;
2218 else if (rssi_level == 2)
2219 ratr_bitmap &= 0x0007f000;
2221 ratr_bitmap &= 0x0007f005;
2223 if (rtlphy->rf_type == RF_1T2R ||
2224 rtlphy->rf_type == RF_1T1R) {
2225 if (rssi_level == 1) {
2226 ratr_bitmap &= 0x000f0000;
2227 } else if (rssi_level == 3) {
2228 ratr_bitmap &= 0x000fc000;
2229 } else if (rssi_level == 5) {
2230 ratr_bitmap &= 0x000ff000;
2233 ratr_bitmap &= 0x000ff015;
2235 ratr_bitmap &= 0x000ff005;
2238 if (rssi_level == 1) {
2239 ratr_bitmap &= 0x0f8f0000;
2240 } else if (rssi_level == 3) {
2241 ratr_bitmap &= 0x0f8fc000;
2242 } else if (rssi_level == 5) {
2243 ratr_bitmap &= 0x0f8ff000;
2246 ratr_bitmap &= 0x0f8ff015;
2248 ratr_bitmap &= 0x0f8ff005;
2253 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2254 (!curtxbw_40mhz && curshortgi_20mhz)) {
2257 else if (macid == 1)
2262 band |= (WIRELESS_11N | WIRELESS_11G | WIRELESS_11B);
2263 ratr_index = RATR_INX_WIRELESS_NGB;
2265 if (rtlphy->rf_type == RF_1T2R)
2266 ratr_bitmap &= 0x000ff0ff;
2268 ratr_bitmap &= 0x0f8ff0ff;
2271 sta_entry->ratr_index = ratr_index;
2273 if (rtlpriv->rtlhal.version >= VERSION_8192S_BCUT)
2274 ratr_bitmap &= 0x0FFFFFFF;
2275 else if (rtlpriv->rtlhal.version == VERSION_8192S_ACUT)
2276 ratr_bitmap &= 0x0FFFFFF0;
2279 ratr_bitmap |= 0x10000000;
2280 /* Get MAX MCS available. */
2281 ratr_value = (ratr_bitmap >> 12);
2282 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2283 if ((1 << shortgi_rate) & ratr_value)
2287 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2288 (shortgi_rate << 4) | (shortgi_rate);
2289 rtl_write_byte(rtlpriv, SG_RATE, shortgi_rate);
2292 mask |= (bmulticast ? 1 : 0) << 9 | (macid & 0x1f) << 4 | (band & 0xf);
2294 RT_TRACE(rtlpriv, COMP_RATR, DBG_TRACE, "mask = %x, bitmap = %x\n",
2296 rtl_write_dword(rtlpriv, 0x2c4, ratr_bitmap);
2297 rtl_write_dword(rtlpriv, WFM5, (FW_RA_UPDATE_MASK | (mask << 8)));
2300 sta_entry->ratr_index = ratr_index;
2303 void rtl92se_update_hal_rate_tbl(struct ieee80211_hw *hw,
2304 struct ieee80211_sta *sta, u8 rssi_level)
2306 struct rtl_priv *rtlpriv = rtl_priv(hw);
2308 if (rtlpriv->dm.useramask)
2309 rtl92se_update_hal_rate_mask(hw, sta, rssi_level);
2311 rtl92se_update_hal_rate_table(hw, sta);
2314 void rtl92se_update_channel_access_setting(struct ieee80211_hw *hw)
2316 struct rtl_priv *rtlpriv = rtl_priv(hw);
2317 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2320 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2322 sifs_timer = 0x0e0e;
2323 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2327 /* this ifunction is for RFKILL, it's different with windows,
2328 * because UI will disable wireless when GPIO Radio Off.
2329 * And here we not check or Disable/Enable ASPM like windows*/
2330 bool rtl92se_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2332 struct rtl_priv *rtlpriv = rtl_priv(hw);
2333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2335 enum rf_pwrstate rfpwr_toset /*, cur_rfstate */;
2336 unsigned long flag = 0;
2337 bool actuallyset = false;
2338 bool turnonbypowerdomain = false;
2340 /* just 8191se can check gpio before firstup, 92c/92d have fixed it */
2341 if ((rtlpci->up_first_time == 1) || (rtlpci->being_init_adapter))
2344 if (ppsc->swrf_processing)
2347 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2348 if (ppsc->rfchange_inprogress) {
2349 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2352 ppsc->rfchange_inprogress = true;
2353 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2356 /* cur_rfstate = ppsc->rfpwr_state;*/
2358 /* because after _rtl92s_phy_set_rfhalt, all power
2359 * closed, so we must open some power for GPIO check,
2360 * or we will always check GPIO RFOFF here,
2361 * And we should close power after GPIO check */
2362 if (RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
2363 _rtl92se_power_domain_init(hw);
2364 turnonbypowerdomain = true;
2367 rfpwr_toset = _rtl92se_rf_onoff_detect(hw);
2369 if ((ppsc->hwradiooff) && (rfpwr_toset == ERFON)) {
2370 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2371 "RFKILL-HW Radio ON, RF ON\n");
2373 rfpwr_toset = ERFON;
2374 ppsc->hwradiooff = false;
2376 } else if ((!ppsc->hwradiooff) && (rfpwr_toset == ERFOFF)) {
2377 RT_TRACE(rtlpriv, COMP_RF,
2378 DBG_DMESG, "RFKILL-HW Radio OFF, RF OFF\n");
2380 rfpwr_toset = ERFOFF;
2381 ppsc->hwradiooff = true;
2386 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2387 ppsc->rfchange_inprogress = false;
2388 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2390 /* this not include ifconfig wlan0 down case */
2391 /* } else if (rfpwr_toset == ERFOFF || cur_rfstate == ERFOFF) { */
2393 /* because power_domain_init may be happen when
2394 * _rtl92s_phy_set_rfhalt, this will open some powers
2395 * and cause current increasing about 40 mA for ips,
2396 * rfoff and ifconfig down, so we set
2397 * _rtl92s_phy_set_rfhalt again here */
2398 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC &&
2399 turnonbypowerdomain) {
2400 _rtl92s_phy_set_rfhalt(hw);
2401 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2404 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2405 ppsc->rfchange_inprogress = false;
2406 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2410 return !ppsc->hwradiooff;
2414 /* Is_wepkey just used for WEP used as group & pairwise key
2415 * if pairwise is AES ang group is WEP Is_wepkey == false.*/
2416 void rtl92se_set_key(struct ieee80211_hw *hw, u32 key_index, u8 *p_macaddr,
2417 bool is_group, u8 enc_algo, bool is_wepkey, bool clear_all)
2419 struct rtl_priv *rtlpriv = rtl_priv(hw);
2420 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2421 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2422 u8 *macaddr = p_macaddr;
2425 bool is_pairwise = false;
2427 static u8 cam_const_addr[4][6] = {
2428 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2429 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2430 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2431 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2433 static u8 cam_const_broad[] = {
2434 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2440 u8 clear_number = 5;
2442 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2444 for (idx = 0; idx < clear_number; idx++) {
2445 rtl_cam_mark_invalid(hw, cam_offset + idx);
2446 rtl_cam_empty_entry(hw, cam_offset + idx);
2449 memset(rtlpriv->sec.key_buf[idx], 0,
2451 rtlpriv->sec.key_len[idx] = 0;
2457 case WEP40_ENCRYPTION:
2458 enc_algo = CAM_WEP40;
2460 case WEP104_ENCRYPTION:
2461 enc_algo = CAM_WEP104;
2463 case TKIP_ENCRYPTION:
2464 enc_algo = CAM_TKIP;
2466 case AESCCMP_ENCRYPTION:
2470 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2471 "switch case %#x not processed\n", enc_algo);
2472 enc_algo = CAM_TKIP;
2476 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2477 macaddr = cam_const_addr[key_index];
2478 entry_id = key_index;
2481 macaddr = cam_const_broad;
2482 entry_id = key_index;
2484 if (mac->opmode == NL80211_IFTYPE_AP) {
2485 entry_id = rtl_cam_get_free_entry(hw,
2487 if (entry_id >= TOTAL_CAM_ENTRY) {
2489 COMP_SEC, DBG_EMERG,
2490 "Can not find free hw security cam entry\n");
2494 entry_id = CAM_PAIRWISE_KEY_POSITION;
2497 key_index = PAIRWISE_KEYIDX;
2502 if (rtlpriv->sec.key_len[key_index] == 0) {
2503 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2504 "delete one entry, entry_id is %d\n",
2506 if (mac->opmode == NL80211_IFTYPE_AP)
2507 rtl_cam_del_entry(hw, p_macaddr);
2508 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2510 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2513 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2514 "set Pairwise key\n");
2516 rtl_cam_add_one_entry(hw, macaddr, key_index,
2518 CAM_CONFIG_NO_USEDK,
2519 rtlpriv->sec.key_buf[key_index]);
2521 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2524 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2525 rtl_cam_add_one_entry(hw,
2528 CAM_PAIRWISE_KEY_POSITION,
2529 enc_algo, CAM_CONFIG_NO_USEDK,
2530 rtlpriv->sec.key_buf[entry_id]);
2533 rtl_cam_add_one_entry(hw, macaddr, key_index,
2535 CAM_CONFIG_NO_USEDK,
2536 rtlpriv->sec.key_buf[entry_id]);
2543 void rtl92se_suspend(struct ieee80211_hw *hw)
2545 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2547 rtlpci->up_first_time = true;
2550 void rtl92se_resume(struct ieee80211_hw *hw)
2552 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2555 pci_read_config_dword(rtlpci->pdev, 0x40, &val);
2556 if ((val & 0x0000ff00) != 0)
2557 pci_write_config_dword(rtlpci->pdev, 0x40,