1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
42 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
44 struct rtl_priv *rtlpriv = rtl_priv(hw);
47 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
48 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
50 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
54 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
55 u16 offset, u32 value, u8 direct)
57 struct rtl_priv *rtlpriv = rtl_priv(hw);
59 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
60 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
61 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
64 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
65 u8 set_bits, u8 clear_bits)
67 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
68 struct rtl_priv *rtlpriv = rtl_priv(hw);
70 rtlpci->reg_bcn_ctrl_val |= set_bits;
71 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
72 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
75 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
80 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
81 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
82 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
83 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
84 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
85 tmp1byte &= ~(BIT(0));
86 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
89 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
91 struct rtl_priv *rtlpriv = rtl_priv(hw);
94 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
95 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
96 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
97 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
98 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
100 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
103 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
105 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
108 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
110 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
113 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
115 struct rtl_priv *rtlpriv = rtl_priv(hw);
116 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
117 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
121 *((u32 *) (val)) = rtlpci->receive_config;
123 case HW_VAR_RF_STATE:
124 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
126 case HW_VAR_FWLPS_RF_ON:{
127 enum rf_pwrstate rfState;
130 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
132 if (rfState == ERFOFF) {
133 *((bool *) (val)) = true;
135 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
136 val_rcr &= 0x00070000;
138 *((bool *) (val)) = false;
140 *((bool *) (val)) = true;
144 case HW_VAR_FW_PSMODE_STATUS:
145 *((bool *) (val)) = ppsc->fw_current_inpsmode;
147 case HW_VAR_CORRECT_TSF:{
149 u32 *ptsf_low = (u32 *)&tsf;
150 u32 *ptsf_high = ((u32 *)&tsf) + 1;
152 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
153 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
154 *((u64 *) (val)) = tsf;
157 case HW_VAR_INT_MIGRATION:
158 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
161 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
166 pr_err("switch case %#x not processed\n", variable);
171 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
173 struct rtl_priv *rtlpriv = rtl_priv(hw);
174 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
175 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
176 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
177 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
178 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
182 case HW_VAR_ETHER_ADDR:
183 for (idx = 0; idx < ETH_ALEN; idx++) {
184 rtl_write_byte(rtlpriv, (REG_MACID + idx),
188 case HW_VAR_BASIC_RATE: {
189 u16 rate_cfg = ((u16 *) val)[0];
192 rate_cfg = rate_cfg & 0x15f;
193 if (mac->vendor == PEER_CISCO &&
194 ((rate_cfg & 0x150) == 0))
196 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
197 rtl_write_byte(rtlpriv, REG_RRSR + 1,
198 (rate_cfg >> 8) & 0xff);
199 while (rate_cfg > 0x1) {
200 rate_cfg = (rate_cfg >> 1);
203 if (rtlhal->fw_version > 0xe)
204 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
209 for (idx = 0; idx < ETH_ALEN; idx++) {
210 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
215 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
216 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
217 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
218 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
220 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
223 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
226 case HW_VAR_SLOT_TIME: {
229 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
230 "HW_VAR_SLOT_TIME %x\n", val[0]);
231 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
232 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
233 rtlpriv->cfg->ops->set_hw_reg(hw,
238 case HW_VAR_ACK_PREAMBLE: {
240 u8 short_preamble = (bool) (*val);
242 reg_tmp = (mac->cur_40_prime_sc) << 5;
245 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
248 case HW_VAR_AMPDU_MIN_SPACE: {
249 u8 min_spacing_to_set;
252 min_spacing_to_set = *val;
253 if (min_spacing_to_set <= 7) {
255 if (min_spacing_to_set < sec_min_space)
256 min_spacing_to_set = sec_min_space;
257 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
259 *val = min_spacing_to_set;
260 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
261 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
263 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
268 case HW_VAR_SHORTGI_DENSITY: {
271 density_to_set = *val;
272 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
273 mac->min_space_cfg |= (density_to_set << 3);
274 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
275 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
277 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
281 case HW_VAR_AMPDU_FACTOR: {
284 u8 *ptmp_byte = NULL;
287 if (rtlhal->macphymode == DUALMAC_DUALPHY)
288 regtoSet = 0xb9726641;
289 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
290 regtoSet = 0x66626641;
292 regtoSet = 0xb972a841;
294 if (factor_toset <= 3) {
295 factor_toset = (1 << (factor_toset + 2));
296 if (factor_toset > 0xf)
298 for (index = 0; index < 4; index++) {
299 ptmp_byte = (u8 *) (®toSet) + index;
300 if ((*ptmp_byte & 0xf0) >
302 *ptmp_byte = (*ptmp_byte & 0x0f)
303 | (factor_toset << 4);
304 if ((*ptmp_byte & 0x0f) > factor_toset)
305 *ptmp_byte = (*ptmp_byte & 0xf0)
308 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
309 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
310 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
315 case HW_VAR_AC_PARAM: {
317 rtl92d_dm_init_edca_turbo(hw);
318 if (rtlpci->acm_method != EACMWAY2_SW)
319 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
323 case HW_VAR_ACM_CTRL: {
325 union aci_aifsn *p_aci_aifsn =
326 (union aci_aifsn *)(&(mac->ac[0].aifs));
327 u8 acm = p_aci_aifsn->f.acm;
328 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
330 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
334 acm_ctrl |= ACMHW_BEQEN;
337 acm_ctrl |= ACMHW_VIQEN;
340 acm_ctrl |= ACMHW_VOQEN;
343 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
344 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
351 acm_ctrl &= (~ACMHW_BEQEN);
354 acm_ctrl &= (~ACMHW_VIQEN);
357 acm_ctrl &= (~ACMHW_VOQEN);
360 pr_err("switch case %#x not processed\n",
365 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
366 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
368 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
372 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
373 rtlpci->receive_config = ((u32 *) (val))[0];
375 case HW_VAR_RETRY_LIMIT: {
376 u8 retry_limit = val[0];
378 rtl_write_word(rtlpriv, REG_RL,
379 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
380 retry_limit << RETRY_LIMIT_LONG_SHIFT);
383 case HW_VAR_DUAL_TSF_RST:
384 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
386 case HW_VAR_EFUSE_BYTES:
387 rtlefuse->efuse_usedbytes = *((u16 *) val);
389 case HW_VAR_EFUSE_USAGE:
390 rtlefuse->efuse_usedpercentage = *val;
393 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
395 case HW_VAR_WPA_CONFIG:
396 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
398 case HW_VAR_SET_RPWM:
399 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
401 case HW_VAR_H2C_FW_PWRMODE:
403 case HW_VAR_FW_PSMODE_STATUS:
404 ppsc->fw_current_inpsmode = *((bool *) val);
406 case HW_VAR_H2C_FW_JOINBSSRPT: {
408 u8 tmp_regcr, tmp_reg422;
409 bool recover = false;
411 if (mstatus == RT_MEDIA_CONNECT) {
412 rtlpriv->cfg->ops->set_hw_reg(hw,
414 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
415 rtl_write_byte(rtlpriv, REG_CR + 1,
416 (tmp_regcr | BIT(0)));
417 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
418 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
419 tmp_reg422 = rtl_read_byte(rtlpriv,
420 REG_FWHW_TXQ_CTRL + 2);
421 if (tmp_reg422 & BIT(6))
423 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
424 tmp_reg422 & (~BIT(6)));
425 rtl92d_set_fw_rsvdpagepkt(hw, 0);
426 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
427 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
429 rtl_write_byte(rtlpriv,
430 REG_FWHW_TXQ_CTRL + 2,
432 rtl_write_byte(rtlpriv, REG_CR + 1,
433 (tmp_regcr & ~(BIT(0))));
435 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
440 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
442 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
446 case HW_VAR_CORRECT_TSF: {
447 u8 btype_ibss = val[0];
450 _rtl92de_stop_tx_beacon(hw);
451 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
452 rtl_write_dword(rtlpriv, REG_TSFTR,
453 (u32) (mac->tsf & 0xffffffff));
454 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
455 (u32) ((mac->tsf >> 32) & 0xffffffff));
456 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
458 _rtl92de_resume_tx_beacon(hw);
462 case HW_VAR_INT_MIGRATION: {
463 bool int_migration = *(bool *) (val);
466 /* Set interrupt migration timer and
467 * corresponding Tx/Rx counter.
468 * timer 25ns*0xfa0=100us for 0xf packets.
469 * 0x306:Rx, 0x307:Tx */
470 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
471 rtlpriv->dm.interrupt_migration = int_migration;
473 /* Reset all interrupt migration settings. */
474 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
475 rtlpriv->dm.interrupt_migration = int_migration;
479 case HW_VAR_INT_AC: {
480 bool disable_ac_int = *((bool *) val);
482 /* Disable four ACs interrupts. */
483 if (disable_ac_int) {
484 /* Disable VO, VI, BE and BK four AC interrupts
485 * to gain more efficient CPU utilization.
486 * When extremely highly Rx OK occurs,
487 * we will disable Tx interrupts.
489 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
491 rtlpriv->dm.disable_tx_int = disable_ac_int;
492 /* Enable four ACs interrupts. */
494 rtlpriv->cfg->ops->update_interrupt_mask(hw,
496 rtlpriv->dm.disable_tx_int = disable_ac_int;
501 pr_err("switch case %#x not processed\n", variable);
506 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
508 struct rtl_priv *rtlpriv = rtl_priv(hw);
511 u32 value = _LLT_INIT_ADDR(address) |
512 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
514 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
516 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
517 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
519 if (count > POLLING_LLT_THRESHOLD) {
520 pr_err("Failed to polling write LLT done at address %d!\n",
529 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
531 struct rtl_priv *rtlpriv = rtl_priv(hw);
536 u32 value32; /* High+low page number */
537 u8 value8; /* normal page number */
539 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
543 value32 = 0x80bf0d29;
548 value32 = 0x80750005;
551 /* Set reserved page for each queue */
552 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
554 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
555 rtl_write_dword(rtlpriv, REG_RQPN, value32);
557 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
558 /* TXRKTBUG_PG_BNDY */
559 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
560 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
563 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
564 /* Beacon Head for TXDMA */
565 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
567 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
569 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
570 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
572 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
574 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
576 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
577 /* Rx can be 64,128,256,512,1024 bytes) */
578 /* 16. PBP [7:0] = 0x11 */
580 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
582 /* 17. DRV_INFO_SZ = 0x04 */
583 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
585 /* 18. LLT_table_init(Adapter); */
586 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
587 status = _rtl92de_llt_write(hw, i, i + 1);
593 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
597 /* Make the other pages as ring buffer */
598 /* This ring buffer is used as beacon buffer if we */
599 /* config this MAC as two MAC transfer. */
600 /* Otherwise used as local loopback buffer. */
601 for (i = txpktbuf_bndy; i < maxPage; i++) {
602 status = _rtl92de_llt_write(hw, i, (i + 1));
607 /* Let last entry point to the start entry of ring buffer */
608 status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
615 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
617 struct rtl_priv *rtlpriv = rtl_priv(hw);
618 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
619 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
620 struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
622 if (rtlpci->up_first_time)
624 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
625 rtl92de_sw_led_on(hw, pled0);
626 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
627 rtl92de_sw_led_on(hw, pled0);
629 rtl92de_sw_led_off(hw, pled0);
632 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
634 struct rtl_priv *rtlpriv = rtl_priv(hw);
635 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
636 unsigned char bytetmp;
637 unsigned short wordtmp;
640 rtl92d_phy_set_poweron(hw);
641 /* Add for resume sequence of power domain according
642 * to power document V11. Chapter V.11.... */
643 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
644 /* unlock ISO/CLK/Power control register */
645 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
646 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
648 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
649 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
650 /* 3. delay (1ms) this is not necessary when initially power on */
652 /* C. Resume Sequence */
653 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
654 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
656 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
657 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
659 /* c. DRV runs power on init flow */
661 /* auto enable WLAN */
662 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
663 /* Power On Reset for MAC Block */
664 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
666 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
669 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
670 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
673 while ((bytetmp & BIT(0)) && retry < 1000) {
675 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
679 /* Enable Radio off, GPIO, and LED function */
680 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
681 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
683 /* release RF digital isolation */
684 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
685 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
686 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
689 /* make sure that BB reset OK. */
690 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
692 /* Disable REG_CR before enable it to assure reset */
693 rtl_write_word(rtlpriv, REG_CR, 0x0);
695 /* Release MAC IO register reset */
696 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
698 /* clear stopping tx/rx dma */
699 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
701 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
704 /* 18. LLT_table_init(Adapter); */
705 if (!_rtl92de_llt_table_init(hw))
708 /* Clear interrupt and enable interrupt */
709 /* 19. HISR 0x124[31:0] = 0xffffffff; */
710 /* HISRE 0x12C[7:0] = 0xFF */
711 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
712 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
714 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
715 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
716 /* The IMR should be enabled later after all init sequence
719 /* 22. PCIE configuration space configuration */
720 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
721 /* and PCIe gated clock function is enabled. */
722 /* PCIE configuration space will be written after
723 * all init sequence.(Or by BIOS) */
725 rtl92d_phy_config_maccoexist_rfpage(hw);
727 /* THe below section is not related to power document Vxx . */
728 /* This is only useful for driver and OS setting. */
729 /* -------------------Software Relative Setting---------------------- */
730 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
733 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
735 /* Reported Tx status from HW for rate adaptive. */
736 /* This should be realtive to power on step 14. But in document V11 */
737 /* still not contain the description.!!! */
738 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
740 /* Set Tx/Rx page size (Tx must be 128 Bytes,
741 * Rx can be 64,128,256,512,1024 bytes) */
742 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
744 /* Set RCR register */
745 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
746 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
748 /* Set TCR register */
749 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
751 /* disable earlymode */
752 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
754 /* Set TX/RX descriptor physical address(from OS API). */
755 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
756 rtlpci->tx_ring[BEACON_QUEUE].dma);
757 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
758 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
759 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
760 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
761 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
762 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
763 /* Set RX Desc Address */
764 rtl_write_dword(rtlpriv, REG_RX_DESA,
765 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
767 /* if we want to support 64 bit DMA, we should set it here,
768 * but now we do not support 64 bit DMA*/
770 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
772 /* Reset interrupt migration setting when initialization */
773 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
775 /* Reconsider when to do this operation after asking HWSD. */
776 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
777 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
780 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
781 } while ((retry < 200) && !(bytetmp & BIT(7)));
783 /* After MACIO reset,we must refresh LED state. */
784 _rtl92de_gen_refresh_led_state(hw);
786 /* Reset H2C protection register */
787 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
792 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
794 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
795 struct rtl_priv *rtlpriv = rtl_priv(hw);
796 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
797 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
800 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
801 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
802 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
803 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
804 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
805 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
806 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
807 rtl_write_word(rtlpriv, REG_RL, 0x0707);
808 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
809 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
810 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
811 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
812 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
813 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
814 /* Aggregation threshold */
815 if (rtlhal->macphymode == DUALMAC_DUALPHY)
816 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
817 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
818 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
820 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
821 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
822 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
823 rtlpci->reg_bcn_ctrl_val = 0x1f;
824 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
825 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
826 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
827 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
828 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
830 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
831 /* ACKTO for IOT issue. */
832 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
833 /* Set Spec SIFS (used in NAV) */
834 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
835 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
836 /* Set SIFS for CCK */
837 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
838 /* Set SIFS for OFDM */
839 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
840 /* Set Multicast Address. */
841 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
842 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
843 switch (rtlpriv->phy.rf_type) {
846 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
850 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
855 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
857 struct rtl_priv *rtlpriv = rtl_priv(hw);
858 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
860 rtl_write_byte(rtlpriv, 0x34b, 0x93);
861 rtl_write_word(rtlpriv, 0x350, 0x870c);
862 rtl_write_byte(rtlpriv, 0x352, 0x1);
863 if (ppsc->support_backdoor)
864 rtl_write_byte(rtlpriv, 0x349, 0x1b);
866 rtl_write_byte(rtlpriv, 0x349, 0x03);
867 rtl_write_word(rtlpriv, 0x350, 0x2718);
868 rtl_write_byte(rtlpriv, 0x352, 0x1);
871 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
873 struct rtl_priv *rtlpriv = rtl_priv(hw);
876 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
877 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
878 rtlpriv->sec.pairwise_enc_algorithm,
879 rtlpriv->sec.group_enc_algorithm);
880 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
881 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
882 "not open hw encryption\n");
885 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
886 if (rtlpriv->sec.use_defaultkey) {
887 sec_reg_value |= SCR_TXUSEDK;
888 sec_reg_value |= SCR_RXUSEDK;
890 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
891 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
892 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
893 "The SECR-value %x\n", sec_reg_value);
894 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
897 int rtl92de_hw_init(struct ieee80211_hw *hw)
899 struct rtl_priv *rtlpriv = rtl_priv(hw);
900 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
901 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
902 struct rtl_phy *rtlphy = &(rtlpriv->phy);
903 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
904 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
905 bool rtstatus = true;
911 rtlpci->being_init_adapter = true;
912 rtlpci->init_ready = false;
913 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
914 /* we should do iqk after disable/enable */
915 rtl92d_phy_reset_iqk_result(hw);
916 /* rtlpriv->intf_ops->disable_aspm(hw); */
917 rtstatus = _rtl92de_init_mac(hw);
919 pr_err("Init MAC failed\n");
921 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
924 err = rtl92d_download_fw(hw);
925 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
927 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
928 "Failed to download FW. Init HW without FW..\n");
931 rtlhal->last_hmeboxnum = 0;
932 rtlpriv->psc.fw_current_inpsmode = false;
934 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
935 tmp_u1b = tmp_u1b | 0x30;
936 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
938 if (rtlhal->earlymode_enable) {
939 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
940 "EarlyMode Enabled!!!\n");
942 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
943 tmp_u1b = tmp_u1b | 0x1f;
944 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
946 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
948 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
949 tmp_u1b = tmp_u1b | 0x40;
950 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
954 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
955 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
956 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
959 rtl92d_phy_mac_config(hw);
960 /* because last function modify RCR, so we update
961 * rcr var here, or TP will unstable for receive_config
962 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
963 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
964 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
965 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
967 rtl92d_phy_bb_config(hw);
969 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
970 /* set before initialize RF */
971 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
974 rtl92d_phy_rf_config(hw);
976 /* After read predefined TXT, we must set BB/MAC/RF
977 * register as our requirement */
978 /* After load BB,RF params,we need do more for 92D. */
979 rtl92d_update_bbrf_configuration(hw);
980 /* set default value after initialize RF, */
981 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
982 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
983 RF_CHNLBW, RFREG_OFFSET_MASK);
984 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
985 RF_CHNLBW, RFREG_OFFSET_MASK);
987 /*---- Set CCK and OFDM Block "ON"----*/
988 if (rtlhal->current_bandtype == BAND_ON_2_4G)
989 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
990 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
991 if (rtlhal->interfaceindex == 0) {
992 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
993 * set to 20MHz by default */
994 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
998 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1002 _rtl92de_hw_configure(hw);
1005 rtl_cam_reset_all_entry(hw);
1006 rtl92de_enable_hw_security_config(hw);
1008 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1009 /* TX power index for different rate set. */
1010 rtl92d_phy_get_hw_reg_originalvalue(hw);
1011 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1013 ppsc->rfpwr_state = ERFON;
1015 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1017 _rtl92de_enable_aspm_back_door(hw);
1018 /* rtlpriv->intf_ops->enable_aspm(hw); */
1021 rtlpci->being_init_adapter = false;
1023 if (ppsc->rfpwr_state == ERFON) {
1024 rtl92d_phy_lc_calibrate(hw);
1025 /* 5G and 2.4G must wait sometime to let RF LO ready */
1026 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1028 for (i = 0; i < 10000; i++) {
1029 udelay(MAX_STALL_TIME);
1031 tmp_rega = rtl_get_rfreg(hw,
1032 (enum radio_path)RF90_PATH_A,
1035 if (((tmp_rega & BIT(11)) == BIT(11)))
1038 /* check that loop was successful. If not, exit now */
1040 rtlpci->init_ready = false;
1045 rtlpci->init_ready = true;
1049 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1051 struct rtl_priv *rtlpriv = rtl_priv(hw);
1052 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1055 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1056 if (!(value32 & 0x000f0000)) {
1057 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1058 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1060 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1061 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1066 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1067 enum nl80211_iftype type)
1069 struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1071 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1076 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1077 type == NL80211_IFTYPE_STATION) {
1078 _rtl92de_stop_tx_beacon(hw);
1079 _rtl92de_enable_bcn_sub_func(hw);
1080 } else if (type == NL80211_IFTYPE_ADHOC ||
1081 type == NL80211_IFTYPE_AP) {
1082 _rtl92de_resume_tx_beacon(hw);
1083 _rtl92de_disable_bcn_sub_func(hw);
1085 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1086 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1089 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1091 case NL80211_IFTYPE_UNSPECIFIED:
1092 bt_msr |= MSR_NOLINK;
1093 ledaction = LED_CTL_LINK;
1094 bcnfunc_enable &= 0xF7;
1095 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1096 "Set Network type to NO LINK!\n");
1098 case NL80211_IFTYPE_ADHOC:
1099 bt_msr |= MSR_ADHOC;
1100 bcnfunc_enable |= 0x08;
1101 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1102 "Set Network type to Ad Hoc!\n");
1104 case NL80211_IFTYPE_STATION:
1105 bt_msr |= MSR_INFRA;
1106 ledaction = LED_CTL_LINK;
1107 bcnfunc_enable &= 0xF7;
1108 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1109 "Set Network type to STA!\n");
1111 case NL80211_IFTYPE_AP:
1113 bcnfunc_enable |= 0x08;
1114 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1115 "Set Network type to AP!\n");
1118 pr_err("Network type %d not supported!\n", type);
1121 rtl_write_byte(rtlpriv, MSR, bt_msr);
1122 rtlpriv->cfg->ops->led_control(hw, ledaction);
1123 if ((bt_msr & MSR_MASK) == MSR_AP)
1124 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1126 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1130 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1132 struct rtl_priv *rtlpriv = rtl_priv(hw);
1135 if (rtlpriv->psc.rfpwr_state != ERFON)
1138 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1141 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1142 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1143 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1144 } else if (!check_bssid) {
1145 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1146 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1147 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1151 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1153 struct rtl_priv *rtlpriv = rtl_priv(hw);
1155 if (_rtl92de_set_media_status(hw, type))
1159 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1160 if (type != NL80211_IFTYPE_AP)
1161 rtl92de_set_check_bssid(hw, true);
1163 rtl92de_set_check_bssid(hw, false);
1168 /* do iqk or reload iqk */
1169 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1170 * but it's very strict for time sequence so we add
1171 * rtl92d_phy_reload_iqk_setting here */
1172 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1177 u8 channel = rtlphy->current_channel;
1179 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1180 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1181 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1182 "Do IQK for channel:%d\n", channel);
1183 rtl92d_phy_iq_calibrate(hw);
1187 /* don't set REG_EDCA_BE_PARAM here because
1188 * mac80211 will send pkt when scan */
1189 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1191 rtl92d_dm_init_edca_turbo(hw);
1194 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1196 struct rtl_priv *rtlpriv = rtl_priv(hw);
1197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1199 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1200 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1201 rtlpci->irq_enabled = true;
1204 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1206 struct rtl_priv *rtlpriv = rtl_priv(hw);
1207 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1209 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1210 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1211 rtlpci->irq_enabled = false;
1214 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1216 struct rtl_priv *rtlpriv = rtl_priv(hw);
1218 unsigned long flags;
1220 rtlpriv->intf_ops->enable_aspm(hw);
1221 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1222 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1223 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1225 /* 0x20:value 05-->04 */
1226 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1228 /* ==== Reset digital sequence ====== */
1229 rtl92d_firmware_selfreset(hw);
1231 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1232 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1234 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1235 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1237 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1239 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1240 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1242 /* i. Value = GPIO_PIN_CTRL[7:0] */
1243 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1245 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1246 /* write external PIN level */
1247 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1248 0x00FF0000 | (u1b_tmp << 8));
1250 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1251 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1253 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1254 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1256 /* ==== Disable analog sequence === */
1258 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1259 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1261 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1262 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1264 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1265 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1267 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1268 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1270 /* ==== interface into suspend === */
1272 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1273 /* According to power document V11, we need to set this */
1274 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1275 /* This indluences power consumption. Bases on SD1's test, */
1276 /* set as 0x00 do not affect power current. And if it */
1277 /* is set as 0x18, they had ever met auto load fail problem. */
1278 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1280 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1281 "In PowerOff,reg0x%x=%X\n",
1282 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1283 /* r. Note: for PCIe interface, PON will not turn */
1284 /* off m-bias and BandGap in PCIe suspend mode. */
1286 /* 0x17[7] 1b': power off in process 0b' : power off over */
1287 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1288 spin_lock_irqsave(&globalmutex_power, flags);
1289 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1290 u1b_tmp &= (~BIT(7));
1291 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1292 spin_unlock_irqrestore(&globalmutex_power, flags);
1295 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1298 void rtl92de_card_disable(struct ieee80211_hw *hw)
1300 struct rtl_priv *rtlpriv = rtl_priv(hw);
1301 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1302 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1303 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1304 enum nl80211_iftype opmode;
1306 mac->link_state = MAC80211_NOLINK;
1307 opmode = NL80211_IFTYPE_UNSPECIFIED;
1308 _rtl92de_set_media_status(hw, opmode);
1310 if (rtlpci->driver_is_goingto_unload ||
1311 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1312 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1313 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1314 /* Power sequence for each MAC. */
1315 /* a. stop tx DMA */
1317 /* c. clear rx buf */
1318 /* d. stop rx DMA */
1321 /* a. stop tx DMA */
1322 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1325 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1327 /* c. ========RF OFF sequence========== */
1328 /* 0x88c[23:20] = 0xf. */
1329 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1330 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1332 /* APSD_CTRL 0x600[7:0] = 0x40 */
1333 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1335 /* Close antenna 0,0xc04,0xd04 */
1336 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1337 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1339 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1340 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1342 /* Mac0 can not do Global reset. Mac1 can do. */
1343 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1344 if (rtlpriv->rtlhal.interfaceindex == 1)
1345 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1348 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1349 /* dma hang issue when disable/enable device. */
1350 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1352 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1354 if (rtl92d_phy_check_poweroff(hw))
1355 _rtl92de_poweroff_adapter(hw);
1359 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1360 u32 *p_inta, u32 *p_intb)
1362 struct rtl_priv *rtlpriv = rtl_priv(hw);
1363 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1365 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1366 rtl_write_dword(rtlpriv, ISR, *p_inta);
1369 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1370 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1374 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1376 struct rtl_priv *rtlpriv = rtl_priv(hw);
1377 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1378 u16 bcn_interval, atim_window;
1380 bcn_interval = mac->beacon_interval;
1382 rtl92de_disable_interrupt(hw);
1383 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1384 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1385 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1386 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1387 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1388 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1390 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1391 rtl_write_byte(rtlpriv, 0x606, 0x30);
1394 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1396 struct rtl_priv *rtlpriv = rtl_priv(hw);
1397 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1398 u16 bcn_interval = mac->beacon_interval;
1400 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1401 "beacon_interval:%d\n", bcn_interval);
1402 rtl92de_disable_interrupt(hw);
1403 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1404 rtl92de_enable_interrupt(hw);
1407 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1408 u32 add_msr, u32 rm_msr)
1410 struct rtl_priv *rtlpriv = rtl_priv(hw);
1411 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1413 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1416 rtlpci->irq_mask[0] |= add_msr;
1418 rtlpci->irq_mask[0] &= (~rm_msr);
1419 rtl92de_disable_interrupt(hw);
1420 rtl92de_enable_interrupt(hw);
1423 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1424 u8 *rom_content, bool autoLoadfail)
1426 u32 rfpath, eeaddr, group, offset1, offset2;
1429 memset(pwrinfo, 0, sizeof(struct txpower_info));
1431 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1432 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1433 if (group < CHANNEL_GROUP_MAX_2G) {
1434 pwrinfo->cck_index[rfpath][group] =
1435 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1436 pwrinfo->ht40_1sindex[rfpath][group] =
1437 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1439 pwrinfo->ht40_1sindex[rfpath][group] =
1440 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1442 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1443 EEPROM_DEFAULT_HT40_2SDIFF;
1444 pwrinfo->ht20indexdiff[rfpath][group] =
1445 EEPROM_DEFAULT_HT20_DIFF;
1446 pwrinfo->ofdmindexdiff[rfpath][group] =
1447 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1448 pwrinfo->ht40maxoffset[rfpath][group] =
1449 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1450 pwrinfo->ht20maxoffset[rfpath][group] =
1451 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1454 for (i = 0; i < 3; i++) {
1455 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1456 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1461 /* Maybe autoload OK,buf the tx power index value is not filled.
1462 * If we find it, we set it to default value. */
1463 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1464 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1465 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1467 pwrinfo->cck_index[rfpath][group] =
1468 (rom_content[eeaddr] == 0xFF) ?
1470 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1471 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1472 rom_content[eeaddr];
1475 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1476 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1477 offset1 = group / 3;
1478 offset2 = group % 3;
1479 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1480 offset2 + offset1 * 21;
1481 pwrinfo->ht40_1sindex[rfpath][group] =
1482 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1483 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1484 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1485 rom_content[eeaddr];
1488 /* These just for 92D efuse offset. */
1489 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1490 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1491 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1493 offset1 = group / 3;
1494 offset2 = group % 3;
1496 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1497 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1498 (rom_content[base1 +
1499 offset2 + offset1 * 21] >> (rfpath * 4))
1502 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1503 EEPROM_DEFAULT_HT40_2SDIFF;
1504 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1505 + offset1 * 21] != 0xFF)
1506 pwrinfo->ht20indexdiff[rfpath][group] =
1507 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1508 + offset2 + offset1 * 21] >> (rfpath * 4))
1511 pwrinfo->ht20indexdiff[rfpath][group] =
1512 EEPROM_DEFAULT_HT20_DIFF;
1513 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1514 + offset1 * 21] != 0xFF)
1515 pwrinfo->ofdmindexdiff[rfpath][group] =
1516 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1517 + offset2 + offset1 * 21] >> (rfpath * 4))
1520 pwrinfo->ofdmindexdiff[rfpath][group] =
1521 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1522 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1523 + offset1 * 21] != 0xFF)
1524 pwrinfo->ht40maxoffset[rfpath][group] =
1525 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1526 + offset2 + offset1 * 21] >> (rfpath * 4))
1529 pwrinfo->ht40maxoffset[rfpath][group] =
1530 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1531 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1532 + offset1 * 21] != 0xFF)
1533 pwrinfo->ht20maxoffset[rfpath][group] =
1534 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1535 offset2 + offset1 * 21] >> (rfpath * 4)) &
1538 pwrinfo->ht20maxoffset[rfpath][group] =
1539 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1542 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1544 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1545 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1547 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1548 pwrinfo->tssi_b[1] =
1549 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1550 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1552 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1554 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1555 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1558 for (i = 0; i < 3; i++) {
1559 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1560 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1565 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1566 bool autoload_fail, u8 *hwinfo)
1568 struct rtl_priv *rtlpriv = rtl_priv(hw);
1569 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1570 struct txpower_info pwrinfo;
1571 u8 tempval[2], i, pwr, diff;
1572 u32 ch, rfPath, group;
1574 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1575 if (!autoload_fail) {
1577 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1578 rtlefuse->eeprom_thermalmeter =
1579 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1580 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1581 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1582 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1583 rtlefuse->txpwr_fromeprom = true;
1584 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1585 IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1586 rtlefuse->internal_pa_5g[0] =
1587 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1588 rtlefuse->internal_pa_5g[1] =
1589 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1590 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1591 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1592 rtlefuse->internal_pa_5g[0],
1593 rtlefuse->internal_pa_5g[1]);
1595 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1596 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1598 rtlefuse->eeprom_regulatory = 0;
1599 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1600 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1601 tempval[0] = tempval[1] = 3;
1604 /* Use default value to fill parameters if
1605 * efuse is not filled on some place. */
1607 /* ThermalMeter from EEPROM */
1608 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1609 rtlefuse->eeprom_thermalmeter > 0x1c)
1610 rtlefuse->eeprom_thermalmeter = 0x12;
1611 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1614 if (rtlefuse->crystalcap == 0xFF)
1615 rtlefuse->crystalcap = 0;
1616 if (rtlefuse->eeprom_regulatory > 3)
1617 rtlefuse->eeprom_regulatory = 0;
1619 for (i = 0; i < 2; i++) {
1620 switch (tempval[i]) {
1637 rtlefuse->delta_iqk = tempval[0];
1639 rtlefuse->delta_lck = tempval[1] - 1;
1640 if (rtlefuse->eeprom_c9 == 0xFF)
1641 rtlefuse->eeprom_c9 = 0x00;
1642 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1643 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1644 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1645 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1646 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1647 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1648 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1649 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1650 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1652 for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1653 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1654 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1655 if (ch < CHANNEL_MAX_NUMBER_2G)
1656 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1657 pwrinfo.cck_index[rfPath][group];
1658 rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1659 pwrinfo.ht40_1sindex[rfPath][group];
1660 rtlefuse->txpwr_ht20diff[rfPath][ch] =
1661 pwrinfo.ht20indexdiff[rfPath][group];
1662 rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1663 pwrinfo.ofdmindexdiff[rfPath][group];
1664 rtlefuse->pwrgroup_ht20[rfPath][ch] =
1665 pwrinfo.ht20maxoffset[rfPath][group];
1666 rtlefuse->pwrgroup_ht40[rfPath][ch] =
1667 pwrinfo.ht40maxoffset[rfPath][group];
1668 pwr = pwrinfo.ht40_1sindex[rfPath][group];
1669 diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1670 rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1671 (pwr > diff) ? (pwr - diff) : 0;
1676 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1679 struct rtl_priv *rtlpriv = rtl_priv(hw);
1680 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1681 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1683 if (macphy_crvalue & BIT(3)) {
1684 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1685 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1686 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1688 rtlhal->macphymode = DUALMAC_DUALPHY;
1689 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1690 "MacPhyMode DUALMAC_DUALPHY\n");
1694 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1697 _rtl92de_read_macphymode_from_prom(hw, content);
1698 rtl92d_phy_config_macphymode(hw);
1699 rtl92d_phy_config_macphymode_info(hw);
1702 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1704 struct rtl_priv *rtlpriv = rtl_priv(hw);
1705 enum version_8192d chipver = rtlpriv->rtlhal.version;
1709 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1711 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1713 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1714 switch (chipvalue) {
1716 chipver |= CHIP_92D_C_CUT;
1717 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1720 chipver |= CHIP_92D_D_CUT;
1721 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1724 chipver |= CHIP_92D_E_CUT;
1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1728 chipver |= CHIP_92D_D_CUT;
1729 pr_err("Unknown CUT!\n");
1732 rtlpriv->rtlhal.version = chipver;
1735 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1737 struct rtl_priv *rtlpriv = rtl_priv(hw);
1738 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1739 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1740 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1741 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR_MAC0_92D,
1742 EEPROM_CHANNEL_PLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1743 COUNTRY_CODE_WORLD_WIDE_13};
1748 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1752 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1755 _rtl92de_efuse_update_chip_version(hw);
1756 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1758 /* Read Permanent MAC address for 2nd interface */
1759 if (rtlhal->interfaceindex != 0) {
1760 for (i = 0; i < 6; i += 2) {
1761 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1762 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1765 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1766 rtlefuse->dev_addr);
1767 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1768 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1770 /* Read Channel Plan */
1771 switch (rtlhal->bandset) {
1773 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1776 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1779 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1782 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1785 rtlefuse->txpwr_fromeprom = true;
1790 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1792 struct rtl_priv *rtlpriv = rtl_priv(hw);
1793 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1794 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1797 rtlhal->version = _rtl92de_read_chip_version(hw);
1798 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1799 rtlefuse->autoload_status = tmp_u1b;
1800 if (tmp_u1b & BIT(4)) {
1801 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1802 rtlefuse->epromtype = EEPROM_93C46;
1804 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1805 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1807 if (tmp_u1b & BIT(5)) {
1808 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1810 rtlefuse->autoload_failflag = false;
1811 _rtl92de_read_adapter_info(hw);
1813 pr_err("Autoload ERR!!\n");
1818 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1819 struct ieee80211_sta *sta)
1821 struct rtl_priv *rtlpriv = rtl_priv(hw);
1822 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1823 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1824 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1827 u8 nmode = mac->ht_enable;
1828 u8 mimo_ps = IEEE80211_SMPS_OFF;
1831 u8 curtxbw_40mhz = mac->bw_40;
1832 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1834 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1836 enum wireless_mode wirelessmode = mac->mode;
1838 if (rtlhal->current_bandtype == BAND_ON_5G)
1839 ratr_value = sta->supp_rates[1] << 4;
1841 ratr_value = sta->supp_rates[0];
1842 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1843 sta->ht_cap.mcs.rx_mask[0] << 12);
1844 switch (wirelessmode) {
1845 case WIRELESS_MODE_A:
1846 ratr_value &= 0x00000FF0;
1848 case WIRELESS_MODE_B:
1849 if (ratr_value & 0x0000000c)
1850 ratr_value &= 0x0000000d;
1852 ratr_value &= 0x0000000f;
1854 case WIRELESS_MODE_G:
1855 ratr_value &= 0x00000FF5;
1857 case WIRELESS_MODE_N_24G:
1858 case WIRELESS_MODE_N_5G:
1860 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1861 ratr_value &= 0x0007F005;
1865 if (get_rf_type(rtlphy) == RF_1T2R ||
1866 get_rf_type(rtlphy) == RF_1T1R) {
1867 ratr_mask = 0x000ff005;
1869 ratr_mask = 0x0f0ff005;
1872 ratr_value &= ratr_mask;
1876 if (rtlphy->rf_type == RF_1T2R)
1877 ratr_value &= 0x000ff0ff;
1879 ratr_value &= 0x0f0ff0ff;
1883 ratr_value &= 0x0FFFFFFF;
1884 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1885 (!curtxbw_40mhz && curshortgi_20mhz))) {
1886 ratr_value |= 0x10000000;
1887 tmp_ratr_value = (ratr_value >> 12);
1888 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1889 if ((1 << shortgi_rate) & tmp_ratr_value)
1892 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1893 (shortgi_rate << 4) | (shortgi_rate);
1895 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1896 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1897 rtl_read_dword(rtlpriv, REG_ARFR0));
1900 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1901 struct ieee80211_sta *sta, u8 rssi_level)
1903 struct rtl_priv *rtlpriv = rtl_priv(hw);
1904 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1905 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1906 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1907 struct rtl_sta_info *sta_entry = NULL;
1910 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1911 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1913 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1915 enum wireless_mode wirelessmode = 0;
1916 bool shortgi = false;
1919 u8 mimo_ps = IEEE80211_SMPS_OFF;
1921 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1922 mimo_ps = sta_entry->mimo_ps;
1923 wirelessmode = sta_entry->wireless_mode;
1924 if (mac->opmode == NL80211_IFTYPE_STATION)
1925 curtxbw_40mhz = mac->bw_40;
1926 else if (mac->opmode == NL80211_IFTYPE_AP ||
1927 mac->opmode == NL80211_IFTYPE_ADHOC)
1928 macid = sta->aid + 1;
1930 if (rtlhal->current_bandtype == BAND_ON_5G)
1931 ratr_bitmap = sta->supp_rates[1] << 4;
1933 ratr_bitmap = sta->supp_rates[0];
1934 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1935 sta->ht_cap.mcs.rx_mask[0] << 12);
1936 switch (wirelessmode) {
1937 case WIRELESS_MODE_B:
1938 ratr_index = RATR_INX_WIRELESS_B;
1939 if (ratr_bitmap & 0x0000000c)
1940 ratr_bitmap &= 0x0000000d;
1942 ratr_bitmap &= 0x0000000f;
1944 case WIRELESS_MODE_G:
1945 ratr_index = RATR_INX_WIRELESS_GB;
1947 if (rssi_level == 1)
1948 ratr_bitmap &= 0x00000f00;
1949 else if (rssi_level == 2)
1950 ratr_bitmap &= 0x00000ff0;
1952 ratr_bitmap &= 0x00000ff5;
1954 case WIRELESS_MODE_A:
1955 ratr_index = RATR_INX_WIRELESS_G;
1956 ratr_bitmap &= 0x00000ff0;
1958 case WIRELESS_MODE_N_24G:
1959 case WIRELESS_MODE_N_5G:
1960 if (wirelessmode == WIRELESS_MODE_N_24G)
1961 ratr_index = RATR_INX_WIRELESS_NGB;
1963 ratr_index = RATR_INX_WIRELESS_NG;
1964 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1965 if (rssi_level == 1)
1966 ratr_bitmap &= 0x00070000;
1967 else if (rssi_level == 2)
1968 ratr_bitmap &= 0x0007f000;
1970 ratr_bitmap &= 0x0007f005;
1972 if (rtlphy->rf_type == RF_1T2R ||
1973 rtlphy->rf_type == RF_1T1R) {
1974 if (curtxbw_40mhz) {
1975 if (rssi_level == 1)
1976 ratr_bitmap &= 0x000f0000;
1977 else if (rssi_level == 2)
1978 ratr_bitmap &= 0x000ff000;
1980 ratr_bitmap &= 0x000ff015;
1982 if (rssi_level == 1)
1983 ratr_bitmap &= 0x000f0000;
1984 else if (rssi_level == 2)
1985 ratr_bitmap &= 0x000ff000;
1987 ratr_bitmap &= 0x000ff005;
1990 if (curtxbw_40mhz) {
1991 if (rssi_level == 1)
1992 ratr_bitmap &= 0x0f0f0000;
1993 else if (rssi_level == 2)
1994 ratr_bitmap &= 0x0f0ff000;
1996 ratr_bitmap &= 0x0f0ff015;
1998 if (rssi_level == 1)
1999 ratr_bitmap &= 0x0f0f0000;
2000 else if (rssi_level == 2)
2001 ratr_bitmap &= 0x0f0ff000;
2003 ratr_bitmap &= 0x0f0ff005;
2007 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2008 (!curtxbw_40mhz && curshortgi_20mhz)) {
2012 else if (macid == 1)
2017 ratr_index = RATR_INX_WIRELESS_NGB;
2019 if (rtlphy->rf_type == RF_1T2R)
2020 ratr_bitmap &= 0x000ff0ff;
2022 ratr_bitmap &= 0x0f0ff0ff;
2026 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2027 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2028 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2029 "ratr_bitmap :%x value0:%x value1:%x\n",
2030 ratr_bitmap, value[0], value[1]);
2031 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2033 sta_entry->ratr_index = ratr_index;
2036 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2037 struct ieee80211_sta *sta, u8 rssi_level)
2039 struct rtl_priv *rtlpriv = rtl_priv(hw);
2041 if (rtlpriv->dm.useramask)
2042 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2044 rtl92de_update_hal_rate_table(hw, sta);
2047 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2049 struct rtl_priv *rtlpriv = rtl_priv(hw);
2050 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2053 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2055 if (!mac->ht_enable)
2056 sifs_timer = 0x0a0a;
2058 sifs_timer = 0x1010;
2059 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2062 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2064 struct rtl_priv *rtlpriv = rtl_priv(hw);
2065 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2066 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2067 enum rf_pwrstate e_rfpowerstate_toset;
2069 bool actuallyset = false;
2072 if (rtlpci->being_init_adapter)
2074 if (ppsc->swrf_processing)
2076 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2077 if (ppsc->rfchange_inprogress) {
2078 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2081 ppsc->rfchange_inprogress = true;
2082 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2084 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2085 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2086 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2087 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2088 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2089 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2090 "GPIOChangeRF - HW Radio ON, RF ON\n");
2091 e_rfpowerstate_toset = ERFON;
2092 ppsc->hwradiooff = false;
2094 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2095 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2096 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2097 e_rfpowerstate_toset = ERFOFF;
2098 ppsc->hwradiooff = true;
2102 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2103 ppsc->rfchange_inprogress = false;
2104 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2106 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2107 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2108 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2109 ppsc->rfchange_inprogress = false;
2110 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2113 return !ppsc->hwradiooff;
2116 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2117 u8 *p_macaddr, bool is_group, u8 enc_algo,
2118 bool is_wepkey, bool clear_all)
2120 struct rtl_priv *rtlpriv = rtl_priv(hw);
2121 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2122 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2123 u8 *macaddr = p_macaddr;
2125 bool is_pairwise = false;
2126 static u8 cam_const_addr[4][6] = {
2127 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2128 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2129 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2130 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2132 static u8 cam_const_broad[] = {
2133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2139 u8 clear_number = 5;
2140 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2141 for (idx = 0; idx < clear_number; idx++) {
2142 rtl_cam_mark_invalid(hw, cam_offset + idx);
2143 rtl_cam_empty_entry(hw, cam_offset + idx);
2146 memset(rtlpriv->sec.key_buf[idx], 0,
2148 rtlpriv->sec.key_len[idx] = 0;
2153 case WEP40_ENCRYPTION:
2154 enc_algo = CAM_WEP40;
2156 case WEP104_ENCRYPTION:
2157 enc_algo = CAM_WEP104;
2159 case TKIP_ENCRYPTION:
2160 enc_algo = CAM_TKIP;
2162 case AESCCMP_ENCRYPTION:
2166 pr_err("switch case %#x not processed\n",
2168 enc_algo = CAM_TKIP;
2171 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2172 macaddr = cam_const_addr[key_index];
2173 entry_id = key_index;
2176 macaddr = cam_const_broad;
2177 entry_id = key_index;
2179 if (mac->opmode == NL80211_IFTYPE_AP) {
2180 entry_id = rtl_cam_get_free_entry(hw,
2182 if (entry_id >= TOTAL_CAM_ENTRY) {
2183 pr_err("Can not find free hw security cam entry\n");
2187 entry_id = CAM_PAIRWISE_KEY_POSITION;
2189 key_index = PAIRWISE_KEYIDX;
2193 if (rtlpriv->sec.key_len[key_index] == 0) {
2194 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2195 "delete one entry, entry_id is %d\n",
2197 if (mac->opmode == NL80211_IFTYPE_AP)
2198 rtl_cam_del_entry(hw, p_macaddr);
2199 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2201 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2202 "The insert KEY length is %d\n",
2203 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2204 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2205 "The insert KEY is %x %x\n",
2206 rtlpriv->sec.key_buf[0][0],
2207 rtlpriv->sec.key_buf[0][1]);
2208 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2211 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2212 "Pairwise Key content",
2213 rtlpriv->sec.pairwise_key,
2215 sec.key_len[PAIRWISE_KEYIDX]);
2216 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2217 "set Pairwise key\n");
2218 rtl_cam_add_one_entry(hw, macaddr, key_index,
2220 CAM_CONFIG_NO_USEDK,
2222 sec.key_buf[key_index]);
2224 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2226 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2227 rtl_cam_add_one_entry(hw,
2230 CAM_PAIRWISE_KEY_POSITION,
2231 enc_algo, CAM_CONFIG_NO_USEDK,
2232 rtlpriv->sec.key_buf[entry_id]);
2234 rtl_cam_add_one_entry(hw, macaddr, key_index,
2236 CAM_CONFIG_NO_USEDK,
2237 rtlpriv->sec.key_buf
2244 void rtl92de_suspend(struct ieee80211_hw *hw)
2246 struct rtl_priv *rtlpriv = rtl_priv(hw);
2248 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2249 REG_MAC_PHY_CTRL_NORMAL);
2252 void rtl92de_resume(struct ieee80211_hw *hw)
2254 struct rtl_priv *rtlpriv = rtl_priv(hw);
2256 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2257 rtlpriv->rtlhal.macphyctl_reg);