1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
46 u32 rtl92de_read_dword_dbi(struct ieee80211_hw *hw, u16 offset, u8 direct)
48 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 rtl_write_word(rtlpriv, REG_DBI_CTRL, (offset & 0xFFC));
52 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(1) | direct);
54 value = rtl_read_dword(rtlpriv, REG_DBI_RDATA);
58 void rtl92de_write_dword_dbi(struct ieee80211_hw *hw,
59 u16 offset, u32 value, u8 direct)
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 rtl_write_word(rtlpriv, REG_DBI_CTRL, ((offset & 0xFFC) | 0xF000));
64 rtl_write_dword(rtlpriv, REG_DBI_WDATA, value);
65 rtl_write_byte(rtlpriv, REG_DBI_FLAG, BIT(0) | direct);
68 static void _rtl92de_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
69 u8 set_bits, u8 clear_bits)
71 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
72 struct rtl_priv *rtlpriv = rtl_priv(hw);
74 rtlpci->reg_bcn_ctrl_val |= set_bits;
75 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
76 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
79 static void _rtl92de_stop_tx_beacon(struct ieee80211_hw *hw)
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
84 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
85 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
86 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
87 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
88 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
89 tmp1byte &= ~(BIT(0));
90 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
93 static void _rtl92de_resume_tx_beacon(struct ieee80211_hw *hw)
95 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
99 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
100 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
101 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
102 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
104 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
107 static void _rtl92de_enable_bcn_sub_func(struct ieee80211_hw *hw)
109 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(1));
112 static void _rtl92de_disable_bcn_sub_func(struct ieee80211_hw *hw)
114 _rtl92de_set_bcn_ctrl_reg(hw, BIT(1), 0);
117 void rtl92de_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
119 struct rtl_priv *rtlpriv = rtl_priv(hw);
120 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
121 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
125 *((u32 *) (val)) = rtlpci->receive_config;
127 case HW_VAR_RF_STATE:
128 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
130 case HW_VAR_FWLPS_RF_ON:{
131 enum rf_pwrstate rfState;
134 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
136 if (rfState == ERFOFF) {
137 *((bool *) (val)) = true;
139 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
140 val_rcr &= 0x00070000;
142 *((bool *) (val)) = false;
144 *((bool *) (val)) = true;
148 case HW_VAR_FW_PSMODE_STATUS:
149 *((bool *) (val)) = ppsc->fw_current_inpsmode;
151 case HW_VAR_CORRECT_TSF:{
153 u32 *ptsf_low = (u32 *)&tsf;
154 u32 *ptsf_high = ((u32 *)&tsf) + 1;
156 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
157 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
158 *((u64 *) (val)) = tsf;
161 case HW_VAR_INT_MIGRATION:
162 *((bool *)(val)) = rtlpriv->dm.interrupt_migration;
165 *((bool *)(val)) = rtlpriv->dm.disable_tx_int;
168 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
169 "switch case not processed\n");
174 void rtl92de_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
176 struct rtl_priv *rtlpriv = rtl_priv(hw);
177 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
178 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
179 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
180 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
181 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
185 case HW_VAR_ETHER_ADDR:
186 for (idx = 0; idx < ETH_ALEN; idx++) {
187 rtl_write_byte(rtlpriv, (REG_MACID + idx),
191 case HW_VAR_BASIC_RATE: {
192 u16 rate_cfg = ((u16 *) val)[0];
195 rate_cfg = rate_cfg & 0x15f;
196 if (mac->vendor == PEER_CISCO &&
197 ((rate_cfg & 0x150) == 0))
199 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
200 rtl_write_byte(rtlpriv, REG_RRSR + 1,
201 (rate_cfg >> 8) & 0xff);
202 while (rate_cfg > 0x1) {
203 rate_cfg = (rate_cfg >> 1);
206 if (rtlhal->fw_version > 0xe)
207 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
212 for (idx = 0; idx < ETH_ALEN; idx++) {
213 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
218 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
219 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
220 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
221 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
223 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
226 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
229 case HW_VAR_SLOT_TIME: {
232 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
233 "HW_VAR_SLOT_TIME %x\n", val[0]);
234 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
235 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
236 rtlpriv->cfg->ops->set_hw_reg(hw,
241 case HW_VAR_ACK_PREAMBLE: {
243 u8 short_preamble = (bool) (*val);
245 reg_tmp = (mac->cur_40_prime_sc) << 5;
248 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
251 case HW_VAR_AMPDU_MIN_SPACE: {
252 u8 min_spacing_to_set;
255 min_spacing_to_set = *val;
256 if (min_spacing_to_set <= 7) {
258 if (min_spacing_to_set < sec_min_space)
259 min_spacing_to_set = sec_min_space;
260 mac->min_space_cfg = ((mac->min_space_cfg & 0xf8) |
262 *val = min_spacing_to_set;
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
266 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
271 case HW_VAR_SHORTGI_DENSITY: {
274 density_to_set = *val;
275 mac->min_space_cfg = rtlpriv->rtlhal.minspace_cfg;
276 mac->min_space_cfg |= (density_to_set << 3);
277 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
278 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
280 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
284 case HW_VAR_AMPDU_FACTOR: {
287 u8 *ptmp_byte = NULL;
290 if (rtlhal->macphymode == DUALMAC_DUALPHY)
291 regtoSet = 0xb9726641;
292 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
293 regtoSet = 0x66626641;
295 regtoSet = 0xb972a841;
297 if (factor_toset <= 3) {
298 factor_toset = (1 << (factor_toset + 2));
299 if (factor_toset > 0xf)
301 for (index = 0; index < 4; index++) {
302 ptmp_byte = (u8 *) (®toSet) + index;
303 if ((*ptmp_byte & 0xf0) >
305 *ptmp_byte = (*ptmp_byte & 0x0f)
306 | (factor_toset << 4);
307 if ((*ptmp_byte & 0x0f) > factor_toset)
308 *ptmp_byte = (*ptmp_byte & 0xf0)
311 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, regtoSet);
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
318 case HW_VAR_AC_PARAM: {
320 rtl92d_dm_init_edca_turbo(hw);
321 if (rtlpci->acm_method != EACMWAY2_SW)
322 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ACM_CTRL,
326 case HW_VAR_ACM_CTRL: {
328 union aci_aifsn *p_aci_aifsn =
329 (union aci_aifsn *)(&(mac->ac[0].aifs));
330 u8 acm = p_aci_aifsn->f.acm;
331 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
333 acm_ctrl = acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
337 acm_ctrl |= ACMHW_BEQEN;
340 acm_ctrl |= ACMHW_VIQEN;
343 acm_ctrl |= ACMHW_VOQEN;
346 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
347 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
354 acm_ctrl &= (~ACMHW_BEQEN);
357 acm_ctrl &= (~ACMHW_VIQEN);
360 acm_ctrl &= (~ACMHW_VOQEN);
363 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
364 "switch case not processed\n");
368 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
369 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
371 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
375 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
376 rtlpci->receive_config = ((u32 *) (val))[0];
378 case HW_VAR_RETRY_LIMIT: {
379 u8 retry_limit = val[0];
381 rtl_write_word(rtlpriv, REG_RL,
382 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
383 retry_limit << RETRY_LIMIT_LONG_SHIFT);
386 case HW_VAR_DUAL_TSF_RST:
387 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
389 case HW_VAR_EFUSE_BYTES:
390 rtlefuse->efuse_usedbytes = *((u16 *) val);
392 case HW_VAR_EFUSE_USAGE:
393 rtlefuse->efuse_usedpercentage = *val;
396 rtl92d_phy_set_io_cmd(hw, (*(enum io_type *)val));
398 case HW_VAR_WPA_CONFIG:
399 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
401 case HW_VAR_SET_RPWM:
402 rtl92d_fill_h2c_cmd(hw, H2C_PWRM, 1, (val));
404 case HW_VAR_H2C_FW_PWRMODE:
406 case HW_VAR_FW_PSMODE_STATUS:
407 ppsc->fw_current_inpsmode = *((bool *) val);
409 case HW_VAR_H2C_FW_JOINBSSRPT: {
411 u8 tmp_regcr, tmp_reg422;
412 bool recover = false;
414 if (mstatus == RT_MEDIA_CONNECT) {
415 rtlpriv->cfg->ops->set_hw_reg(hw,
417 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
418 rtl_write_byte(rtlpriv, REG_CR + 1,
419 (tmp_regcr | BIT(0)));
420 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
421 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
422 tmp_reg422 = rtl_read_byte(rtlpriv,
423 REG_FWHW_TXQ_CTRL + 2);
424 if (tmp_reg422 & BIT(6))
426 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
427 tmp_reg422 & (~BIT(6)));
428 rtl92d_set_fw_rsvdpagepkt(hw, 0);
429 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
430 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
432 rtl_write_byte(rtlpriv,
433 REG_FWHW_TXQ_CTRL + 2,
435 rtl_write_byte(rtlpriv, REG_CR + 1,
436 (tmp_regcr & ~(BIT(0))));
438 rtl92d_set_fw_joinbss_report_cmd(hw, (*val));
443 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
445 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
449 case HW_VAR_CORRECT_TSF: {
450 u8 btype_ibss = val[0];
453 _rtl92de_stop_tx_beacon(hw);
454 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(3));
455 rtl_write_dword(rtlpriv, REG_TSFTR,
456 (u32) (mac->tsf & 0xffffffff));
457 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
458 (u32) ((mac->tsf >> 32) & 0xffffffff));
459 _rtl92de_set_bcn_ctrl_reg(hw, BIT(3), 0);
461 _rtl92de_resume_tx_beacon(hw);
465 case HW_VAR_INT_MIGRATION: {
466 bool int_migration = *(bool *) (val);
469 /* Set interrupt migration timer and
470 * corresponding Tx/Rx counter.
471 * timer 25ns*0xfa0=100us for 0xf packets.
472 * 0x306:Rx, 0x307:Tx */
473 rtl_write_dword(rtlpriv, REG_INT_MIG, 0xfe000fa0);
474 rtlpriv->dm.interrupt_migration = int_migration;
476 /* Reset all interrupt migration settings. */
477 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
478 rtlpriv->dm.interrupt_migration = int_migration;
482 case HW_VAR_INT_AC: {
483 bool disable_ac_int = *((bool *) val);
485 /* Disable four ACs interrupts. */
486 if (disable_ac_int) {
487 /* Disable VO, VI, BE and BK four AC interrupts
488 * to gain more efficient CPU utilization.
489 * When extremely highly Rx OK occurs,
490 * we will disable Tx interrupts.
492 rtlpriv->cfg->ops->update_interrupt_mask(hw, 0,
494 rtlpriv->dm.disable_tx_int = disable_ac_int;
495 /* Enable four ACs interrupts. */
497 rtlpriv->cfg->ops->update_interrupt_mask(hw,
499 rtlpriv->dm.disable_tx_int = disable_ac_int;
504 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
505 "switch case not processed\n");
510 static bool _rtl92de_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
515 u32 value = _LLT_INIT_ADDR(address) |
516 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
518 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
520 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
521 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
523 if (count > POLLING_LLT_THRESHOLD) {
524 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
525 "Failed to polling write LLT done at address %d!\n",
534 static bool _rtl92de_llt_table_init(struct ieee80211_hw *hw)
536 struct rtl_priv *rtlpriv = rtl_priv(hw);
541 u32 value32; /* High+low page number */
542 u8 value8; /* normal page number */
544 if (rtlpriv->rtlhal.macphymode == SINGLEMAC_SINGLEPHY) {
548 value32 = 0x80bf0d29;
553 value32 = 0x80750005;
556 /* Set reserved page for each queue */
557 /* 11. RQPN 0x200[31:0] = 0x80BD1C1C */
559 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
560 rtl_write_dword(rtlpriv, REG_RQPN, value32);
562 /* 12. TXRKTBUG_PG_BNDY 0x114[31:0] = 0x27FF00F6 */
563 /* TXRKTBUG_PG_BNDY */
564 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY,
565 (rtl_read_word(rtlpriv, REG_TRXFF_BNDY + 2) << 16 |
568 /* 13. TDECTRL[15:8] 0x209[7:0] = 0xF6 */
569 /* Beacon Head for TXDMA */
570 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
572 /* 14. BCNQ_PGBNDY 0x424[7:0] = 0xF6 */
574 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
575 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
577 /* 15. WMAC_LBK_BF_HD 0x45D[7:0] = 0xF6 */
579 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
581 /* Set Tx/Rx page size (Tx must be 128 Bytes, */
582 /* Rx can be 64,128,256,512,1024 bytes) */
583 /* 16. PBP [7:0] = 0x11 */
585 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
587 /* 17. DRV_INFO_SZ = 0x04 */
588 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
590 /* 18. LLT_table_init(Adapter); */
591 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
592 status = _rtl92de_llt_write(hw, i, i + 1);
598 status = _rtl92de_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
602 /* Make the other pages as ring buffer */
603 /* This ring buffer is used as beacon buffer if we */
604 /* config this MAC as two MAC transfer. */
605 /* Otherwise used as local loopback buffer. */
606 for (i = txpktbuf_bndy; i < maxPage; i++) {
607 status = _rtl92de_llt_write(hw, i, (i + 1));
612 /* Let last entry point to the start entry of ring buffer */
613 status = _rtl92de_llt_write(hw, maxPage, txpktbuf_bndy);
620 static void _rtl92de_gen_refresh_led_state(struct ieee80211_hw *hw)
622 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
623 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
624 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
625 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
627 if (rtlpci->up_first_time)
629 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
630 rtl92de_sw_led_on(hw, pLed0);
631 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
632 rtl92de_sw_led_on(hw, pLed0);
634 rtl92de_sw_led_off(hw, pLed0);
637 static bool _rtl92de_init_mac(struct ieee80211_hw *hw)
639 struct rtl_priv *rtlpriv = rtl_priv(hw);
640 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
641 unsigned char bytetmp;
642 unsigned short wordtmp;
645 rtl92d_phy_set_poweron(hw);
646 /* Add for resume sequence of power domain according
647 * to power document V11. Chapter V.11.... */
648 /* 0. RSV_CTRL 0x1C[7:0] = 0x00 */
649 /* unlock ISO/CLK/Power control register */
650 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
651 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x05);
653 /* 1. AFE_XTAL_CTRL [7:0] = 0x0F enable XTAL */
654 /* 2. SPS0_CTRL 0x11[7:0] = 0x2b enable SPS into PWM mode */
655 /* 3. delay (1ms) this is not necessary when initially power on */
657 /* C. Resume Sequence */
658 /* a. SPS0_CTRL 0x11[7:0] = 0x2b */
659 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
661 /* b. AFE_XTAL_CTRL [7:0] = 0x0F */
662 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
664 /* c. DRV runs power on init flow */
666 /* auto enable WLAN */
667 /* 4. APS_FSMCO 0x04[8] = 1; wait till 0x04[8] = 0 */
668 /* Power On Reset for MAC Block */
669 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
671 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
674 /* 5. Wait while 0x04[8] == 0 goto 2, otherwise goto 1 */
675 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
678 while ((bytetmp & BIT(0)) && retry < 1000) {
680 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
684 /* Enable Radio off, GPIO, and LED function */
685 /* 6. APS_FSMCO 0x04[15:0] = 0x0012 when enable HWPDN */
686 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
688 /* release RF digital isolation */
689 /* 7. SYS_ISO_CTRL 0x01[1] = 0x0; */
690 /*Set REG_SYS_ISO_CTRL 0x1=0x82 to prevent wake# problem. */
691 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
694 /* make sure that BB reset OK. */
695 /* rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3); */
697 /* Disable REG_CR before enable it to assure reset */
698 rtl_write_word(rtlpriv, REG_CR, 0x0);
700 /* Release MAC IO register reset */
701 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
703 /* clear stopping tx/rx dma */
704 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0x0);
706 /* rtl_write_word(rtlpriv,REG_CR+2, 0x2); */
709 /* 18. LLT_table_init(Adapter); */
710 if (!_rtl92de_llt_table_init(hw))
713 /* Clear interrupt and enable interrupt */
714 /* 19. HISR 0x124[31:0] = 0xffffffff; */
715 /* HISRE 0x12C[7:0] = 0xFF */
716 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
717 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
719 /* 20. HIMR 0x120[31:0] |= [enable INT mask bit map]; */
720 /* 21. HIMRE 0x128[7:0] = [enable INT mask bit map] */
721 /* The IMR should be enabled later after all init sequence
724 /* 22. PCIE configuration space configuration */
725 /* 23. Ensure PCIe Device 0x80[15:0] = 0x0143 (ASPM+CLKREQ), */
726 /* and PCIe gated clock function is enabled. */
727 /* PCIE configuration space will be written after
728 * all init sequence.(Or by BIOS) */
730 rtl92d_phy_config_maccoexist_rfpage(hw);
732 /* THe below section is not related to power document Vxx . */
733 /* This is only useful for driver and OS setting. */
734 /* -------------------Software Relative Setting---------------------- */
735 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
738 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
740 /* Reported Tx status from HW for rate adaptive. */
741 /* This should be realtive to power on step 14. But in document V11 */
742 /* still not contain the description.!!! */
743 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
745 /* Set Tx/Rx page size (Tx must be 128 Bytes,
746 * Rx can be 64,128,256,512,1024 bytes) */
747 /* rtl_write_byte(rtlpriv,REG_PBP, 0x11); */
749 /* Set RCR register */
750 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
751 /* rtl_write_byte(rtlpriv,REG_RX_DRVINFO_SZ, 4); */
753 /* Set TCR register */
754 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
756 /* disable earlymode */
757 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
759 /* Set TX/RX descriptor physical address(from OS API). */
760 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
761 rtlpci->tx_ring[BEACON_QUEUE].dma);
762 rtl_write_dword(rtlpriv, REG_MGQ_DESA, rtlpci->tx_ring[MGNT_QUEUE].dma);
763 rtl_write_dword(rtlpriv, REG_VOQ_DESA, rtlpci->tx_ring[VO_QUEUE].dma);
764 rtl_write_dword(rtlpriv, REG_VIQ_DESA, rtlpci->tx_ring[VI_QUEUE].dma);
765 rtl_write_dword(rtlpriv, REG_BEQ_DESA, rtlpci->tx_ring[BE_QUEUE].dma);
766 rtl_write_dword(rtlpriv, REG_BKQ_DESA, rtlpci->tx_ring[BK_QUEUE].dma);
767 rtl_write_dword(rtlpriv, REG_HQ_DESA, rtlpci->tx_ring[HIGH_QUEUE].dma);
768 /* Set RX Desc Address */
769 rtl_write_dword(rtlpriv, REG_RX_DESA,
770 rtlpci->rx_ring[RX_MPDU_QUEUE].dma);
772 /* if we want to support 64 bit DMA, we should set it here,
773 * but now we do not support 64 bit DMA*/
775 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x33);
777 /* Reset interrupt migration setting when initialization */
778 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
780 /* Reconsider when to do this operation after asking HWSD. */
781 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
782 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
785 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
786 } while ((retry < 200) && !(bytetmp & BIT(7)));
788 /* After MACIO reset,we must refresh LED state. */
789 _rtl92de_gen_refresh_led_state(hw);
791 /* Reset H2C protection register */
792 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
797 static void _rtl92de_hw_configure(struct ieee80211_hw *hw)
799 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
800 struct rtl_priv *rtlpriv = rtl_priv(hw);
801 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
802 u8 reg_bw_opmode = BW_OPMODE_20MHZ;
805 reg_rrsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
806 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
807 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
808 rtl_write_dword(rtlpriv, REG_RRSR, reg_rrsr);
809 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
810 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
811 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
812 rtl_write_word(rtlpriv, REG_RL, 0x0707);
813 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
814 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
815 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
816 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
817 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
818 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
819 /* Aggregation threshold */
820 if (rtlhal->macphymode == DUALMAC_DUALPHY)
821 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb9726641);
822 else if (rtlhal->macphymode == DUALMAC_SINGLEPHY)
823 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x66626641);
825 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
826 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
827 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0x0a);
828 rtlpci->reg_bcn_ctrl_val = 0x1f;
829 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
830 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
831 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
832 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
833 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
835 rtl_write_word(rtlpriv, REG_FAST_EDCA_CTRL, 0x6666);
836 /* ACKTO for IOT issue. */
837 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
838 /* Set Spec SIFS (used in NAV) */
839 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
840 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
841 /* Set SIFS for CCK */
842 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
843 /* Set SIFS for OFDM */
844 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
845 /* Set Multicast Address. */
846 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
847 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
848 switch (rtlpriv->phy.rf_type) {
851 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_1T << 3);
855 rtlhal->minspace_cfg = (MAX_MSS_DENSITY_2T << 3);
860 static void _rtl92de_enable_aspm_back_door(struct ieee80211_hw *hw)
862 struct rtl_priv *rtlpriv = rtl_priv(hw);
863 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
865 rtl_write_byte(rtlpriv, 0x34b, 0x93);
866 rtl_write_word(rtlpriv, 0x350, 0x870c);
867 rtl_write_byte(rtlpriv, 0x352, 0x1);
868 if (ppsc->support_backdoor)
869 rtl_write_byte(rtlpriv, 0x349, 0x1b);
871 rtl_write_byte(rtlpriv, 0x349, 0x03);
872 rtl_write_word(rtlpriv, 0x350, 0x2718);
873 rtl_write_byte(rtlpriv, 0x352, 0x1);
876 void rtl92de_enable_hw_security_config(struct ieee80211_hw *hw)
878 struct rtl_priv *rtlpriv = rtl_priv(hw);
881 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
882 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
883 rtlpriv->sec.pairwise_enc_algorithm,
884 rtlpriv->sec.group_enc_algorithm);
885 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
886 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
887 "not open hw encryption\n");
890 sec_reg_value = SCR_TXENCENABLE | SCR_RXENCENABLE;
891 if (rtlpriv->sec.use_defaultkey) {
892 sec_reg_value |= SCR_TXUSEDK;
893 sec_reg_value |= SCR_RXUSEDK;
895 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
896 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
897 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
898 "The SECR-value %x\n", sec_reg_value);
899 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
902 int rtl92de_hw_init(struct ieee80211_hw *hw)
904 struct rtl_priv *rtlpriv = rtl_priv(hw);
905 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
906 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
907 struct rtl_phy *rtlphy = &(rtlpriv->phy);
908 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
909 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
910 bool rtstatus = true;
916 rtlpci->being_init_adapter = true;
917 rtlpci->init_ready = false;
918 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
919 /* we should do iqk after disable/enable */
920 rtl92d_phy_reset_iqk_result(hw);
921 /* rtlpriv->intf_ops->disable_aspm(hw); */
922 rtstatus = _rtl92de_init_mac(hw);
924 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
926 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
929 err = rtl92d_download_fw(hw);
930 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
932 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
933 "Failed to download FW. Init HW without FW..\n");
936 rtlhal->last_hmeboxnum = 0;
937 rtlpriv->psc.fw_current_inpsmode = false;
939 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
940 tmp_u1b = tmp_u1b | 0x30;
941 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
943 if (rtlhal->earlymode_enable) {
944 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
945 "EarlyMode Enabled!!!\n");
947 tmp_u1b = rtl_read_byte(rtlpriv, 0x4d0);
948 tmp_u1b = tmp_u1b | 0x1f;
949 rtl_write_byte(rtlpriv, 0x4d0, tmp_u1b);
951 rtl_write_byte(rtlpriv, 0x4d3, 0x80);
953 tmp_u1b = rtl_read_byte(rtlpriv, 0x605);
954 tmp_u1b = tmp_u1b | 0x40;
955 rtl_write_byte(rtlpriv, 0x605, tmp_u1b);
959 rtl_write_byte(rtlpriv, REG_RD_CTRL, 0xff);
960 rtl_write_word(rtlpriv, REG_RD_NAV_NXT, 0x200);
961 rtl_write_byte(rtlpriv, REG_RD_RESP_PKT_TH, 0x05);
964 rtl92d_phy_mac_config(hw);
965 /* because last function modify RCR, so we update
966 * rcr var here, or TP will unstable for receive_config
967 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
968 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
969 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
970 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
972 rtl92d_phy_bb_config(hw);
974 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
975 /* set before initialize RF */
976 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
979 rtl92d_phy_rf_config(hw);
981 /* After read predefined TXT, we must set BB/MAC/RF
982 * register as our requirement */
983 /* After load BB,RF params,we need do more for 92D. */
984 rtl92d_update_bbrf_configuration(hw);
985 /* set default value after initialize RF, */
986 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0);
987 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
988 RF_CHNLBW, RFREG_OFFSET_MASK);
989 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
990 RF_CHNLBW, RFREG_OFFSET_MASK);
992 /*---- Set CCK and OFDM Block "ON"----*/
993 if (rtlhal->current_bandtype == BAND_ON_2_4G)
994 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
995 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
996 if (rtlhal->interfaceindex == 0) {
997 /* RFPGA0_ANALOGPARAMETER2: cck clock select,
998 * set to 20MHz by default */
999 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10) |
1003 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(11) |
1007 _rtl92de_hw_configure(hw);
1010 rtl_cam_reset_all_entry(hw);
1011 rtl92de_enable_hw_security_config(hw);
1013 /* Read EEPROM TX power index and PHY_REG_PG.txt to capture correct */
1014 /* TX power index for different rate set. */
1015 rtl92d_phy_get_hw_reg_originalvalue(hw);
1016 rtl92d_phy_set_txpower_level(hw, rtlphy->current_channel);
1018 ppsc->rfpwr_state = ERFON;
1020 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1022 _rtl92de_enable_aspm_back_door(hw);
1023 /* rtlpriv->intf_ops->enable_aspm(hw); */
1026 rtlpci->being_init_adapter = false;
1028 if (ppsc->rfpwr_state == ERFON) {
1029 rtl92d_phy_lc_calibrate(hw);
1030 /* 5G and 2.4G must wait sometime to let RF LO ready */
1031 if (rtlhal->macphymode == DUALMAC_DUALPHY) {
1033 for (i = 0; i < 10000; i++) {
1034 udelay(MAX_STALL_TIME);
1036 tmp_rega = rtl_get_rfreg(hw,
1037 (enum radio_path)RF90_PATH_A,
1040 if (((tmp_rega & BIT(11)) == BIT(11)))
1043 /* check that loop was successful. If not, exit now */
1045 rtlpci->init_ready = false;
1050 rtlpci->init_ready = true;
1054 static enum version_8192d _rtl92de_read_chip_version(struct ieee80211_hw *hw)
1056 struct rtl_priv *rtlpriv = rtl_priv(hw);
1057 enum version_8192d version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1060 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1061 if (!(value32 & 0x000f0000)) {
1062 version = VERSION_TEST_CHIP_92D_SINGLEPHY;
1063 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "TEST CHIP!!!\n");
1065 version = VERSION_NORMAL_CHIP_92D_SINGLEPHY;
1066 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Normal CHIP!!!\n");
1071 static int _rtl92de_set_media_status(struct ieee80211_hw *hw,
1072 enum nl80211_iftype type)
1074 struct rtl_priv *rtlpriv = rtl_priv(hw);
1075 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1076 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1081 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1082 type == NL80211_IFTYPE_STATION) {
1083 _rtl92de_stop_tx_beacon(hw);
1084 _rtl92de_enable_bcn_sub_func(hw);
1085 } else if (type == NL80211_IFTYPE_ADHOC ||
1086 type == NL80211_IFTYPE_AP) {
1087 _rtl92de_resume_tx_beacon(hw);
1088 _rtl92de_disable_bcn_sub_func(hw);
1090 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1091 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1094 bcnfunc_enable = rtl_read_byte(rtlpriv, REG_BCN_CTRL);
1096 case NL80211_IFTYPE_UNSPECIFIED:
1097 bt_msr |= MSR_NOLINK;
1098 ledaction = LED_CTL_LINK;
1099 bcnfunc_enable &= 0xF7;
1100 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1101 "Set Network type to NO LINK!\n");
1103 case NL80211_IFTYPE_ADHOC:
1104 bt_msr |= MSR_ADHOC;
1105 bcnfunc_enable |= 0x08;
1106 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1107 "Set Network type to Ad Hoc!\n");
1109 case NL80211_IFTYPE_STATION:
1110 bt_msr |= MSR_INFRA;
1111 ledaction = LED_CTL_LINK;
1112 bcnfunc_enable &= 0xF7;
1113 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1114 "Set Network type to STA!\n");
1116 case NL80211_IFTYPE_AP:
1118 bcnfunc_enable |= 0x08;
1119 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1120 "Set Network type to AP!\n");
1123 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1124 "Network type %d not supported!\n", type);
1129 rtl_write_byte(rtlpriv, MSR, bt_msr);
1130 rtlpriv->cfg->ops->led_control(hw, ledaction);
1131 if ((bt_msr & MSR_MASK) == MSR_AP)
1132 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1134 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1138 void rtl92de_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1140 struct rtl_priv *rtlpriv = rtl_priv(hw);
1143 if (rtlpriv->psc.rfpwr_state != ERFON)
1146 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1149 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1150 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1151 _rtl92de_set_bcn_ctrl_reg(hw, 0, BIT(4));
1152 } else if (!check_bssid) {
1153 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1154 _rtl92de_set_bcn_ctrl_reg(hw, BIT(4), 0);
1155 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1159 int rtl92de_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1161 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 if (_rtl92de_set_media_status(hw, type))
1167 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1168 if (type != NL80211_IFTYPE_AP)
1169 rtl92de_set_check_bssid(hw, true);
1171 rtl92de_set_check_bssid(hw, false);
1176 /* do iqk or reload iqk */
1177 /* windows just rtl92d_phy_reload_iqk_setting in set channel,
1178 * but it's very strict for time sequence so we add
1179 * rtl92d_phy_reload_iqk_setting here */
1180 void rtl92d_linked_set_reg(struct ieee80211_hw *hw)
1182 struct rtl_priv *rtlpriv = rtl_priv(hw);
1183 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1185 u8 channel = rtlphy->current_channel;
1187 indexforchannel = rtl92d_get_rightchnlplace_for_iqk(channel);
1188 if (!rtlphy->iqk_matrix[indexforchannel].iqk_done) {
1189 RT_TRACE(rtlpriv, COMP_SCAN | COMP_INIT, DBG_DMESG,
1190 "Do IQK for channel:%d\n", channel);
1191 rtl92d_phy_iq_calibrate(hw);
1195 /* don't set REG_EDCA_BE_PARAM here because
1196 * mac80211 will send pkt when scan */
1197 void rtl92de_set_qos(struct ieee80211_hw *hw, int aci)
1199 rtl92d_dm_init_edca_turbo(hw);
1202 void rtl92de_enable_interrupt(struct ieee80211_hw *hw)
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1205 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1207 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1208 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1209 rtlpci->irq_enabled = true;
1212 void rtl92de_disable_interrupt(struct ieee80211_hw *hw)
1214 struct rtl_priv *rtlpriv = rtl_priv(hw);
1215 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1217 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1218 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1219 rtlpci->irq_enabled = false;
1222 static void _rtl92de_poweroff_adapter(struct ieee80211_hw *hw)
1224 struct rtl_priv *rtlpriv = rtl_priv(hw);
1226 unsigned long flags;
1228 rtlpriv->intf_ops->enable_aspm(hw);
1229 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1230 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(3), 0);
1231 rtl_set_bbreg(hw, RFPGA0_XCD_RFPARAMETER, BIT(15), 0);
1233 /* 0x20:value 05-->04 */
1234 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1236 /* ==== Reset digital sequence ====== */
1237 rtl92d_firmware_selfreset(hw);
1239 /* f. SYS_FUNC_EN 0x03[7:0]=0x51 reset MCU, MAC register, DCORE */
1240 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1242 /* g. MCUFWDL 0x80[1:0]=0 reset MCU ready status */
1243 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1245 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1247 /* h. GPIO_PIN_CTRL 0x44[31:0]=0x000 */
1248 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1250 /* i. Value = GPIO_PIN_CTRL[7:0] */
1251 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1253 /* j. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); */
1254 /* write external PIN level */
1255 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL,
1256 0x00FF0000 | (u1b_tmp << 8));
1258 /* k. GPIO_MUXCFG 0x42 [15:0] = 0x0780 */
1259 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1261 /* l. LEDCFG 0x4C[15:0] = 0x8080 */
1262 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1264 /* ==== Disable analog sequence === */
1266 /* m. AFE_PLL_CTRL[7:0] = 0x80 disable PLL */
1267 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1269 /* n. SPS0_CTRL 0x11[7:0] = 0x22 enter PFM mode */
1270 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1272 /* o. AFE_XTAL_CTRL 0x24[7:0] = 0x0E disable XTAL, if No BT COEX */
1273 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1275 /* p. RSV_CTRL 0x1C[7:0] = 0x0E lock ISO/CLK/Power control register */
1276 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1278 /* ==== interface into suspend === */
1280 /* q. APS_FSMCO[15:8] = 0x58 PCIe suspend mode */
1281 /* According to power document V11, we need to set this */
1282 /* value as 0x18. Otherwise, we may not L0s sometimes. */
1283 /* This indluences power consumption. Bases on SD1's test, */
1284 /* set as 0x00 do not affect power current. And if it */
1285 /* is set as 0x18, they had ever met auto load fail problem. */
1286 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1288 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1289 "In PowerOff,reg0x%x=%X\n",
1290 REG_SPS0_CTRL, rtl_read_byte(rtlpriv, REG_SPS0_CTRL));
1291 /* r. Note: for PCIe interface, PON will not turn */
1292 /* off m-bias and BandGap in PCIe suspend mode. */
1294 /* 0x17[7] 1b': power off in process 0b' : power off over */
1295 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
1296 spin_lock_irqsave(&globalmutex_power, flags);
1297 u1b_tmp = rtl_read_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS);
1298 u1b_tmp &= (~BIT(7));
1299 rtl_write_byte(rtlpriv, REG_POWER_OFF_IN_PROCESS, u1b_tmp);
1300 spin_unlock_irqrestore(&globalmutex_power, flags);
1303 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "<=======\n");
1306 void rtl92de_card_disable(struct ieee80211_hw *hw)
1308 struct rtl_priv *rtlpriv = rtl_priv(hw);
1309 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1310 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1311 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1312 enum nl80211_iftype opmode;
1314 mac->link_state = MAC80211_NOLINK;
1315 opmode = NL80211_IFTYPE_UNSPECIFIED;
1316 _rtl92de_set_media_status(hw, opmode);
1318 if (rtlpci->driver_is_goingto_unload ||
1319 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1320 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1321 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1322 /* Power sequence for each MAC. */
1323 /* a. stop tx DMA */
1325 /* c. clear rx buf */
1326 /* d. stop rx DMA */
1329 /* a. stop tx DMA */
1330 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xFE);
1333 /* b. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue */
1335 /* c. ========RF OFF sequence========== */
1336 /* 0x88c[23:20] = 0xf. */
1337 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER4, 0x00f00000, 0xf);
1338 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1340 /* APSD_CTRL 0x600[7:0] = 0x40 */
1341 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1343 /* Close antenna 0,0xc04,0xd04 */
1344 rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0);
1345 rtl_set_bbreg(hw, ROFDM1_TRXPATHENABLE, BDWORD, 0);
1347 /* SYS_FUNC_EN 0x02[7:0] = 0xE2 reset BB state machine */
1348 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1350 /* Mac0 can not do Global reset. Mac1 can do. */
1351 /* SYS_FUNC_EN 0x02[7:0] = 0xE0 reset BB state machine */
1352 if (rtlpriv->rtlhal.interfaceindex == 1)
1353 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1356 /* d. stop tx/rx dma before disable REG_CR (0x100) to fix */
1357 /* dma hang issue when disable/enable device. */
1358 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 1, 0xff);
1360 rtl_write_byte(rtlpriv, REG_CR, 0x0);
1361 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "==> Do power off.......\n");
1362 if (rtl92d_phy_check_poweroff(hw))
1363 _rtl92de_poweroff_adapter(hw);
1367 void rtl92de_interrupt_recognized(struct ieee80211_hw *hw,
1368 u32 *p_inta, u32 *p_intb)
1370 struct rtl_priv *rtlpriv = rtl_priv(hw);
1371 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1373 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1374 rtl_write_dword(rtlpriv, ISR, *p_inta);
1377 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1378 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1382 void rtl92de_set_beacon_related_registers(struct ieee80211_hw *hw)
1384 struct rtl_priv *rtlpriv = rtl_priv(hw);
1385 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1386 u16 bcn_interval, atim_window;
1388 bcn_interval = mac->beacon_interval;
1390 rtl92de_disable_interrupt(hw);
1391 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1392 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1393 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1394 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x20);
1395 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
1396 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x30);
1398 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x20);
1399 rtl_write_byte(rtlpriv, 0x606, 0x30);
1402 void rtl92de_set_beacon_interval(struct ieee80211_hw *hw)
1404 struct rtl_priv *rtlpriv = rtl_priv(hw);
1405 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1406 u16 bcn_interval = mac->beacon_interval;
1408 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1409 "beacon_interval:%d\n", bcn_interval);
1410 rtl92de_disable_interrupt(hw);
1411 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1412 rtl92de_enable_interrupt(hw);
1415 void rtl92de_update_interrupt_mask(struct ieee80211_hw *hw,
1416 u32 add_msr, u32 rm_msr)
1418 struct rtl_priv *rtlpriv = rtl_priv(hw);
1419 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1421 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1424 rtlpci->irq_mask[0] |= add_msr;
1426 rtlpci->irq_mask[0] &= (~rm_msr);
1427 rtl92de_disable_interrupt(hw);
1428 rtl92de_enable_interrupt(hw);
1431 static void _rtl92de_readpowervalue_fromprom(struct txpower_info *pwrinfo,
1432 u8 *rom_content, bool autoLoadfail)
1434 u32 rfpath, eeaddr, group, offset1, offset2;
1437 memset(pwrinfo, 0, sizeof(struct txpower_info));
1439 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1440 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1441 if (group < CHANNEL_GROUP_MAX_2G) {
1442 pwrinfo->cck_index[rfpath][group] =
1443 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1444 pwrinfo->ht40_1sindex[rfpath][group] =
1445 EEPROM_DEFAULT_TXPOWERLEVEL_2G;
1447 pwrinfo->ht40_1sindex[rfpath][group] =
1448 EEPROM_DEFAULT_TXPOWERLEVEL_5G;
1450 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1451 EEPROM_DEFAULT_HT40_2SDIFF;
1452 pwrinfo->ht20indexdiff[rfpath][group] =
1453 EEPROM_DEFAULT_HT20_DIFF;
1454 pwrinfo->ofdmindexdiff[rfpath][group] =
1455 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1456 pwrinfo->ht40maxoffset[rfpath][group] =
1457 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1458 pwrinfo->ht20maxoffset[rfpath][group] =
1459 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1462 for (i = 0; i < 3; i++) {
1463 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1464 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1469 /* Maybe autoload OK,buf the tx power index value is not filled.
1470 * If we find it, we set it to default value. */
1471 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1472 for (group = 0; group < CHANNEL_GROUP_MAX_2G; group++) {
1473 eeaddr = EEPROM_CCK_TX_PWR_INX_2G + (rfpath * 3)
1475 pwrinfo->cck_index[rfpath][group] =
1476 (rom_content[eeaddr] == 0xFF) ?
1478 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1479 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1480 rom_content[eeaddr];
1483 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1484 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1485 offset1 = group / 3;
1486 offset2 = group % 3;
1487 eeaddr = EEPROM_HT40_1S_TX_PWR_INX_2G + (rfpath * 3) +
1488 offset2 + offset1 * 21;
1489 pwrinfo->ht40_1sindex[rfpath][group] =
1490 (rom_content[eeaddr] == 0xFF) ? (eeaddr > 0x7B ?
1491 EEPROM_DEFAULT_TXPOWERLEVEL_5G :
1492 EEPROM_DEFAULT_TXPOWERLEVEL_2G) :
1493 rom_content[eeaddr];
1496 /* These just for 92D efuse offset. */
1497 for (group = 0; group < CHANNEL_GROUP_MAX; group++) {
1498 for (rfpath = 0; rfpath < RF6052_MAX_PATH; rfpath++) {
1499 int base1 = EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G;
1501 offset1 = group / 3;
1502 offset2 = group % 3;
1504 if (rom_content[base1 + offset2 + offset1 * 21] != 0xFF)
1505 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1506 (rom_content[base1 +
1507 offset2 + offset1 * 21] >> (rfpath * 4))
1510 pwrinfo->ht40_2sindexdiff[rfpath][group] =
1511 EEPROM_DEFAULT_HT40_2SDIFF;
1512 if (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G + offset2
1513 + offset1 * 21] != 0xFF)
1514 pwrinfo->ht20indexdiff[rfpath][group] =
1515 (rom_content[EEPROM_HT20_TX_PWR_INX_DIFF_2G
1516 + offset2 + offset1 * 21] >> (rfpath * 4))
1519 pwrinfo->ht20indexdiff[rfpath][group] =
1520 EEPROM_DEFAULT_HT20_DIFF;
1521 if (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G + offset2
1522 + offset1 * 21] != 0xFF)
1523 pwrinfo->ofdmindexdiff[rfpath][group] =
1524 (rom_content[EEPROM_OFDM_TX_PWR_INX_DIFF_2G
1525 + offset2 + offset1 * 21] >> (rfpath * 4))
1528 pwrinfo->ofdmindexdiff[rfpath][group] =
1529 EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1530 if (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G + offset2
1531 + offset1 * 21] != 0xFF)
1532 pwrinfo->ht40maxoffset[rfpath][group] =
1533 (rom_content[EEPROM_HT40_MAX_PWR_OFFSET_2G
1534 + offset2 + offset1 * 21] >> (rfpath * 4))
1537 pwrinfo->ht40maxoffset[rfpath][group] =
1538 EEPROM_DEFAULT_HT40_PWRMAXOFFSET;
1539 if (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G + offset2
1540 + offset1 * 21] != 0xFF)
1541 pwrinfo->ht20maxoffset[rfpath][group] =
1542 (rom_content[EEPROM_HT20_MAX_PWR_OFFSET_2G +
1543 offset2 + offset1 * 21] >> (rfpath * 4)) &
1546 pwrinfo->ht20maxoffset[rfpath][group] =
1547 EEPROM_DEFAULT_HT20_PWRMAXOFFSET;
1550 if (rom_content[EEPROM_TSSI_A_5G] != 0xFF) {
1552 pwrinfo->tssi_a[0] = rom_content[EEPROM_TSSI_A_5G] & 0x3F;
1553 pwrinfo->tssi_b[0] = rom_content[EEPROM_TSSI_B_5G] & 0x3F;
1555 pwrinfo->tssi_a[1] = rom_content[EEPROM_TSSI_AB_5G] & 0x3F;
1556 pwrinfo->tssi_b[1] =
1557 (rom_content[EEPROM_TSSI_AB_5G] & 0xC0) >> 6 |
1558 (rom_content[EEPROM_TSSI_AB_5G + 1] & 0x0F) << 2;
1560 pwrinfo->tssi_a[2] = (rom_content[EEPROM_TSSI_AB_5G + 1] &
1562 (rom_content[EEPROM_TSSI_AB_5G + 2] & 0x03) << 4;
1563 pwrinfo->tssi_b[2] = (rom_content[EEPROM_TSSI_AB_5G + 2] &
1566 for (i = 0; i < 3; i++) {
1567 pwrinfo->tssi_a[i] = EEPROM_DEFAULT_TSSI;
1568 pwrinfo->tssi_b[i] = EEPROM_DEFAULT_TSSI;
1573 static void _rtl92de_read_txpower_info(struct ieee80211_hw *hw,
1574 bool autoload_fail, u8 *hwinfo)
1576 struct rtl_priv *rtlpriv = rtl_priv(hw);
1577 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1578 struct txpower_info pwrinfo;
1579 u8 tempval[2], i, pwr, diff;
1580 u32 ch, rfPath, group;
1582 _rtl92de_readpowervalue_fromprom(&pwrinfo, hwinfo, autoload_fail);
1583 if (!autoload_fail) {
1585 rtlefuse->eeprom_regulatory = (hwinfo[EEPROM_RF_OPT1] & 0x7);
1586 rtlefuse->eeprom_thermalmeter =
1587 hwinfo[EEPROM_THERMAL_METER] & 0x1f;
1588 rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_K];
1589 tempval[0] = hwinfo[EEPROM_IQK_DELTA] & 0x03;
1590 tempval[1] = (hwinfo[EEPROM_LCK_DELTA] & 0x0C) >> 2;
1591 rtlefuse->txpwr_fromeprom = true;
1592 if (IS_92D_D_CUT(rtlpriv->rtlhal.version) ||
1593 IS_92D_E_CUT(rtlpriv->rtlhal.version)) {
1594 rtlefuse->internal_pa_5g[0] =
1595 !((hwinfo[EEPROM_TSSI_A_5G] & BIT(6)) >> 6);
1596 rtlefuse->internal_pa_5g[1] =
1597 !((hwinfo[EEPROM_TSSI_B_5G] & BIT(6)) >> 6);
1598 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1599 "Is D cut,Internal PA0 %d Internal PA1 %d\n",
1600 rtlefuse->internal_pa_5g[0],
1601 rtlefuse->internal_pa_5g[1]);
1603 rtlefuse->eeprom_c9 = hwinfo[EEPROM_RF_OPT6];
1604 rtlefuse->eeprom_cc = hwinfo[EEPROM_RF_OPT7];
1606 rtlefuse->eeprom_regulatory = 0;
1607 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1608 rtlefuse->crystalcap = EEPROM_DEFAULT_CRYSTALCAP;
1609 tempval[0] = tempval[1] = 3;
1612 /* Use default value to fill parameters if
1613 * efuse is not filled on some place. */
1615 /* ThermalMeter from EEPROM */
1616 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
1617 rtlefuse->eeprom_thermalmeter > 0x1c)
1618 rtlefuse->eeprom_thermalmeter = 0x12;
1619 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1622 if (rtlefuse->crystalcap == 0xFF)
1623 rtlefuse->crystalcap = 0;
1624 if (rtlefuse->eeprom_regulatory > 3)
1625 rtlefuse->eeprom_regulatory = 0;
1627 for (i = 0; i < 2; i++) {
1628 switch (tempval[i]) {
1645 rtlefuse->delta_iqk = tempval[0];
1647 rtlefuse->delta_lck = tempval[1] - 1;
1648 if (rtlefuse->eeprom_c9 == 0xFF)
1649 rtlefuse->eeprom_c9 = 0x00;
1650 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1651 "EEPROMRegulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1652 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1653 "ThermalMeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1654 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1655 "CrystalCap = 0x%x\n", rtlefuse->crystalcap);
1656 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1657 "Delta_IQK = 0x%x Delta_LCK = 0x%x\n",
1658 rtlefuse->delta_iqk, rtlefuse->delta_lck);
1660 for (rfPath = 0; rfPath < RF6052_MAX_PATH; rfPath++) {
1661 for (ch = 0; ch < CHANNEL_MAX_NUMBER; ch++) {
1662 group = rtl92d_get_chnlgroup_fromarray((u8) ch);
1663 if (ch < CHANNEL_MAX_NUMBER_2G)
1664 rtlefuse->txpwrlevel_cck[rfPath][ch] =
1665 pwrinfo.cck_index[rfPath][group];
1666 rtlefuse->txpwrlevel_ht40_1s[rfPath][ch] =
1667 pwrinfo.ht40_1sindex[rfPath][group];
1668 rtlefuse->txpwr_ht20diff[rfPath][ch] =
1669 pwrinfo.ht20indexdiff[rfPath][group];
1670 rtlefuse->txpwr_legacyhtdiff[rfPath][ch] =
1671 pwrinfo.ofdmindexdiff[rfPath][group];
1672 rtlefuse->pwrgroup_ht20[rfPath][ch] =
1673 pwrinfo.ht20maxoffset[rfPath][group];
1674 rtlefuse->pwrgroup_ht40[rfPath][ch] =
1675 pwrinfo.ht40maxoffset[rfPath][group];
1676 pwr = pwrinfo.ht40_1sindex[rfPath][group];
1677 diff = pwrinfo.ht40_2sindexdiff[rfPath][group];
1678 rtlefuse->txpwrlevel_ht40_2s[rfPath][ch] =
1679 (pwr > diff) ? (pwr - diff) : 0;
1684 static void _rtl92de_read_macphymode_from_prom(struct ieee80211_hw *hw,
1687 struct rtl_priv *rtlpriv = rtl_priv(hw);
1688 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1689 u8 macphy_crvalue = content[EEPROM_MAC_FUNCTION];
1691 if (macphy_crvalue & BIT(3)) {
1692 rtlhal->macphymode = SINGLEMAC_SINGLEPHY;
1693 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1694 "MacPhyMode SINGLEMAC_SINGLEPHY\n");
1696 rtlhal->macphymode = DUALMAC_DUALPHY;
1697 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1698 "MacPhyMode DUALMAC_DUALPHY\n");
1702 static void _rtl92de_read_macphymode_and_bandtype(struct ieee80211_hw *hw,
1705 _rtl92de_read_macphymode_from_prom(hw, content);
1706 rtl92d_phy_config_macphymode(hw);
1707 rtl92d_phy_config_macphymode_info(hw);
1710 static void _rtl92de_efuse_update_chip_version(struct ieee80211_hw *hw)
1712 struct rtl_priv *rtlpriv = rtl_priv(hw);
1713 enum version_8192d chipver = rtlpriv->rtlhal.version;
1717 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_H,
1719 rtlpriv->intf_ops->read_efuse_byte(hw, EEPROME_CHIP_VERSION_L,
1721 chipvalue = (cutvalue[1] << 8) | cutvalue[0];
1722 switch (chipvalue) {
1724 chipver |= CHIP_92D_C_CUT;
1725 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "C-CUT!!!\n");
1728 chipver |= CHIP_92D_D_CUT;
1729 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "D-CUT!!!\n");
1732 chipver |= CHIP_92D_E_CUT;
1733 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "E-CUT!!!\n");
1736 chipver |= CHIP_92D_D_CUT;
1737 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Unknown CUT!\n");
1740 rtlpriv->rtlhal.version = chipver;
1743 static void _rtl92de_read_adapter_info(struct ieee80211_hw *hw)
1745 struct rtl_priv *rtlpriv = rtl_priv(hw);
1746 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1747 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1749 u8 hwinfo[HWSET_MAX_SIZE];
1751 unsigned long flags;
1753 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1754 spin_lock_irqsave(&globalmutex_for_power_and_efuse, flags);
1755 rtl_efuse_shadow_map_update(hw);
1756 _rtl92de_efuse_update_chip_version(hw);
1757 spin_unlock_irqrestore(&globalmutex_for_power_and_efuse, flags);
1758 memcpy((void *)hwinfo, (void *)&rtlefuse->efuse_map
1759 [EFUSE_INIT_MAP][0],
1761 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1762 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1763 "RTL819X Not boot from eeprom, check it !!\n");
1765 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1766 hwinfo, HWSET_MAX_SIZE);
1768 eeprom_id = *((u16 *)&hwinfo[0]);
1769 if (eeprom_id != RTL8190_EEPROM_ID) {
1770 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1771 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1772 rtlefuse->autoload_failflag = true;
1774 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1775 rtlefuse->autoload_failflag = false;
1777 if (rtlefuse->autoload_failflag) {
1778 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1779 "RTL819X Not boot from eeprom, check it !!\n");
1782 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
1783 _rtl92de_read_macphymode_and_bandtype(hw, hwinfo);
1785 /* VID, DID SE 0xA-D */
1786 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1787 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1788 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1789 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1790 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROMId = 0x%4x\n", eeprom_id);
1791 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1792 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1793 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1794 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1795 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1796 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1797 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1798 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1800 /* Read Permanent MAC address */
1801 if (rtlhal->interfaceindex == 0) {
1802 for (i = 0; i < 6; i += 2) {
1803 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC0_92D + i];
1804 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1807 for (i = 0; i < 6; i += 2) {
1808 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR_MAC1_92D + i];
1809 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1812 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR,
1813 rtlefuse->dev_addr);
1814 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1815 _rtl92de_read_txpower_info(hw, rtlefuse->autoload_failflag, hwinfo);
1817 /* Read Channel Plan */
1818 switch (rtlhal->bandset) {
1820 rtlefuse->channel_plan = COUNTRY_CODE_TELEC;
1823 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1826 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1829 rtlefuse->channel_plan = COUNTRY_CODE_FCC;
1832 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1833 rtlefuse->txpwr_fromeprom = true;
1834 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1835 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1838 void rtl92de_read_eeprom_info(struct ieee80211_hw *hw)
1840 struct rtl_priv *rtlpriv = rtl_priv(hw);
1841 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1842 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1845 rtlhal->version = _rtl92de_read_chip_version(hw);
1846 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1847 rtlefuse->autoload_status = tmp_u1b;
1848 if (tmp_u1b & BIT(4)) {
1849 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1850 rtlefuse->epromtype = EEPROM_93C46;
1852 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1853 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1855 if (tmp_u1b & BIT(5)) {
1856 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1858 rtlefuse->autoload_failflag = false;
1859 _rtl92de_read_adapter_info(hw);
1861 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1866 static void rtl92de_update_hal_rate_table(struct ieee80211_hw *hw,
1867 struct ieee80211_sta *sta)
1869 struct rtl_priv *rtlpriv = rtl_priv(hw);
1870 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1871 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1872 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1875 u8 nmode = mac->ht_enable;
1876 u8 mimo_ps = IEEE80211_SMPS_OFF;
1879 u8 curtxbw_40mhz = mac->bw_40;
1880 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1882 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1884 enum wireless_mode wirelessmode = mac->mode;
1886 if (rtlhal->current_bandtype == BAND_ON_5G)
1887 ratr_value = sta->supp_rates[1] << 4;
1889 ratr_value = sta->supp_rates[0];
1890 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1891 sta->ht_cap.mcs.rx_mask[0] << 12);
1892 switch (wirelessmode) {
1893 case WIRELESS_MODE_A:
1894 ratr_value &= 0x00000FF0;
1896 case WIRELESS_MODE_B:
1897 if (ratr_value & 0x0000000c)
1898 ratr_value &= 0x0000000d;
1900 ratr_value &= 0x0000000f;
1902 case WIRELESS_MODE_G:
1903 ratr_value &= 0x00000FF5;
1905 case WIRELESS_MODE_N_24G:
1906 case WIRELESS_MODE_N_5G:
1908 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1909 ratr_value &= 0x0007F005;
1913 if (get_rf_type(rtlphy) == RF_1T2R ||
1914 get_rf_type(rtlphy) == RF_1T1R) {
1915 ratr_mask = 0x000ff005;
1917 ratr_mask = 0x0f0ff005;
1920 ratr_value &= ratr_mask;
1924 if (rtlphy->rf_type == RF_1T2R)
1925 ratr_value &= 0x000ff0ff;
1927 ratr_value &= 0x0f0ff0ff;
1931 ratr_value &= 0x0FFFFFFF;
1932 if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
1933 (!curtxbw_40mhz && curshortgi_20mhz))) {
1934 ratr_value |= 0x10000000;
1935 tmp_ratr_value = (ratr_value >> 12);
1936 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1937 if ((1 << shortgi_rate) & tmp_ratr_value)
1940 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1941 (shortgi_rate << 4) | (shortgi_rate);
1943 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1944 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1945 rtl_read_dword(rtlpriv, REG_ARFR0));
1948 static void rtl92de_update_hal_rate_mask(struct ieee80211_hw *hw,
1949 struct ieee80211_sta *sta, u8 rssi_level)
1951 struct rtl_priv *rtlpriv = rtl_priv(hw);
1952 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1953 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1954 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1955 struct rtl_sta_info *sta_entry = NULL;
1958 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1959 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1961 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1963 enum wireless_mode wirelessmode = 0;
1964 bool shortgi = false;
1967 u8 mimo_ps = IEEE80211_SMPS_OFF;
1969 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1970 mimo_ps = sta_entry->mimo_ps;
1971 wirelessmode = sta_entry->wireless_mode;
1972 if (mac->opmode == NL80211_IFTYPE_STATION)
1973 curtxbw_40mhz = mac->bw_40;
1974 else if (mac->opmode == NL80211_IFTYPE_AP ||
1975 mac->opmode == NL80211_IFTYPE_ADHOC)
1976 macid = sta->aid + 1;
1978 if (rtlhal->current_bandtype == BAND_ON_5G)
1979 ratr_bitmap = sta->supp_rates[1] << 4;
1981 ratr_bitmap = sta->supp_rates[0];
1982 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1983 sta->ht_cap.mcs.rx_mask[0] << 12);
1984 switch (wirelessmode) {
1985 case WIRELESS_MODE_B:
1986 ratr_index = RATR_INX_WIRELESS_B;
1987 if (ratr_bitmap & 0x0000000c)
1988 ratr_bitmap &= 0x0000000d;
1990 ratr_bitmap &= 0x0000000f;
1992 case WIRELESS_MODE_G:
1993 ratr_index = RATR_INX_WIRELESS_GB;
1995 if (rssi_level == 1)
1996 ratr_bitmap &= 0x00000f00;
1997 else if (rssi_level == 2)
1998 ratr_bitmap &= 0x00000ff0;
2000 ratr_bitmap &= 0x00000ff5;
2002 case WIRELESS_MODE_A:
2003 ratr_index = RATR_INX_WIRELESS_G;
2004 ratr_bitmap &= 0x00000ff0;
2006 case WIRELESS_MODE_N_24G:
2007 case WIRELESS_MODE_N_5G:
2008 if (wirelessmode == WIRELESS_MODE_N_24G)
2009 ratr_index = RATR_INX_WIRELESS_NGB;
2011 ratr_index = RATR_INX_WIRELESS_NG;
2012 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2013 if (rssi_level == 1)
2014 ratr_bitmap &= 0x00070000;
2015 else if (rssi_level == 2)
2016 ratr_bitmap &= 0x0007f000;
2018 ratr_bitmap &= 0x0007f005;
2020 if (rtlphy->rf_type == RF_1T2R ||
2021 rtlphy->rf_type == RF_1T1R) {
2022 if (curtxbw_40mhz) {
2023 if (rssi_level == 1)
2024 ratr_bitmap &= 0x000f0000;
2025 else if (rssi_level == 2)
2026 ratr_bitmap &= 0x000ff000;
2028 ratr_bitmap &= 0x000ff015;
2030 if (rssi_level == 1)
2031 ratr_bitmap &= 0x000f0000;
2032 else if (rssi_level == 2)
2033 ratr_bitmap &= 0x000ff000;
2035 ratr_bitmap &= 0x000ff005;
2038 if (curtxbw_40mhz) {
2039 if (rssi_level == 1)
2040 ratr_bitmap &= 0x0f0f0000;
2041 else if (rssi_level == 2)
2042 ratr_bitmap &= 0x0f0ff000;
2044 ratr_bitmap &= 0x0f0ff015;
2046 if (rssi_level == 1)
2047 ratr_bitmap &= 0x0f0f0000;
2048 else if (rssi_level == 2)
2049 ratr_bitmap &= 0x0f0ff000;
2051 ratr_bitmap &= 0x0f0ff005;
2055 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2056 (!curtxbw_40mhz && curshortgi_20mhz)) {
2060 else if (macid == 1)
2065 ratr_index = RATR_INX_WIRELESS_NGB;
2067 if (rtlphy->rf_type == RF_1T2R)
2068 ratr_bitmap &= 0x000ff0ff;
2070 ratr_bitmap &= 0x0f0ff0ff;
2074 value[0] = (ratr_bitmap & 0x0fffffff) | (ratr_index << 28);
2075 value[1] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2076 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2077 "ratr_bitmap :%x value0:%x value1:%x\n",
2078 ratr_bitmap, value[0], value[1]);
2079 rtl92d_fill_h2c_cmd(hw, H2C_RA_MASK, 5, (u8 *) value);
2081 sta_entry->ratr_index = ratr_index;
2084 void rtl92de_update_hal_rate_tbl(struct ieee80211_hw *hw,
2085 struct ieee80211_sta *sta, u8 rssi_level)
2087 struct rtl_priv *rtlpriv = rtl_priv(hw);
2089 if (rtlpriv->dm.useramask)
2090 rtl92de_update_hal_rate_mask(hw, sta, rssi_level);
2092 rtl92de_update_hal_rate_table(hw, sta);
2095 void rtl92de_update_channel_access_setting(struct ieee80211_hw *hw)
2097 struct rtl_priv *rtlpriv = rtl_priv(hw);
2098 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2101 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2103 if (!mac->ht_enable)
2104 sifs_timer = 0x0a0a;
2106 sifs_timer = 0x1010;
2107 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2110 bool rtl92de_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2112 struct rtl_priv *rtlpriv = rtl_priv(hw);
2113 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2114 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2115 enum rf_pwrstate e_rfpowerstate_toset;
2117 bool actuallyset = false;
2120 if (rtlpci->being_init_adapter)
2122 if (ppsc->swrf_processing)
2124 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2125 if (ppsc->rfchange_inprogress) {
2126 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2129 ppsc->rfchange_inprogress = true;
2130 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2132 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2133 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2134 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2135 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2136 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2137 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2138 "GPIOChangeRF - HW Radio ON, RF ON\n");
2139 e_rfpowerstate_toset = ERFON;
2140 ppsc->hwradiooff = false;
2142 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2143 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2144 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2145 e_rfpowerstate_toset = ERFOFF;
2146 ppsc->hwradiooff = true;
2150 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2151 ppsc->rfchange_inprogress = false;
2152 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2154 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2155 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2156 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2157 ppsc->rfchange_inprogress = false;
2158 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2161 return !ppsc->hwradiooff;
2164 void rtl92de_set_key(struct ieee80211_hw *hw, u32 key_index,
2165 u8 *p_macaddr, bool is_group, u8 enc_algo,
2166 bool is_wepkey, bool clear_all)
2168 struct rtl_priv *rtlpriv = rtl_priv(hw);
2169 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2170 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2171 u8 *macaddr = p_macaddr;
2173 bool is_pairwise = false;
2174 static u8 cam_const_addr[4][6] = {
2175 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2176 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2177 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2178 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2180 static u8 cam_const_broad[] = {
2181 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2187 u8 clear_number = 5;
2188 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2189 for (idx = 0; idx < clear_number; idx++) {
2190 rtl_cam_mark_invalid(hw, cam_offset + idx);
2191 rtl_cam_empty_entry(hw, cam_offset + idx);
2194 memset(rtlpriv->sec.key_buf[idx], 0,
2196 rtlpriv->sec.key_len[idx] = 0;
2201 case WEP40_ENCRYPTION:
2202 enc_algo = CAM_WEP40;
2204 case WEP104_ENCRYPTION:
2205 enc_algo = CAM_WEP104;
2207 case TKIP_ENCRYPTION:
2208 enc_algo = CAM_TKIP;
2210 case AESCCMP_ENCRYPTION:
2214 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2215 "switch case not processed\n");
2216 enc_algo = CAM_TKIP;
2219 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2220 macaddr = cam_const_addr[key_index];
2221 entry_id = key_index;
2224 macaddr = cam_const_broad;
2225 entry_id = key_index;
2227 if (mac->opmode == NL80211_IFTYPE_AP) {
2228 entry_id = rtl_cam_get_free_entry(hw,
2230 if (entry_id >= TOTAL_CAM_ENTRY) {
2231 RT_TRACE(rtlpriv, COMP_SEC,
2233 "Can not find free hw security cam entry\n");
2237 entry_id = CAM_PAIRWISE_KEY_POSITION;
2239 key_index = PAIRWISE_KEYIDX;
2243 if (rtlpriv->sec.key_len[key_index] == 0) {
2244 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2245 "delete one entry, entry_id is %d\n",
2247 if (mac->opmode == NL80211_IFTYPE_AP)
2248 rtl_cam_del_entry(hw, p_macaddr);
2249 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2251 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2252 "The insert KEY length is %d\n",
2253 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2254 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2255 "The insert KEY is %x %x\n",
2256 rtlpriv->sec.key_buf[0][0],
2257 rtlpriv->sec.key_buf[0][1]);
2258 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2261 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2262 "Pairwise Key content",
2263 rtlpriv->sec.pairwise_key,
2265 sec.key_len[PAIRWISE_KEYIDX]);
2266 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2267 "set Pairwise key\n");
2268 rtl_cam_add_one_entry(hw, macaddr, key_index,
2270 CAM_CONFIG_NO_USEDK,
2272 sec.key_buf[key_index]);
2274 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2276 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2277 rtl_cam_add_one_entry(hw,
2280 CAM_PAIRWISE_KEY_POSITION,
2281 enc_algo, CAM_CONFIG_NO_USEDK,
2282 rtlpriv->sec.key_buf[entry_id]);
2284 rtl_cam_add_one_entry(hw, macaddr, key_index,
2286 CAM_CONFIG_NO_USEDK,
2287 rtlpriv->sec.key_buf
2294 void rtl92de_suspend(struct ieee80211_hw *hw)
2296 struct rtl_priv *rtlpriv = rtl_priv(hw);
2298 rtlpriv->rtlhal.macphyctl_reg = rtl_read_byte(rtlpriv,
2299 REG_MAC_PHY_CTRL_NORMAL);
2302 void rtl92de_resume(struct ieee80211_hw *hw)
2304 struct rtl_priv *rtlpriv = rtl_priv(hw);
2306 rtl_write_byte(rtlpriv, REG_MAC_PHY_CTRL_NORMAL,
2307 rtlpriv->rtlhal.macphyctl_reg);