drivers/net/wireless/realtek/rtlwifi/rtl8192cu/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../cam.h"
  30 #include "../ps.h"
  31 #include "../usb.h"
  32 #include "reg.h"
  33 #include "def.h"
  34 #include "phy.h"
  35 #include "../rtl8192c/phy_common.h"
  36 #include "mac.h"
  37 #include "dm.h"
  38 #include "../rtl8192c/dm_common.h"
  39 #include "../rtl8192c/fw_common.h"
  40 #include "hw.h"
  41 #include "../rtl8192ce/hw.h"
  42 #include "trx.h"
  43 #include "led.h"
  44 #include "table.h"
  45
  46 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
  47 {
  48         struct rtl_priv *rtlpriv = rtl_priv(hw);
  49         struct rtl_phy *rtlphy = &(rtlpriv->phy);
  50         struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
  51
  52         rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
  53         rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
  54         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  55                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  56                         RTL8192CUPHY_REG_Array_PG_HPLength;
  57                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  58                         RTL8192CUPHY_REG_Array_PG_HP;
  59         } else {
  60                 rtlphy->hwparam_tables[PHY_REG_PG].length =
  61                         RTL8192CUPHY_REG_ARRAY_PGLENGTH;
  62                 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
  63                         RTL8192CUPHY_REG_ARRAY_PG;
  64         }
  65         /* 2T */
  66         rtlphy->hwparam_tables[PHY_REG_2T].length =
  67                         RTL8192CUPHY_REG_2TARRAY_LENGTH;
  68         rtlphy->hwparam_tables[PHY_REG_2T].pdata =
  69                         RTL8192CUPHY_REG_2TARRAY;
  70         rtlphy->hwparam_tables[RADIOA_2T].length =
  71                         RTL8192CURADIOA_2TARRAYLENGTH;
  72         rtlphy->hwparam_tables[RADIOA_2T].pdata =
  73                         RTL8192CURADIOA_2TARRAY;
  74         rtlphy->hwparam_tables[RADIOB_2T].length =
  75                         RTL8192CURADIOB_2TARRAYLENGTH;
  76         rtlphy->hwparam_tables[RADIOB_2T].pdata =
  77                         RTL8192CU_RADIOB_2TARRAY;
  78         rtlphy->hwparam_tables[AGCTAB_2T].length =
  79                         RTL8192CUAGCTAB_2TARRAYLENGTH;
  80         rtlphy->hwparam_tables[AGCTAB_2T].pdata =
  81                         RTL8192CUAGCTAB_2TARRAY;
  82         /* 1T */
  83         if (IS_HIGHT_PA(rtlefuse->board_type)) {
  84                 rtlphy->hwparam_tables[PHY_REG_1T].length =
  85                         RTL8192CUPHY_REG_1T_HPArrayLength;
  86                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
  87                         RTL8192CUPHY_REG_1T_HPArray;
  88                 rtlphy->hwparam_tables[RADIOA_1T].length =
  89                         RTL8192CURadioA_1T_HPArrayLength;
  90                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
  91                         RTL8192CURadioA_1T_HPArray;
  92                 rtlphy->hwparam_tables[RADIOB_1T].length =
  93                         RTL8192CURADIOB_1TARRAYLENGTH;
  94                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
  95                         RTL8192CU_RADIOB_1TARRAY;
  96                 rtlphy->hwparam_tables[AGCTAB_1T].length =
  97                         RTL8192CUAGCTAB_1T_HPArrayLength;
  98                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
  99                         Rtl8192CUAGCTAB_1T_HPArray;
 100         } else {
 101                 rtlphy->hwparam_tables[PHY_REG_1T].length =
 102                          RTL8192CUPHY_REG_1TARRAY_LENGTH;
 103                 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
 104                         RTL8192CUPHY_REG_1TARRAY;
 105                 rtlphy->hwparam_tables[RADIOA_1T].length =
 106                         RTL8192CURADIOA_1TARRAYLENGTH;
 107                 rtlphy->hwparam_tables[RADIOA_1T].pdata =
 108                         RTL8192CU_RADIOA_1TARRAY;
 109                 rtlphy->hwparam_tables[RADIOB_1T].length =
 110                         RTL8192CURADIOB_1TARRAYLENGTH;
 111                 rtlphy->hwparam_tables[RADIOB_1T].pdata =
 112                         RTL8192CU_RADIOB_1TARRAY;
 113                 rtlphy->hwparam_tables[AGCTAB_1T].length =
 114                         RTL8192CUAGCTAB_1TARRAYLENGTH;
 115                 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
 116                         RTL8192CUAGCTAB_1TARRAY;
 117         }
 118 }
 119
 120 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
 121                                                  bool autoload_fail,
 122                                                  u8 *hwinfo)
 123 {
 124         struct rtl_priv *rtlpriv = rtl_priv(hw);
 125         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 126         u8 rf_path, index, tempval;
 127         u16 i;
 128
 129         for (rf_path = 0; rf_path < 2; rf_path++) {
 130                 for (i = 0; i < 3; i++) {
 131                         if (!autoload_fail) {
 132                                 rtlefuse->
 133                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 134                                     hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
 135                                 rtlefuse->
 136                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 137                                     hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
 138                                            i];
 139                         } else {
 140                                 rtlefuse->
 141                                     eeprom_chnlarea_txpwr_cck[rf_path][i] =
 142                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 143                                 rtlefuse->
 144                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
 145                                     EEPROM_DEFAULT_TXPOWERLEVEL;
 146                         }
 147                 }
 148         }
 149         for (i = 0; i < 3; i++) {
 150                 if (!autoload_fail)
 151                         tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
 152                 else
 153                         tempval = EEPROM_DEFAULT_HT40_2SDIFF;
 154                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
 155                     (tempval & 0xf);
 156                 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
 157                     ((tempval & 0xf0) >> 4);
 158         }
 159         for (rf_path = 0; rf_path < 2; rf_path++)
 160                 for (i = 0; i < 3; i++)
 161                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 162                                 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
 163                                 rf_path, i,
 164                                 rtlefuse->
 165                                 eeprom_chnlarea_txpwr_cck[rf_path][i]);
 166         for (rf_path = 0; rf_path < 2; rf_path++)
 167                 for (i = 0; i < 3; i++)
 168                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 169                                 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
 170                                 rf_path, i,
 171                                 rtlefuse->
 172                                 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
 173         for (rf_path = 0; rf_path < 2; rf_path++)
 174                 for (i = 0; i < 3; i++)
 175                         RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
 176                                 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
 177                                 rf_path, i,
 178                                 rtlefuse->
 179                                 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
 180         for (rf_path = 0; rf_path < 2; rf_path++) {
 181                 for (i = 0; i < 14; i++) {
 182                         index = rtl92c_get_chnl_group((u8)i);
 183                         rtlefuse->txpwrlevel_cck[rf_path][i] =
 184                             rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
 185                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
 186                             rtlefuse->
 187                             eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
 188                         if ((rtlefuse->
 189                              eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
 190                              rtlefuse->
 191                              eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
 192                             > 0) {
 193                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
 194                                     rtlefuse->
 195                                     eeprom_chnlarea_txpwr_ht40_1s[rf_path]
 196                                     [index] - rtlefuse->
 197                                     eprom_chnl_txpwr_ht40_2sdf[rf_path]
 198                                     [index];
 199                         } else {
 200                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
 201                         }
 202                 }
 203                 for (i = 0; i < 14; i++) {
 204                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 205                                 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
 206                                 rtlefuse->txpwrlevel_cck[rf_path][i],
 207                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
 208                                 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
 209                 }
 210         }
 211         for (i = 0; i < 3; i++) {
 212                 if (!autoload_fail) {
 213                         rtlefuse->eeprom_pwrlimit_ht40[i] =
 214                             hwinfo[EEPROM_TXPWR_GROUP + i];
 215                         rtlefuse->eeprom_pwrlimit_ht20[i] =
 216                             hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
 217                 } else {
 218                         rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
 219                         rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
 220                 }
 221         }
 222         for (rf_path = 0; rf_path < 2; rf_path++) {
 223                 for (i = 0; i < 14; i++) {
 224                         index = rtl92c_get_chnl_group((u8)i);
 225                         if (rf_path == RF90_PATH_A) {
 226                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 227                                     (rtlefuse->eeprom_pwrlimit_ht20[index]
 228                                      & 0xf);
 229                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 230                                     (rtlefuse->eeprom_pwrlimit_ht40[index]
 231                                      & 0xf);
 232                         } else if (rf_path == RF90_PATH_B) {
 233                                 rtlefuse->pwrgroup_ht20[rf_path][i] =
 234                                     ((rtlefuse->eeprom_pwrlimit_ht20[index]
 235                                       & 0xf0) >> 4);
 236                                 rtlefuse->pwrgroup_ht40[rf_path][i] =
 237                                     ((rtlefuse->eeprom_pwrlimit_ht40[index]
 238                                       & 0xf0) >> 4);
 239                         }
 240                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 241                                 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
 242                                 rf_path, i,
 243                                 rtlefuse->pwrgroup_ht20[rf_path][i]);
 244                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 245                                 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
 246                                 rf_path, i,
 247                                 rtlefuse->pwrgroup_ht40[rf_path][i]);
 248                 }
 249         }
 250         for (i = 0; i < 14; i++) {
 251                 index = rtl92c_get_chnl_group((u8)i);
 252                 if (!autoload_fail)
 253                         tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
 254                 else
 255                         tempval = EEPROM_DEFAULT_HT20_DIFF;
 256                 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
 257                 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
 258                     ((tempval >> 4) & 0xF);
 259                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
 260                         rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
 261                 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
 262                         rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
 263                 index = rtl92c_get_chnl_group((u8)i);
 264                 if (!autoload_fail)
 265                         tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
 266                 else
 267                         tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
 268                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
 269                 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
 270                     ((tempval >> 4) & 0xF);
 271         }
 272         rtlefuse->legacy_ht_txpowerdiff =
 273             rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
 274         for (i = 0; i < 14; i++)
 275                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 276                         "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
 277                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
 278         for (i = 0; i < 14; i++)
 279                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 280                         "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
 281                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
 282         for (i = 0; i < 14; i++)
 283                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 284                         "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
 285                         i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
 286         for (i = 0; i < 14; i++)
 287                 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 288                         "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
 289                         i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
 290         if (!autoload_fail)
 291                 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
 292         else
 293                 rtlefuse->eeprom_regulatory = 0;
 294         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 295                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
 296         if (!autoload_fail) {
 297                 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
 298                 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
 299         } else {
 300                 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
 301                 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
 302         }
 303         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 304                 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
 305                 rtlefuse->eeprom_tssi[RF90_PATH_A],
 306                 rtlefuse->eeprom_tssi[RF90_PATH_B]);
 307         if (!autoload_fail)
 308                 tempval = hwinfo[EEPROM_THERMAL_METER];
 309         else
 310                 tempval = EEPROM_DEFAULT_THERMALMETER;
 311         rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
 312         if (rtlefuse->eeprom_thermalmeter < 0x06 ||
 313             rtlefuse->eeprom_thermalmeter > 0x1c)
 314                 rtlefuse->eeprom_thermalmeter = 0x12;
 315         if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
 316                 rtlefuse->apk_thermalmeterignore = true;
 317         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
 318         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
 319                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
 320 }
 321
 322 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
 323 {
 324         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 325         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 326         u8 boardType;
 327
 328         if (IS_NORMAL_CHIP(rtlhal->version)) {
 329                 boardType = ((contents[EEPROM_RF_OPT1]) &
 330                             BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
 331         } else {
 332                 boardType = contents[EEPROM_RF_OPT4];
 333                 boardType &= BOARD_TYPE_TEST_MASK;
 334         }
 335         rtlefuse->board_type = boardType;
 336         if (IS_HIGHT_PA(rtlefuse->board_type))
 337                 rtlefuse->external_pa = 1;
 338         pr_info("Board Type %x\n", rtlefuse->board_type);
 339 }
 340
 341 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
 342 {
 343         struct rtl_priv *rtlpriv = rtl_priv(hw);
 344         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 345         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 346         int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
 347                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
 348                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
 349                         0};
 350         u8 *hwinfo;
 351
 352         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
 353         if (!hwinfo)
 354                 return;
 355
 356         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
 357                 goto exit;
 358
 359         _rtl92cu_read_txpower_info_from_hwpg(hw,
 360                                            rtlefuse->autoload_failflag, hwinfo);
 361         _rtl92cu_read_board_type(hw, hwinfo);
 362
 363         rtlefuse->txpwr_fromeprom = true;
 364         if (rtlhal->oem_id == RT_CID_DEFAULT) {
 365                 switch (rtlefuse->eeprom_oemid) {
 366                 case EEPROM_CID_DEFAULT:
 367                         if (rtlefuse->eeprom_did == 0x8176) {
 368                                 if ((rtlefuse->eeprom_svid == 0x103C &&
 369                                      rtlefuse->eeprom_smid == 0x1629))
 370                                         rtlhal->oem_id = RT_CID_819X_HP;
 371                                 else
 372                                         rtlhal->oem_id = RT_CID_DEFAULT;
 373                         } else {
 374                                 rtlhal->oem_id = RT_CID_DEFAULT;
 375                         }
 376                         break;
 377                 case EEPROM_CID_TOSHIBA:
 378                         rtlhal->oem_id = RT_CID_TOSHIBA;
 379                         break;
 380                 case EEPROM_CID_QMI:
 381                         rtlhal->oem_id = RT_CID_819X_QMI;
 382                         break;
 383                 case EEPROM_CID_WHQL:
 384                 default:
 385                         rtlhal->oem_id = RT_CID_DEFAULT;
 386                         break;
 387                 }
 388         }
 389 exit:
 390         kfree(hwinfo);
 391 }
 392
 393 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
 394 {
 395         struct rtl_priv *rtlpriv = rtl_priv(hw);
 396         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 397
 398         switch (rtlhal->oem_id) {
 399         case RT_CID_819X_HP:
 400                 rtlpriv->ledctl.led_opendrain = true;
 401                 break;
 402         case RT_CID_819X_LENOVO:
 403         case RT_CID_DEFAULT:
 404         case RT_CID_TOSHIBA:
 405         case RT_CID_CCX:
 406         case RT_CID_819X_ACER:
 407         case RT_CID_WHQL:
 408         default:
 409                 break;
 410         }
 411         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
 412                  rtlhal->oem_id);
 413 }
 414
 415 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
 416 {
 417
 418         struct rtl_priv *rtlpriv = rtl_priv(hw);
 419         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 420         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 421         u8 tmp_u1b;
 422
 423         if (!IS_NORMAL_CHIP(rtlhal->version))
 424                 return;
 425         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
 426         rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
 427                                EEPROM_93C46 : EEPROM_BOOT_EFUSE;
 428         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
 429                  tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
 430         rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
 431         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
 432                  tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
 433         _rtl92cu_read_adapter_info(hw);
 434         _rtl92cu_hal_customized_behavior(hw);
 435         return;
 436 }
 437
 438 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
 439 {
 440         struct rtl_priv *rtlpriv = rtl_priv(hw);
 441         int             status = 0;
 442         u16             value16;
 443         u8              value8;
 444         /*  polling autoload done. */
 445         u32     pollingCount = 0;
 446
 447         do {
 448                 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
 449                         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 450                                  "Autoload Done!\n");
 451                         break;
 452                 }
 453                 if (pollingCount++ > 100) {
 454                         pr_err("Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
 455                         return -ENODEV;
 456                 }
 457         } while (true);
 458         /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
 459         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
 460         /* Power on when re-enter from IPS/Radio off/card disable */
 461         /* enable SPS into PWM mode */
 462         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
 463         udelay(100);
 464         value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
 465         if (0 == (value8 & LDV12_EN)) {
 466                 value8 |= LDV12_EN;
 467                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
 468                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
 469                          " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
 470                          value8);
 471                 udelay(100);
 472                 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
 473                 value8 &= ~ISO_MD2PP;
 474                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
 475         }
 476         /*  auto enable WLAN */
 477         pollingCount = 0;
 478         value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
 479         value16 |= APFM_ONMAC;
 480         rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
 481         do {
 482                 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
 483                         pr_info("MAC auto ON okay!\n");
 484                         break;
 485                 }
 486                 if (pollingCount++ > 1000) {
 487                         pr_err("Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
 488                         return -ENODEV;
 489                 }
 490         } while (true);
 491         /* Enable Radio ,GPIO ,and LED function */
 492         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
 493         /* release RF digital isolation */
 494         value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
 495         value16 &= ~ISO_DIOR;
 496         rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
 497         /* Reconsider when to do this operation after asking HWSD. */
 498         pollingCount = 0;
 499         rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
 500                                                 REG_APSD_CTRL) & ~BIT(6)));
 501         do {
 502                 pollingCount++;
 503         } while ((pollingCount < 200) &&
 504                  (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
 505         /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 506         value16 = rtl_read_word(rtlpriv,  REG_CR);
 507         value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
 508                     PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
 509         rtl_write_word(rtlpriv, REG_CR, value16);
 510         return status;
 511 }
 512
 513 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
 514                                               bool wmm_enable,
 515                                               u8 out_ep_num,
 516                                               u8 queue_sel)
 517 {
 518         struct rtl_priv *rtlpriv = rtl_priv(hw);
 519         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 520         bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
 521         u32 outEPNum = (u32)out_ep_num;
 522         u32 numHQ = 0;
 523         u32 numLQ = 0;
 524         u32 numNQ = 0;
 525         u32 numPubQ;
 526         u32 value32;
 527         u8 value8;
 528         u32 txQPageNum, txQPageUnit, txQRemainPage;
 529
 530         if (!wmm_enable) {
 531                 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
 532                           CHIP_A_PAGE_NUM_PUBQ;
 533                 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
 534
 535                 txQPageUnit = txQPageNum/outEPNum;
 536                 txQRemainPage = txQPageNum % outEPNum;
 537                 if (queue_sel & TX_SELE_HQ)
 538                         numHQ = txQPageUnit;
 539                 if (queue_sel & TX_SELE_LQ)
 540                         numLQ = txQPageUnit;
 541                 /* HIGH priority queue always present in the configuration of
 542                  * 2 out-ep. Remainder pages have assigned to High queue */
 543                 if ((outEPNum > 1) && (txQRemainPage))
 544                         numHQ += txQRemainPage;
 545                 /* NOTE: This step done before writting REG_RQPN. */
 546                 if (isChipN) {
 547                         if (queue_sel & TX_SELE_NQ)
 548                                 numNQ = txQPageUnit;
 549                         value8 = (u8)_NPQ(numNQ);
 550                         rtl_write_byte(rtlpriv,  REG_RQPN_NPQ, value8);
 551                 }
 552         } else {
 553                 /* for WMM ,number of out-ep must more than or equal to 2! */
 554                 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
 555                           WMM_CHIP_A_PAGE_NUM_PUBQ;
 556                 if (queue_sel & TX_SELE_HQ) {
 557                         numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
 558                                 WMM_CHIP_A_PAGE_NUM_HPQ;
 559                 }
 560                 if (queue_sel & TX_SELE_LQ) {
 561                         numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
 562                                 WMM_CHIP_A_PAGE_NUM_LPQ;
 563                 }
 564                 /* NOTE: This step done before writting REG_RQPN. */
 565                 if (isChipN) {
 566                         if (queue_sel & TX_SELE_NQ)
 567                                 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
 568                         value8 = (u8)_NPQ(numNQ);
 569                         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
 570                 }
 571         }
 572         /* TX DMA */
 573         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 574         rtl_write_dword(rtlpriv, REG_RQPN, value32);
 575 }
 576
 577 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
 578 {
 579         struct rtl_priv *rtlpriv = rtl_priv(hw);
 580         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 581         u8      txpktbuf_bndy;
 582         u8      value8;
 583
 584         if (!wmm_enable)
 585                 txpktbuf_bndy = TX_PAGE_BOUNDARY;
 586         else /* for WMM */
 587                 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
 588                                                 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 589                                                 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 590         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 591         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 592         rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
 593         rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
 594         rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
 595         rtl_write_word(rtlpriv,  (REG_TRXFF_BNDY + 2), 0x27FF);
 596         value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
 597         rtl_write_byte(rtlpriv, REG_PBP, value8);
 598 }
 599
 600 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
 601                                             u16 bkQ, u16 viQ, u16 voQ,
 602                                             u16 mgtQ, u16 hiQ)
 603 {
 604         struct rtl_priv *rtlpriv = rtl_priv(hw);
 605         u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
 606
 607         value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
 608                    _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
 609                    _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
 610         rtl_write_word(rtlpriv,  REG_TRXDMA_CTRL, value16);
 611 }
 612
 613 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
 614                                                     bool wmm_enable,
 615                                                     u8 queue_sel)
 616 {
 617         u16 uninitialized_var(value);
 618
 619         switch (queue_sel) {
 620         case TX_SELE_HQ:
 621                 value = QUEUE_HIGH;
 622                 break;
 623         case TX_SELE_LQ:
 624                 value = QUEUE_LOW;
 625                 break;
 626         case TX_SELE_NQ:
 627                 value = QUEUE_NORMAL;
 628                 break;
 629         default:
 630                 WARN_ON(1); /* Shall not reach here! */
 631                 break;
 632         }
 633         _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
 634                                         value, value);
 635         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 636 }
 637
 638 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
 639                                                                 bool wmm_enable,
 640                                                                 u8 queue_sel)
 641 {
 642         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 643         u16 uninitialized_var(valueHi);
 644         u16 uninitialized_var(valueLow);
 645
 646         switch (queue_sel) {
 647         case (TX_SELE_HQ | TX_SELE_LQ):
 648                 valueHi = QUEUE_HIGH;
 649                 valueLow = QUEUE_LOW;
 650                 break;
 651         case (TX_SELE_NQ | TX_SELE_LQ):
 652                 valueHi = QUEUE_NORMAL;
 653                 valueLow = QUEUE_LOW;
 654                 break;
 655         case (TX_SELE_HQ | TX_SELE_NQ):
 656                 valueHi = QUEUE_HIGH;
 657                 valueLow = QUEUE_NORMAL;
 658                 break;
 659         default:
 660                 WARN_ON(1);
 661                 break;
 662         }
 663         if (!wmm_enable) {
 664                 beQ = valueLow;
 665                 bkQ = valueLow;
 666                 viQ = valueHi;
 667                 voQ = valueHi;
 668                 mgtQ = valueHi;
 669                 hiQ = valueHi;
 670         } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
 671                 beQ = valueHi;
 672                 bkQ = valueLow;
 673                 viQ = valueLow;
 674                 voQ = valueHi;
 675                 mgtQ = valueHi;
 676                 hiQ = valueHi;
 677         }
 678         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 679         pr_info("Tx queue select: 0x%02x\n", queue_sel);
 680 }
 681
 682 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
 683                                                       bool wmm_enable,
 684                                                       u8 queue_sel)
 685 {
 686         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 687
 688         if (!wmm_enable) { /* typical setting */
 689                 beQ     = QUEUE_LOW;
 690                 bkQ     = QUEUE_LOW;
 691                 viQ     = QUEUE_NORMAL;
 692                 voQ     = QUEUE_HIGH;
 693                 mgtQ    = QUEUE_HIGH;
 694                 hiQ     = QUEUE_HIGH;
 695         } else { /* for WMM */
 696                 beQ     = QUEUE_LOW;
 697                 bkQ     = QUEUE_NORMAL;
 698                 viQ     = QUEUE_NORMAL;
 699                 voQ     = QUEUE_HIGH;
 700                 mgtQ    = QUEUE_HIGH;
 701                 hiQ     = QUEUE_HIGH;
 702         }
 703         _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 704         pr_info("Tx queue select :0x%02x..\n", queue_sel);
 705 }
 706
 707 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
 708                                                bool wmm_enable,
 709                                                u8 out_ep_num,
 710                                                u8 queue_sel)
 711 {
 712         switch (out_ep_num) {
 713         case 1:
 714                 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
 715                                                         queue_sel);
 716                 break;
 717         case 2:
 718                 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
 719                                                         queue_sel);
 720                 break;
 721         case 3:
 722                 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
 723                                                           queue_sel);
 724                 break;
 725         default:
 726                 WARN_ON(1); /* Shall not reach here! */
 727                 break;
 728         }
 729 }
 730
 731 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
 732                                                bool wmm_enable,
 733                                                u8 out_ep_num,
 734                                                u8 queue_sel)
 735 {
 736         u8 hq_sele = 0;
 737         struct rtl_priv *rtlpriv = rtl_priv(hw);
 738
 739         switch (out_ep_num) {
 740         case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
 741                 if (!wmm_enable) /* typical setting */
 742                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
 743                                    HQSEL_HIQ;
 744                 else    /* for WMM */
 745                         hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
 746                                   HQSEL_HIQ;
 747                 break;
 748         case 1:
 749                 if (TX_SELE_LQ == queue_sel) {
 750                         /* map all endpoint to Low queue */
 751                         hq_sele = 0;
 752                 } else if (TX_SELE_HQ == queue_sel) {
 753                         /* map all endpoint to High queue */
 754                         hq_sele =  HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
 755                                    HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
 756                 }
 757                 break;
 758         default:
 759                 WARN_ON(1); /* Shall not reach here! */
 760                 break;
 761         }
 762         rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
 763         pr_info("Tx queue select :0x%02x..\n", hq_sele);
 764 }
 765
 766 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
 767                                                 bool wmm_enable,
 768                                                 u8 out_ep_num,
 769                                                 u8 queue_sel)
 770 {
 771         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 772         if (IS_NORMAL_CHIP(rtlhal->version))
 773                 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
 774                                                    queue_sel);
 775         else
 776                 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
 777                                                    queue_sel);
 778 }
 779
 780 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
 781 {
 782         u16 value16;
 783         u32 value32;
 784         struct rtl_priv *rtlpriv = rtl_priv(hw);
 785
 786         value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
 787                    RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
 788                    RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
 789         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));
 790         /* Accept all multicast address */
 791         rtl_write_dword(rtlpriv,  REG_MAR, 0xFFFFFFFF);
 792         rtl_write_dword(rtlpriv,  REG_MAR + 4, 0xFFFFFFFF);
 793         /* Accept all management frames */
 794         value16 = 0xFFFF;
 795         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
 796                                       (u8 *)(&value16));
 797         /* Reject all control frame - default value is 0 */
 798         value16 = 0x0;
 799         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
 800                                       (u8 *)(&value16));
 801         /* Accept all data frames */
 802         value16 = 0xFFFF;
 803         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,
 804                                       (u8 *)(&value16));
 805 }
 806
 807 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)
 808 {
 809         struct rtl_priv *rtlpriv = rtl_priv(hw);
 810         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 811
 812         rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
 813
 814         /* TODO: Remove these magic number */
 815         rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
 816         rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
 817         rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
 818         /* Change beacon AIFS to the largest number
 819          * beacause test chip does not contension before sending beacon.
 820          */
 821         if (IS_NORMAL_CHIP(rtlhal->version))
 822                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
 823         else
 824                 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
 825 }
 826
 827 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
 828 {
 829         struct rtl_priv *rtlpriv = rtl_priv(hw);
 830         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 831         struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
 832         struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
 833         int err = 0;
 834         u32     boundary = 0;
 835         u8 wmm_enable = false; /* TODO */
 836         u8 out_ep_nums = rtlusb->out_ep_nums;
 837         u8 queue_sel = rtlusb->out_queue_sel;
 838         err = _rtl92cu_init_power_on(hw);
 839
 840         if (err) {
 841                 pr_err("Failed to init power on!\n");
 842                 return err;
 843         }
 844         if (!wmm_enable) {
 845                 boundary = TX_PAGE_BOUNDARY;
 846         } else { /* for WMM */
 847                 boundary = (IS_NORMAL_CHIP(rtlhal->version))
 848                                         ? WMM_CHIP_B_TX_PAGE_BOUNDARY
 849                                         : WMM_CHIP_A_TX_PAGE_BOUNDARY;
 850         }
 851         if (false == rtl92c_init_llt_table(hw, boundary)) {
 852                 pr_err("Failed to init LLT Table!\n");
 853                 return -EINVAL;
 854         }
 855         _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
 856                                           queue_sel);
 857         _rtl92c_init_trx_buffer(hw, wmm_enable);
 858         _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
 859                                      queue_sel);
 860         /* Get Rx PHY status in order to report RSSI and others. */
 861         rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
 862         rtl92c_init_interrupt(hw);
 863         rtl92c_init_network_type(hw);
 864         _rtl92cu_init_wmac_setting(hw);
 865         rtl92c_init_adaptive_ctrl(hw);
 866         rtl92c_init_edca(hw);
 867         rtl92c_init_rate_fallback(hw);
 868         rtl92c_init_retry_function(hw);
 869         rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
 870         rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
 871         _rtl92cu_init_beacon_parameters(hw);
 872         rtl92c_init_ampdu_aggregation(hw);
 873         rtl92c_init_beacon_max_error(hw);
 874         return err;
 875 }
 876
 877 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
 878 {
 879         struct rtl_priv *rtlpriv = rtl_priv(hw);
 880         u8 sec_reg_value = 0x0;
 881         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
 882
 883         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 884                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
 885                  rtlpriv->sec.pairwise_enc_algorithm,
 886                  rtlpriv->sec.group_enc_algorithm);
 887         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
 888                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
 889                          "not open sw encryption\n");
 890                 return;
 891         }
 892         sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
 893         if (rtlpriv->sec.use_defaultkey) {
 894                 sec_reg_value |= SCR_TxUseDK;
 895                 sec_reg_value |= SCR_RxUseDK;
 896         }
 897         if (IS_NORMAL_CHIP(rtlhal->version))
 898                 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
 899         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
 900         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
 901                  sec_reg_value);
 902         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
 903 }
 904
 905 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
 906 {
 907         struct rtl_priv *rtlpriv = rtl_priv(hw);
 908         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
 909
 910         /* To Fix MAC loopback mode fail. */
 911         rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
 912         rtl_write_byte(rtlpriv, 0x15, 0xe9);
 913         /* HW SEQ CTRL */
 914         /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 915         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 916         /* fixed USB interface interference issue */
 917         rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
 918         rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
 919         rtl_write_byte(rtlpriv, 0xfe42, 0x80);
 920         rtlusb->reg_bcn_ctrl_val = 0x18;
 921         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
 922 }
 923
 924 static void _InitPABias(struct ieee80211_hw *hw)
 925 {
 926         struct rtl_priv *rtlpriv = rtl_priv(hw);
 927         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 928         u8 pa_setting;
 929
 930         /* FIXED PA current issue */
 931         pa_setting = efuse_read_1byte(hw, 0x1FA);
 932         if (!(pa_setting & BIT(0))) {
 933                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
 934                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
 935                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
 936                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
 937         }
 938         if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
 939             IS_92C_SERIAL(rtlhal->version)) {
 940                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
 941                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
 942                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
 943                 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
 944         }
 945         if (!(pa_setting & BIT(4))) {
 946                 pa_setting = rtl_read_byte(rtlpriv, 0x16);
 947                 pa_setting &= 0x0F;
 948                 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
 949         }
 950 }
 951
 952 int rtl92cu_hw_init(struct ieee80211_hw *hw)
 953 {
 954         struct rtl_priv *rtlpriv = rtl_priv(hw);
 955         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 956         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 957         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 958         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 959         int err = 0;
 960         unsigned long flags;
 961
 962         /* As this function can take a very long time (up to 350 ms)
 963          * and can be called with irqs disabled, reenable the irqs
 964          * to let the other devices continue being serviced.
 965          *
 966          * It is safe doing so since our own interrupts will only be enabled
 967          * in a subsequent step.
 968          */
 969         local_save_flags(flags);
 970         local_irq_enable();
 971
 972         rtlhal->fw_ready = false;
 973         rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
 974         err = _rtl92cu_init_mac(hw);
 975         if (err) {
 976                 pr_err("init mac failed!\n");
 977                 goto exit;
 978         }
 979         err = rtl92c_download_fw(hw);
 980         if (err) {
 981                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 982                          "Failed to download FW. Init HW without FW now..\n");
 983                 err = 1;
 984                 goto exit;
 985         }
 986
 987         rtlhal->fw_ready = true;
 988         rtlhal->last_hmeboxnum = 0; /* h2c */
 989         _rtl92cu_phy_param_tab_init(hw);
 990         rtl92cu_phy_mac_config(hw);
 991         rtl92cu_phy_bb_config(hw);
 992         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
 993         rtl92c_phy_rf_config(hw);
 994         if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
 995             !IS_92C_SERIAL(rtlhal->version)) {
 996                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
 997                 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
 998         }
 999         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1000                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1001         rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1002                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1003         rtl92cu_bb_block_on(hw);
1004         rtl_cam_reset_all_entry(hw);
1005         rtl92cu_enable_hw_security_config(hw);
1006         ppsc->rfpwr_state = ERFON;
1007         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1008         if (ppsc->rfpwr_state == ERFON) {
1009                 rtl92c_phy_set_rfpath_switch(hw, 1);
1010                 if (rtlphy->iqk_initialized) {
1011                         rtl92c_phy_iq_calibrate(hw, true);
1012                 } else {
1013                         rtl92c_phy_iq_calibrate(hw, false);
1014                         rtlphy->iqk_initialized = true;
1015                 }
1016                 rtl92c_dm_check_txpower_tracking(hw);
1017                 rtl92c_phy_lc_calibrate(hw);
1018         }
1019         _rtl92cu_hw_configure(hw);
1020         _InitPABias(hw);
1021         rtl92c_dm_init(hw);
1022 exit:
1023         local_irq_disable();
1024         local_irq_restore(flags);
1025         return err;
1026 }
1027
1028 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1029 {
1030         struct rtl_priv *rtlpriv = rtl_priv(hw);
1031 /**************************************
1032 a.      TXPAUSE 0x522[7:0] = 0xFF       Pause MAC TX queue
1033 b.      RF path 0 offset 0x00 = 0x00    disable RF
1034 c.      APSD_CTRL 0x600[7:0] = 0x40
1035 d.      SYS_FUNC_EN 0x02[7:0] = 0x16    reset BB state machine
1036 e.      SYS_FUNC_EN 0x02[7:0] = 0x14    reset BB state machine
1037 ***************************************/
1038         u8 eRFPath = 0, value8 = 0;
1039         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1040         rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1041
1042         value8 |= APSDOFF;
1043         rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1044         value8 = 0;
1045         value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1046         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1047         value8 &= (~FEN_BB_GLB_RSTn);
1048         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1049 }
1050
1051 static void  _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1052 {
1053         struct rtl_priv *rtlpriv = rtl_priv(hw);
1054         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1055
1056         if (rtlhal->fw_version <=  0x20) {
1057                 /*****************************
1058                 f. MCUFWDL 0x80[7:0]=0          reset MCU ready status
1059                 g. SYS_FUNC_EN 0x02[10]= 0      reset MCU reg, (8051 reset)
1060                 h. SYS_FUNC_EN 0x02[15-12]= 5   reset MAC reg, DCORE
1061                 i. SYS_FUNC_EN 0x02[10]= 1      enable MCU reg, (8051 enable)
1062                 ******************************/
1063                 u16 valu16 = 0;
1064
1065                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1066                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1067                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1068                                (~FEN_CPUEN))); /* reset MCU ,8051 */
1069                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1070                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1071                               (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1072                 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1073                 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1074                                FEN_CPUEN)); /* enable MCU ,8051 */
1075         } else {
1076                 u8 retry_cnts = 0;
1077
1078                 /* IF fw in RAM code, do reset */
1079                 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1080                         /* reset MCU ready status */
1081                         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1082                         /* 8051 reset by self */
1083                         rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1084                         while ((retry_cnts++ < 100) &&
1085                                (FEN_CPUEN & rtl_read_word(rtlpriv,
1086                                REG_SYS_FUNC_EN))) {
1087                                 udelay(50);
1088                         }
1089                         if (retry_cnts >= 100) {
1090                                 pr_err("8051 reset failed!.........................\n");
1091                                 /* if 8051 reset fail, reset MAC. */
1092                                 rtl_write_byte(rtlpriv,
1093                                                REG_SYS_FUNC_EN + 1,
1094                                                0x50);
1095                                 udelay(100);
1096                         }
1097                 }
1098                 /* Reset MAC and Enable 8051 */
1099                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1100                 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1101         }
1102         if (bWithoutHWSM) {
1103                 /*****************************
1104                   Without HW auto state machine
1105                 g.SYS_CLKR 0x08[15:0] = 0x30A3          disable MAC clock
1106                 h.AFE_PLL_CTRL 0x28[7:0] = 0x80         disable AFE PLL
1107                 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F     gated AFE DIG_CLOCK
1108                 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9         isolated digital to PON
1109                 ******************************/
1110                 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1111                 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1112                 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1113                 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1114         }
1115 }
1116
1117 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1118 {
1119         struct rtl_priv *rtlpriv = rtl_priv(hw);
1120 /*****************************
1121 k. SYS_FUNC_EN 0x03[7:0] = 0x44         disable ELDR runction
1122 l. SYS_CLKR 0x08[15:0] = 0x3083         disable ELDR clock
1123 m. SYS_ISO_CTRL 0x01[7:0] = 0x83        isolated ELDR to PON
1124 ******************************/
1125         rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1126         rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1127 }
1128
1129 static void _DisableGPIO(struct ieee80211_hw *hw)
1130 {
1131         struct rtl_priv *rtlpriv = rtl_priv(hw);
1132 /***************************************
1133 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1134 k. Value = GPIO_PIN_CTRL[7:0]
1135 l.  GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1136 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1137 n. LEDCFG 0x4C[15:0] = 0x8080
1138 ***************************************/
1139         u8      value8;
1140         u16     value16;
1141         u32     value32;
1142
1143         /* 1. Disable GPIO[7:0] */
1144         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1145         value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1146         value8 = (u8)(value32&0x000000FF);
1147         value32 |= ((value8<<8) | 0x00FF0000);
1148         rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1149         /* 2. Disable GPIO[10:8] */
1150         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1151         value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1152         value8 = (u8)(value16&0x000F);
1153         value16 |= ((value8<<4) | 0x0780);
1154         rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1155         /* 3. Disable LED0 & 1 */
1156         rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1157 }
1158
1159 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1160 {
1161         struct rtl_priv *rtlpriv = rtl_priv(hw);
1162         u16 value16 = 0;
1163         u8 value8 = 0;
1164
1165         if (bWithoutHWSM) {
1166                 /*****************************
1167                 n. LDOA15_CTRL 0x20[7:0] = 0x04  disable A15 power
1168                 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1169                 r. When driver call disable, the ASIC will turn off remaining
1170                    clock automatically
1171                 ******************************/
1172                 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1173                 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1174                 value8 &= (~LDV12_EN);
1175                 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1176         }
1177
1178 /*****************************
1179 h. SPS0_CTRL 0x11[7:0] = 0x23           enter PFM mode
1180 i. APS_FSMCO 0x04[15:0] = 0x4802        set USB suspend
1181 ******************************/
1182         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1183         value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1184         rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1185         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1186 }
1187
1188 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1189 {
1190         /* ==== RF Off Sequence ==== */
1191         _DisableRFAFEAndResetBB(hw);
1192         /* ==== Reset digital sequence   ====== */
1193         _ResetDigitalProcedure1(hw, false);
1194         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1195         _DisableGPIO(hw);
1196         /* ==== Disable analog sequence === */
1197         _DisableAnalog(hw, false);
1198 }
1199
1200 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1201 {
1202         /*==== RF Off Sequence ==== */
1203         _DisableRFAFEAndResetBB(hw);
1204         /*  ==== Reset digital sequence   ====== */
1205         _ResetDigitalProcedure1(hw, true);
1206         /*  ==== Pull GPIO PIN to balance level and LED control ====== */
1207         _DisableGPIO(hw);
1208         /*  ==== Reset digital sequence   ====== */
1209         _ResetDigitalProcedure2(hw);
1210         /*  ==== Disable analog sequence === */
1211         _DisableAnalog(hw, true);
1212 }
1213
1214 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1215                                       u8 set_bits, u8 clear_bits)
1216 {
1217         struct rtl_priv *rtlpriv = rtl_priv(hw);
1218         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1219
1220         rtlusb->reg_bcn_ctrl_val |= set_bits;
1221         rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1222         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1223 }
1224
1225 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1226 {
1227         struct rtl_priv *rtlpriv = rtl_priv(hw);
1228         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1229         u8 tmp1byte = 0;
1230         if (IS_NORMAL_CHIP(rtlhal->version)) {
1231                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1232                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1233                                tmp1byte & (~BIT(6)));
1234                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1235                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1236                 tmp1byte &= ~(BIT(0));
1237                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1238         } else {
1239                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1240                                rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1241         }
1242 }
1243
1244 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1245 {
1246         struct rtl_priv *rtlpriv = rtl_priv(hw);
1247         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1248         u8 tmp1byte = 0;
1249
1250         if (IS_NORMAL_CHIP(rtlhal->version)) {
1251                 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1252                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1253                                tmp1byte | BIT(6));
1254                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1255                 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1256                 tmp1byte |= BIT(0);
1257                 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1258         } else {
1259                 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1260                                rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1261         }
1262 }
1263
1264 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1265 {
1266         struct rtl_priv *rtlpriv = rtl_priv(hw);
1267         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1268
1269         if (IS_NORMAL_CHIP(rtlhal->version))
1270                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1271         else
1272                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1273 }
1274
1275 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1276 {
1277         struct rtl_priv *rtlpriv = rtl_priv(hw);
1278         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1279
1280         if (IS_NORMAL_CHIP(rtlhal->version))
1281                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1282         else
1283                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1284 }
1285
1286 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1287                                      enum nl80211_iftype type)
1288 {
1289         struct rtl_priv *rtlpriv = rtl_priv(hw);
1290         u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1291         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1292
1293         bt_msr &= 0xfc;
1294         if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1295             NL80211_IFTYPE_STATION) {
1296                 _rtl92cu_stop_tx_beacon(hw);
1297                 _rtl92cu_enable_bcn_sub_func(hw);
1298         } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1299                 _rtl92cu_resume_tx_beacon(hw);
1300                 _rtl92cu_disable_bcn_sub_func(hw);
1301         } else {
1302                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1303                          "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1304                          type);
1305         }
1306         switch (type) {
1307         case NL80211_IFTYPE_UNSPECIFIED:
1308                 bt_msr |= MSR_NOLINK;
1309                 ledaction = LED_CTL_LINK;
1310                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1311                          "Set Network type to NO LINK!\n");
1312                 break;
1313         case NL80211_IFTYPE_ADHOC:
1314                 bt_msr |= MSR_ADHOC;
1315                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1316                          "Set Network type to Ad Hoc!\n");
1317                 break;
1318         case NL80211_IFTYPE_STATION:
1319                 bt_msr |= MSR_INFRA;
1320                 ledaction = LED_CTL_LINK;
1321                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1322                          "Set Network type to STA!\n");
1323                 break;
1324         case NL80211_IFTYPE_AP:
1325                 bt_msr |= MSR_AP;
1326                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1327                          "Set Network type to AP!\n");
1328                 break;
1329         default:
1330                 pr_err("Network type %d not supported!\n", type);
1331                 goto error_out;
1332         }
1333         rtl_write_byte(rtlpriv, MSR, bt_msr);
1334         rtlpriv->cfg->ops->led_control(hw, ledaction);
1335         if ((bt_msr & MSR_MASK) == MSR_AP)
1336                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1337         else
1338                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1339         return 0;
1340 error_out:
1341         return 1;
1342 }
1343
1344 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1345 {
1346         struct rtl_priv *rtlpriv = rtl_priv(hw);
1347         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1348         struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1349         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1350         enum nl80211_iftype opmode;
1351
1352         mac->link_state = MAC80211_NOLINK;
1353         opmode = NL80211_IFTYPE_UNSPECIFIED;
1354         _rtl92cu_set_media_status(hw, opmode);
1355         rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1356         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1357         if (rtlusb->disableHWSM)
1358                 _CardDisableHWSM(hw);
1359         else
1360                 _CardDisableWithoutHWSM(hw);
1361
1362         /* after power off we should do iqk again */
1363         rtlpriv->phy.iqk_initialized = false;
1364 }
1365
1366 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1367 {
1368         struct rtl_priv *rtlpriv = rtl_priv(hw);
1369         struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1370         u32 reg_rcr;
1371
1372         if (rtlpriv->psc.rfpwr_state != ERFON)
1373                 return;
1374
1375         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(&reg_rcr));
1376
1377         if (check_bssid) {
1378                 u8 tmp;
1379                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1380                         reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1381                         tmp = BIT(4);
1382                 } else {
1383                         reg_rcr |= RCR_CBSSID;
1384                         tmp = BIT(4) | BIT(5);
1385                 }
1386                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1387                                               (u8 *) (&reg_rcr));
1388                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1389         } else {
1390                 u8 tmp;
1391                 if (IS_NORMAL_CHIP(rtlhal->version)) {
1392                         reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1393                         tmp = BIT(4);
1394                 } else {
1395                         reg_rcr &= ~RCR_CBSSID;
1396                         tmp = BIT(4) | BIT(5);
1397                 }
1398                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1399                 rtlpriv->cfg->ops->set_hw_reg(hw,
1400                                               HW_VAR_RCR, (u8 *) (&reg_rcr));
1401                 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1402         }
1403 }
1404
1405 /*========================================================================== */
1406
1407 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1408 {
1409         struct rtl_priv *rtlpriv = rtl_priv(hw);
1410
1411         if (_rtl92cu_set_media_status(hw, type))
1412                 return -EOPNOTSUPP;
1413
1414         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1415                 if (type != NL80211_IFTYPE_AP)
1416                         rtl92cu_set_check_bssid(hw, true);
1417         } else {
1418                 rtl92cu_set_check_bssid(hw, false);
1419         }
1420
1421         return 0;
1422 }
1423
1424 static void _beacon_function_enable(struct ieee80211_hw *hw)
1425 {
1426         struct rtl_priv *rtlpriv = rtl_priv(hw);
1427
1428         _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1429         rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1430 }
1431
1432 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1433 {
1434
1435         struct rtl_priv *rtlpriv = rtl_priv(hw);
1436         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1437         u16 bcn_interval, atim_window;
1438         u32 value32;
1439
1440         bcn_interval = mac->beacon_interval;
1441         atim_window = 2;        /*FIX MERGE */
1442         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1443         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1444         _rtl92cu_init_beacon_parameters(hw);
1445         rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1446         /*
1447          * Force beacon frame transmission even after receiving beacon frame
1448          * from other ad hoc STA
1449          *
1450          *
1451          * Reset TSF Timer to zero, added by Roger. 2008.06.24
1452          */
1453         value32 = rtl_read_dword(rtlpriv, REG_TCR);
1454         value32 &= ~TSFRST;
1455         rtl_write_dword(rtlpriv, REG_TCR, value32);
1456         value32 |= TSFRST;
1457         rtl_write_dword(rtlpriv, REG_TCR, value32);
1458         RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1459                  "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1460                  value32);
1461         /* TODO: Modify later (Find the right parameters)
1462          * NOTE: Fix test chip's bug (about contention windows's randomness) */
1463         if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1464             (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1465             (mac->opmode == NL80211_IFTYPE_AP)) {
1466                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1467                 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1468         }
1469         _beacon_function_enable(hw);
1470 }
1471
1472 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1473 {
1474         struct rtl_priv *rtlpriv = rtl_priv(hw);
1475         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1476         u16 bcn_interval = mac->beacon_interval;
1477
1478         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1479                  bcn_interval);
1480         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1481 }
1482
1483 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1484                                    u32 add_msr, u32 rm_msr)
1485 {
1486 }
1487
1488 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1489 {
1490         struct rtl_priv *rtlpriv = rtl_priv(hw);
1491         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1492         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1493
1494         switch (variable) {
1495         case HW_VAR_RCR:
1496                 *((u32 *)(val)) = mac->rx_conf;
1497                 break;
1498         case HW_VAR_RF_STATE:
1499                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1500                 break;
1501         case HW_VAR_FWLPS_RF_ON:{
1502                         enum rf_pwrstate rfState;
1503                         u32 val_rcr;
1504
1505                         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1506                                                       (u8 *)(&rfState));
1507                         if (rfState == ERFOFF) {
1508                                 *((bool *) (val)) = true;
1509                         } else {
1510                                 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1511                                 val_rcr &= 0x00070000;
1512                                 if (val_rcr)
1513                                         *((bool *) (val)) = false;
1514                                 else
1515                                         *((bool *) (val)) = true;
1516                         }
1517                         break;
1518                 }
1519         case HW_VAR_FW_PSMODE_STATUS:
1520                 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1521                 break;
1522         case HW_VAR_CORRECT_TSF:{
1523                         u64 tsf;
1524                         u32 *ptsf_low = (u32 *)&tsf;
1525                         u32 *ptsf_high = ((u32 *)&tsf) + 1;
1526
1527                         *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1528                         *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1529                         *((u64 *)(val)) = tsf;
1530                         break;
1531                 }
1532         case HW_VAR_MGT_FILTER:
1533                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1534                 break;
1535         case HW_VAR_CTRL_FILTER:
1536                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1537                 break;
1538         case HW_VAR_DATA_FILTER:
1539                 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1540                 break;
1541         case HAL_DEF_WOWLAN:
1542                 break;
1543         default:
1544                 pr_err("switch case %#x not processed\n", variable);
1545                 break;
1546         }
1547 }
1548
1549 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1550 {
1551   /* Currently nothing happens here.
1552    * Traffic stops after some seconds in WPA2 802.11n mode.
1553    * Maybe because rtl8192cu chip should be set from here?
1554    * If I understand correctly, the realtek vendor driver sends some urbs
1555    * if its "here".
1556    *
1557    * This is maybe necessary:
1558    * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb);
1559    */
1560         dev_kfree_skb(skb);
1561
1562         return true;
1563 }
1564
1565 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1566 {
1567         struct rtl_priv *rtlpriv = rtl_priv(hw);
1568         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1569         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1570         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1571         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1572         enum wireless_mode wirelessmode = mac->mode;
1573         u8 idx = 0;
1574
1575         switch (variable) {
1576         case HW_VAR_ETHER_ADDR:{
1577                         for (idx = 0; idx < ETH_ALEN; idx++) {
1578                                 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1579                                                val[idx]);
1580                         }
1581                         break;
1582                 }
1583         case HW_VAR_BASIC_RATE:{
1584                         u16 rate_cfg = ((u16 *) val)[0];
1585                         u8 rate_index = 0;
1586
1587                         rate_cfg &= 0x15f;
1588                         /* TODO */
1589                         /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1590                          *     && ((rate_cfg & 0x150) == 0)) {
1591                          *        rate_cfg |= 0x010;
1592                          * } */
1593                         rate_cfg |= 0x01;
1594                         rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1595                         rtl_write_byte(rtlpriv, REG_RRSR + 1,
1596                                        (rate_cfg >> 8) & 0xff);
1597                         while (rate_cfg > 0x1) {
1598                                 rate_cfg >>= 1;
1599                                 rate_index++;
1600                         }
1601                         rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1602                                        rate_index);
1603                         break;
1604                 }
1605         case HW_VAR_BSSID:{
1606                         for (idx = 0; idx < ETH_ALEN; idx++) {
1607                                 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1608                                                val[idx]);
1609                         }
1610                         break;
1611                 }
1612         case HW_VAR_SIFS:{
1613                         rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1614                         rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1615                         rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1616                         rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1617                         rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1618                         rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1619                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1620                         break;
1621                 }
1622         case HW_VAR_SLOT_TIME:{
1623                         u8 e_aci;
1624                         u8 QOS_MODE = 1;
1625
1626                         rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1627                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1628                                  "HW_VAR_SLOT_TIME %x\n", val[0]);
1629                         if (QOS_MODE) {
1630                                 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1631                                         rtlpriv->cfg->ops->set_hw_reg(hw,
1632                                                                 HW_VAR_AC_PARAM,
1633                                                                 &e_aci);
1634                         } else {
1635                                 u8 sifstime = 0;
1636                                 u8      u1bAIFS;
1637
1638                                 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1639                                     IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1640                                     IS_WIRELESS_MODE_N_5G(wirelessmode))
1641                                         sifstime = 16;
1642                                 else
1643                                         sifstime = 10;
1644                                 u1bAIFS = sifstime + (2 *  val[0]);
1645                                 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1646                                                u1bAIFS);
1647                                 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1648                                                u1bAIFS);
1649                                 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1650                                                u1bAIFS);
1651                                 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1652                                                u1bAIFS);
1653                         }
1654                         break;
1655                 }
1656         case HW_VAR_ACK_PREAMBLE:{
1657                         u8 reg_tmp;
1658                         u8 short_preamble = (bool)*val;
1659                         reg_tmp = 0;
1660                         if (short_preamble)
1661                                 reg_tmp |= 0x80;
1662                         rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1663                         break;
1664                 }
1665         case HW_VAR_AMPDU_MIN_SPACE:{
1666                         u8 min_spacing_to_set;
1667                         u8 sec_min_space;
1668
1669                         min_spacing_to_set = *val;
1670                         if (min_spacing_to_set <= 7) {
1671                                 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1672                                 case NO_ENCRYPTION:
1673                                 case AESCCMP_ENCRYPTION:
1674                                         sec_min_space = 0;
1675                                         break;
1676                                 case WEP40_ENCRYPTION:
1677                                 case WEP104_ENCRYPTION:
1678                                 case TKIP_ENCRYPTION:
1679                                         sec_min_space = 6;
1680                                         break;
1681                                 default:
1682                                         sec_min_space = 7;
1683                                         break;
1684                                 }
1685                                 if (min_spacing_to_set < sec_min_space)
1686                                         min_spacing_to_set = sec_min_space;
1687                                 mac->min_space_cfg = ((mac->min_space_cfg &
1688                                                      0xf8) |
1689                                                      min_spacing_to_set);
1690                                 *val = min_spacing_to_set;
1691                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1692                                          "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1693                                          mac->min_space_cfg);
1694                                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1695                                                mac->min_space_cfg);
1696                         }
1697                         break;
1698                 }
1699         case HW_VAR_SHORTGI_DENSITY:{
1700                         u8 density_to_set;
1701
1702                         density_to_set = *val;
1703                         density_to_set &= 0x1f;
1704                         mac->min_space_cfg &= 0x07;
1705                         mac->min_space_cfg |= (density_to_set << 3);
1706                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1707                                  "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1708                                  mac->min_space_cfg);
1709                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1710                                        mac->min_space_cfg);
1711                         break;
1712                 }
1713         case HW_VAR_AMPDU_FACTOR:{
1714                         u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1715                         u8 factor_toset;
1716                         u8 *p_regtoset = NULL;
1717                         u8 index = 0;
1718
1719                         p_regtoset = regtoset_normal;
1720                         factor_toset = *val;
1721                         if (factor_toset <= 3) {
1722                                 factor_toset = (1 << (factor_toset + 2));
1723                                 if (factor_toset > 0xf)
1724                                         factor_toset = 0xf;
1725                                 for (index = 0; index < 4; index++) {
1726                                         if ((p_regtoset[index] & 0xf0) >
1727                                             (factor_toset << 4))
1728                                                 p_regtoset[index] =
1729                                                      (p_regtoset[index] & 0x0f)
1730                                                      | (factor_toset << 4);
1731                                         if ((p_regtoset[index] & 0x0f) >
1732                                              factor_toset)
1733                                                 p_regtoset[index] =
1734                                                      (p_regtoset[index] & 0xf0)
1735                                                      | (factor_toset);
1736                                         rtl_write_byte(rtlpriv,
1737                                                        (REG_AGGLEN_LMT + index),
1738                                                        p_regtoset[index]);
1739                                 }
1740                                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1741                                          "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1742                                          factor_toset);
1743                         }
1744                         break;
1745                 }
1746         case HW_VAR_AC_PARAM:{
1747                         u8 e_aci = *val;
1748                         u32 u4b_ac_param;
1749                         u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1750                         u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1751                         u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1752
1753                         u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1754                         u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1755                                          AC_PARAM_ECW_MIN_OFFSET);
1756                         u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1757                                          AC_PARAM_ECW_MAX_OFFSET);
1758                         u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1759                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1760                                  "queue:%x, ac_param:%x\n",
1761                                  e_aci, u4b_ac_param);
1762                         switch (e_aci) {
1763                         case AC1_BK:
1764                                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1765                                                 u4b_ac_param);
1766                                 break;
1767                         case AC0_BE:
1768                                 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1769                                                 u4b_ac_param);
1770                                 break;
1771                         case AC2_VI:
1772                                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1773                                                 u4b_ac_param);
1774                                 break;
1775                         case AC3_VO:
1776                                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1777                                                 u4b_ac_param);
1778                                 break;
1779                         default:
1780                                 WARN_ONCE(true, "rtl8192cu: invalid aci: %d !\n",
1781                                           e_aci);
1782                                 break;
1783                         }
1784                         break;
1785                 }
1786         case HW_VAR_RCR:{
1787                         rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1788                         mac->rx_conf = ((u32 *) (val))[0];
1789                         RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1790                                  "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1791                         break;
1792                 }
1793         case HW_VAR_RETRY_LIMIT:{
1794                         u8 retry_limit = val[0];
1795
1796                         rtl_write_word(rtlpriv, REG_RL,
1797                                        retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1798                                        retry_limit << RETRY_LIMIT_LONG_SHIFT);
1799                         RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1800                                  "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1801                                  retry_limit);
1802                         break;
1803                 }
1804         case HW_VAR_DUAL_TSF_RST:
1805                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1806                 break;
1807         case HW_VAR_EFUSE_BYTES:
1808                 rtlefuse->efuse_usedbytes = *((u16 *) val);
1809                 break;
1810         case HW_VAR_EFUSE_USAGE:
1811                 rtlefuse->efuse_usedpercentage = *val;
1812                 break;
1813         case HW_VAR_IO_CMD:
1814                 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1815                 break;
1816         case HW_VAR_WPA_CONFIG:
1817                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1818                 break;
1819         case HW_VAR_SET_RPWM:{
1820                         u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1821
1822                         if (rpwm_val & BIT(7))
1823                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1824                         else
1825                                 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1826                                                *val | BIT(7));
1827                         break;
1828                 }
1829         case HW_VAR_H2C_FW_PWRMODE:{
1830                         u8 psmode = *val;
1831
1832                         if ((psmode != FW_PS_ACTIVE_MODE) &&
1833                            (!IS_92C_SERIAL(rtlhal->version)))
1834                                 rtl92c_dm_rf_saving(hw, true);
1835                         rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1836                         break;
1837                 }
1838         case HW_VAR_FW_PSMODE_STATUS:
1839                 ppsc->fw_current_inpsmode = *((bool *) val);
1840                 break;
1841         case HW_VAR_H2C_FW_JOINBSSRPT:{
1842                         u8 mstatus = *val;
1843                         u8 tmp_reg422;
1844                         bool recover = false;
1845
1846                         if (mstatus == RT_MEDIA_CONNECT) {
1847                                 rtlpriv->cfg->ops->set_hw_reg(hw,
1848                                                          HW_VAR_AID, NULL);
1849                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1850                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1851                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1852                                 tmp_reg422 = rtl_read_byte(rtlpriv,
1853                                                         REG_FWHW_TXQ_CTRL + 2);
1854                                 if (tmp_reg422 & BIT(6))
1855                                         recover = true;
1856                                 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1857                                                tmp_reg422 & (~BIT(6)));
1858                                 rtl92c_set_fw_rsvdpagepkt(hw,
1859                                                           &usb_cmd_send_packet);
1860                                 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1861                                 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1862                                 if (recover)
1863                                         rtl_write_byte(rtlpriv,
1864                                                  REG_FWHW_TXQ_CTRL + 2,
1865                                                 tmp_reg422 | BIT(6));
1866                                 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1867                         }
1868                         rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1869                         break;
1870                 }
1871         case HW_VAR_AID:{
1872                         u16 u2btmp;
1873
1874                         u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1875                         u2btmp &= 0xC000;
1876                         rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1877                                        (u2btmp | mac->assoc_id));
1878                         break;
1879                 }
1880         case HW_VAR_CORRECT_TSF:{
1881                         u8 btype_ibss = val[0];
1882
1883                         if (btype_ibss)
1884                                 _rtl92cu_stop_tx_beacon(hw);
1885                         _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1886                         rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1887                                         0xffffffff));
1888                         rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1889                                         (u32)((mac->tsf >> 32) & 0xffffffff));
1890                         _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1891                         if (btype_ibss)
1892                                 _rtl92cu_resume_tx_beacon(hw);
1893                         break;
1894                 }
1895         case HW_VAR_MGT_FILTER:
1896                 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1897                 mac->rx_mgt_filter = *(u16 *)val;
1898                 break;
1899         case HW_VAR_CTRL_FILTER:
1900                 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1901                 mac->rx_ctrl_filter = *(u16 *)val;
1902                 break;
1903         case HW_VAR_DATA_FILTER:
1904                 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1905                 mac->rx_data_filter = *(u16 *)val;
1906                 break;
1907         case HW_VAR_KEEP_ALIVE:{
1908                         u8 array[2];
1909                         array[0] = 0xff;
1910                         array[1] = *((u8 *)val);
1911                         rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,
1912                                             array);
1913                         break;
1914                 }
1915         default:
1916                 pr_err("switch case %#x not processed\n", variable);
1917                 break;
1918         }
1919 }
1920
1921 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1922                                           struct ieee80211_sta *sta)
1923 {
1924         struct rtl_priv *rtlpriv = rtl_priv(hw);
1925         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1926         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1927         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1928         u32 ratr_value;
1929         u8 ratr_index = 0;
1930         u8 nmode = mac->ht_enable;
1931         u8 mimo_ps = IEEE80211_SMPS_OFF;
1932         u16 shortgi_rate;
1933         u32 tmp_ratr_value;
1934         u8 curtxbw_40mhz = mac->bw_40;
1935         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1936                                1 : 0;
1937         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1938                                1 : 0;
1939         enum wireless_mode wirelessmode = mac->mode;
1940
1941         if (rtlhal->current_bandtype == BAND_ON_5G)
1942                 ratr_value = sta->supp_rates[1] << 4;
1943         else
1944                 ratr_value = sta->supp_rates[0];
1945         if (mac->opmode == NL80211_IFTYPE_ADHOC)
1946                 ratr_value = 0xfff;
1947
1948         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1949                         sta->ht_cap.mcs.rx_mask[0] << 12);
1950         switch (wirelessmode) {
1951         case WIRELESS_MODE_B:
1952                 if (ratr_value & 0x0000000c)
1953                         ratr_value &= 0x0000000d;
1954                 else
1955                         ratr_value &= 0x0000000f;
1956                 break;
1957         case WIRELESS_MODE_G:
1958                 ratr_value &= 0x00000FF5;
1959                 break;
1960         case WIRELESS_MODE_N_24G:
1961         case WIRELESS_MODE_N_5G:
1962                 nmode = 1;
1963                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1964                         ratr_value &= 0x0007F005;
1965                 } else {
1966                         u32 ratr_mask;
1967
1968                         if (get_rf_type(rtlphy) == RF_1T2R ||
1969                             get_rf_type(rtlphy) == RF_1T1R)
1970                                 ratr_mask = 0x000ff005;
1971                         else
1972                                 ratr_mask = 0x0f0ff005;
1973
1974                         ratr_value &= ratr_mask;
1975                 }
1976                 break;
1977         default:
1978                 if (rtlphy->rf_type == RF_1T2R)
1979                         ratr_value &= 0x000ff0ff;
1980                 else
1981                         ratr_value &= 0x0f0ff0ff;
1982
1983                 break;
1984         }
1985
1986         ratr_value &= 0x0FFFFFFF;
1987
1988         if (nmode && ((curtxbw_40mhz &&
1989                          curshortgi_40mhz) || (!curtxbw_40mhz &&
1990                                                curshortgi_20mhz))) {
1991
1992                 ratr_value |= 0x10000000;
1993                 tmp_ratr_value = (ratr_value >> 12);
1994
1995                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1996                         if ((1 << shortgi_rate) & tmp_ratr_value)
1997                                 break;
1998                 }
1999
2000                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2001                     (shortgi_rate << 4) | (shortgi_rate);
2002         }
2003
2004         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2005
2006         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2007                  rtl_read_dword(rtlpriv, REG_ARFR0));
2008 }
2009
2010 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2011                                          struct ieee80211_sta *sta,
2012                                          u8 rssi_level)
2013 {
2014         struct rtl_priv *rtlpriv = rtl_priv(hw);
2015         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2016         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2017         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2018         struct rtl_sta_info *sta_entry = NULL;
2019         u32 ratr_bitmap;
2020         u8 ratr_index;
2021         u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2022         u8 curshortgi_40mhz = curtxbw_40mhz &&
2023                               (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2024                                 1 : 0;
2025         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2026                                 1 : 0;
2027         enum wireless_mode wirelessmode = 0;
2028         bool shortgi = false;
2029         u8 rate_mask[5];
2030         u8 macid = 0;
2031         u8 mimo_ps = IEEE80211_SMPS_OFF;
2032
2033         sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2034         wirelessmode = sta_entry->wireless_mode;
2035         if (mac->opmode == NL80211_IFTYPE_STATION ||
2036             mac->opmode == NL80211_IFTYPE_MESH_POINT)
2037                 curtxbw_40mhz = mac->bw_40;
2038         else if (mac->opmode == NL80211_IFTYPE_AP ||
2039                 mac->opmode == NL80211_IFTYPE_ADHOC)
2040                 macid = sta->aid + 1;
2041
2042         if (rtlhal->current_bandtype == BAND_ON_5G)
2043                 ratr_bitmap = sta->supp_rates[1] << 4;
2044         else
2045                 ratr_bitmap = sta->supp_rates[0];
2046         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2047                 ratr_bitmap = 0xfff;
2048         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2049                         sta->ht_cap.mcs.rx_mask[0] << 12);
2050         switch (wirelessmode) {
2051         case WIRELESS_MODE_B:
2052                 ratr_index = RATR_INX_WIRELESS_B;
2053                 if (ratr_bitmap & 0x0000000c)
2054                         ratr_bitmap &= 0x0000000d;
2055                 else
2056                         ratr_bitmap &= 0x0000000f;
2057                 break;
2058         case WIRELESS_MODE_G:
2059                 ratr_index = RATR_INX_WIRELESS_GB;
2060
2061                 if (rssi_level == 1)
2062                         ratr_bitmap &= 0x00000f00;
2063                 else if (rssi_level == 2)
2064                         ratr_bitmap &= 0x00000ff0;
2065                 else
2066                         ratr_bitmap &= 0x00000ff5;
2067                 break;
2068         case WIRELESS_MODE_A:
2069                 ratr_index = RATR_INX_WIRELESS_A;
2070                 ratr_bitmap &= 0x00000ff0;
2071                 break;
2072         case WIRELESS_MODE_N_24G:
2073         case WIRELESS_MODE_N_5G:
2074                 ratr_index = RATR_INX_WIRELESS_NGB;
2075
2076                 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2077                         if (rssi_level == 1)
2078                                 ratr_bitmap &= 0x00070000;
2079                         else if (rssi_level == 2)
2080                                 ratr_bitmap &= 0x0007f000;
2081                         else
2082                                 ratr_bitmap &= 0x0007f005;
2083                 } else {
2084                         if (rtlphy->rf_type == RF_1T2R ||
2085                             rtlphy->rf_type == RF_1T1R) {
2086                                 if (curtxbw_40mhz) {
2087                                         if (rssi_level == 1)
2088                                                 ratr_bitmap &= 0x000f0000;
2089                                         else if (rssi_level == 2)
2090                                                 ratr_bitmap &= 0x000ff000;
2091                                         else
2092                                                 ratr_bitmap &= 0x000ff015;
2093                                 } else {
2094                                         if (rssi_level == 1)
2095                                                 ratr_bitmap &= 0x000f0000;
2096                                         else if (rssi_level == 2)
2097                                                 ratr_bitmap &= 0x000ff000;
2098                                         else
2099                                                 ratr_bitmap &= 0x000ff005;
2100                                 }
2101                         } else {
2102                                 if (curtxbw_40mhz) {
2103                                         if (rssi_level == 1)
2104                                                 ratr_bitmap &= 0x0f0f0000;
2105                                         else if (rssi_level == 2)
2106                                                 ratr_bitmap &= 0x0f0ff000;
2107                                         else
2108                                                 ratr_bitmap &= 0x0f0ff015;
2109                                 } else {
2110                                         if (rssi_level == 1)
2111                                                 ratr_bitmap &= 0x0f0f0000;
2112                                         else if (rssi_level == 2)
2113                                                 ratr_bitmap &= 0x0f0ff000;
2114                                         else
2115                                                 ratr_bitmap &= 0x0f0ff005;
2116                                 }
2117                         }
2118                 }
2119
2120                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2121                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2122
2123                         if (macid == 0)
2124                                 shortgi = true;
2125                         else if (macid == 1)
2126                                 shortgi = false;
2127                 }
2128                 break;
2129         default:
2130                 ratr_index = RATR_INX_WIRELESS_NGB;
2131
2132                 if (rtlphy->rf_type == RF_1T2R)
2133                         ratr_bitmap &= 0x000ff0ff;
2134                 else
2135                         ratr_bitmap &= 0x0f0ff0ff;
2136                 break;
2137         }
2138         sta_entry->ratr_index = ratr_index;
2139
2140         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2141                  "ratr_bitmap :%x\n", ratr_bitmap);
2142         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2143                                      (ratr_index << 28);
2144         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2145         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2146                  "Rate_index:%x, ratr_val:%x, %5phC\n",
2147                  ratr_index, ratr_bitmap, rate_mask);
2148         memcpy(rtlpriv->rate_mask, rate_mask, 5);
2149         /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2150          * "scheduled while atomic" if called directly */
2151         schedule_work(&rtlpriv->works.fill_h2c_cmd);
2152
2153         if (macid != 0)
2154                 sta_entry->ratr_index = ratr_index;
2155 }
2156
2157 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2158                                  struct ieee80211_sta *sta,
2159                                  u8 rssi_level)
2160 {
2161         struct rtl_priv *rtlpriv = rtl_priv(hw);
2162
2163         if (rtlpriv->dm.useramask)
2164                 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2165         else
2166                 rtl92cu_update_hal_rate_table(hw, sta);
2167 }
2168
2169 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2170 {
2171         struct rtl_priv *rtlpriv = rtl_priv(hw);
2172         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2173         u16 sifs_timer;
2174
2175         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2176                                       &mac->slot_time);
2177         if (!mac->ht_enable)
2178                 sifs_timer = 0x0a0a;
2179         else
2180                 sifs_timer = 0x0e0e;
2181         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2182 }
2183
2184 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2185 {
2186         struct rtl_priv *rtlpriv = rtl_priv(hw);
2187         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2188         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2189         u8 u1tmp = 0;
2190         bool actuallyset = false;
2191         unsigned long flag = 0;
2192         /* to do - usb autosuspend */
2193         u8 usb_autosuspend = 0;
2194
2195         if (ppsc->swrf_processing)
2196                 return false;
2197         spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2198         if (ppsc->rfchange_inprogress) {
2199                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2200                 return false;
2201         } else {
2202                 ppsc->rfchange_inprogress = true;
2203                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2204         }
2205         cur_rfstate = ppsc->rfpwr_state;
2206         if (usb_autosuspend) {
2207                 /* to do................... */
2208         } else {
2209                 if (ppsc->pwrdown_mode) {
2210                         u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2211                         e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2212                                                ERFOFF : ERFON;
2213                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2214                                  "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2215                 } else {
2216                         rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2217                                        rtl_read_byte(rtlpriv,
2218                                        REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2219                         u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2220                         e_rfpowerstate_toset  = (u1tmp & BIT(3)) ?
2221                                                  ERFON : ERFOFF;
2222                         RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2223                                  "GPIO_IN=%02x\n", u1tmp);
2224                 }
2225                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2226                          e_rfpowerstate_toset);
2227         }
2228         if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2229                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2230                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2231                 ppsc->hwradiooff = false;
2232                 actuallyset = true;
2233         } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset  ==
2234                     ERFOFF)) {
2235                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2236                          "GPIOChangeRF  - HW Radio OFF\n");
2237                 ppsc->hwradiooff = true;
2238                 actuallyset = true;
2239         } else {
2240                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2241                          "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2242                          ppsc->hwradiooff, e_rfpowerstate_toset);
2243         }
2244         if (actuallyset) {
2245                 ppsc->hwradiooff = true;
2246                 if (e_rfpowerstate_toset == ERFON) {
2247                         if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM) &&
2248                              RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2249                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2250                         else if ((ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2251                                  && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2252                                 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2253                 }
2254                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2255                 ppsc->rfchange_inprogress = false;
2256                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2257                 /* For power down module, we need to enable register block
2258                  * contrl reg at 0x1c. Then enable power down control bit
2259                  * of register 0x04 BIT4 and BIT15 as 1.
2260                  */
2261                 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2262                         /* Enable register area 0x0-0xc. */
2263                         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2264                         rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2265                 }
2266                 if (e_rfpowerstate_toset == ERFOFF) {
2267                         if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2268                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2269                         else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2270                                 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2271                 }
2272         } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2273                 /* Enter D3 or ASPM after GPIO had been done. */
2274                 if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_ASPM)
2275                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2276                 else if (ppsc->reg_rfps_level  & RT_RF_OFF_LEVL_PCI_D3)
2277                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2278                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2279                 ppsc->rfchange_inprogress = false;
2280                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2281         } else {
2282                 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2283                 ppsc->rfchange_inprogress = false;
2284                 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2285         }
2286         *valid = 1;
2287         return !ppsc->hwradiooff;
2288 }