1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
39 #include "../rtl8192c/phy_common.h"
42 #include "../rtl8192c/dm_common.h"
43 #include "../rtl8192c/fw_common.h"
45 #include "../rtl8192ce/hw.h"
50 static void _rtl92cu_phy_param_tab_init(struct ieee80211_hw *hw)
52 struct rtl_priv *rtlpriv = rtl_priv(hw);
53 struct rtl_phy *rtlphy = &(rtlpriv->phy);
54 struct rtl_efuse *rtlefuse = rtl_efuse(rtlpriv);
56 rtlphy->hwparam_tables[MAC_REG].length = RTL8192CUMAC_2T_ARRAYLENGTH;
57 rtlphy->hwparam_tables[MAC_REG].pdata = RTL8192CUMAC_2T_ARRAY;
58 if (IS_HIGHT_PA(rtlefuse->board_type)) {
59 rtlphy->hwparam_tables[PHY_REG_PG].length =
60 RTL8192CUPHY_REG_Array_PG_HPLength;
61 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
62 RTL8192CUPHY_REG_Array_PG_HP;
64 rtlphy->hwparam_tables[PHY_REG_PG].length =
65 RTL8192CUPHY_REG_ARRAY_PGLENGTH;
66 rtlphy->hwparam_tables[PHY_REG_PG].pdata =
67 RTL8192CUPHY_REG_ARRAY_PG;
70 rtlphy->hwparam_tables[PHY_REG_2T].length =
71 RTL8192CUPHY_REG_2TARRAY_LENGTH;
72 rtlphy->hwparam_tables[PHY_REG_2T].pdata =
73 RTL8192CUPHY_REG_2TARRAY;
74 rtlphy->hwparam_tables[RADIOA_2T].length =
75 RTL8192CURADIOA_2TARRAYLENGTH;
76 rtlphy->hwparam_tables[RADIOA_2T].pdata =
77 RTL8192CURADIOA_2TARRAY;
78 rtlphy->hwparam_tables[RADIOB_2T].length =
79 RTL8192CURADIOB_2TARRAYLENGTH;
80 rtlphy->hwparam_tables[RADIOB_2T].pdata =
81 RTL8192CU_RADIOB_2TARRAY;
82 rtlphy->hwparam_tables[AGCTAB_2T].length =
83 RTL8192CUAGCTAB_2TARRAYLENGTH;
84 rtlphy->hwparam_tables[AGCTAB_2T].pdata =
85 RTL8192CUAGCTAB_2TARRAY;
87 if (IS_HIGHT_PA(rtlefuse->board_type)) {
88 rtlphy->hwparam_tables[PHY_REG_1T].length =
89 RTL8192CUPHY_REG_1T_HPArrayLength;
90 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
91 RTL8192CUPHY_REG_1T_HPArray;
92 rtlphy->hwparam_tables[RADIOA_1T].length =
93 RTL8192CURadioA_1T_HPArrayLength;
94 rtlphy->hwparam_tables[RADIOA_1T].pdata =
95 RTL8192CURadioA_1T_HPArray;
96 rtlphy->hwparam_tables[RADIOB_1T].length =
97 RTL8192CURADIOB_1TARRAYLENGTH;
98 rtlphy->hwparam_tables[RADIOB_1T].pdata =
99 RTL8192CU_RADIOB_1TARRAY;
100 rtlphy->hwparam_tables[AGCTAB_1T].length =
101 RTL8192CUAGCTAB_1T_HPArrayLength;
102 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
103 Rtl8192CUAGCTAB_1T_HPArray;
105 rtlphy->hwparam_tables[PHY_REG_1T].length =
106 RTL8192CUPHY_REG_1TARRAY_LENGTH;
107 rtlphy->hwparam_tables[PHY_REG_1T].pdata =
108 RTL8192CUPHY_REG_1TARRAY;
109 rtlphy->hwparam_tables[RADIOA_1T].length =
110 RTL8192CURADIOA_1TARRAYLENGTH;
111 rtlphy->hwparam_tables[RADIOA_1T].pdata =
112 RTL8192CU_RADIOA_1TARRAY;
113 rtlphy->hwparam_tables[RADIOB_1T].length =
114 RTL8192CURADIOB_1TARRAYLENGTH;
115 rtlphy->hwparam_tables[RADIOB_1T].pdata =
116 RTL8192CU_RADIOB_1TARRAY;
117 rtlphy->hwparam_tables[AGCTAB_1T].length =
118 RTL8192CUAGCTAB_1TARRAYLENGTH;
119 rtlphy->hwparam_tables[AGCTAB_1T].pdata =
120 RTL8192CUAGCTAB_1TARRAY;
124 static void _rtl92cu_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
128 struct rtl_priv *rtlpriv = rtl_priv(hw);
129 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
130 u8 rf_path, index, tempval;
133 for (rf_path = 0; rf_path < 2; rf_path++) {
134 for (i = 0; i < 3; i++) {
135 if (!autoload_fail) {
137 eeprom_chnlarea_txpwr_cck[rf_path][i] =
138 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
140 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
141 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
145 eeprom_chnlarea_txpwr_cck[rf_path][i] =
146 EEPROM_DEFAULT_TXPOWERLEVEL;
148 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
149 EEPROM_DEFAULT_TXPOWERLEVEL;
153 for (i = 0; i < 3; i++) {
155 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
157 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
158 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
160 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
161 ((tempval & 0xf0) >> 4);
163 for (rf_path = 0; rf_path < 2; rf_path++)
164 for (i = 0; i < 3; i++)
165 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
166 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
169 eeprom_chnlarea_txpwr_cck[rf_path][i]);
170 for (rf_path = 0; rf_path < 2; rf_path++)
171 for (i = 0; i < 3; i++)
172 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
173 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
176 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
177 for (rf_path = 0; rf_path < 2; rf_path++)
178 for (i = 0; i < 3; i++)
179 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
180 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
183 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
184 for (rf_path = 0; rf_path < 2; rf_path++) {
185 for (i = 0; i < 14; i++) {
186 index = rtl92c_get_chnl_group((u8)i);
187 rtlefuse->txpwrlevel_cck[rf_path][i] =
188 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
189 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
191 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
193 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
195 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
197 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
199 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
201 eprom_chnl_txpwr_ht40_2sdf[rf_path]
204 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
207 for (i = 0; i < 14; i++) {
208 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
209 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n", rf_path, i,
210 rtlefuse->txpwrlevel_cck[rf_path][i],
211 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
212 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
215 for (i = 0; i < 3; i++) {
216 if (!autoload_fail) {
217 rtlefuse->eeprom_pwrlimit_ht40[i] =
218 hwinfo[EEPROM_TXPWR_GROUP + i];
219 rtlefuse->eeprom_pwrlimit_ht20[i] =
220 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
222 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
223 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
226 for (rf_path = 0; rf_path < 2; rf_path++) {
227 for (i = 0; i < 14; i++) {
228 index = rtl92c_get_chnl_group((u8)i);
229 if (rf_path == RF90_PATH_A) {
230 rtlefuse->pwrgroup_ht20[rf_path][i] =
231 (rtlefuse->eeprom_pwrlimit_ht20[index]
233 rtlefuse->pwrgroup_ht40[rf_path][i] =
234 (rtlefuse->eeprom_pwrlimit_ht40[index]
236 } else if (rf_path == RF90_PATH_B) {
237 rtlefuse->pwrgroup_ht20[rf_path][i] =
238 ((rtlefuse->eeprom_pwrlimit_ht20[index]
240 rtlefuse->pwrgroup_ht40[rf_path][i] =
241 ((rtlefuse->eeprom_pwrlimit_ht40[index]
244 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
245 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
247 rtlefuse->pwrgroup_ht20[rf_path][i]);
248 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
249 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
251 rtlefuse->pwrgroup_ht40[rf_path][i]);
254 for (i = 0; i < 14; i++) {
255 index = rtl92c_get_chnl_group((u8)i);
257 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
259 tempval = EEPROM_DEFAULT_HT20_DIFF;
260 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
261 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
262 ((tempval >> 4) & 0xF);
263 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
264 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
265 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
266 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
267 index = rtl92c_get_chnl_group((u8)i);
269 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
271 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
272 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
273 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
274 ((tempval >> 4) & 0xF);
276 rtlefuse->legacy_ht_txpowerdiff =
277 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
278 for (i = 0; i < 14; i++)
279 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
280 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
281 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
282 for (i = 0; i < 14; i++)
283 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
284 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
285 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
286 for (i = 0; i < 14; i++)
287 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
288 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
289 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
290 for (i = 0; i < 14; i++)
291 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
292 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
293 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
295 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
297 rtlefuse->eeprom_regulatory = 0;
298 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
299 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
300 if (!autoload_fail) {
301 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
302 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
304 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
305 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
307 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
308 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
309 rtlefuse->eeprom_tssi[RF90_PATH_A],
310 rtlefuse->eeprom_tssi[RF90_PATH_B]);
312 tempval = hwinfo[EEPROM_THERMAL_METER];
314 tempval = EEPROM_DEFAULT_THERMALMETER;
315 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
316 if (rtlefuse->eeprom_thermalmeter < 0x06 ||
317 rtlefuse->eeprom_thermalmeter > 0x1c)
318 rtlefuse->eeprom_thermalmeter = 0x12;
319 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
320 rtlefuse->apk_thermalmeterignore = true;
321 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
322 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
323 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
326 static void _rtl92cu_read_board_type(struct ieee80211_hw *hw, u8 *contents)
328 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
329 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
332 if (IS_NORMAL_CHIP(rtlhal->version)) {
333 boardType = ((contents[EEPROM_RF_OPT1]) &
334 BOARD_TYPE_NORMAL_MASK) >> 5; /*bit[7:5]*/
336 boardType = contents[EEPROM_RF_OPT4];
337 boardType &= BOARD_TYPE_TEST_MASK;
339 rtlefuse->board_type = boardType;
340 if (IS_HIGHT_PA(rtlefuse->board_type))
341 rtlefuse->external_pa = 1;
342 pr_info("Board Type %x\n", rtlefuse->board_type);
345 static void _rtl92cu_read_adapter_info(struct ieee80211_hw *hw)
347 struct rtl_priv *rtlpriv = rtl_priv(hw);
348 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
349 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
351 u8 hwinfo[HWSET_MAX_SIZE] = {0};
354 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
355 rtl_efuse_shadow_map_update(hw);
356 memcpy((void *)hwinfo,
357 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
359 } else if (rtlefuse->epromtype == EEPROM_93C46) {
360 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
361 "RTL819X Not boot from eeprom, check it !!\n");
363 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_LOUD, "MAP",
364 hwinfo, HWSET_MAX_SIZE);
365 eeprom_id = le16_to_cpu(*((__le16 *)&hwinfo[0]));
366 if (eeprom_id != RTL8190_EEPROM_ID) {
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
369 rtlefuse->autoload_failflag = true;
371 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
372 rtlefuse->autoload_failflag = false;
374 if (rtlefuse->autoload_failflag)
376 for (i = 0; i < 6; i += 2) {
377 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
378 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
380 pr_info("MAC address: %pM\n", rtlefuse->dev_addr);
381 _rtl92cu_read_txpower_info_from_hwpg(hw,
382 rtlefuse->autoload_failflag, hwinfo);
383 rtlefuse->eeprom_vid = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VID]);
384 rtlefuse->eeprom_did = le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_DID]);
385 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, " VID = 0x%02x PID = 0x%02x\n",
386 rtlefuse->eeprom_vid, rtlefuse->eeprom_did);
387 rtlefuse->eeprom_channelplan = hwinfo[EEPROM_CHANNELPLAN];
388 rtlefuse->eeprom_version =
389 le16_to_cpu(*(__le16 *)&hwinfo[EEPROM_VERSION]);
390 rtlefuse->txpwr_fromeprom = true;
391 rtlefuse->eeprom_oemid = hwinfo[EEPROM_CUSTOMER_ID];
392 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "EEPROM Customer ID: 0x%2x\n",
393 rtlefuse->eeprom_oemid);
394 if (rtlhal->oem_id == RT_CID_DEFAULT) {
395 switch (rtlefuse->eeprom_oemid) {
396 case EEPROM_CID_DEFAULT:
397 if (rtlefuse->eeprom_did == 0x8176) {
398 if ((rtlefuse->eeprom_svid == 0x103C &&
399 rtlefuse->eeprom_smid == 0x1629))
400 rtlhal->oem_id = RT_CID_819X_HP;
402 rtlhal->oem_id = RT_CID_DEFAULT;
404 rtlhal->oem_id = RT_CID_DEFAULT;
407 case EEPROM_CID_TOSHIBA:
408 rtlhal->oem_id = RT_CID_TOSHIBA;
411 rtlhal->oem_id = RT_CID_819X_QMI;
413 case EEPROM_CID_WHQL:
415 rtlhal->oem_id = RT_CID_DEFAULT;
419 _rtl92cu_read_board_type(hw, hwinfo);
422 static void _rtl92cu_hal_customized_behavior(struct ieee80211_hw *hw)
424 struct rtl_priv *rtlpriv = rtl_priv(hw);
425 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
426 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
428 switch (rtlhal->oem_id) {
430 usb_priv->ledctl.led_opendrain = true;
432 case RT_CID_819X_LENOVO:
436 case RT_CID_819X_ACER:
441 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "RT Customized ID: 0x%02X\n",
445 void rtl92cu_read_eeprom_info(struct ieee80211_hw *hw)
448 struct rtl_priv *rtlpriv = rtl_priv(hw);
449 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
450 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
453 if (!IS_NORMAL_CHIP(rtlhal->version))
455 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
456 rtlefuse->epromtype = (tmp_u1b & BOOT_FROM_EEPROM) ?
457 EEPROM_93C46 : EEPROM_BOOT_EFUSE;
458 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from %s\n",
459 tmp_u1b & BOOT_FROM_EEPROM ? "EERROM" : "EFUSE");
460 rtlefuse->autoload_failflag = (tmp_u1b & EEPROM_EN) ? false : true;
461 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload %s\n",
462 tmp_u1b & EEPROM_EN ? "OK!!" : "ERR!!");
463 _rtl92cu_read_adapter_info(hw);
464 _rtl92cu_hal_customized_behavior(hw);
468 static int _rtl92cu_init_power_on(struct ieee80211_hw *hw)
470 struct rtl_priv *rtlpriv = rtl_priv(hw);
474 /* polling autoload done. */
475 u32 pollingCount = 0;
478 if (rtl_read_byte(rtlpriv, REG_APS_FSMCO) & PFM_ALDN) {
479 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
483 if (pollingCount++ > 100) {
484 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
485 "Failed to polling REG_APS_FSMCO[PFM_ALDN] done!\n");
489 /* 0. RSV_CTRL 0x1C[7:0] = 0 unlock ISO/CLK/Power control register */
490 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
491 /* Power on when re-enter from IPS/Radio off/card disable */
492 /* enable SPS into PWM mode */
493 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
495 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
496 if (0 == (value8 & LDV12_EN)) {
498 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
499 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
500 " power-on :REG_LDOV12D_CTRL Reg0x21:0x%02x\n",
503 value8 = rtl_read_byte(rtlpriv, REG_SYS_ISO_CTRL);
504 value8 &= ~ISO_MD2PP;
505 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, value8);
507 /* auto enable WLAN */
509 value16 = rtl_read_word(rtlpriv, REG_APS_FSMCO);
510 value16 |= APFM_ONMAC;
511 rtl_write_word(rtlpriv, REG_APS_FSMCO, value16);
513 if (!(rtl_read_word(rtlpriv, REG_APS_FSMCO) & APFM_ONMAC)) {
514 pr_info("MAC auto ON okay!\n");
517 if (pollingCount++ > 1000) {
518 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
519 "Failed to polling REG_APS_FSMCO[APFM_ONMAC] done!\n");
523 /* Enable Radio ,GPIO ,and LED function */
524 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x0812);
525 /* release RF digital isolation */
526 value16 = rtl_read_word(rtlpriv, REG_SYS_ISO_CTRL);
527 value16 &= ~ISO_DIOR;
528 rtl_write_word(rtlpriv, REG_SYS_ISO_CTRL, value16);
529 /* Reconsider when to do this operation after asking HWSD. */
531 rtl_write_byte(rtlpriv, REG_APSD_CTRL, (rtl_read_byte(rtlpriv,
532 REG_APSD_CTRL) & ~BIT(6)));
535 } while ((pollingCount < 200) &&
536 (rtl_read_byte(rtlpriv, REG_APSD_CTRL) & BIT(7)));
537 /* Enable MAC DMA/WMAC/SCHEDULE/SEC block */
538 value16 = rtl_read_word(rtlpriv, REG_CR);
539 value16 |= (HCI_TXDMA_EN | HCI_RXDMA_EN | TXDMA_EN | RXDMA_EN |
540 PROTOCOL_EN | SCHEDULE_EN | MACTXEN | MACRXEN | ENSEC);
541 rtl_write_word(rtlpriv, REG_CR, value16);
545 static void _rtl92cu_init_queue_reserved_page(struct ieee80211_hw *hw,
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
552 bool isChipN = IS_NORMAL_CHIP(rtlhal->version);
553 u32 outEPNum = (u32)out_ep_num;
560 u32 txQPageNum, txQPageUnit, txQRemainPage;
563 numPubQ = (isChipN) ? CHIP_B_PAGE_NUM_PUBQ :
564 CHIP_A_PAGE_NUM_PUBQ;
565 txQPageNum = TX_TOTAL_PAGE_NUMBER - numPubQ;
567 txQPageUnit = txQPageNum/outEPNum;
568 txQRemainPage = txQPageNum % outEPNum;
569 if (queue_sel & TX_SELE_HQ)
571 if (queue_sel & TX_SELE_LQ)
573 /* HIGH priority queue always present in the configuration of
574 * 2 out-ep. Remainder pages have assigned to High queue */
575 if ((outEPNum > 1) && (txQRemainPage))
576 numHQ += txQRemainPage;
577 /* NOTE: This step done before writting REG_RQPN. */
579 if (queue_sel & TX_SELE_NQ)
581 value8 = (u8)_NPQ(numNQ);
582 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
585 /* for WMM ,number of out-ep must more than or equal to 2! */
586 numPubQ = isChipN ? WMM_CHIP_B_PAGE_NUM_PUBQ :
587 WMM_CHIP_A_PAGE_NUM_PUBQ;
588 if (queue_sel & TX_SELE_HQ) {
589 numHQ = isChipN ? WMM_CHIP_B_PAGE_NUM_HPQ :
590 WMM_CHIP_A_PAGE_NUM_HPQ;
592 if (queue_sel & TX_SELE_LQ) {
593 numLQ = isChipN ? WMM_CHIP_B_PAGE_NUM_LPQ :
594 WMM_CHIP_A_PAGE_NUM_LPQ;
596 /* NOTE: This step done before writting REG_RQPN. */
598 if (queue_sel & TX_SELE_NQ)
599 numNQ = WMM_CHIP_B_PAGE_NUM_NPQ;
600 value8 = (u8)_NPQ(numNQ);
601 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, value8);
605 value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
606 rtl_write_dword(rtlpriv, REG_RQPN, value32);
609 static void _rtl92c_init_trx_buffer(struct ieee80211_hw *hw, bool wmm_enable)
611 struct rtl_priv *rtlpriv = rtl_priv(hw);
612 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
617 txpktbuf_bndy = TX_PAGE_BOUNDARY;
619 txpktbuf_bndy = (IS_NORMAL_CHIP(rtlhal->version))
620 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
621 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
624 rtl_write_byte(rtlpriv, REG_TXPKTBUF_WMAC_LBK_BF_HD, txpktbuf_bndy);
625 rtl_write_byte(rtlpriv, REG_TRXFF_BNDY, txpktbuf_bndy);
626 rtl_write_byte(rtlpriv, REG_TDECTRL+1, txpktbuf_bndy);
627 rtl_write_word(rtlpriv, (REG_TRXFF_BNDY + 2), 0x27FF);
628 value8 = _PSRX(RX_PAGE_SIZE_REG_VALUE) | _PSTX(PBP_128);
629 rtl_write_byte(rtlpriv, REG_PBP, value8);
632 static void _rtl92c_init_chipN_reg_priority(struct ieee80211_hw *hw, u16 beQ,
633 u16 bkQ, u16 viQ, u16 voQ,
636 struct rtl_priv *rtlpriv = rtl_priv(hw);
637 u16 value16 = (rtl_read_word(rtlpriv, REG_TRXDMA_CTRL) & 0x7);
639 value16 |= _TXDMA_BEQ_MAP(beQ) | _TXDMA_BKQ_MAP(bkQ) |
640 _TXDMA_VIQ_MAP(viQ) | _TXDMA_VOQ_MAP(voQ) |
641 _TXDMA_MGQ_MAP(mgtQ) | _TXDMA_HIQ_MAP(hiQ);
642 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, value16);
645 static void _rtl92cu_init_chipN_one_out_ep_priority(struct ieee80211_hw *hw,
649 u16 uninitialized_var(value);
659 value = QUEUE_NORMAL;
662 WARN_ON(1); /* Shall not reach here! */
665 _rtl92c_init_chipN_reg_priority(hw, value, value, value, value,
667 pr_info("Tx queue select: 0x%02x\n", queue_sel);
670 static void _rtl92cu_init_chipN_two_out_ep_priority(struct ieee80211_hw *hw,
674 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
675 u16 uninitialized_var(valueHi);
676 u16 uninitialized_var(valueLow);
679 case (TX_SELE_HQ | TX_SELE_LQ):
680 valueHi = QUEUE_HIGH;
681 valueLow = QUEUE_LOW;
683 case (TX_SELE_NQ | TX_SELE_LQ):
684 valueHi = QUEUE_NORMAL;
685 valueLow = QUEUE_LOW;
687 case (TX_SELE_HQ | TX_SELE_NQ):
688 valueHi = QUEUE_HIGH;
689 valueLow = QUEUE_NORMAL;
702 } else {/* for WMM ,CONFIG_OUT_EP_WIFI_MODE */
710 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
711 pr_info("Tx queue select: 0x%02x\n", queue_sel);
714 static void _rtl92cu_init_chipN_three_out_ep_priority(struct ieee80211_hw *hw,
718 u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
719 struct rtl_priv *rtlpriv = rtl_priv(hw);
721 if (!wmm_enable) { /* typical setting */
728 } else { /* for WMM */
736 _rtl92c_init_chipN_reg_priority(hw, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
737 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
741 static void _rtl92cu_init_chipN_queue_priority(struct ieee80211_hw *hw,
746 switch (out_ep_num) {
748 _rtl92cu_init_chipN_one_out_ep_priority(hw, wmm_enable,
752 _rtl92cu_init_chipN_two_out_ep_priority(hw, wmm_enable,
756 _rtl92cu_init_chipN_three_out_ep_priority(hw, wmm_enable,
760 WARN_ON(1); /* Shall not reach here! */
765 static void _rtl92cu_init_chipT_queue_priority(struct ieee80211_hw *hw,
771 struct rtl_priv *rtlpriv = rtl_priv(hw);
773 switch (out_ep_num) {
774 case 2: /* (TX_SELE_HQ|TX_SELE_LQ) */
775 if (!wmm_enable) /* typical setting */
776 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_MGTQ |
779 hq_sele = HQSEL_VOQ | HQSEL_BEQ | HQSEL_MGTQ |
783 if (TX_SELE_LQ == queue_sel) {
784 /* map all endpoint to Low queue */
786 } else if (TX_SELE_HQ == queue_sel) {
787 /* map all endpoint to High queue */
788 hq_sele = HQSEL_VOQ | HQSEL_VIQ | HQSEL_BEQ |
789 HQSEL_BKQ | HQSEL_MGTQ | HQSEL_HIQ;
793 WARN_ON(1); /* Shall not reach here! */
796 rtl_write_byte(rtlpriv, (REG_TRXDMA_CTRL+1), hq_sele);
797 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG, "Tx queue select :0x%02x..\n",
801 static void _rtl92cu_init_queue_priority(struct ieee80211_hw *hw,
806 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
807 if (IS_NORMAL_CHIP(rtlhal->version))
808 _rtl92cu_init_chipN_queue_priority(hw, wmm_enable, out_ep_num,
811 _rtl92cu_init_chipT_queue_priority(hw, wmm_enable, out_ep_num,
815 static void _rtl92cu_init_usb_aggregation(struct ieee80211_hw *hw)
819 static void _rtl92cu_init_wmac_setting(struct ieee80211_hw *hw)
823 struct rtl_priv *rtlpriv = rtl_priv(hw);
825 value32 = (RCR_APM | RCR_AM | RCR_ADF | RCR_AB | RCR_APPFCS |
826 RCR_APP_ICV | RCR_AMF | RCR_HTC_LOC_CTRL |
827 RCR_APP_MIC | RCR_APP_PHYSTS | RCR_ACRC32);
828 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR, (u8 *)(&value32));
829 /* Accept all multicast address */
830 rtl_write_dword(rtlpriv, REG_MAR, 0xFFFFFFFF);
831 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xFFFFFFFF);
832 /* Accept all management frames */
834 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_MGT_FILTER,
836 /* Reject all control frame - default value is 0 */
838 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_CTRL_FILTER,
840 /* Accept all data frames */
842 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_DATA_FILTER,
846 static void _rtl92cu_init_beacon_parameters(struct ieee80211_hw *hw)
848 struct rtl_priv *rtlpriv = rtl_priv(hw);
849 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
851 rtl_write_word(rtlpriv, REG_BCN_CTRL, 0x1010);
853 /* TODO: Remove these magic number */
854 rtl_write_word(rtlpriv, REG_TBTT_PROHIBIT, 0x6404);
855 rtl_write_byte(rtlpriv, REG_DRVERLYINT, DRIVER_EARLY_INT_TIME);
856 rtl_write_byte(rtlpriv, REG_BCNDMATIM, BCN_DMA_ATIME_INT_TIME);
857 /* Change beacon AIFS to the largest number
858 * beacause test chip does not contension before sending beacon.
860 if (IS_NORMAL_CHIP(rtlhal->version))
861 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660F);
863 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x66FF);
866 static int _rtl92cu_init_mac(struct ieee80211_hw *hw)
868 struct rtl_priv *rtlpriv = rtl_priv(hw);
869 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
870 struct rtl_usb_priv *usb_priv = rtl_usbpriv(hw);
871 struct rtl_usb *rtlusb = rtl_usbdev(usb_priv);
874 u8 wmm_enable = false; /* TODO */
875 u8 out_ep_nums = rtlusb->out_ep_nums;
876 u8 queue_sel = rtlusb->out_queue_sel;
877 err = _rtl92cu_init_power_on(hw);
880 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
881 "Failed to init power on!\n");
885 boundary = TX_PAGE_BOUNDARY;
886 } else { /* for WMM */
887 boundary = (IS_NORMAL_CHIP(rtlhal->version))
888 ? WMM_CHIP_B_TX_PAGE_BOUNDARY
889 : WMM_CHIP_A_TX_PAGE_BOUNDARY;
891 if (false == rtl92c_init_llt_table(hw, boundary)) {
892 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
893 "Failed to init LLT Table!\n");
896 _rtl92cu_init_queue_reserved_page(hw, wmm_enable, out_ep_nums,
898 _rtl92c_init_trx_buffer(hw, wmm_enable);
899 _rtl92cu_init_queue_priority(hw, wmm_enable, out_ep_nums,
901 /* Get Rx PHY status in order to report RSSI and others. */
902 rtl92c_init_driver_info_size(hw, RTL92C_DRIVER_INFO_SIZE);
903 rtl92c_init_interrupt(hw);
904 rtl92c_init_network_type(hw);
905 _rtl92cu_init_wmac_setting(hw);
906 rtl92c_init_adaptive_ctrl(hw);
907 rtl92c_init_edca(hw);
908 rtl92c_init_rate_fallback(hw);
909 rtl92c_init_retry_function(hw);
910 _rtl92cu_init_usb_aggregation(hw);
911 rtlpriv->cfg->ops->set_bw_mode(hw, NL80211_CHAN_HT20);
912 rtl92c_set_min_space(hw, IS_92C_SERIAL(rtlhal->version));
913 _rtl92cu_init_beacon_parameters(hw);
914 rtl92c_init_ampdu_aggregation(hw);
915 rtl92c_init_beacon_max_error(hw);
919 void rtl92cu_enable_hw_security_config(struct ieee80211_hw *hw)
921 struct rtl_priv *rtlpriv = rtl_priv(hw);
922 u8 sec_reg_value = 0x0;
923 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
925 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
926 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
927 rtlpriv->sec.pairwise_enc_algorithm,
928 rtlpriv->sec.group_enc_algorithm);
929 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
930 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
931 "not open sw encryption\n");
934 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
935 if (rtlpriv->sec.use_defaultkey) {
936 sec_reg_value |= SCR_TxUseDK;
937 sec_reg_value |= SCR_RxUseDK;
939 if (IS_NORMAL_CHIP(rtlhal->version))
940 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
941 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
942 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD, "The SECR-value %x\n",
944 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
947 static void _rtl92cu_hw_configure(struct ieee80211_hw *hw)
949 struct rtl_priv *rtlpriv = rtl_priv(hw);
950 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
952 /* To Fix MAC loopback mode fail. */
953 rtl_write_byte(rtlpriv, REG_LDOHCI12_CTRL, 0x0f);
954 rtl_write_byte(rtlpriv, 0x15, 0xe9);
956 /* set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
957 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
958 /* fixed USB interface interference issue */
959 rtl_write_byte(rtlpriv, 0xfe40, 0xe0);
960 rtl_write_byte(rtlpriv, 0xfe41, 0x8d);
961 rtl_write_byte(rtlpriv, 0xfe42, 0x80);
962 rtlusb->reg_bcn_ctrl_val = 0x18;
963 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
966 static void _InitPABias(struct ieee80211_hw *hw)
968 struct rtl_priv *rtlpriv = rtl_priv(hw);
969 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
972 /* FIXED PA current issue */
973 pa_setting = efuse_read_1byte(hw, 0x1FA);
974 if (!(pa_setting & BIT(0))) {
975 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x0F406);
976 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x4F406);
977 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0x8F406);
978 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0FFFFF, 0xCF406);
980 if (!(pa_setting & BIT(1)) && IS_NORMAL_CHIP(rtlhal->version) &&
981 IS_92C_SERIAL(rtlhal->version)) {
982 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x0F406);
983 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x4F406);
984 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0x8F406);
985 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0FFFFF, 0xCF406);
987 if (!(pa_setting & BIT(4))) {
988 pa_setting = rtl_read_byte(rtlpriv, 0x16);
990 rtl_write_byte(rtlpriv, 0x16, pa_setting | 0x90);
994 int rtl92cu_hw_init(struct ieee80211_hw *hw)
996 struct rtl_priv *rtlpriv = rtl_priv(hw);
997 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
998 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
999 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1000 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1002 unsigned long flags;
1004 /* As this function can take a very long time (up to 350 ms)
1005 * and can be called with irqs disabled, reenable the irqs
1006 * to let the other devices continue being serviced.
1008 * It is safe doing so since our own interrupts will only be enabled
1009 * in a subsequent step.
1011 local_save_flags(flags);
1014 rtlhal->fw_ready = false;
1015 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CU;
1016 err = _rtl92cu_init_mac(hw);
1018 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "init mac failed!\n");
1021 err = rtl92c_download_fw(hw);
1023 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1024 "Failed to download FW. Init HW without FW now..\n");
1029 rtlhal->fw_ready = true;
1030 rtlhal->last_hmeboxnum = 0; /* h2c */
1031 _rtl92cu_phy_param_tab_init(hw);
1032 rtl92cu_phy_mac_config(hw);
1033 rtl92cu_phy_bb_config(hw);
1034 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1035 rtl92c_phy_rf_config(hw);
1036 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
1037 !IS_92C_SERIAL(rtlhal->version)) {
1038 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
1039 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1041 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1042 RF_CHNLBW, RFREG_OFFSET_MASK);
1043 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1044 RF_CHNLBW, RFREG_OFFSET_MASK);
1045 rtl92cu_bb_block_on(hw);
1046 rtl_cam_reset_all_entry(hw);
1047 rtl92cu_enable_hw_security_config(hw);
1048 ppsc->rfpwr_state = ERFON;
1049 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1050 if (ppsc->rfpwr_state == ERFON) {
1051 rtl92c_phy_set_rfpath_switch(hw, 1);
1052 if (rtlphy->iqk_initialized) {
1053 rtl92c_phy_iq_calibrate(hw, true);
1055 rtl92c_phy_iq_calibrate(hw, false);
1056 rtlphy->iqk_initialized = true;
1058 rtl92c_dm_check_txpower_tracking(hw);
1059 rtl92c_phy_lc_calibrate(hw);
1061 _rtl92cu_hw_configure(hw);
1065 local_irq_disable();
1066 local_irq_restore(flags);
1070 static void _DisableRFAFEAndResetBB(struct ieee80211_hw *hw)
1072 struct rtl_priv *rtlpriv = rtl_priv(hw);
1073 /**************************************
1074 a. TXPAUSE 0x522[7:0] = 0xFF Pause MAC TX queue
1075 b. RF path 0 offset 0x00 = 0x00 disable RF
1076 c. APSD_CTRL 0x600[7:0] = 0x40
1077 d. SYS_FUNC_EN 0x02[7:0] = 0x16 reset BB state machine
1078 e. SYS_FUNC_EN 0x02[7:0] = 0x14 reset BB state machine
1079 ***************************************/
1080 u8 eRFPath = 0, value8 = 0;
1081 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1082 rtl_set_rfreg(hw, (enum radio_path)eRFPath, 0x0, MASKBYTE0, 0x0);
1085 rtl_write_byte(rtlpriv, REG_APSD_CTRL, value8); /*0x40*/
1087 value8 |= (FEN_USBD | FEN_USBA | FEN_BB_GLB_RSTn);
1088 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8);/*0x16*/
1089 value8 &= (~FEN_BB_GLB_RSTn);
1090 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, value8); /*0x14*/
1093 static void _ResetDigitalProcedure1(struct ieee80211_hw *hw, bool bWithoutHWSM)
1095 struct rtl_priv *rtlpriv = rtl_priv(hw);
1096 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1098 if (rtlhal->fw_version <= 0x20) {
1099 /*****************************
1100 f. MCUFWDL 0x80[7:0]=0 reset MCU ready status
1101 g. SYS_FUNC_EN 0x02[10]= 0 reset MCU reg, (8051 reset)
1102 h. SYS_FUNC_EN 0x02[15-12]= 5 reset MAC reg, DCORE
1103 i. SYS_FUNC_EN 0x02[10]= 1 enable MCU reg, (8051 enable)
1104 ******************************/
1107 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1108 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1109 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 &
1110 (~FEN_CPUEN))); /* reset MCU ,8051 */
1111 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN)&0x0FFF;
1112 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1113 (FEN_HWPDN|FEN_ELDR))); /* reset MAC */
1114 valu16 = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
1115 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN, (valu16 |
1116 FEN_CPUEN)); /* enable MCU ,8051 */
1120 /* IF fw in RAM code, do reset */
1121 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(1)) {
1122 /* reset MCU ready status */
1123 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1124 /* 8051 reset by self */
1125 rtl_write_byte(rtlpriv, REG_HMETFR+3, 0x20);
1126 while ((retry_cnts++ < 100) &&
1127 (FEN_CPUEN & rtl_read_word(rtlpriv,
1128 REG_SYS_FUNC_EN))) {
1131 if (retry_cnts >= 100) {
1132 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1133 "#####=> 8051 reset failed!.........................\n");
1134 /* if 8051 reset fail, reset MAC. */
1135 rtl_write_byte(rtlpriv,
1136 REG_SYS_FUNC_EN + 1,
1141 /* Reset MAC and Enable 8051 */
1142 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x54);
1143 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0);
1146 /*****************************
1147 Without HW auto state machine
1148 g.SYS_CLKR 0x08[15:0] = 0x30A3 disable MAC clock
1149 h.AFE_PLL_CTRL 0x28[7:0] = 0x80 disable AFE PLL
1150 i.AFE_XTAL_CTRL 0x24[15:0] = 0x880F gated AFE DIG_CLOCK
1151 j.SYS_ISu_CTRL 0x00[7:0] = 0xF9 isolated digital to PON
1152 ******************************/
1153 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1154 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1155 rtl_write_word(rtlpriv, REG_AFE_XTAL_CTRL, 0x880F);
1156 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL, 0xF9);
1160 static void _ResetDigitalProcedure2(struct ieee80211_hw *hw)
1162 struct rtl_priv *rtlpriv = rtl_priv(hw);
1163 /*****************************
1164 k. SYS_FUNC_EN 0x03[7:0] = 0x44 disable ELDR runction
1165 l. SYS_CLKR 0x08[15:0] = 0x3083 disable ELDR clock
1166 m. SYS_ISO_CTRL 0x01[7:0] = 0x83 isolated ELDR to PON
1167 ******************************/
1168 rtl_write_word(rtlpriv, REG_SYS_CLKR, 0x70A3);
1169 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL+1, 0x82);
1172 static void _DisableGPIO(struct ieee80211_hw *hw)
1174 struct rtl_priv *rtlpriv = rtl_priv(hw);
1175 /***************************************
1176 j. GPIO_PIN_CTRL 0x44[31:0]=0x000
1177 k. Value = GPIO_PIN_CTRL[7:0]
1178 l. GPIO_PIN_CTRL 0x44[31:0] = 0x00FF0000 | (value <<8); write ext PIN level
1179 m. GPIO_MUXCFG 0x42 [15:0] = 0x0780
1180 n. LEDCFG 0x4C[15:0] = 0x8080
1181 ***************************************/
1186 /* 1. Disable GPIO[7:0] */
1187 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, 0x0000);
1188 value32 = rtl_read_dword(rtlpriv, REG_GPIO_PIN_CTRL) & 0xFFFF00FF;
1189 value8 = (u8)(value32&0x000000FF);
1190 value32 |= ((value8<<8) | 0x00FF0000);
1191 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, value32);
1192 /* 2. Disable GPIO[10:8] */
1193 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+3, 0x00);
1194 value16 = rtl_read_word(rtlpriv, REG_GPIO_MUXCFG+2) & 0xFF0F;
1195 value8 = (u8)(value16&0x000F);
1196 value16 |= ((value8<<4) | 0x0780);
1197 rtl_write_word(rtlpriv, REG_GPIO_PIN_CTRL+2, value16);
1198 /* 3. Disable LED0 & 1 */
1199 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1202 static void _DisableAnalog(struct ieee80211_hw *hw, bool bWithoutHWSM)
1204 struct rtl_priv *rtlpriv = rtl_priv(hw);
1209 /*****************************
1210 n. LDOA15_CTRL 0x20[7:0] = 0x04 disable A15 power
1211 o. LDOV12D_CTRL 0x21[7:0] = 0x54 disable digital core power
1212 r. When driver call disable, the ASIC will turn off remaining
1214 ******************************/
1215 rtl_write_byte(rtlpriv, REG_LDOA15_CTRL, 0x04);
1216 value8 = rtl_read_byte(rtlpriv, REG_LDOV12D_CTRL);
1217 value8 &= (~LDV12_EN);
1218 rtl_write_byte(rtlpriv, REG_LDOV12D_CTRL, value8);
1221 /*****************************
1222 h. SPS0_CTRL 0x11[7:0] = 0x23 enter PFM mode
1223 i. APS_FSMCO 0x04[15:0] = 0x4802 set USB suspend
1224 ******************************/
1225 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1226 value16 |= (APDM_HOST | AFSM_HSUS | PFM_ALDN);
1227 rtl_write_word(rtlpriv, REG_APS_FSMCO, (u16)value16);
1228 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1231 static void _CardDisableHWSM(struct ieee80211_hw *hw)
1233 /* ==== RF Off Sequence ==== */
1234 _DisableRFAFEAndResetBB(hw);
1235 /* ==== Reset digital sequence ====== */
1236 _ResetDigitalProcedure1(hw, false);
1237 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1239 /* ==== Disable analog sequence === */
1240 _DisableAnalog(hw, false);
1243 static void _CardDisableWithoutHWSM(struct ieee80211_hw *hw)
1245 /*==== RF Off Sequence ==== */
1246 _DisableRFAFEAndResetBB(hw);
1247 /* ==== Reset digital sequence ====== */
1248 _ResetDigitalProcedure1(hw, true);
1249 /* ==== Pull GPIO PIN to balance level and LED control ====== */
1251 /* ==== Reset digital sequence ====== */
1252 _ResetDigitalProcedure2(hw);
1253 /* ==== Disable analog sequence === */
1254 _DisableAnalog(hw, true);
1257 static void _rtl92cu_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
1258 u8 set_bits, u8 clear_bits)
1260 struct rtl_priv *rtlpriv = rtl_priv(hw);
1261 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1263 rtlusb->reg_bcn_ctrl_val |= set_bits;
1264 rtlusb->reg_bcn_ctrl_val &= ~clear_bits;
1265 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlusb->reg_bcn_ctrl_val);
1268 static void _rtl92cu_stop_tx_beacon(struct ieee80211_hw *hw)
1270 struct rtl_priv *rtlpriv = rtl_priv(hw);
1271 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1273 if (IS_NORMAL_CHIP(rtlhal->version)) {
1274 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1275 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1276 tmp1byte & (~BIT(6)));
1277 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
1278 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1279 tmp1byte &= ~(BIT(0));
1280 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1282 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1283 rtl_read_byte(rtlpriv, REG_TXPAUSE) | BIT(6));
1287 static void _rtl92cu_resume_tx_beacon(struct ieee80211_hw *hw)
1289 struct rtl_priv *rtlpriv = rtl_priv(hw);
1290 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1293 if (IS_NORMAL_CHIP(rtlhal->version)) {
1294 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
1295 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1297 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
1298 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
1300 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
1302 rtl_write_byte(rtlpriv, REG_TXPAUSE,
1303 rtl_read_byte(rtlpriv, REG_TXPAUSE) & (~BIT(6)));
1307 static void _rtl92cu_enable_bcn_sub_func(struct ieee80211_hw *hw)
1309 struct rtl_priv *rtlpriv = rtl_priv(hw);
1310 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1312 if (IS_NORMAL_CHIP(rtlhal->version))
1313 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(1));
1315 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1318 static void _rtl92cu_disable_bcn_sub_func(struct ieee80211_hw *hw)
1320 struct rtl_priv *rtlpriv = rtl_priv(hw);
1321 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1323 if (IS_NORMAL_CHIP(rtlhal->version))
1324 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(1), 0);
1326 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1329 static int _rtl92cu_set_media_status(struct ieee80211_hw *hw,
1330 enum nl80211_iftype type)
1332 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1334 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1337 if (type == NL80211_IFTYPE_UNSPECIFIED || type ==
1338 NL80211_IFTYPE_STATION) {
1339 _rtl92cu_stop_tx_beacon(hw);
1340 _rtl92cu_enable_bcn_sub_func(hw);
1341 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP) {
1342 _rtl92cu_resume_tx_beacon(hw);
1343 _rtl92cu_disable_bcn_sub_func(hw);
1345 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1346 "Set HW_VAR_MEDIA_STATUS:No such media status(%x)\n",
1350 case NL80211_IFTYPE_UNSPECIFIED:
1351 bt_msr |= MSR_NOLINK;
1352 ledaction = LED_CTL_LINK;
1353 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1354 "Set Network type to NO LINK!\n");
1356 case NL80211_IFTYPE_ADHOC:
1357 bt_msr |= MSR_ADHOC;
1358 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1359 "Set Network type to Ad Hoc!\n");
1361 case NL80211_IFTYPE_STATION:
1362 bt_msr |= MSR_INFRA;
1363 ledaction = LED_CTL_LINK;
1364 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1365 "Set Network type to STA!\n");
1367 case NL80211_IFTYPE_AP:
1369 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1370 "Set Network type to AP!\n");
1373 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1374 "Network type %d not supported!\n", type);
1377 rtl_write_byte(rtlpriv, MSR, bt_msr);
1378 rtlpriv->cfg->ops->led_control(hw, ledaction);
1379 if ((bt_msr & MSR_MASK) == MSR_AP)
1380 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1382 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1388 void rtl92cu_card_disable(struct ieee80211_hw *hw)
1390 struct rtl_priv *rtlpriv = rtl_priv(hw);
1391 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1392 struct rtl_usb *rtlusb = rtl_usbdev(rtl_usbpriv(hw));
1393 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1394 enum nl80211_iftype opmode;
1396 mac->link_state = MAC80211_NOLINK;
1397 opmode = NL80211_IFTYPE_UNSPECIFIED;
1398 _rtl92cu_set_media_status(hw, opmode);
1399 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1400 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1401 if (rtlusb->disableHWSM)
1402 _CardDisableHWSM(hw);
1404 _CardDisableWithoutHWSM(hw);
1406 /* after power off we should do iqk again */
1407 rtlpriv->phy.iqk_initialized = false;
1410 void rtl92cu_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1412 struct rtl_priv *rtlpriv = rtl_priv(hw);
1413 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1416 if (rtlpriv->psc.rfpwr_state != ERFON)
1419 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1423 if (IS_NORMAL_CHIP(rtlhal->version)) {
1424 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1427 reg_rcr |= RCR_CBSSID;
1428 tmp = BIT(4) | BIT(5);
1430 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1432 _rtl92cu_set_bcn_ctrl_reg(hw, 0, tmp);
1435 if (IS_NORMAL_CHIP(rtlhal->version)) {
1436 reg_rcr &= ~(RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1439 reg_rcr &= ~RCR_CBSSID;
1440 tmp = BIT(4) | BIT(5);
1442 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1443 rtlpriv->cfg->ops->set_hw_reg(hw,
1444 HW_VAR_RCR, (u8 *) (®_rcr));
1445 _rtl92cu_set_bcn_ctrl_reg(hw, tmp, 0);
1449 /*========================================================================== */
1451 int rtl92cu_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1453 struct rtl_priv *rtlpriv = rtl_priv(hw);
1455 if (_rtl92cu_set_media_status(hw, type))
1458 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1459 if (type != NL80211_IFTYPE_AP)
1460 rtl92cu_set_check_bssid(hw, true);
1462 rtl92cu_set_check_bssid(hw, false);
1468 static void _beacon_function_enable(struct ieee80211_hw *hw)
1470 struct rtl_priv *rtlpriv = rtl_priv(hw);
1472 _rtl92cu_set_bcn_ctrl_reg(hw, (BIT(4) | BIT(3) | BIT(1)), 0x00);
1473 rtl_write_byte(rtlpriv, REG_RD_CTRL+1, 0x6F);
1476 void rtl92cu_set_beacon_related_registers(struct ieee80211_hw *hw)
1479 struct rtl_priv *rtlpriv = rtl_priv(hw);
1480 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1481 u16 bcn_interval, atim_window;
1484 bcn_interval = mac->beacon_interval;
1485 atim_window = 2; /*FIX MERGE */
1486 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1487 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1488 _rtl92cu_init_beacon_parameters(hw);
1489 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
1491 * Force beacon frame transmission even after receiving beacon frame
1492 * from other ad hoc STA
1495 * Reset TSF Timer to zero, added by Roger. 2008.06.24
1497 value32 = rtl_read_dword(rtlpriv, REG_TCR);
1499 rtl_write_dword(rtlpriv, REG_TCR, value32);
1501 rtl_write_dword(rtlpriv, REG_TCR, value32);
1502 RT_TRACE(rtlpriv, COMP_INIT|COMP_BEACON, DBG_LOUD,
1503 "SetBeaconRelatedRegisters8192CUsb(): Set TCR(%x)\n",
1505 /* TODO: Modify later (Find the right parameters)
1506 * NOTE: Fix test chip's bug (about contention windows's randomness) */
1507 if ((mac->opmode == NL80211_IFTYPE_ADHOC) ||
1508 (mac->opmode == NL80211_IFTYPE_MESH_POINT) ||
1509 (mac->opmode == NL80211_IFTYPE_AP)) {
1510 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x50);
1511 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x50);
1513 _beacon_function_enable(hw);
1516 void rtl92cu_set_beacon_interval(struct ieee80211_hw *hw)
1518 struct rtl_priv *rtlpriv = rtl_priv(hw);
1519 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1520 u16 bcn_interval = mac->beacon_interval;
1522 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG, "beacon_interval:%d\n",
1524 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1527 void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
1528 u32 add_msr, u32 rm_msr)
1532 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1534 struct rtl_priv *rtlpriv = rtl_priv(hw);
1535 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1536 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1540 *((u32 *)(val)) = mac->rx_conf;
1542 case HW_VAR_RF_STATE:
1543 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
1545 case HW_VAR_FWLPS_RF_ON:{
1546 enum rf_pwrstate rfState;
1549 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE,
1551 if (rfState == ERFOFF) {
1552 *((bool *) (val)) = true;
1554 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1555 val_rcr &= 0x00070000;
1557 *((bool *) (val)) = false;
1559 *((bool *) (val)) = true;
1563 case HW_VAR_FW_PSMODE_STATUS:
1564 *((bool *) (val)) = ppsc->fw_current_inpsmode;
1566 case HW_VAR_CORRECT_TSF:{
1568 u32 *ptsf_low = (u32 *)&tsf;
1569 u32 *ptsf_high = ((u32 *)&tsf) + 1;
1571 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
1572 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
1573 *((u64 *)(val)) = tsf;
1576 case HW_VAR_MGT_FILTER:
1577 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP0);
1579 case HW_VAR_CTRL_FILTER:
1580 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP1);
1582 case HW_VAR_DATA_FILTER:
1583 *((u16 *) (val)) = rtl_read_word(rtlpriv, REG_RXFLTMAP2);
1585 case HAL_DEF_WOWLAN:
1588 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1589 "switch case not processed\n");
1594 static bool usb_cmd_send_packet(struct ieee80211_hw *hw, struct sk_buff *skb)
1596 /* Currently nothing happens here.
1597 * Traffic stops after some seconds in WPA2 802.11n mode.
1598 * Maybe because rtl8192cu chip should be set from here?
1599 * If I understand correctly, the realtek vendor driver sends some urbs
1602 * This is maybe necessary:
1603 * rtlpriv->cfg->ops->fill_tx_cmddesc(hw, buffer, 1, 1, skb);
1610 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
1612 struct rtl_priv *rtlpriv = rtl_priv(hw);
1613 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1614 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1615 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1616 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1617 enum wireless_mode wirelessmode = mac->mode;
1621 case HW_VAR_ETHER_ADDR:{
1622 for (idx = 0; idx < ETH_ALEN; idx++) {
1623 rtl_write_byte(rtlpriv, (REG_MACID + idx),
1628 case HW_VAR_BASIC_RATE:{
1629 u16 rate_cfg = ((u16 *) val)[0];
1634 /* if (mac->current_network.vender == HT_IOT_PEER_CISCO
1635 * && ((rate_cfg & 0x150) == 0)) {
1636 * rate_cfg |= 0x010;
1639 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
1640 rtl_write_byte(rtlpriv, REG_RRSR + 1,
1641 (rate_cfg >> 8) & 0xff);
1642 while (rate_cfg > 0x1) {
1646 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
1651 for (idx = 0; idx < ETH_ALEN; idx++) {
1652 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
1658 rtl_write_byte(rtlpriv, REG_SIFS_CCK + 1, val[0]);
1659 rtl_write_byte(rtlpriv, REG_SIFS_OFDM + 1, val[1]);
1660 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
1661 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
1662 rtl_write_byte(rtlpriv, REG_R2T_SIFS+1, val[0]);
1663 rtl_write_byte(rtlpriv, REG_T2T_SIFS+1, val[0]);
1664 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD, "HW_VAR_SIFS\n");
1667 case HW_VAR_SLOT_TIME:{
1671 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
1672 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1673 "HW_VAR_SLOT_TIME %x\n", val[0]);
1675 for (e_aci = 0; e_aci < AC_MAX; e_aci++)
1676 rtlpriv->cfg->ops->set_hw_reg(hw,
1683 if (IS_WIRELESS_MODE_A(wirelessmode) ||
1684 IS_WIRELESS_MODE_N_24G(wirelessmode) ||
1685 IS_WIRELESS_MODE_N_5G(wirelessmode))
1689 u1bAIFS = sifstime + (2 * val[0]);
1690 rtl_write_byte(rtlpriv, REG_EDCA_VO_PARAM,
1692 rtl_write_byte(rtlpriv, REG_EDCA_VI_PARAM,
1694 rtl_write_byte(rtlpriv, REG_EDCA_BE_PARAM,
1696 rtl_write_byte(rtlpriv, REG_EDCA_BK_PARAM,
1701 case HW_VAR_ACK_PREAMBLE:{
1703 u8 short_preamble = (bool)*val;
1707 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
1710 case HW_VAR_AMPDU_MIN_SPACE:{
1711 u8 min_spacing_to_set;
1714 min_spacing_to_set = *val;
1715 if (min_spacing_to_set <= 7) {
1716 switch (rtlpriv->sec.pairwise_enc_algorithm) {
1718 case AESCCMP_ENCRYPTION:
1721 case WEP40_ENCRYPTION:
1722 case WEP104_ENCRYPTION:
1723 case TKIP_ENCRYPTION:
1730 if (min_spacing_to_set < sec_min_space)
1731 min_spacing_to_set = sec_min_space;
1732 mac->min_space_cfg = ((mac->min_space_cfg &
1734 min_spacing_to_set);
1735 *val = min_spacing_to_set;
1736 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1737 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
1738 mac->min_space_cfg);
1739 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1740 mac->min_space_cfg);
1744 case HW_VAR_SHORTGI_DENSITY:{
1747 density_to_set = *val;
1748 density_to_set &= 0x1f;
1749 mac->min_space_cfg &= 0x07;
1750 mac->min_space_cfg |= (density_to_set << 3);
1751 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1752 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
1753 mac->min_space_cfg);
1754 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
1755 mac->min_space_cfg);
1758 case HW_VAR_AMPDU_FACTOR:{
1759 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
1761 u8 *p_regtoset = NULL;
1764 p_regtoset = regtoset_normal;
1765 factor_toset = *val;
1766 if (factor_toset <= 3) {
1767 factor_toset = (1 << (factor_toset + 2));
1768 if (factor_toset > 0xf)
1770 for (index = 0; index < 4; index++) {
1771 if ((p_regtoset[index] & 0xf0) >
1772 (factor_toset << 4))
1774 (p_regtoset[index] & 0x0f)
1775 | (factor_toset << 4);
1776 if ((p_regtoset[index] & 0x0f) >
1779 (p_regtoset[index] & 0xf0)
1781 rtl_write_byte(rtlpriv,
1782 (REG_AGGLEN_LMT + index),
1785 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1786 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
1791 case HW_VAR_AC_PARAM:{
1794 u16 cw_min = le16_to_cpu(mac->ac[e_aci].cw_min);
1795 u16 cw_max = le16_to_cpu(mac->ac[e_aci].cw_max);
1796 u16 tx_op = le16_to_cpu(mac->ac[e_aci].tx_op);
1798 u4b_ac_param = (u32) mac->ac[e_aci].aifs;
1799 u4b_ac_param |= (u32) ((cw_min & 0xF) <<
1800 AC_PARAM_ECW_MIN_OFFSET);
1801 u4b_ac_param |= (u32) ((cw_max & 0xF) <<
1802 AC_PARAM_ECW_MAX_OFFSET);
1803 u4b_ac_param |= (u32) tx_op << AC_PARAM_TXOP_OFFSET;
1804 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
1805 "queue:%x, ac_param:%x\n",
1806 e_aci, u4b_ac_param);
1809 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM,
1813 rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM,
1817 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM,
1821 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM,
1825 RT_ASSERT(false, "invalid aci: %d !\n",
1832 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
1833 mac->rx_conf = ((u32 *) (val))[0];
1834 RT_TRACE(rtlpriv, COMP_RECV, DBG_DMESG,
1835 "### Set RCR(0x%08x) ###\n", mac->rx_conf);
1838 case HW_VAR_RETRY_LIMIT:{
1839 u8 retry_limit = val[0];
1841 rtl_write_word(rtlpriv, REG_RL,
1842 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
1843 retry_limit << RETRY_LIMIT_LONG_SHIFT);
1844 RT_TRACE(rtlpriv, COMP_MLME, DBG_DMESG,
1845 "Set HW_VAR_RETRY_LIMIT(0x%08x)\n",
1849 case HW_VAR_DUAL_TSF_RST:
1850 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
1852 case HW_VAR_EFUSE_BYTES:
1853 rtlefuse->efuse_usedbytes = *((u16 *) val);
1855 case HW_VAR_EFUSE_USAGE:
1856 rtlefuse->efuse_usedpercentage = *val;
1859 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
1861 case HW_VAR_WPA_CONFIG:
1862 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
1864 case HW_VAR_SET_RPWM:{
1865 u8 rpwm_val = rtl_read_byte(rtlpriv, REG_USB_HRPWM);
1867 if (rpwm_val & BIT(7))
1868 rtl_write_byte(rtlpriv, REG_USB_HRPWM, *val);
1870 rtl_write_byte(rtlpriv, REG_USB_HRPWM,
1874 case HW_VAR_H2C_FW_PWRMODE:{
1877 if ((psmode != FW_PS_ACTIVE_MODE) &&
1878 (!IS_92C_SERIAL(rtlhal->version)))
1879 rtl92c_dm_rf_saving(hw, true);
1880 rtl92c_set_fw_pwrmode_cmd(hw, (*val));
1883 case HW_VAR_FW_PSMODE_STATUS:
1884 ppsc->fw_current_inpsmode = *((bool *) val);
1886 case HW_VAR_H2C_FW_JOINBSSRPT:{
1889 bool recover = false;
1891 if (mstatus == RT_MEDIA_CONNECT) {
1892 rtlpriv->cfg->ops->set_hw_reg(hw,
1894 rtl_write_byte(rtlpriv, REG_CR + 1, 0x03);
1895 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1896 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(4), 0);
1897 tmp_reg422 = rtl_read_byte(rtlpriv,
1898 REG_FWHW_TXQ_CTRL + 2);
1899 if (tmp_reg422 & BIT(6))
1901 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
1902 tmp_reg422 & (~BIT(6)));
1903 rtl92c_set_fw_rsvdpagepkt(hw,
1904 &usb_cmd_send_packet);
1905 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1906 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(4));
1908 rtl_write_byte(rtlpriv,
1909 REG_FWHW_TXQ_CTRL + 2,
1910 tmp_reg422 | BIT(6));
1911 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1913 rtl92c_set_fw_joinbss_report_cmd(hw, (*val));
1919 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
1921 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
1922 (u2btmp | mac->assoc_id));
1925 case HW_VAR_CORRECT_TSF:{
1926 u8 btype_ibss = val[0];
1929 _rtl92cu_stop_tx_beacon(hw);
1930 _rtl92cu_set_bcn_ctrl_reg(hw, 0, BIT(3));
1931 rtl_write_dword(rtlpriv, REG_TSFTR, (u32)(mac->tsf &
1933 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
1934 (u32)((mac->tsf >> 32) & 0xffffffff));
1935 _rtl92cu_set_bcn_ctrl_reg(hw, BIT(3), 0);
1937 _rtl92cu_resume_tx_beacon(hw);
1940 case HW_VAR_MGT_FILTER:
1941 rtl_write_word(rtlpriv, REG_RXFLTMAP0, *(u16 *)val);
1942 mac->rx_mgt_filter = *(u16 *)val;
1944 case HW_VAR_CTRL_FILTER:
1945 rtl_write_word(rtlpriv, REG_RXFLTMAP1, *(u16 *)val);
1946 mac->rx_ctrl_filter = *(u16 *)val;
1948 case HW_VAR_DATA_FILTER:
1949 rtl_write_word(rtlpriv, REG_RXFLTMAP2, *(u16 *)val);
1950 mac->rx_data_filter = *(u16 *)val;
1952 case HW_VAR_KEEP_ALIVE:{
1955 array[1] = *((u8 *)val);
1956 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2,
1961 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1962 "switch case not processed\n");
1967 static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
1968 struct ieee80211_sta *sta)
1970 struct rtl_priv *rtlpriv = rtl_priv(hw);
1971 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1972 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1973 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1976 u8 nmode = mac->ht_enable;
1977 u8 mimo_ps = IEEE80211_SMPS_OFF;
1980 u8 curtxbw_40mhz = mac->bw_40;
1981 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1983 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1985 enum wireless_mode wirelessmode = mac->mode;
1987 if (rtlhal->current_bandtype == BAND_ON_5G)
1988 ratr_value = sta->supp_rates[1] << 4;
1990 ratr_value = sta->supp_rates[0];
1991 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1994 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1995 sta->ht_cap.mcs.rx_mask[0] << 12);
1996 switch (wirelessmode) {
1997 case WIRELESS_MODE_B:
1998 if (ratr_value & 0x0000000c)
1999 ratr_value &= 0x0000000d;
2001 ratr_value &= 0x0000000f;
2003 case WIRELESS_MODE_G:
2004 ratr_value &= 0x00000FF5;
2006 case WIRELESS_MODE_N_24G:
2007 case WIRELESS_MODE_N_5G:
2009 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2010 ratr_value &= 0x0007F005;
2014 if (get_rf_type(rtlphy) == RF_1T2R ||
2015 get_rf_type(rtlphy) == RF_1T1R)
2016 ratr_mask = 0x000ff005;
2018 ratr_mask = 0x0f0ff005;
2020 ratr_value &= ratr_mask;
2024 if (rtlphy->rf_type == RF_1T2R)
2025 ratr_value &= 0x000ff0ff;
2027 ratr_value &= 0x0f0ff0ff;
2032 ratr_value &= 0x0FFFFFFF;
2034 if (nmode && ((curtxbw_40mhz &&
2035 curshortgi_40mhz) || (!curtxbw_40mhz &&
2036 curshortgi_20mhz))) {
2038 ratr_value |= 0x10000000;
2039 tmp_ratr_value = (ratr_value >> 12);
2041 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2042 if ((1 << shortgi_rate) & tmp_ratr_value)
2046 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2047 (shortgi_rate << 4) | (shortgi_rate);
2050 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2052 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
2053 rtl_read_dword(rtlpriv, REG_ARFR0));
2056 static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
2057 struct ieee80211_sta *sta,
2060 struct rtl_priv *rtlpriv = rtl_priv(hw);
2061 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2062 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2063 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2064 struct rtl_sta_info *sta_entry = NULL;
2067 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
2068 u8 curshortgi_40mhz = curtxbw_40mhz &&
2069 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2071 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2073 enum wireless_mode wirelessmode = 0;
2074 bool shortgi = false;
2077 u8 mimo_ps = IEEE80211_SMPS_OFF;
2079 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
2080 wirelessmode = sta_entry->wireless_mode;
2081 if (mac->opmode == NL80211_IFTYPE_STATION ||
2082 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2083 curtxbw_40mhz = mac->bw_40;
2084 else if (mac->opmode == NL80211_IFTYPE_AP ||
2085 mac->opmode == NL80211_IFTYPE_ADHOC)
2086 macid = sta->aid + 1;
2088 if (rtlhal->current_bandtype == BAND_ON_5G)
2089 ratr_bitmap = sta->supp_rates[1] << 4;
2091 ratr_bitmap = sta->supp_rates[0];
2092 if (mac->opmode == NL80211_IFTYPE_ADHOC)
2093 ratr_bitmap = 0xfff;
2094 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2095 sta->ht_cap.mcs.rx_mask[0] << 12);
2096 switch (wirelessmode) {
2097 case WIRELESS_MODE_B:
2098 ratr_index = RATR_INX_WIRELESS_B;
2099 if (ratr_bitmap & 0x0000000c)
2100 ratr_bitmap &= 0x0000000d;
2102 ratr_bitmap &= 0x0000000f;
2104 case WIRELESS_MODE_G:
2105 ratr_index = RATR_INX_WIRELESS_GB;
2107 if (rssi_level == 1)
2108 ratr_bitmap &= 0x00000f00;
2109 else if (rssi_level == 2)
2110 ratr_bitmap &= 0x00000ff0;
2112 ratr_bitmap &= 0x00000ff5;
2114 case WIRELESS_MODE_A:
2115 ratr_index = RATR_INX_WIRELESS_A;
2116 ratr_bitmap &= 0x00000ff0;
2118 case WIRELESS_MODE_N_24G:
2119 case WIRELESS_MODE_N_5G:
2120 ratr_index = RATR_INX_WIRELESS_NGB;
2122 if (mimo_ps == IEEE80211_SMPS_STATIC) {
2123 if (rssi_level == 1)
2124 ratr_bitmap &= 0x00070000;
2125 else if (rssi_level == 2)
2126 ratr_bitmap &= 0x0007f000;
2128 ratr_bitmap &= 0x0007f005;
2130 if (rtlphy->rf_type == RF_1T2R ||
2131 rtlphy->rf_type == RF_1T1R) {
2132 if (curtxbw_40mhz) {
2133 if (rssi_level == 1)
2134 ratr_bitmap &= 0x000f0000;
2135 else if (rssi_level == 2)
2136 ratr_bitmap &= 0x000ff000;
2138 ratr_bitmap &= 0x000ff015;
2140 if (rssi_level == 1)
2141 ratr_bitmap &= 0x000f0000;
2142 else if (rssi_level == 2)
2143 ratr_bitmap &= 0x000ff000;
2145 ratr_bitmap &= 0x000ff005;
2148 if (curtxbw_40mhz) {
2149 if (rssi_level == 1)
2150 ratr_bitmap &= 0x0f0f0000;
2151 else if (rssi_level == 2)
2152 ratr_bitmap &= 0x0f0ff000;
2154 ratr_bitmap &= 0x0f0ff015;
2156 if (rssi_level == 1)
2157 ratr_bitmap &= 0x0f0f0000;
2158 else if (rssi_level == 2)
2159 ratr_bitmap &= 0x0f0ff000;
2161 ratr_bitmap &= 0x0f0ff005;
2166 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2167 (!curtxbw_40mhz && curshortgi_20mhz)) {
2171 else if (macid == 1)
2176 ratr_index = RATR_INX_WIRELESS_NGB;
2178 if (rtlphy->rf_type == RF_1T2R)
2179 ratr_bitmap &= 0x000ff0ff;
2181 ratr_bitmap &= 0x0f0ff0ff;
2184 sta_entry->ratr_index = ratr_index;
2186 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2187 "ratr_bitmap :%x\n", ratr_bitmap);
2188 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2190 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2191 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2192 "Rate_index:%x, ratr_val:%x, %5phC\n",
2193 ratr_index, ratr_bitmap, rate_mask);
2194 memcpy(rtlpriv->rate_mask, rate_mask, 5);
2195 /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
2196 * "scheduled while atomic" if called directly */
2197 schedule_work(&rtlpriv->works.fill_h2c_cmd);
2200 sta_entry->ratr_index = ratr_index;
2203 void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
2204 struct ieee80211_sta *sta,
2207 struct rtl_priv *rtlpriv = rtl_priv(hw);
2209 if (rtlpriv->dm.useramask)
2210 rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
2212 rtl92cu_update_hal_rate_table(hw, sta);
2215 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
2217 struct rtl_priv *rtlpriv = rtl_priv(hw);
2218 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2221 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2223 if (!mac->ht_enable)
2224 sifs_timer = 0x0a0a;
2226 sifs_timer = 0x0e0e;
2227 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2230 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid)
2232 struct rtl_priv *rtlpriv = rtl_priv(hw);
2233 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2234 enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2236 bool actuallyset = false;
2237 unsigned long flag = 0;
2238 /* to do - usb autosuspend */
2239 u8 usb_autosuspend = 0;
2241 if (ppsc->swrf_processing)
2243 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2244 if (ppsc->rfchange_inprogress) {
2245 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2248 ppsc->rfchange_inprogress = true;
2249 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2251 cur_rfstate = ppsc->rfpwr_state;
2252 if (usb_autosuspend) {
2253 /* to do................... */
2255 if (ppsc->pwrdown_mode) {
2256 u1tmp = rtl_read_byte(rtlpriv, REG_HSISR);
2257 e_rfpowerstate_toset = (u1tmp & BIT(7)) ?
2259 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2260 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp);
2262 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG,
2263 rtl_read_byte(rtlpriv,
2264 REG_MAC_PINMUX_CFG) & ~(BIT(3)));
2265 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2266 e_rfpowerstate_toset = (u1tmp & BIT(3)) ?
2268 RT_TRACE(rtlpriv, COMP_POWER, DBG_DMESG,
2269 "GPIO_IN=%02x\n", u1tmp);
2271 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD, "N-SS RF =%x\n",
2272 e_rfpowerstate_toset);
2274 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2275 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2276 "GPIOChangeRF - HW Radio ON, RF ON\n");
2277 ppsc->hwradiooff = false;
2279 } else if ((!ppsc->hwradiooff) && (e_rfpowerstate_toset ==
2281 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2282 "GPIOChangeRF - HW Radio OFF\n");
2283 ppsc->hwradiooff = true;
2286 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
2287 "pHalData->bHwRadioOff and eRfPowerStateToSet do not match: pHalData->bHwRadioOff %x, eRfPowerStateToSet %x\n",
2288 ppsc->hwradiooff, e_rfpowerstate_toset);
2291 ppsc->hwradiooff = true;
2292 if (e_rfpowerstate_toset == ERFON) {
2293 if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM) &&
2294 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM))
2295 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2296 else if ((ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2297 && RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3))
2298 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2300 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2301 ppsc->rfchange_inprogress = false;
2302 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2303 /* For power down module, we need to enable register block
2304 * contrl reg at 0x1c. Then enable power down control bit
2305 * of register 0x04 BIT4 and BIT15 as 1.
2307 if (ppsc->pwrdown_mode && e_rfpowerstate_toset == ERFOFF) {
2308 /* Enable register area 0x0-0xc. */
2309 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0);
2310 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x8812);
2312 if (e_rfpowerstate_toset == ERFOFF) {
2313 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2314 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2315 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2316 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2318 } else if (e_rfpowerstate_toset == ERFOFF || cur_rfstate == ERFOFF) {
2319 /* Enter D3 or ASPM after GPIO had been done. */
2320 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_ASPM)
2321 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_ASPM);
2322 else if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_PCI_D3)
2323 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_PCI_D3);
2324 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2325 ppsc->rfchange_inprogress = false;
2326 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2328 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2329 ppsc->rfchange_inprogress = false;
2330 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2333 return !ppsc->hwradiooff;