1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
33 static bool _rtl92ce_phy_rf6052_config_parafile(struct ieee80211_hw *hw);
35 void rtl92ce_phy_rf6052_set_bandwidth(struct ieee80211_hw *hw, u8 bandwidth)
37 struct rtl_priv *rtlpriv = rtl_priv(hw);
38 struct rtl_phy *rtlphy = &(rtlpriv->phy);
41 case HT_CHANNEL_WIDTH_20:
42 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
43 0xfffff3ff) | 0x0400);
44 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
45 rtlphy->rfreg_chnlval[0]);
47 case HT_CHANNEL_WIDTH_20_40:
48 rtlphy->rfreg_chnlval[0] = ((rtlphy->rfreg_chnlval[0] &
50 rtl_set_rfreg(hw, RF90_PATH_A, RF_CHNLBW, RFREG_OFFSET_MASK,
51 rtlphy->rfreg_chnlval[0]);
54 pr_err("unknown bandwidth: %#X\n", bandwidth);
59 void rtl92ce_phy_rf6052_set_cck_txpower(struct ieee80211_hw *hw,
62 struct rtl_priv *rtlpriv = rtl_priv(hw);
63 struct rtl_phy *rtlphy = &(rtlpriv->phy);
64 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
65 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
66 u32 tx_agc[2] = {0, 0}, tmpval;
67 bool turbo_scanoff = false;
71 if (rtlefuse->eeprom_regulatory != 0)
74 if (mac->act_scanning) {
75 tx_agc[RF90_PATH_A] = 0x3f3f3f3f;
76 tx_agc[RF90_PATH_B] = 0x3f3f3f3f;
79 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
80 tx_agc[idx1] = ppowerlevel[idx1] |
81 (ppowerlevel[idx1] << 8) |
82 (ppowerlevel[idx1] << 16) |
83 (ppowerlevel[idx1] << 24);
87 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
88 tx_agc[idx1] = ppowerlevel[idx1] |
89 (ppowerlevel[idx1] << 8) |
90 (ppowerlevel[idx1] << 16) |
91 (ppowerlevel[idx1] << 24);
94 if (rtlefuse->eeprom_regulatory == 0) {
95 tmpval = (rtlphy->mcs_offset[0][6]) +
96 (rtlphy->mcs_offset[0][7] << 8);
97 tx_agc[RF90_PATH_A] += tmpval;
99 tmpval = (rtlphy->mcs_offset[0][14]) +
100 (rtlphy->mcs_offset[0][15] << 24);
101 tx_agc[RF90_PATH_B] += tmpval;
105 for (idx1 = RF90_PATH_A; idx1 <= RF90_PATH_B; idx1++) {
106 ptr = (u8 *) (&(tx_agc[idx1]));
107 for (idx2 = 0; idx2 < 4; idx2++) {
108 if (*ptr > RF6052_MAX_TX_PWR)
109 *ptr = RF6052_MAX_TX_PWR;
114 tmpval = tx_agc[RF90_PATH_A] & 0xff;
115 rtl_set_bbreg(hw, RTXAGC_A_CCK1_MCS32, MASKBYTE1, tmpval);
117 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
118 "CCK PWR 1M (rf-A) = 0x%x (reg 0x%x)\n",
119 tmpval, RTXAGC_A_CCK1_MCS32);
121 tmpval = tx_agc[RF90_PATH_A] >> 8;
123 tmpval = tmpval & 0xff00ffff;
125 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, 0xffffff00, tmpval);
127 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
128 "CCK PWR 2~11M (rf-A) = 0x%x (reg 0x%x)\n",
129 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
131 tmpval = tx_agc[RF90_PATH_B] >> 24;
132 rtl_set_bbreg(hw, RTXAGC_B_CCK11_A_CCK2_11, MASKBYTE0, tmpval);
134 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
135 "CCK PWR 11M (rf-B) = 0x%x (reg 0x%x)\n",
136 tmpval, RTXAGC_B_CCK11_A_CCK2_11);
138 tmpval = tx_agc[RF90_PATH_B] & 0x00ffffff;
139 rtl_set_bbreg(hw, RTXAGC_B_CCK1_55_MCS32, 0xffffff00, tmpval);
141 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
142 "CCK PWR 1~5.5M (rf-B) = 0x%x (reg 0x%x)\n",
143 tmpval, RTXAGC_B_CCK1_55_MCS32);
146 static void rtl92c_phy_get_power_base(struct ieee80211_hw *hw,
147 u8 *ppowerlevel, u8 channel,
148 u32 *ofdmbase, u32 *mcsbase)
150 struct rtl_priv *rtlpriv = rtl_priv(hw);
151 struct rtl_phy *rtlphy = &(rtlpriv->phy);
152 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
153 u32 powerBase0, powerBase1;
154 u8 legacy_pwrdiff, ht20_pwrdiff;
157 for (i = 0; i < 2; i++) {
158 powerlevel[i] = ppowerlevel[i];
159 legacy_pwrdiff = rtlefuse->txpwr_legacyhtdiff[i][channel - 1];
160 powerBase0 = powerlevel[i] + legacy_pwrdiff;
162 powerBase0 = (powerBase0 << 24) | (powerBase0 << 16) |
163 (powerBase0 << 8) | powerBase0;
164 *(ofdmbase + i) = powerBase0;
165 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
166 " [OFDM power base index rf(%c) = 0x%x]\n",
167 i == 0 ? 'A' : 'B', *(ofdmbase + i));
170 for (i = 0; i < 2; i++) {
171 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
172 ht20_pwrdiff = rtlefuse->txpwr_ht20diff[i][channel - 1];
173 powerlevel[i] += ht20_pwrdiff;
175 powerBase1 = powerlevel[i];
176 powerBase1 = (powerBase1 << 24) |
177 (powerBase1 << 16) | (powerBase1 << 8) | powerBase1;
179 *(mcsbase + i) = powerBase1;
181 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
182 " [MCS power base index rf(%c) = 0x%x]\n",
183 i == 0 ? 'A' : 'B', *(mcsbase + i));
187 static void _rtl92c_get_txpower_writeval_by_regulatory(struct ieee80211_hw *hw,
188 u8 channel, u8 index,
193 struct rtl_priv *rtlpriv = rtl_priv(hw);
194 struct rtl_phy *rtlphy = &(rtlpriv->phy);
195 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
196 u8 i, chnlgroup = 0, pwr_diff_limit[4];
197 u32 writeVal, customer_limit, rf;
199 for (rf = 0; rf < 2; rf++) {
200 switch (rtlefuse->eeprom_regulatory) {
204 writeVal = rtlphy->mcs_offset[chnlgroup][index +
206 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
208 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
209 "RTK better performance, writeVal(%c) = 0x%x\n",
210 rf == 0 ? 'A' : 'B', writeVal);
213 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
214 writeVal = ((index < 2) ? powerBase0[rf] :
217 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
218 "Realtek regulatory, 40MHz, writeVal(%c) = 0x%x\n",
219 rf == 0 ? 'A' : 'B', writeVal);
221 if (rtlphy->pwrgroup_cnt == 1)
223 if (rtlphy->pwrgroup_cnt >= 3) {
226 else if (channel >= 4 && channel <= 9)
228 else if (channel > 9)
230 if (rtlphy->pwrgroup_cnt == 4)
234 writeVal = rtlphy->mcs_offset[chnlgroup]
235 [index + (rf ? 8 : 0)] + ((index < 2) ?
239 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
240 "Realtek regulatory, 20MHz, writeVal(%c) = 0x%x\n",
241 rf == 0 ? 'A' : 'B', writeVal);
246 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
248 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
249 "Better regulatory, writeVal(%c) = 0x%x\n",
250 rf == 0 ? 'A' : 'B', writeVal);
255 if (rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20_40) {
256 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
257 "customer's limit, 40MHz rf(%c) = 0x%x\n",
259 rtlefuse->pwrgroup_ht40[rf][channel -
262 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
263 "customer's limit, 20MHz rf(%c) = 0x%x\n",
265 rtlefuse->pwrgroup_ht20[rf][channel -
268 for (i = 0; i < 4; i++) {
269 pwr_diff_limit[i] = (u8) ((rtlphy->mcs_offset
271 (rf ? 8 : 0)] & (0x7f << (i * 8))) >>
274 if (rtlphy->current_chan_bw ==
275 HT_CHANNEL_WIDTH_20_40) {
276 if (pwr_diff_limit[i] >
278 pwrgroup_ht40[rf][channel - 1])
280 rtlefuse->pwrgroup_ht40[rf]
283 if (pwr_diff_limit[i] >
285 pwrgroup_ht20[rf][channel - 1])
287 rtlefuse->pwrgroup_ht20[rf]
292 customer_limit = (pwr_diff_limit[3] << 24) |
293 (pwr_diff_limit[2] << 16) |
294 (pwr_diff_limit[1] << 8) | (pwr_diff_limit[0]);
296 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
297 "Customer's limit rf(%c) = 0x%x\n",
298 rf == 0 ? 'A' : 'B', customer_limit);
300 writeVal = customer_limit +
301 ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
303 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
304 "Customer, writeVal rf(%c)= 0x%x\n",
305 rf == 0 ? 'A' : 'B', writeVal);
309 writeVal = rtlphy->mcs_offset[chnlgroup]
310 [index + (rf ? 8 : 0)]
311 + ((index < 2) ? powerBase0[rf] : powerBase1[rf]);
313 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
314 "RTK better performance, writeVal rf(%c) = 0x%x\n",
315 rf == 0 ? 'A' : 'B', writeVal);
319 if (rtlpriv->dm.dynamic_txhighpower_lvl == TXHIGHPWRLEVEL_BT1)
320 writeVal = writeVal - 0x06060606;
321 else if (rtlpriv->dm.dynamic_txhighpower_lvl ==
323 writeVal = writeVal - 0x0c0c0c0c;
324 *(p_outwriteval + rf) = writeVal;
328 static void _rtl92c_write_ofdm_power_reg(struct ieee80211_hw *hw,
329 u8 index, u32 *pValue)
331 struct rtl_priv *rtlpriv = rtl_priv(hw);
332 struct rtl_phy *rtlphy = &(rtlpriv->phy);
334 u16 regoffset_a[6] = {
335 RTXAGC_A_RATE18_06, RTXAGC_A_RATE54_24,
336 RTXAGC_A_MCS03_MCS00, RTXAGC_A_MCS07_MCS04,
337 RTXAGC_A_MCS11_MCS08, RTXAGC_A_MCS15_MCS12
339 u16 regoffset_b[6] = {
340 RTXAGC_B_RATE18_06, RTXAGC_B_RATE54_24,
341 RTXAGC_B_MCS03_MCS00, RTXAGC_B_MCS07_MCS04,
342 RTXAGC_B_MCS11_MCS08, RTXAGC_B_MCS15_MCS12
344 u8 i, rf, pwr_val[4];
348 for (rf = 0; rf < 2; rf++) {
349 writeVal = pValue[rf];
350 for (i = 0; i < 4; i++) {
351 pwr_val[i] = (u8) ((writeVal & (0x7f <<
352 (i * 8))) >> (i * 8));
354 if (pwr_val[i] > RF6052_MAX_TX_PWR)
355 pwr_val[i] = RF6052_MAX_TX_PWR;
357 writeVal = (pwr_val[3] << 24) | (pwr_val[2] << 16) |
358 (pwr_val[1] << 8) | pwr_val[0];
361 regoffset = regoffset_a[index];
363 regoffset = regoffset_b[index];
364 rtl_set_bbreg(hw, regoffset, MASKDWORD, writeVal);
366 RTPRINT(rtlpriv, FPHY, PHY_TXPWR,
367 "Set 0x%x = %08x\n", regoffset, writeVal);
369 if (((get_rf_type(rtlphy) == RF_2T2R) &&
370 (regoffset == RTXAGC_A_MCS15_MCS12 ||
371 regoffset == RTXAGC_B_MCS15_MCS12)) ||
372 ((get_rf_type(rtlphy) != RF_2T2R) &&
373 (regoffset == RTXAGC_A_MCS07_MCS04 ||
374 regoffset == RTXAGC_B_MCS07_MCS04))) {
376 writeVal = pwr_val[3];
377 if (regoffset == RTXAGC_A_MCS15_MCS12 ||
378 regoffset == RTXAGC_A_MCS07_MCS04)
380 if (regoffset == RTXAGC_B_MCS15_MCS12 ||
381 regoffset == RTXAGC_B_MCS07_MCS04)
384 for (i = 0; i < 3; i++) {
385 writeVal = (writeVal > 6) ? (writeVal - 6) : 0;
386 rtl_write_byte(rtlpriv, (u32) (regoffset + i),
393 void rtl92ce_phy_rf6052_set_ofdm_txpower(struct ieee80211_hw *hw,
394 u8 *ppowerlevel, u8 channel)
396 u32 writeVal[2], powerBase0[2], powerBase1[2];
399 rtl92c_phy_get_power_base(hw, ppowerlevel,
400 channel, &powerBase0[0], &powerBase1[0]);
402 for (index = 0; index < 6; index++) {
403 _rtl92c_get_txpower_writeval_by_regulatory(hw,
409 _rtl92c_write_ofdm_power_reg(hw, index, &writeVal[0]);
413 bool rtl92ce_phy_rf6052_config(struct ieee80211_hw *hw)
415 struct rtl_priv *rtlpriv = rtl_priv(hw);
416 struct rtl_phy *rtlphy = &(rtlpriv->phy);
418 if (rtlphy->rf_type == RF_1T1R)
419 rtlphy->num_total_rfpath = 1;
421 rtlphy->num_total_rfpath = 2;
423 return _rtl92ce_phy_rf6052_config_parafile(hw);
427 static bool _rtl92ce_phy_rf6052_config_parafile(struct ieee80211_hw *hw)
429 struct rtl_priv *rtlpriv = rtl_priv(hw);
430 struct rtl_phy *rtlphy = &(rtlpriv->phy);
433 bool rtstatus = true;
434 struct bb_reg_def *pphyreg;
436 for (rfpath = 0; rfpath < rtlphy->num_total_rfpath; rfpath++) {
438 pphyreg = &rtlphy->phyreg_def[rfpath];
443 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
448 u4_regvalue = rtl_get_bbreg(hw, pphyreg->rfintfs,
453 rtl_set_bbreg(hw, pphyreg->rfintfe, BRFSI_RFENV << 16, 0x1);
456 rtl_set_bbreg(hw, pphyreg->rfintfo, BRFSI_RFENV, 0x1);
459 rtl_set_bbreg(hw, pphyreg->rfhssi_para2,
460 B3WIREADDREAALENGTH, 0x0);
463 rtl_set_bbreg(hw, pphyreg->rfhssi_para2, B3WIREDATALENGTH, 0x0);
468 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
469 (enum radio_path)rfpath);
472 rtstatus = rtl92c_phy_config_rf_with_headerfile(hw,
473 (enum radio_path)rfpath);
484 rtl_set_bbreg(hw, pphyreg->rfintfs,
485 BRFSI_RFENV, u4_regvalue);
489 rtl_set_bbreg(hw, pphyreg->rfintfs,
490 BRFSI_RFENV << 16, u4_regvalue);
495 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
496 "Radio[%d] Fail!!\n", rfpath);
502 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "<---\n");