1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
38 #include "../rtl8192c/phy_common.h"
41 #include "../rtl8192c/dm_common.h"
42 #include "../rtl8192c/fw_common.h"
45 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw);
47 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
48 enum radio_path rfpath, u32 regaddr, u32 bitmask)
50 struct rtl_priv *rtlpriv = rtl_priv(hw);
51 u32 original_value, readback_value, bitshift;
52 struct rtl_phy *rtlphy = &(rtlpriv->phy);
54 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
55 "regaddr(%#x), rfpath(%#x), bitmask(%#x)\n",
56 regaddr, rfpath, bitmask);
58 spin_lock(&rtlpriv->locks.rf_lock);
60 if (rtlphy->rf_mode != RF_OP_BY_FW) {
61 original_value = _rtl92c_phy_rf_serial_read(hw,
64 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
68 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
69 readback_value = (original_value & bitmask) >> bitshift;
71 spin_unlock(&rtlpriv->locks.rf_lock);
73 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
74 "regaddr(%#x), rfpath(%#x), bitmask(%#x), original_value(%#x)\n",
75 regaddr, rfpath, bitmask, original_value);
77 return readback_value;
80 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw)
82 struct rtl_priv *rtlpriv = rtl_priv(hw);
83 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
84 bool is92c = IS_92C_SERIAL(rtlhal->version);
85 bool rtstatus = _rtl92c_phy_config_mac_with_headerfile(hw);
88 rtl_write_byte(rtlpriv, 0x14, 0x71);
90 rtl_write_byte(rtlpriv, 0x04CA, 0x0A);
94 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw)
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 u8 reg_hwparafile = 1;
102 _rtl92c_phy_init_bb_rf_register_definition(hw);
103 regval = rtl_read_word(rtlpriv, REG_SYS_FUNC_EN);
104 rtl_write_word(rtlpriv, REG_SYS_FUNC_EN,
105 regval | BIT(13) | BIT(0) | BIT(1));
106 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x83);
107 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL + 1, 0xdb);
108 rtl_write_byte(rtlpriv, REG_RF_CTRL, RF_EN | RF_RSTB | RF_SDMRSTB);
109 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN,
110 FEN_PPLL | FEN_PCIEA | FEN_DIO_PCIE |
111 FEN_BB_GLB_RSTn | FEN_BBRSTB);
112 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL + 1, 0x80);
113 regvaldw = rtl_read_dword(rtlpriv, REG_LEDCFG0);
114 rtl_write_dword(rtlpriv, REG_LEDCFG0, regvaldw | BIT(23));
115 if (reg_hwparafile == 1)
116 rtstatus = _rtl92c_phy_bb8192c_config_parafile(hw);
120 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw *hw,
121 enum radio_path rfpath,
122 u32 regaddr, u32 bitmask, u32 data)
124 struct rtl_priv *rtlpriv = rtl_priv(hw);
125 struct rtl_phy *rtlphy = &(rtlpriv->phy);
126 u32 original_value, bitshift;
128 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
129 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
130 regaddr, bitmask, data, rfpath);
132 spin_lock(&rtlpriv->locks.rf_lock);
134 if (rtlphy->rf_mode != RF_OP_BY_FW) {
135 if (bitmask != RFREG_OFFSET_MASK) {
136 original_value = _rtl92c_phy_rf_serial_read(hw,
139 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
141 ((original_value & (~bitmask)) |
145 _rtl92c_phy_rf_serial_write(hw, rfpath, regaddr, data);
147 if (bitmask != RFREG_OFFSET_MASK) {
148 original_value = _rtl92c_phy_fw_rf_serial_read(hw,
151 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
153 ((original_value & (~bitmask)) |
156 _rtl92c_phy_fw_rf_serial_write(hw, rfpath, regaddr, data);
159 spin_unlock(&rtlpriv->locks.rf_lock);
161 RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
162 "regaddr(%#x), bitmask(%#x), data(%#x), rfpath(%#x)\n",
163 regaddr, bitmask, data, rfpath);
166 static bool _rtl92c_phy_config_mac_with_headerfile(struct ieee80211_hw *hw)
168 struct rtl_priv *rtlpriv = rtl_priv(hw);
173 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Read Rtl819XMACPHY_Array\n");
174 arraylength = MAC_2T_ARRAYLENGTH;
175 ptrarray = RTL8192CEMAC_2T_ARRAY;
176 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Img:RTL8192CEMAC_2T_ARRAY\n");
177 for (i = 0; i < arraylength; i = i + 2)
178 rtl_write_byte(rtlpriv, ptrarray[i], (u8) ptrarray[i + 1]);
182 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw *hw,
186 u32 *phy_regarray_table;
187 u32 *agctab_array_table;
188 u16 phy_reg_arraylen, agctab_arraylen;
189 struct rtl_priv *rtlpriv = rtl_priv(hw);
190 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
192 if (IS_92C_SERIAL(rtlhal->version)) {
193 agctab_arraylen = AGCTAB_2TARRAYLENGTH;
194 agctab_array_table = RTL8192CEAGCTAB_2TARRAY;
195 phy_reg_arraylen = PHY_REG_2TARRAY_LENGTH;
196 phy_regarray_table = RTL8192CEPHY_REG_2TARRAY;
198 agctab_arraylen = AGCTAB_1TARRAYLENGTH;
199 agctab_array_table = RTL8192CEAGCTAB_1TARRAY;
200 phy_reg_arraylen = PHY_REG_1TARRAY_LENGTH;
201 phy_regarray_table = RTL8192CEPHY_REG_1TARRAY;
203 if (configtype == BASEBAND_CONFIG_PHY_REG) {
204 for (i = 0; i < phy_reg_arraylen; i = i + 2) {
205 rtl_addr_delay(phy_regarray_table[i]);
206 rtl_set_bbreg(hw, phy_regarray_table[i], MASKDWORD,
207 phy_regarray_table[i + 1]);
209 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
210 "The phy_regarray_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
211 phy_regarray_table[i],
212 phy_regarray_table[i + 1]);
214 } else if (configtype == BASEBAND_CONFIG_AGC_TAB) {
215 for (i = 0; i < agctab_arraylen; i = i + 2) {
216 rtl_set_bbreg(hw, agctab_array_table[i], MASKDWORD,
217 agctab_array_table[i + 1]);
219 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
220 "The agctab_array_table[0] is %x Rtl819XPHY_REGArray[1] is %x\n",
221 agctab_array_table[i],
222 agctab_array_table[i + 1]);
228 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw *hw,
231 struct rtl_priv *rtlpriv = rtl_priv(hw);
233 u32 *phy_regarray_table_pg;
234 u16 phy_regarray_pg_len;
236 phy_regarray_pg_len = PHY_REG_ARRAY_PGLENGTH;
237 phy_regarray_table_pg = RTL8192CEPHY_REG_ARRAY_PG;
239 if (configtype == BASEBAND_CONFIG_PHY_REG) {
240 for (i = 0; i < phy_regarray_pg_len; i = i + 3) {
241 rtl_addr_delay(phy_regarray_table_pg[i]);
243 _rtl92c_store_pwrIndex_diffrate_offset(hw,
244 phy_regarray_table_pg[i],
245 phy_regarray_table_pg[i + 1],
246 phy_regarray_table_pg[i + 2]);
250 RT_TRACE(rtlpriv, COMP_SEND, DBG_TRACE,
251 "configtype != BaseBand_Config_PHY_REG\n");
256 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
257 enum radio_path rfpath)
261 u32 *radioa_array_table;
262 u32 *radiob_array_table;
263 u16 radioa_arraylen, radiob_arraylen;
264 struct rtl_priv *rtlpriv = rtl_priv(hw);
265 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
267 if (IS_92C_SERIAL(rtlhal->version)) {
268 radioa_arraylen = RADIOA_2TARRAYLENGTH;
269 radioa_array_table = RTL8192CERADIOA_2TARRAY;
270 radiob_arraylen = RADIOB_2TARRAYLENGTH;
271 radiob_array_table = RTL8192CE_RADIOB_2TARRAY;
272 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
273 "Radio_A:RTL8192CERADIOA_2TARRAY\n");
274 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
275 "Radio_B:RTL8192CE_RADIOB_2TARRAY\n");
277 radioa_arraylen = RADIOA_1TARRAYLENGTH;
278 radioa_array_table = RTL8192CE_RADIOA_1TARRAY;
279 radiob_arraylen = RADIOB_1TARRAYLENGTH;
280 radiob_array_table = RTL8192CE_RADIOB_1TARRAY;
281 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
282 "Radio_A:RTL8192CE_RADIOA_1TARRAY\n");
283 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
284 "Radio_B:RTL8192CE_RADIOB_1TARRAY\n");
286 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Radio No %x\n", rfpath);
289 for (i = 0; i < radioa_arraylen; i = i + 2) {
290 rtl_rfreg_delay(hw, rfpath, radioa_array_table[i],
292 radioa_array_table[i + 1]);
296 for (i = 0; i < radiob_arraylen; i = i + 2) {
297 rtl_rfreg_delay(hw, rfpath, radiob_array_table[i],
299 radiob_array_table[i + 1]);
304 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
305 "switch case %#x not processed\n", rfpath);
313 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw *hw)
315 struct rtl_priv *rtlpriv = rtl_priv(hw);
316 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
317 struct rtl_phy *rtlphy = &(rtlpriv->phy);
318 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
322 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "Switch to %s bandwidth\n",
323 rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20 ?
326 if (is_hal_stop(rtlhal)) {
327 rtlphy->set_bwmode_inprogress = false;
331 reg_bw_opmode = rtl_read_byte(rtlpriv, REG_BWOPMODE);
332 reg_prsr_rsc = rtl_read_byte(rtlpriv, REG_RRSR + 2);
334 switch (rtlphy->current_chan_bw) {
335 case HT_CHANNEL_WIDTH_20:
336 reg_bw_opmode |= BW_OPMODE_20MHZ;
337 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
339 case HT_CHANNEL_WIDTH_20_40:
340 reg_bw_opmode &= ~BW_OPMODE_20MHZ;
341 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
343 (reg_prsr_rsc & 0x90) | (mac->cur_40_prime_sc << 5);
344 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_prsr_rsc);
347 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
348 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
352 switch (rtlphy->current_chan_bw) {
353 case HT_CHANNEL_WIDTH_20:
354 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x0);
355 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x0);
356 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
358 case HT_CHANNEL_WIDTH_20_40:
359 rtl_set_bbreg(hw, RFPGA0_RFMOD, BRFMOD, 0x1);
360 rtl_set_bbreg(hw, RFPGA1_RFMOD, BRFMOD, 0x1);
362 rtl_set_bbreg(hw, RCCK0_SYSTEM, BCCK_SIDEBAND,
363 (mac->cur_40_prime_sc >> 1));
364 rtl_set_bbreg(hw, ROFDM1_LSTF, 0xC00, mac->cur_40_prime_sc);
365 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 0);
367 rtl_set_bbreg(hw, 0x818, (BIT(26) | BIT(27)),
368 (mac->cur_40_prime_sc ==
369 HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
372 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
373 "unknown bandwidth: %#X\n", rtlphy->current_chan_bw);
376 rtl92ce_phy_rf6052_set_bandwidth(hw, rtlphy->current_chan_bw);
377 rtlphy->set_bwmode_inprogress = false;
378 RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "<==\n");
381 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw *hw, bool is2t)
384 u32 rf_a_mode = 0, rf_b_mode = 0, lc_cal;
385 struct rtl_priv *rtlpriv = rtl_priv(hw);
387 tmpreg = rtl_read_byte(rtlpriv, 0xd03);
389 if ((tmpreg & 0x70) != 0)
390 rtl_write_byte(rtlpriv, 0xd03, tmpreg & 0x8F);
392 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
394 if ((tmpreg & 0x70) != 0) {
395 rf_a_mode = rtl_get_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS);
398 rf_b_mode = rtl_get_rfreg(hw, RF90_PATH_B, 0x00,
401 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS,
402 (rf_a_mode & 0x8FFFF) | 0x10000);
405 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
406 (rf_b_mode & 0x8FFFF) | 0x10000);
408 lc_cal = rtl_get_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS);
410 rtl_set_rfreg(hw, RF90_PATH_A, 0x18, MASK12BITS, lc_cal | 0x08000);
414 if ((tmpreg & 0x70) != 0) {
415 rtl_write_byte(rtlpriv, 0xd03, tmpreg);
416 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, MASK12BITS, rf_a_mode);
419 rtl_set_rfreg(hw, RF90_PATH_B, 0x00, MASK12BITS,
422 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
426 static void _rtl92ce_phy_set_rf_sleep(struct ieee80211_hw *hw)
430 struct rtl_priv *rtlpriv = rtl_priv(hw);
432 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
433 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
434 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
435 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
436 while (u4b_tmp != 0 && delay > 0) {
437 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
438 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
439 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
440 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
444 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
445 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
446 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
447 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
448 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
449 "Switch RF timeout !!!\n");
452 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
453 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
456 static bool _rtl92ce_phy_set_rf_power_state(struct ieee80211_hw *hw,
457 enum rf_pwrstate rfpwr_state)
459 struct rtl_priv *rtlpriv = rtl_priv(hw);
460 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
461 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
462 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
465 struct rtl8192_tx_ring *ring = NULL;
467 switch (rfpwr_state) {
469 if ((ppsc->rfpwr_state == ERFOFF) &&
470 RT_IN_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC)) {
472 u32 InitializeCount = 0;
475 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
476 "IPS Set eRf nic enable\n");
477 rtstatus = rtl_ps_enable_nic(hw);
478 } while (!rtstatus && (InitializeCount < 10));
479 RT_CLEAR_PS_LEVEL(ppsc,
480 RT_RF_OFF_LEVL_HALT_NIC);
482 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
483 "Set ERFON sleeped:%d ms\n",
484 jiffies_to_msecs(jiffies -
486 last_sleep_jiffies));
487 ppsc->last_awake_jiffies = jiffies;
488 rtl92ce_phy_set_rf_on(hw);
490 if (mac->link_state == MAC80211_LINKED) {
491 rtlpriv->cfg->ops->led_control(hw,
494 rtlpriv->cfg->ops->led_control(hw,
500 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC) {
501 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
502 "IPS Set eRf nic disable\n");
503 rtl_ps_disable_nic(hw);
504 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
506 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS) {
507 rtlpriv->cfg->ops->led_control(hw,
510 rtlpriv->cfg->ops->led_control(hw,
517 if (ppsc->rfpwr_state == ERFOFF)
519 for (queue_id = 0, i = 0;
520 queue_id < RTL_PCI_MAX_TX_QUEUE_COUNT;) {
521 ring = &pcipriv->dev.tx_ring[queue_id];
522 if (queue_id == BEACON_QUEUE ||
523 skb_queue_len(&ring->queue) == 0) {
527 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
528 "eRf Off/Sleep: %d times TcbBusyQueue[%d] =%d before doze!\n",
530 skb_queue_len(&ring->queue));
535 if (i >= MAX_DOZE_WAITING_TIMES_9x) {
536 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
537 "ERFSLEEP: %d times TcbBusyQueue[%d] = %d !\n",
538 MAX_DOZE_WAITING_TIMES_9x,
540 skb_queue_len(&ring->queue));
544 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
545 "Set ERFSLEEP awaked:%d ms\n",
546 jiffies_to_msecs(jiffies -
547 ppsc->last_awake_jiffies));
548 ppsc->last_sleep_jiffies = jiffies;
549 _rtl92ce_phy_set_rf_sleep(hw);
553 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
554 "switch case %#x not processed\n", rfpwr_state);
559 ppsc->rfpwr_state = rfpwr_state;
563 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
564 enum rf_pwrstate rfpwr_state)
566 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
568 bool bresult = false;
570 if (rfpwr_state == ppsc->rfpwr_state)
572 bresult = _rtl92ce_phy_set_rf_power_state(hw, rfpwr_state);