1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
40 #include "../rtl8192c/dm_common.h"
41 #include "../rtl8192c/fw_common.h"
42 #include "../rtl8192c/phy_common.h"
49 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
50 u8 set_bits, u8 clear_bits)
52 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
53 struct rtl_priv *rtlpriv = rtl_priv(hw);
55 rtlpci->reg_bcn_ctrl_val |= set_bits;
56 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
58 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8)rtlpci->reg_bcn_ctrl_val);
61 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
63 struct rtl_priv *rtlpriv = rtl_priv(hw);
66 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
67 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
68 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
69 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
70 tmp1byte &= ~(BIT(0));
71 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
74 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
76 struct rtl_priv *rtlpriv = rtl_priv(hw);
79 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
80 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
81 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
82 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
84 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
87 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
89 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
92 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
94 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
97 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
99 struct rtl_priv *rtlpriv = rtl_priv(hw);
100 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
101 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
105 *((u32 *) (val)) = rtlpci->receive_config;
107 case HW_VAR_RF_STATE:
108 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
110 case HW_VAR_FWLPS_RF_ON:{
111 enum rf_pwrstate rfState;
114 rtlpriv->cfg->ops->get_hw_reg(hw,
117 if (rfState == ERFOFF) {
118 *((bool *) (val)) = true;
120 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
121 val_rcr &= 0x00070000;
123 *((bool *) (val)) = false;
125 *((bool *) (val)) = true;
129 case HW_VAR_FW_PSMODE_STATUS:
130 *((bool *) (val)) = ppsc->fw_current_inpsmode;
132 case HW_VAR_CORRECT_TSF:{
134 u32 *ptsf_low = (u32 *)&tsf;
135 u32 *ptsf_high = ((u32 *)&tsf) + 1;
137 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
138 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
140 *((u64 *) (val)) = tsf;
147 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
148 "switch case %#x not processed\n", variable);
153 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
155 struct rtl_priv *rtlpriv = rtl_priv(hw);
156 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
157 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
158 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
159 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
160 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
161 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
165 case HW_VAR_ETHER_ADDR:{
166 for (idx = 0; idx < ETH_ALEN; idx++) {
167 rtl_write_byte(rtlpriv, (REG_MACID + idx),
172 case HW_VAR_BASIC_RATE:{
173 u16 rate_cfg = ((u16 *) val)[0];
177 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
178 rtl_write_byte(rtlpriv, REG_RRSR + 1,
179 (rate_cfg >> 8) & 0xff);
180 while (rate_cfg > 0x1) {
181 rate_cfg = (rate_cfg >> 1);
184 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
189 for (idx = 0; idx < ETH_ALEN; idx++) {
190 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
196 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
197 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
199 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
200 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
203 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
206 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
210 case HW_VAR_SLOT_TIME:{
213 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
214 "HW_VAR_SLOT_TIME %x\n", val[0]);
216 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
218 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
219 rtlpriv->cfg->ops->set_hw_reg(hw,
225 case HW_VAR_ACK_PREAMBLE:{
227 u8 short_preamble = (bool)*val;
228 reg_tmp = (mac->cur_40_prime_sc) << 5;
232 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
235 case HW_VAR_AMPDU_MIN_SPACE:{
236 u8 min_spacing_to_set;
239 min_spacing_to_set = *val;
240 if (min_spacing_to_set <= 7) {
243 if (min_spacing_to_set < sec_min_space)
244 min_spacing_to_set = sec_min_space;
246 mac->min_space_cfg = ((mac->min_space_cfg &
250 *val = min_spacing_to_set;
252 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
253 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
256 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
261 case HW_VAR_SHORTGI_DENSITY:{
264 density_to_set = *val;
265 mac->min_space_cfg |= (density_to_set << 3);
267 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
268 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
271 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
276 case HW_VAR_AMPDU_FACTOR:{
277 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
278 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
281 u8 *p_regtoset = NULL;
284 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
285 (rtlpcipriv->bt_coexist.bt_coexist_type ==
287 p_regtoset = regtoset_bt;
289 p_regtoset = regtoset_normal;
291 factor_toset = *(val);
292 if (factor_toset <= 3) {
293 factor_toset = (1 << (factor_toset + 2));
294 if (factor_toset > 0xf)
297 for (index = 0; index < 4; index++) {
298 if ((p_regtoset[index] & 0xf0) >
301 (p_regtoset[index] & 0x0f) |
304 if ((p_regtoset[index] & 0x0f) >
307 (p_regtoset[index] & 0xf0) |
310 rtl_write_byte(rtlpriv,
311 (REG_AGGLEN_LMT + index),
316 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
317 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
322 case HW_VAR_AC_PARAM:{
324 rtl92c_dm_init_edca_turbo(hw);
326 if (rtlpci->acm_method != EACMWAY2_SW)
327 rtlpriv->cfg->ops->set_hw_reg(hw,
332 case HW_VAR_ACM_CTRL:{
334 union aci_aifsn *p_aci_aifsn =
335 (union aci_aifsn *)(&(mac->ac[0].aifs));
336 u8 acm = p_aci_aifsn->f.acm;
337 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
340 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
345 acm_ctrl |= AcmHw_BeqEn;
348 acm_ctrl |= AcmHw_ViqEn;
351 acm_ctrl |= AcmHw_VoqEn;
354 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
355 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
362 acm_ctrl &= (~AcmHw_BeqEn);
365 acm_ctrl &= (~AcmHw_ViqEn);
368 acm_ctrl &= (~AcmHw_VoqEn);
371 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
372 "switch case %#x not processed\n",
378 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
379 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
381 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
385 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
386 rtlpci->receive_config = ((u32 *) (val))[0];
389 case HW_VAR_RETRY_LIMIT:{
390 u8 retry_limit = val[0];
392 rtl_write_word(rtlpriv, REG_RL,
393 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
394 retry_limit << RETRY_LIMIT_LONG_SHIFT);
397 case HW_VAR_DUAL_TSF_RST:
398 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
400 case HW_VAR_EFUSE_BYTES:
401 rtlefuse->efuse_usedbytes = *((u16 *) val);
403 case HW_VAR_EFUSE_USAGE:
404 rtlefuse->efuse_usedpercentage = *val;
407 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
409 case HW_VAR_WPA_CONFIG:
410 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
412 case HW_VAR_SET_RPWM:{
415 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
418 if (rpwm_val & BIT(7)) {
419 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
421 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
427 case HW_VAR_H2C_FW_PWRMODE:{
430 if ((psmode != FW_PS_ACTIVE_MODE) &&
431 (!IS_92C_SERIAL(rtlhal->version))) {
432 rtl92c_dm_rf_saving(hw, true);
435 rtl92c_set_fw_pwrmode_cmd(hw, *val);
438 case HW_VAR_FW_PSMODE_STATUS:
439 ppsc->fw_current_inpsmode = *((bool *) val);
441 case HW_VAR_H2C_FW_JOINBSSRPT:{
443 u8 tmp_regcr, tmp_reg422;
444 bool recover = false;
446 if (mstatus == RT_MEDIA_CONNECT) {
447 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
450 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
451 rtl_write_byte(rtlpriv, REG_CR + 1,
452 (tmp_regcr | BIT(0)));
454 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
455 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
458 rtl_read_byte(rtlpriv,
459 REG_FWHW_TXQ_CTRL + 2);
460 if (tmp_reg422 & BIT(6))
462 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
463 tmp_reg422 & (~BIT(6)));
465 rtl92c_set_fw_rsvdpagepkt(hw, NULL);
467 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
468 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
471 rtl_write_byte(rtlpriv,
472 REG_FWHW_TXQ_CTRL + 2,
476 rtl_write_byte(rtlpriv, REG_CR + 1,
477 (tmp_regcr & ~(BIT(0))));
479 rtl92c_set_fw_joinbss_report_cmd(hw, *val);
483 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
484 rtl92c_set_p2p_ps_offload_cmd(hw, *val);
488 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
490 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
495 case HW_VAR_CORRECT_TSF:{
496 u8 btype_ibss = val[0];
499 _rtl92ce_stop_tx_beacon(hw);
501 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
503 rtl_write_dword(rtlpriv, REG_TSFTR,
504 (u32) (mac->tsf & 0xffffffff));
505 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
506 (u32) ((mac->tsf >> 32) & 0xffffffff));
508 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
511 _rtl92ce_resume_tx_beacon(hw);
516 case HW_VAR_FW_LPS_ACTION: {
517 bool enter_fwlps = *((bool *)val);
518 u8 rpwm_val, fw_pwrmode;
519 bool fw_current_inps;
522 rpwm_val = 0x02; /* RF off */
523 fw_current_inps = true;
524 rtlpriv->cfg->ops->set_hw_reg(hw,
525 HW_VAR_FW_PSMODE_STATUS,
526 (u8 *)(&fw_current_inps));
527 rtlpriv->cfg->ops->set_hw_reg(hw,
528 HW_VAR_H2C_FW_PWRMODE,
529 &ppsc->fwctrl_psmode);
531 rtlpriv->cfg->ops->set_hw_reg(hw,
535 rpwm_val = 0x0C; /* RF on */
536 fw_pwrmode = FW_PS_ACTIVE_MODE;
537 fw_current_inps = false;
538 rtlpriv->cfg->ops->set_hw_reg(hw,
541 rtlpriv->cfg->ops->set_hw_reg(hw,
542 HW_VAR_H2C_FW_PWRMODE,
545 rtlpriv->cfg->ops->set_hw_reg(hw,
546 HW_VAR_FW_PSMODE_STATUS,
547 (u8 *)(&fw_current_inps));
550 case HW_VAR_KEEP_ALIVE: {
554 array[1] = *((u8 *)val);
555 rtl92c_fill_h2c_cmd(hw, H2C_92C_KEEP_ALIVE_CTRL, 2, array);
558 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
559 "switch case %d not processed\n", variable);
564 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
566 struct rtl_priv *rtlpriv = rtl_priv(hw);
569 u32 value = _LLT_INIT_ADDR(address) |
570 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
572 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
575 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
576 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
579 if (count > POLLING_LLT_THRESHOLD) {
580 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
581 "Failed to polling write LLT done at address %d!\n",
591 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
593 struct rtl_priv *rtlpriv = rtl_priv(hw);
602 #elif LLT_CONFIG == 2
605 #elif LLT_CONFIG == 3
608 #elif LLT_CONFIG == 4
611 #elif LLT_CONFIG == 5
617 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
618 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
619 #elif LLT_CONFIG == 2
620 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
621 #elif LLT_CONFIG == 3
622 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
623 #elif LLT_CONFIG == 4
624 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
625 #elif LLT_CONFIG == 5
626 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
628 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
631 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
632 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
634 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
635 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
637 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
638 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
639 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
641 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
642 status = _rtl92ce_llt_write(hw, i, i + 1);
647 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
651 for (i = txpktbuf_bndy; i < maxPage; i++) {
652 status = _rtl92ce_llt_write(hw, i, (i + 1));
657 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
664 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
666 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
667 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
668 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
669 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
671 if (rtlpci->up_first_time)
674 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
675 rtl92ce_sw_led_on(hw, pLed0);
676 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
677 rtl92ce_sw_led_on(hw, pLed0);
679 rtl92ce_sw_led_off(hw, pLed0);
682 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
684 struct rtl_priv *rtlpriv = rtl_priv(hw);
685 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
686 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
687 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
689 unsigned char bytetmp;
690 unsigned short wordtmp;
693 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
694 if (rtlpcipriv->bt_coexist.bt_coexistence) {
696 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
697 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
698 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
700 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
701 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
703 if (rtlpcipriv->bt_coexist.bt_coexistence) {
704 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
706 u4b_tmp &= (~0x00024800);
707 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
710 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
713 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
716 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
720 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
721 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
723 while ((bytetmp & BIT(0)) && retry < 1000) {
726 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
727 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
728 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
732 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
734 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
737 if (rtlpcipriv->bt_coexist.bt_coexistence) {
738 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
739 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
742 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
744 if (!_rtl92ce_llt_table_init(hw))
747 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
748 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
750 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
752 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
755 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
757 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
758 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
759 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
761 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
763 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
764 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
766 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
767 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
769 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
770 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
771 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
772 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
773 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
774 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
775 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
776 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
777 rtl_write_dword(rtlpriv, REG_HQ_DESA,
778 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
780 rtl_write_dword(rtlpriv, REG_RX_DESA,
781 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
784 if (IS_92C_SERIAL(rtlhal->version))
785 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
787 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
789 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
791 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
792 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
795 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
796 } while ((retry < 200) && (bytetmp & BIT(7)));
798 _rtl92ce_gen_refresh_led_state(hw);
800 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
805 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
807 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
808 struct rtl_priv *rtlpriv = rtl_priv(hw);
809 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
813 reg_bw_opmode = BW_OPMODE_20MHZ;
814 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
816 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
818 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
820 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
822 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
824 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
826 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
828 rtl_write_word(rtlpriv, REG_RL, 0x0707);
830 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
832 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
834 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
835 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
836 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
837 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
839 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
840 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
841 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
843 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
845 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
847 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
849 rtlpci->reg_bcn_ctrl_val = 0x1f;
850 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
852 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
854 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
856 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
857 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
859 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
860 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
861 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
862 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
864 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
865 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
868 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
869 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
870 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
872 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
874 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
876 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
877 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
879 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
881 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
883 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
884 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
888 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
890 struct rtl_priv *rtlpriv = rtl_priv(hw);
891 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
893 rtl_write_byte(rtlpriv, 0x34b, 0x93);
894 rtl_write_word(rtlpriv, 0x350, 0x870c);
895 rtl_write_byte(rtlpriv, 0x352, 0x1);
897 if (ppsc->support_backdoor)
898 rtl_write_byte(rtlpriv, 0x349, 0x1b);
900 rtl_write_byte(rtlpriv, 0x349, 0x03);
902 rtl_write_word(rtlpriv, 0x350, 0x2718);
903 rtl_write_byte(rtlpriv, 0x352, 0x1);
906 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
908 struct rtl_priv *rtlpriv = rtl_priv(hw);
911 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
912 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
913 rtlpriv->sec.pairwise_enc_algorithm,
914 rtlpriv->sec.group_enc_algorithm);
916 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
917 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
918 "not open hw encryption\n");
922 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
924 if (rtlpriv->sec.use_defaultkey) {
925 sec_reg_value |= SCR_TxUseDK;
926 sec_reg_value |= SCR_RxUseDK;
929 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
931 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
933 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
934 "The SECR-value %x\n", sec_reg_value);
936 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
940 int rtl92ce_hw_init(struct ieee80211_hw *hw)
942 struct rtl_priv *rtlpriv = rtl_priv(hw);
943 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
944 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
945 struct rtl_phy *rtlphy = &(rtlpriv->phy);
946 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
947 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
948 bool rtstatus = true;
954 rtlpci->being_init_adapter = true;
956 /* Since this function can take a very long time (up to 350 ms)
957 * and can be called with irqs disabled, reenable the irqs
958 * to let the other devices continue being serviced.
960 * It is safe doing so since our own interrupts will only be enabled
961 * in a subsequent step.
963 local_save_flags(flags);
966 rtlhal->fw_ready = false;
967 rtlpriv->intf_ops->disable_aspm(hw);
968 rtstatus = _rtl92ce_init_mac(hw);
970 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
975 err = rtl92c_download_fw(hw);
977 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
978 "Failed to download FW. Init HW without FW now..\n");
983 rtlhal->fw_ready = true;
984 rtlhal->last_hmeboxnum = 0;
985 rtl92c_phy_mac_config(hw);
986 /* because last function modify RCR, so we update
987 * rcr var here, or TP will unstable for receive_config
988 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
989 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
990 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
991 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
992 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
993 rtl92c_phy_bb_config(hw);
994 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
995 rtl92c_phy_rf_config(hw);
996 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
997 !IS_92C_SERIAL(rtlhal->version)) {
998 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
999 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
1000 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
1001 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
1002 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
1003 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
1004 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
1005 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
1006 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
1008 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1009 RF_CHNLBW, RFREG_OFFSET_MASK);
1010 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
1011 RF_CHNLBW, RFREG_OFFSET_MASK);
1012 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1013 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1014 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
1015 _rtl92ce_hw_configure(hw);
1016 rtl_cam_reset_all_entry(hw);
1017 rtl92ce_enable_hw_security_config(hw);
1019 ppsc->rfpwr_state = ERFON;
1021 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1022 _rtl92ce_enable_aspm_back_door(hw);
1023 rtlpriv->intf_ops->enable_aspm(hw);
1025 rtl8192ce_bt_hw_init(hw);
1027 if (ppsc->rfpwr_state == ERFON) {
1028 rtl92c_phy_set_rfpath_switch(hw, 1);
1029 if (rtlphy->iqk_initialized) {
1030 rtl92c_phy_iq_calibrate(hw, true);
1032 rtl92c_phy_iq_calibrate(hw, false);
1033 rtlphy->iqk_initialized = true;
1036 rtl92c_dm_check_txpower_tracking(hw);
1037 rtl92c_phy_lc_calibrate(hw);
1040 is92c = IS_92C_SERIAL(rtlhal->version);
1041 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1042 if (!(tmp_u1b & BIT(0))) {
1043 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1044 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1047 if (!(tmp_u1b & BIT(1)) && is92c) {
1048 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1049 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1052 if (!(tmp_u1b & BIT(4))) {
1053 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1055 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1057 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1058 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1062 local_irq_restore(flags);
1063 rtlpci->being_init_adapter = false;
1067 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1069 struct rtl_priv *rtlpriv = rtl_priv(hw);
1070 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1071 enum version_8192c version = VERSION_UNKNOWN;
1073 const char *versionid;
1075 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1076 if (value32 & TRP_VAUX_EN) {
1077 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1080 version = (enum version_8192c) (CHIP_VER_B |
1081 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1082 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1083 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1084 CHIP_VER_RTL_MASK)) {
1085 version = (enum version_8192c)(version |
1086 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1087 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1090 if (IS_92C_SERIAL(version)) {
1091 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1092 version = (enum version_8192c)(version |
1093 ((CHIP_BONDING_IDENTIFIER(value32)
1094 == CHIP_BONDING_92C_1T2R) ?
1100 case VERSION_B_CHIP_92C:
1101 versionid = "B_CHIP_92C";
1103 case VERSION_B_CHIP_88C:
1104 versionid = "B_CHIP_88C";
1106 case VERSION_A_CHIP_92C:
1107 versionid = "A_CHIP_92C";
1109 case VERSION_A_CHIP_88C:
1110 versionid = "A_CHIP_88C";
1112 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1113 versionid = "A_CUT_92C_1T2R";
1115 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1116 versionid = "A_CUT_92C";
1118 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1119 versionid = "A_CUT_88C";
1121 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1122 versionid = "B_CUT_92C_1T2R";
1124 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1125 versionid = "B_CUT_92C";
1127 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1128 versionid = "B_CUT_88C";
1131 versionid = "Unknown. Bug?";
1135 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1136 "Chip Version ID: %s\n", versionid);
1138 switch (version & 0x3) {
1140 rtlphy->rf_type = RF_1T1R;
1143 rtlphy->rf_type = RF_2T2R;
1146 rtlphy->rf_type = RF_1T2R;
1149 rtlphy->rf_type = RF_1T1R;
1150 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1151 "ERROR RF_Type is set!!\n");
1155 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1156 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1161 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1162 enum nl80211_iftype type)
1164 struct rtl_priv *rtlpriv = rtl_priv(hw);
1165 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1166 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1167 u8 mode = MSR_NOLINK;
1172 case NL80211_IFTYPE_UNSPECIFIED:
1174 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1175 "Set Network type to NO LINK!\n");
1177 case NL80211_IFTYPE_ADHOC:
1179 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1180 "Set Network type to Ad Hoc!\n");
1182 case NL80211_IFTYPE_STATION:
1184 ledaction = LED_CTL_LINK;
1185 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1186 "Set Network type to STA!\n");
1188 case NL80211_IFTYPE_AP:
1190 ledaction = LED_CTL_LINK;
1191 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1192 "Set Network type to AP!\n");
1194 case NL80211_IFTYPE_MESH_POINT:
1196 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1197 "Set Network type to Mesh Point!\n");
1200 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1201 "Network type %d not supported!\n", type);
1206 /* MSR_INFRA == Link in infrastructure network;
1207 * MSR_ADHOC == Link in ad hoc network;
1208 * Therefore, check link state is necessary.
1210 * MSR_AP == AP mode; link state does not matter here.
1212 if (mode != MSR_AP &&
1213 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1215 ledaction = LED_CTL_NO_LINK;
1217 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1218 _rtl92ce_stop_tx_beacon(hw);
1219 _rtl92ce_enable_bcn_sub_func(hw);
1220 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1221 _rtl92ce_resume_tx_beacon(hw);
1222 _rtl92ce_disable_bcn_sub_func(hw);
1224 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1225 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1228 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1230 rtlpriv->cfg->ops->led_control(hw, ledaction);
1232 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1234 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1238 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1240 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 if (rtlpriv->psc.rfpwr_state != ERFON)
1246 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RCR, (u8 *)(®_rcr));
1249 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1250 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1252 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1253 } else if (!check_bssid) {
1254 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1255 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1256 rtlpriv->cfg->ops->set_hw_reg(hw,
1257 HW_VAR_RCR, (u8 *) (®_rcr));
1262 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1264 struct rtl_priv *rtlpriv = rtl_priv(hw);
1266 if (_rtl92ce_set_media_status(hw, type))
1269 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1270 if (type != NL80211_IFTYPE_AP &&
1271 type != NL80211_IFTYPE_MESH_POINT)
1272 rtl92ce_set_check_bssid(hw, true);
1274 rtl92ce_set_check_bssid(hw, false);
1280 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1281 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1283 struct rtl_priv *rtlpriv = rtl_priv(hw);
1284 rtl92c_dm_init_edca_turbo(hw);
1287 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1290 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1293 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1296 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1299 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1304 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1306 struct rtl_priv *rtlpriv = rtl_priv(hw);
1307 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1309 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1310 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1311 rtlpci->irq_enabled = true;
1314 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1316 struct rtl_priv *rtlpriv = rtl_priv(hw);
1317 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1319 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1320 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1321 rtlpci->irq_enabled = false;
1324 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1326 struct rtl_priv *rtlpriv = rtl_priv(hw);
1327 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1328 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1332 rtlpriv->intf_ops->enable_aspm(hw);
1333 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1334 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1335 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1336 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1337 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1338 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1339 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1340 rtl92c_firmware_selfreset(hw);
1341 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1342 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1343 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1344 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1345 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1346 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1347 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1348 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1351 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1354 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1355 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1356 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1357 if (!IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version))
1358 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1359 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1360 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1361 u4b_tmp |= 0x03824800;
1362 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1364 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1367 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1368 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1371 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1373 struct rtl_priv *rtlpriv = rtl_priv(hw);
1374 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1375 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1376 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1377 enum nl80211_iftype opmode;
1379 mac->link_state = MAC80211_NOLINK;
1380 opmode = NL80211_IFTYPE_UNSPECIFIED;
1381 _rtl92ce_set_media_status(hw, opmode);
1382 if (rtlpci->driver_is_goingto_unload ||
1383 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1384 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1385 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1386 _rtl92ce_poweroff_adapter(hw);
1388 /* after power off we should do iqk again */
1389 rtlpriv->phy.iqk_initialized = false;
1392 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1393 u32 *p_inta, u32 *p_intb)
1395 struct rtl_priv *rtlpriv = rtl_priv(hw);
1396 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1398 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1399 rtl_write_dword(rtlpriv, ISR, *p_inta);
1402 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1403 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1407 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1410 struct rtl_priv *rtlpriv = rtl_priv(hw);
1411 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1412 u16 bcn_interval, atim_window;
1414 bcn_interval = mac->beacon_interval;
1415 atim_window = 2; /*FIX MERGE */
1416 rtl92ce_disable_interrupt(hw);
1417 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1418 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1419 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1420 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1421 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1422 rtl_write_byte(rtlpriv, 0x606, 0x30);
1423 rtl92ce_enable_interrupt(hw);
1426 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1428 struct rtl_priv *rtlpriv = rtl_priv(hw);
1429 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1430 u16 bcn_interval = mac->beacon_interval;
1432 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1433 "beacon_interval:%d\n", bcn_interval);
1434 rtl92ce_disable_interrupt(hw);
1435 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1436 rtl92ce_enable_interrupt(hw);
1439 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1440 u32 add_msr, u32 rm_msr)
1442 struct rtl_priv *rtlpriv = rtl_priv(hw);
1443 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1445 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1449 rtlpci->irq_mask[0] |= add_msr;
1451 rtlpci->irq_mask[0] &= (~rm_msr);
1452 rtl92ce_disable_interrupt(hw);
1453 rtl92ce_enable_interrupt(hw);
1456 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1460 struct rtl_priv *rtlpriv = rtl_priv(hw);
1461 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1462 u8 rf_path, index, tempval;
1465 for (rf_path = 0; rf_path < 2; rf_path++) {
1466 for (i = 0; i < 3; i++) {
1467 if (!autoload_fail) {
1469 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1470 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1472 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1473 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1477 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1478 EEPROM_DEFAULT_TXPOWERLEVEL;
1480 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1481 EEPROM_DEFAULT_TXPOWERLEVEL;
1486 for (i = 0; i < 3; i++) {
1488 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1490 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1491 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1493 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1494 ((tempval & 0xf0) >> 4);
1497 for (rf_path = 0; rf_path < 2; rf_path++)
1498 for (i = 0; i < 3; i++)
1499 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1500 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1503 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1504 for (rf_path = 0; rf_path < 2; rf_path++)
1505 for (i = 0; i < 3; i++)
1506 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1507 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1510 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1511 for (rf_path = 0; rf_path < 2; rf_path++)
1512 for (i = 0; i < 3; i++)
1513 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1514 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1517 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1519 for (rf_path = 0; rf_path < 2; rf_path++) {
1520 for (i = 0; i < 14; i++) {
1521 index = rtl92c_get_chnl_group((u8)i);
1523 rtlefuse->txpwrlevel_cck[rf_path][i] =
1524 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1525 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1527 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1530 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1532 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1534 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1536 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1539 eprom_chnl_txpwr_ht40_2sdf[rf_path]
1542 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1546 for (i = 0; i < 14; i++) {
1547 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1548 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1550 rtlefuse->txpwrlevel_cck[rf_path][i],
1551 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1552 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1556 for (i = 0; i < 3; i++) {
1557 if (!autoload_fail) {
1558 rtlefuse->eeprom_pwrlimit_ht40[i] =
1559 hwinfo[EEPROM_TXPWR_GROUP + i];
1560 rtlefuse->eeprom_pwrlimit_ht20[i] =
1561 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1563 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1564 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1568 for (rf_path = 0; rf_path < 2; rf_path++) {
1569 for (i = 0; i < 14; i++) {
1570 index = rtl92c_get_chnl_group((u8)i);
1572 if (rf_path == RF90_PATH_A) {
1573 rtlefuse->pwrgroup_ht20[rf_path][i] =
1574 (rtlefuse->eeprom_pwrlimit_ht20[index]
1576 rtlefuse->pwrgroup_ht40[rf_path][i] =
1577 (rtlefuse->eeprom_pwrlimit_ht40[index]
1579 } else if (rf_path == RF90_PATH_B) {
1580 rtlefuse->pwrgroup_ht20[rf_path][i] =
1581 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1583 rtlefuse->pwrgroup_ht40[rf_path][i] =
1584 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1588 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1589 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1591 rtlefuse->pwrgroup_ht20[rf_path][i]);
1592 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1593 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1595 rtlefuse->pwrgroup_ht40[rf_path][i]);
1599 for (i = 0; i < 14; i++) {
1600 index = rtl92c_get_chnl_group((u8)i);
1603 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1605 tempval = EEPROM_DEFAULT_HT20_DIFF;
1607 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1608 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1609 ((tempval >> 4) & 0xF);
1611 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1612 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1614 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1615 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1617 index = rtl92c_get_chnl_group((u8)i);
1620 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1622 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1624 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1625 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1626 ((tempval >> 4) & 0xF);
1629 rtlefuse->legacy_ht_txpowerdiff =
1630 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1632 for (i = 0; i < 14; i++)
1633 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1634 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1635 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1636 for (i = 0; i < 14; i++)
1637 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1638 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1639 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1640 for (i = 0; i < 14; i++)
1641 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1642 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1643 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1644 for (i = 0; i < 14; i++)
1645 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1646 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1647 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1650 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1652 rtlefuse->eeprom_regulatory = 0;
1653 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1654 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1656 if (!autoload_fail) {
1657 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1658 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1660 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1661 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1663 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1664 rtlefuse->eeprom_tssi[RF90_PATH_A],
1665 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1668 tempval = hwinfo[EEPROM_THERMAL_METER];
1670 tempval = EEPROM_DEFAULT_THERMALMETER;
1671 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1673 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1674 rtlefuse->apk_thermalmeterignore = true;
1676 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1677 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1678 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1681 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1683 struct rtl_priv *rtlpriv = rtl_priv(hw);
1684 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1685 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1686 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1687 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1688 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1689 COUNTRY_CODE_WORLD_WIDE_13};
1692 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1696 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1699 _rtl92ce_read_txpower_info_from_hwpg(hw,
1700 rtlefuse->autoload_failflag,
1703 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1704 rtlefuse->autoload_failflag,
1706 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1707 switch (rtlefuse->eeprom_oemid) {
1708 case EEPROM_CID_DEFAULT:
1709 if (rtlefuse->eeprom_did == 0x8176) {
1710 if ((rtlefuse->eeprom_svid == 0x103C &&
1711 rtlefuse->eeprom_smid == 0x1629))
1712 rtlhal->oem_id = RT_CID_819X_HP;
1714 rtlhal->oem_id = RT_CID_DEFAULT;
1716 rtlhal->oem_id = RT_CID_DEFAULT;
1719 case EEPROM_CID_TOSHIBA:
1720 rtlhal->oem_id = RT_CID_TOSHIBA;
1722 case EEPROM_CID_QMI:
1723 rtlhal->oem_id = RT_CID_819X_QMI;
1725 case EEPROM_CID_WHQL:
1727 rtlhal->oem_id = RT_CID_DEFAULT;
1735 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1737 struct rtl_priv *rtlpriv = rtl_priv(hw);
1738 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1739 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1741 switch (rtlhal->oem_id) {
1742 case RT_CID_819X_HP:
1743 pcipriv->ledctl.led_opendrain = true;
1745 case RT_CID_819X_LENOVO:
1746 case RT_CID_DEFAULT:
1747 case RT_CID_TOSHIBA:
1749 case RT_CID_819X_ACER:
1754 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1755 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1758 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1760 struct rtl_priv *rtlpriv = rtl_priv(hw);
1761 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1762 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1763 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1766 rtlhal->version = _rtl92ce_read_chip_version(hw);
1767 if (get_rf_type(rtlphy) == RF_1T1R)
1768 rtlpriv->dm.rfpath_rxenable[0] = true;
1770 rtlpriv->dm.rfpath_rxenable[0] =
1771 rtlpriv->dm.rfpath_rxenable[1] = true;
1772 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1774 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1775 if (tmp_u1b & BIT(4)) {
1776 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1777 rtlefuse->epromtype = EEPROM_93C46;
1779 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1780 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1782 if (tmp_u1b & BIT(5)) {
1783 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1784 rtlefuse->autoload_failflag = false;
1785 _rtl92ce_read_adapter_info(hw);
1787 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1789 _rtl92ce_hal_customized_behavior(hw);
1792 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1793 struct ieee80211_sta *sta)
1795 struct rtl_priv *rtlpriv = rtl_priv(hw);
1796 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1797 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1798 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1799 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1802 u8 nmode = mac->ht_enable;
1805 u8 curtxbw_40mhz = mac->bw_40;
1806 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1808 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1810 enum wireless_mode wirelessmode = mac->mode;
1813 if (rtlhal->current_bandtype == BAND_ON_5G)
1814 ratr_value = sta->supp_rates[1] << 4;
1816 ratr_value = sta->supp_rates[0];
1817 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1820 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1821 sta->ht_cap.mcs.rx_mask[0] << 12);
1822 switch (wirelessmode) {
1823 case WIRELESS_MODE_B:
1824 if (ratr_value & 0x0000000c)
1825 ratr_value &= 0x0000000d;
1827 ratr_value &= 0x0000000f;
1829 case WIRELESS_MODE_G:
1830 ratr_value &= 0x00000FF5;
1832 case WIRELESS_MODE_N_24G:
1833 case WIRELESS_MODE_N_5G:
1835 if (get_rf_type(rtlphy) == RF_1T2R ||
1836 get_rf_type(rtlphy) == RF_1T1R)
1837 ratr_mask = 0x000ff005;
1839 ratr_mask = 0x0f0ff005;
1841 ratr_value &= ratr_mask;
1844 if (rtlphy->rf_type == RF_1T2R)
1845 ratr_value &= 0x000ff0ff;
1847 ratr_value &= 0x0f0ff0ff;
1852 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1853 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1854 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1855 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1856 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1857 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1858 ratr_value &= 0x0fffcfc0;
1860 ratr_value &= 0x0FFFFFFF;
1862 if (nmode && ((curtxbw_40mhz &&
1863 curshortgi_40mhz) || (!curtxbw_40mhz &&
1864 curshortgi_20mhz))) {
1866 ratr_value |= 0x10000000;
1867 tmp_ratr_value = (ratr_value >> 12);
1869 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1870 if ((1 << shortgi_rate) & tmp_ratr_value)
1874 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1875 (shortgi_rate << 4) | (shortgi_rate);
1878 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1880 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1881 rtl_read_dword(rtlpriv, REG_ARFR0));
1884 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1885 struct ieee80211_sta *sta, u8 rssi_level)
1887 struct rtl_priv *rtlpriv = rtl_priv(hw);
1888 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1889 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1890 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1891 struct rtl_sta_info *sta_entry = NULL;
1894 u8 curtxbw_40mhz = (sta->ht_cap.cap &
1895 IEEE80211_HT_CAP_SUP_WIDTH_20_40) ? 1 : 0;
1896 u8 curshortgi_40mhz = (sta->ht_cap.cap &
1897 IEEE80211_HT_CAP_SGI_40) ? 1 : 0;
1898 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1900 enum wireless_mode wirelessmode = 0;
1901 bool shortgi = false;
1905 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1906 wirelessmode = sta_entry->wireless_mode;
1907 if (mac->opmode == NL80211_IFTYPE_STATION ||
1908 mac->opmode == NL80211_IFTYPE_MESH_POINT)
1909 curtxbw_40mhz = mac->bw_40;
1910 else if (mac->opmode == NL80211_IFTYPE_AP ||
1911 mac->opmode == NL80211_IFTYPE_ADHOC)
1912 macid = sta->aid + 1;
1914 if (rtlhal->current_bandtype == BAND_ON_5G)
1915 ratr_bitmap = sta->supp_rates[1] << 4;
1917 ratr_bitmap = sta->supp_rates[0];
1918 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1919 ratr_bitmap = 0xfff;
1920 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1921 sta->ht_cap.mcs.rx_mask[0] << 12);
1922 switch (wirelessmode) {
1923 case WIRELESS_MODE_B:
1924 ratr_index = RATR_INX_WIRELESS_B;
1925 if (ratr_bitmap & 0x0000000c)
1926 ratr_bitmap &= 0x0000000d;
1928 ratr_bitmap &= 0x0000000f;
1930 case WIRELESS_MODE_G:
1931 ratr_index = RATR_INX_WIRELESS_GB;
1933 if (rssi_level == 1)
1934 ratr_bitmap &= 0x00000f00;
1935 else if (rssi_level == 2)
1936 ratr_bitmap &= 0x00000ff0;
1938 ratr_bitmap &= 0x00000ff5;
1940 case WIRELESS_MODE_A:
1941 ratr_index = RATR_INX_WIRELESS_A;
1942 ratr_bitmap &= 0x00000ff0;
1944 case WIRELESS_MODE_N_24G:
1945 case WIRELESS_MODE_N_5G:
1946 ratr_index = RATR_INX_WIRELESS_NGB;
1948 if (rtlphy->rf_type == RF_1T2R ||
1949 rtlphy->rf_type == RF_1T1R) {
1950 if (curtxbw_40mhz) {
1951 if (rssi_level == 1)
1952 ratr_bitmap &= 0x000f0000;
1953 else if (rssi_level == 2)
1954 ratr_bitmap &= 0x000ff000;
1956 ratr_bitmap &= 0x000ff015;
1958 if (rssi_level == 1)
1959 ratr_bitmap &= 0x000f0000;
1960 else if (rssi_level == 2)
1961 ratr_bitmap &= 0x000ff000;
1963 ratr_bitmap &= 0x000ff005;
1966 if (curtxbw_40mhz) {
1967 if (rssi_level == 1)
1968 ratr_bitmap &= 0x0f0f0000;
1969 else if (rssi_level == 2)
1970 ratr_bitmap &= 0x0f0ff000;
1972 ratr_bitmap &= 0x0f0ff015;
1974 if (rssi_level == 1)
1975 ratr_bitmap &= 0x0f0f0000;
1976 else if (rssi_level == 2)
1977 ratr_bitmap &= 0x0f0ff000;
1979 ratr_bitmap &= 0x0f0ff005;
1983 if ((curtxbw_40mhz && curshortgi_40mhz) ||
1984 (!curtxbw_40mhz && curshortgi_20mhz)) {
1988 else if (macid == 1)
1993 ratr_index = RATR_INX_WIRELESS_NGB;
1995 if (rtlphy->rf_type == RF_1T2R)
1996 ratr_bitmap &= 0x000ff0ff;
1998 ratr_bitmap &= 0x0f0ff0ff;
2001 sta_entry->ratr_index = ratr_index;
2003 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2004 "ratr_bitmap :%x\n", ratr_bitmap);
2005 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2007 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2008 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2009 "Rate_index:%x, ratr_val:%x, %5phC\n",
2010 ratr_index, ratr_bitmap, rate_mask);
2011 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2014 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
2015 struct ieee80211_sta *sta, u8 rssi_level)
2017 struct rtl_priv *rtlpriv = rtl_priv(hw);
2019 if (rtlpriv->dm.useramask)
2020 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
2022 rtl92ce_update_hal_rate_table(hw, sta);
2025 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
2027 struct rtl_priv *rtlpriv = rtl_priv(hw);
2028 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2031 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2033 if (!mac->ht_enable)
2034 sifs_timer = 0x0a0a;
2036 sifs_timer = 0x1010;
2037 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2040 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2042 struct rtl_priv *rtlpriv = rtl_priv(hw);
2043 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2044 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2045 enum rf_pwrstate e_rfpowerstate_toset;
2047 bool actuallyset = false;
2050 if (rtlpci->being_init_adapter)
2053 if (ppsc->swrf_processing)
2056 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2057 if (ppsc->rfchange_inprogress) {
2058 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2061 ppsc->rfchange_inprogress = true;
2062 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2065 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2066 REG_MAC_PINMUX_CFG)&~(BIT(3)));
2068 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2069 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2071 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2072 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2073 "GPIOChangeRF - HW Radio ON, RF ON\n");
2075 e_rfpowerstate_toset = ERFON;
2076 ppsc->hwradiooff = false;
2078 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2079 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2080 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2082 e_rfpowerstate_toset = ERFOFF;
2083 ppsc->hwradiooff = true;
2088 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2089 ppsc->rfchange_inprogress = false;
2090 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2092 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2093 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2095 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2096 ppsc->rfchange_inprogress = false;
2097 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2101 return !ppsc->hwradiooff;
2105 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2106 u8 *p_macaddr, bool is_group, u8 enc_algo,
2107 bool is_wepkey, bool clear_all)
2109 struct rtl_priv *rtlpriv = rtl_priv(hw);
2110 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2111 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2112 u8 *macaddr = p_macaddr;
2114 bool is_pairwise = false;
2116 static u8 cam_const_addr[4][6] = {
2117 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2118 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2119 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2120 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2122 static u8 cam_const_broad[] = {
2123 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2129 u8 clear_number = 5;
2131 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2133 for (idx = 0; idx < clear_number; idx++) {
2134 rtl_cam_mark_invalid(hw, cam_offset + idx);
2135 rtl_cam_empty_entry(hw, cam_offset + idx);
2138 memset(rtlpriv->sec.key_buf[idx], 0,
2140 rtlpriv->sec.key_len[idx] = 0;
2146 case WEP40_ENCRYPTION:
2147 enc_algo = CAM_WEP40;
2149 case WEP104_ENCRYPTION:
2150 enc_algo = CAM_WEP104;
2152 case TKIP_ENCRYPTION:
2153 enc_algo = CAM_TKIP;
2155 case AESCCMP_ENCRYPTION:
2159 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2160 "switch case %#x not processed\n", enc_algo);
2161 enc_algo = CAM_TKIP;
2165 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2166 macaddr = cam_const_addr[key_index];
2167 entry_id = key_index;
2170 macaddr = cam_const_broad;
2171 entry_id = key_index;
2173 if (mac->opmode == NL80211_IFTYPE_AP ||
2174 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2175 entry_id = rtl_cam_get_free_entry(hw,
2177 if (entry_id >= TOTAL_CAM_ENTRY) {
2178 RT_TRACE(rtlpriv, COMP_SEC,
2180 "Can not find free hw security cam entry\n");
2184 entry_id = CAM_PAIRWISE_KEY_POSITION;
2187 key_index = PAIRWISE_KEYIDX;
2192 if (rtlpriv->sec.key_len[key_index] == 0) {
2193 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2194 "delete one entry, entry_id is %d\n",
2196 if (mac->opmode == NL80211_IFTYPE_AP ||
2197 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2198 rtl_cam_del_entry(hw, p_macaddr);
2199 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2201 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2202 "The insert KEY length is %d\n",
2203 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2204 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2205 "The insert KEY is %x %x\n",
2206 rtlpriv->sec.key_buf[0][0],
2207 rtlpriv->sec.key_buf[0][1]);
2209 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2212 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2213 "Pairwise Key content",
2214 rtlpriv->sec.pairwise_key,
2216 key_len[PAIRWISE_KEYIDX]);
2218 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2219 "set Pairwise key\n");
2221 rtl_cam_add_one_entry(hw, macaddr, key_index,
2223 CAM_CONFIG_NO_USEDK,
2225 key_buf[key_index]);
2227 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2230 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2231 rtl_cam_add_one_entry(hw,
2234 CAM_PAIRWISE_KEY_POSITION,
2236 CAM_CONFIG_NO_USEDK,
2237 rtlpriv->sec.key_buf
2241 rtl_cam_add_one_entry(hw, macaddr, key_index,
2243 CAM_CONFIG_NO_USEDK,
2244 rtlpriv->sec.key_buf[entry_id]);
2251 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2253 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2255 rtlpcipriv->bt_coexist.bt_coexistence =
2256 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2257 rtlpcipriv->bt_coexist.bt_ant_num =
2258 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2259 rtlpcipriv->bt_coexist.bt_coexist_type =
2260 rtlpcipriv->bt_coexist.eeprom_bt_type;
2262 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2263 rtlpcipriv->bt_coexist.bt_ant_isolation =
2264 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol;
2266 rtlpcipriv->bt_coexist.bt_ant_isolation =
2267 rtlpcipriv->bt_coexist.reg_bt_iso;
2269 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2270 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2272 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2274 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2275 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2276 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2277 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2278 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2279 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2280 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2281 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2283 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2285 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2286 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2287 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2291 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2292 bool auto_load_fail, u8 *hwinfo)
2294 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2297 if (!auto_load_fail) {
2298 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2299 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2300 val = hwinfo[RF_OPTION4];
2301 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1);
2302 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1);
2303 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2304 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2305 ((val & 0x20) >> 5);
2307 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2308 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2309 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2310 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2311 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2314 rtl8192ce_bt_var_init(hw);
2317 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2319 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2321 /* 0:Low, 1:High, 2:From Efuse. */
2322 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2323 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2324 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2325 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2326 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2330 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2332 struct rtl_priv *rtlpriv = rtl_priv(hw);
2333 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2334 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2338 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2339 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2340 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2342 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2343 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2345 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2346 BIT_OFFSET_LEN_MASK_32(0, 1);
2348 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2349 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2350 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2351 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2352 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2354 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2355 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2356 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2358 /* Config to 1T1R. */
2359 if (rtlphy->rf_type == RF_1T1R) {
2360 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2361 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2362 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2364 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2365 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2366 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2371 void rtl92ce_suspend(struct ieee80211_hw *hw)
2375 void rtl92ce_resume(struct ieee80211_hw *hw)