1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __RTL92C_PHY_COMMON_H__
27 #define __RTL92C_PHY_COMMON_H__
29 #define MAX_PRECMD_CNT 16
30 #define MAX_RFDEPENDCMD_CNT 16
31 #define MAX_POSTCMD_CNT 16
33 #define MAX_DOZE_WAITING_TIMES_9x 64
35 #define RT_CANNOT_IO(hw) false
36 #define HIGHPOWER_RADIOA_ARRAYLEN 22
38 #define MAX_TOLERANCE 5
40 #define APK_BB_REG_NUM 5
41 #define APK_AFE_REG_NUM 16
42 #define APK_CURVE_REG_NUM 4
46 #define MAX_STALL_TIME 50
47 #define AntennaDiversityValue 0x80
48 #define MAX_TXPWR_IDX_NMODE_92S 63
49 #define Reset_Cnt_Limit 3
51 #define IQK_ADDA_REG_NUM 16
52 #define IQK_MAC_REG_NUM 4
54 #define IQK_DELAY_TIME 1
55 #define RF90_PATH_MAX 2
57 #define CT_OFFSET_MAC_ADDR 0X16
59 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
60 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
61 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
62 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
63 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
65 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
66 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
68 #define CT_OFFSET_CHANNEL_PLAH 0x75
69 #define CT_OFFSET_THERMAL_METER 0x78
70 #define CT_OFFSET_RF_OPTION 0x79
71 #define CT_OFFSET_VERSION 0x7E
72 #define CT_OFFSET_CUSTOMER_ID 0x7F
74 #define RTL92C_MAX_PATH_NUM 2
75 #define LLT_LAST_ENTRY_OF_TX_PKT_BUFFER 255
79 CMDID_SET_TXPOWEROWER_LEVEL,
81 CMDID_WRITEPORT_ULONG,
82 CMDID_WRITEPORT_USHORT,
83 CMDID_WRITEPORT_UCHAR,
88 enum swchnlcmd_id cmdid;
99 HW90_BLOCK_MAXIMUM = 4,
102 enum baseband_config_type {
103 BASEBAND_CONFIG_PHY_REG = 0,
104 BASEBAND_CONFIG_AGC_TAB = 1,
107 enum ra_offset_area {
108 RA_OFFSET_LEGACY_OFDM1,
109 RA_OFFSET_LEGACY_OFDM2,
136 struct r_antenna_select_ofdm {
143 u32 r_ant_non_ht_s1:4;
148 struct r_antenna_select_cck {
149 u8 r_cckrx_enable_2:2;
154 struct efuse_contents {
155 u8 mac_addr[ETH_ALEN];
156 u8 cck_tx_power_idx[6];
157 u8 ht40_1s_tx_power_idx[6];
158 u8 ht40_2s_tx_power_idx_diff[3];
159 u8 ht20_tx_power_idx_diff[3];
160 u8 ofdm_tx_power_idx_diff[3];
161 u8 ht40_max_power_offset[3];
162 u8 ht20_max_power_offset[3];
171 struct tx_power_struct {
172 u8 cck[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
173 u8 ht40_1s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
174 u8 ht40_2s[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
175 u8 ht20_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
176 u8 legacy_ht_diff[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
177 u8 legacy_ht_txpowerdiff;
178 u8 groupht20[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
179 u8 groupht40[RTL92C_MAX_PATH_NUM][CHANNEL_MAX_NUMBER];
181 u32 mcs_original_offset[4][16];
184 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw,
185 u32 regaddr, u32 bitmask);
186 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
187 u32 regaddr, u32 bitmask, u32 data);
188 u32 rtl92c_phy_query_rf_reg(struct ieee80211_hw *hw,
189 enum radio_path rfpath, u32 regaddr,
191 bool rtl92c_phy_mac_config(struct ieee80211_hw *hw);
192 bool rtl92c_phy_bb_config(struct ieee80211_hw *hw);
193 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw);
194 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
195 enum radio_path rfpath);
196 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
197 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw,
199 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
200 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw,
202 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
203 enum nl80211_channel_type ch_type);
204 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw);
205 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw);
206 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery);
207 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw *hw,
209 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
210 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
211 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain);
212 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
213 enum radio_path rfpath);
214 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw,
216 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw *hw,
217 enum rf_pwrstate rfpwr_state);
218 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw);
219 void rtl92c_phy_set_io(struct ieee80211_hw *hw);
220 void rtl92c_bb_block_on(struct ieee80211_hw *hw);
221 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask);
222 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
223 enum wireless_mode wirelessmode,
225 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
226 enum wireless_mode wirelessmode,
228 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw);
229 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw);
230 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
231 u8 channel, u8 *stage, u8 *step,
233 u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw);
234 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
235 enum radio_path rfpath, u32 offset);
236 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
237 enum radio_path rfpath, u32 offset,
239 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
240 enum radio_path rfpath, u32 offset);
241 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
242 enum radio_path rfpath, u32 offset,
244 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw);
245 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
246 u32 regaddr, u32 bitmask,
248 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);