drivers/net/wireless/realtek/rtlwifi/rtl8192c/phy_common.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * wlanfae <wlanfae@realtek.com>
  23  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24  * Hsinchu 300, Taiwan.
  25  *
  26  * Larry Finger <Larry.Finger@lwfinger.net>
  27  *
  28  *****************************************************************************/
  29
  30 #include "../wifi.h"
  31 #include "../rtl8192ce/reg.h"
  32 #include "../rtl8192ce/def.h"
  33 #include "dm_common.h"
  34 #include "fw_common.h"
  35 #include "phy_common.h"
  36 #include <linux/export.h>
  37
  38 u32 rtl92c_phy_query_bb_reg(struct ieee80211_hw *hw, u32 regaddr, u32 bitmask)
  39 {
  40         struct rtl_priv *rtlpriv = rtl_priv(hw);
  41         u32 returnvalue, originalvalue, bitshift;
  42
  43         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "regaddr(%#x), bitmask(%#x)\n",
  44                  regaddr, bitmask);
  45         originalvalue = rtl_read_dword(rtlpriv, regaddr);
  46         bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  47         returnvalue = (originalvalue & bitmask) >> bitshift;
  48
  49         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  50                  "BBR MASK=0x%x Addr[0x%x]=0x%x\n",
  51                  bitmask, regaddr, originalvalue);
  52
  53         return returnvalue;
  54 }
  55 EXPORT_SYMBOL(rtl92c_phy_query_bb_reg);
  56
  57 void rtl92c_phy_set_bb_reg(struct ieee80211_hw *hw,
  58                            u32 regaddr, u32 bitmask, u32 data)
  59 {
  60         struct rtl_priv *rtlpriv = rtl_priv(hw);
  61         u32 originalvalue, bitshift;
  62
  63         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  64                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  65                  regaddr, bitmask, data);
  66
  67         if (bitmask != MASKDWORD) {
  68                 originalvalue = rtl_read_dword(rtlpriv, regaddr);
  69                 bitshift = _rtl92c_phy_calculate_bit_shift(bitmask);
  70                 data = ((originalvalue & (~bitmask)) | (data << bitshift));
  71         }
  72
  73         rtl_write_dword(rtlpriv, regaddr, data);
  74
  75         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE,
  76                  "regaddr(%#x), bitmask(%#x), data(%#x)\n",
  77                  regaddr, bitmask, data);
  78 }
  79 EXPORT_SYMBOL(rtl92c_phy_set_bb_reg);
  80
  81 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw,
  82                                   enum radio_path rfpath, u32 offset)
  83 {
  84         RT_ASSERT(false, "deprecated!\n");
  85         return 0;
  86 }
  87 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_read);
  88
  89 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw *hw,
  90                                     enum radio_path rfpath, u32 offset,
  91                                     u32 data)
  92 {
  93         RT_ASSERT(false, "deprecated!\n");
  94 }
  95 EXPORT_SYMBOL(_rtl92c_phy_fw_rf_serial_write);
  96
  97 u32 _rtl92c_phy_rf_serial_read(struct ieee80211_hw *hw,
  98                                enum radio_path rfpath, u32 offset)
  99 {
 100         struct rtl_priv *rtlpriv = rtl_priv(hw);
 101         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 102         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 103         u32 newoffset;
 104         u32 tmplong, tmplong2;
 105         u8 rfpi_enable = 0;
 106         u32 retvalue;
 107
 108         offset &= 0x3f;
 109         newoffset = offset;
 110         if (RT_CANNOT_IO(hw)) {
 111                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "return all one\n");
 112                 return 0xFFFFFFFF;
 113         }
 114         tmplong = rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD);
 115         if (rfpath == RF90_PATH_A)
 116                 tmplong2 = tmplong;
 117         else
 118                 tmplong2 = rtl_get_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD);
 119         tmplong2 = (tmplong2 & (~BLSSIREADADDRESS)) |
 120             (newoffset << 23) | BLSSIREADEDGE;
 121         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 122                       tmplong & (~BLSSIREADEDGE));
 123         mdelay(1);
 124         rtl_set_bbreg(hw, pphyreg->rfhssi_para2, MASKDWORD, tmplong2);
 125         mdelay(1);
 126         rtl_set_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, MASKDWORD,
 127                       tmplong | BLSSIREADEDGE);
 128         mdelay(1);
 129         if (rfpath == RF90_PATH_A)
 130                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
 131                                                  BIT(8));
 132         else if (rfpath == RF90_PATH_B)
 133                 rfpi_enable = (u8)rtl_get_bbreg(hw, RFPGA0_XB_HSSIPARAMETER1,
 134                                                  BIT(8));
 135         if (rfpi_enable)
 136                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rbpi,
 137                                          BLSSIREADBACKDATA);
 138         else
 139                 retvalue = rtl_get_bbreg(hw, pphyreg->rf_rb,
 140                                          BLSSIREADBACKDATA);
 141         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFR-%d Addr[0x%x]=0x%x\n",
 142                                                rfpath, pphyreg->rf_rb,
 143                                                retvalue);
 144         return retvalue;
 145 }
 146 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_read);
 147
 148 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw *hw,
 149                                  enum radio_path rfpath, u32 offset,
 150                                  u32 data)
 151 {
 152         u32 data_and_addr;
 153         u32 newoffset;
 154         struct rtl_priv *rtlpriv = rtl_priv(hw);
 155         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 156         struct bb_reg_def *pphyreg = &rtlphy->phyreg_def[rfpath];
 157
 158         if (RT_CANNOT_IO(hw)) {
 159                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "stop\n");
 160                 return;
 161         }
 162         offset &= 0x3f;
 163         newoffset = offset;
 164         data_and_addr = ((newoffset << 20) | (data & 0x000fffff)) & 0x0fffffff;
 165         rtl_set_bbreg(hw, pphyreg->rf3wire_offset, MASKDWORD, data_and_addr);
 166         RT_TRACE(rtlpriv, COMP_RF, DBG_TRACE, "RFW-%d Addr[0x%x]=0x%x\n",
 167                                                rfpath, pphyreg->rf3wire_offset,
 168                                                data_and_addr);
 169 }
 170 EXPORT_SYMBOL(_rtl92c_phy_rf_serial_write);
 171
 172 u32 _rtl92c_phy_calculate_bit_shift(u32 bitmask)
 173 {
 174         u32 i;
 175
 176         for (i = 0; i <= 31; i++) {
 177                 if (((bitmask >> i) & 0x1) == 1)
 178                         break;
 179         }
 180         return i;
 181 }
 182 EXPORT_SYMBOL(_rtl92c_phy_calculate_bit_shift);
 183
 184 static void _rtl92c_phy_bb_config_1t(struct ieee80211_hw *hw)
 185 {
 186         rtl_set_bbreg(hw, RFPGA0_TXINFO, 0x3, 0x2);
 187         rtl_set_bbreg(hw, RFPGA1_TXINFO, 0x300033, 0x200022);
 188         rtl_set_bbreg(hw, RCCK0_AFESETTING, MASKBYTE3, 0x45);
 189         rtl_set_bbreg(hw, ROFDM0_TRXPATHENABLE, MASKBYTE0, 0x23);
 190         rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, 0x30, 0x1);
 191         rtl_set_bbreg(hw, 0xe74, 0x0c000000, 0x2);
 192         rtl_set_bbreg(hw, 0xe78, 0x0c000000, 0x2);
 193         rtl_set_bbreg(hw, 0xe7c, 0x0c000000, 0x2);
 194         rtl_set_bbreg(hw, 0xe80, 0x0c000000, 0x2);
 195         rtl_set_bbreg(hw, 0xe88, 0x0c000000, 0x2);
 196 }
 197
 198 bool rtl92c_phy_rf_config(struct ieee80211_hw *hw)
 199 {
 200         struct rtl_priv *rtlpriv = rtl_priv(hw);
 201
 202         return rtlpriv->cfg->ops->phy_rf6052_config(hw);
 203 }
 204 EXPORT_SYMBOL(rtl92c_phy_rf_config);
 205
 206 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw *hw)
 207 {
 208         struct rtl_priv *rtlpriv = rtl_priv(hw);
 209         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 210         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 211         bool rtstatus;
 212
 213         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 214                                                  BASEBAND_CONFIG_PHY_REG);
 215         if (!rtstatus) {
 216                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Write BB Reg Fail!!\n");
 217                 return false;
 218         }
 219         if (rtlphy->rf_type == RF_1T2R) {
 220                 _rtl92c_phy_bb_config_1t(hw);
 221                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Config to 1T!!\n");
 222         }
 223         if (rtlefuse->autoload_failflag == false) {
 224                 rtlphy->pwrgroup_cnt = 0;
 225                 rtstatus = rtlpriv->cfg->ops->config_bb_with_pgheaderfile(hw,
 226                                                    BASEBAND_CONFIG_PHY_REG);
 227         }
 228         if (!rtstatus) {
 229                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "BB_PG Reg Fail!!\n");
 230                 return false;
 231         }
 232         rtstatus = rtlpriv->cfg->ops->config_bb_with_headerfile(hw,
 233                                                  BASEBAND_CONFIG_AGC_TAB);
 234         if (!rtstatus) {
 235                 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "AGC Table Fail\n");
 236                 return false;
 237         }
 238         rtlphy->cck_high_power =
 239                 (bool)(rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER2, 0x200));
 240
 241         return true;
 242 }
 243
 244 EXPORT_SYMBOL(_rtl92c_phy_bb8192c_config_parafile);
 245
 246 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw *hw,
 247                                             u32 regaddr, u32 bitmask,
 248                                             u32 data)
 249 {
 250         struct rtl_priv *rtlpriv = rtl_priv(hw);
 251         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 252
 253         if (regaddr == RTXAGC_A_RATE18_06) {
 254                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][0] =
 255                     data;
 256                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 257                          "MCSTxPowerLevelOriginalOffset[%d][0] = 0x%x\n",
 258                           rtlphy->pwrgroup_cnt,
 259                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 260                                                             pwrgroup_cnt][0]);
 261         }
 262         if (regaddr == RTXAGC_A_RATE54_24) {
 263                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][1] =
 264                     data;
 265                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 266                          "MCSTxPowerLevelOriginalOffset[%d][1] = 0x%x\n",
 267                           rtlphy->pwrgroup_cnt,
 268                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 269                                                             pwrgroup_cnt][1]);
 270         }
 271         if (regaddr == RTXAGC_A_CCK1_MCS32) {
 272                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][6] =
 273                     data;
 274                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 275                          "MCSTxPowerLevelOriginalOffset[%d][6] = 0x%x\n",
 276                           rtlphy->pwrgroup_cnt,
 277                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 278                                                             pwrgroup_cnt][6]);
 279         }
 280         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0xffffff00) {
 281                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][7] =
 282                     data;
 283                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 284                          "MCSTxPowerLevelOriginalOffset[%d][7] = 0x%x\n",
 285                           rtlphy->pwrgroup_cnt,
 286                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 287                                                             pwrgroup_cnt][7]);
 288         }
 289         if (regaddr == RTXAGC_A_MCS03_MCS00) {
 290                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][2] =
 291                     data;
 292                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 293                          "MCSTxPowerLevelOriginalOffset[%d][2] = 0x%x\n",
 294                           rtlphy->pwrgroup_cnt,
 295                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 296                                                             pwrgroup_cnt][2]);
 297         }
 298         if (regaddr == RTXAGC_A_MCS07_MCS04) {
 299                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][3] =
 300                     data;
 301                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 302                          "MCSTxPowerLevelOriginalOffset[%d][3] = 0x%x\n",
 303                           rtlphy->pwrgroup_cnt,
 304                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 305                                                             pwrgroup_cnt][3]);
 306         }
 307         if (regaddr == RTXAGC_A_MCS11_MCS08) {
 308                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][4] =
 309                     data;
 310                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 311                          "MCSTxPowerLevelOriginalOffset[%d][4] = 0x%x\n",
 312                           rtlphy->pwrgroup_cnt,
 313                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 314                                                             pwrgroup_cnt][4]);
 315         }
 316         if (regaddr == RTXAGC_A_MCS15_MCS12) {
 317                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][5] =
 318                     data;
 319                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 320                          "MCSTxPowerLevelOriginalOffset[%d][5] = 0x%x\n",
 321                           rtlphy->pwrgroup_cnt,
 322                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 323                                                             pwrgroup_cnt][5]);
 324         }
 325         if (regaddr == RTXAGC_B_RATE18_06) {
 326                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][8] =
 327                     data;
 328                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 329                          "MCSTxPowerLevelOriginalOffset[%d][8] = 0x%x\n",
 330                           rtlphy->pwrgroup_cnt,
 331                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 332                                                             pwrgroup_cnt][8]);
 333         }
 334         if (regaddr == RTXAGC_B_RATE54_24) {
 335                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][9] =
 336                     data;
 337                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 338                          "MCSTxPowerLevelOriginalOffset[%d][9] = 0x%x\n",
 339                           rtlphy->pwrgroup_cnt,
 340                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 341                                                             pwrgroup_cnt][9]);
 342         }
 343         if (regaddr == RTXAGC_B_CCK1_55_MCS32) {
 344                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][14] =
 345                     data;
 346                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 347                          "MCSTxPowerLevelOriginalOffset[%d][14] = 0x%x\n",
 348                           rtlphy->pwrgroup_cnt,
 349                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 350                                                             pwrgroup_cnt][14]);
 351         }
 352         if (regaddr == RTXAGC_B_CCK11_A_CCK2_11 && bitmask == 0x000000ff) {
 353                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][15] =
 354                     data;
 355                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 356                          "MCSTxPowerLevelOriginalOffset[%d][15] = 0x%x\n",
 357                           rtlphy->pwrgroup_cnt,
 358                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 359                                                             pwrgroup_cnt][15]);
 360         }
 361         if (regaddr == RTXAGC_B_MCS03_MCS00) {
 362                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][10] =
 363                     data;
 364                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 365                          "MCSTxPowerLevelOriginalOffset[%d][10] = 0x%x\n",
 366                           rtlphy->pwrgroup_cnt,
 367                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 368                                                             pwrgroup_cnt][10]);
 369         }
 370         if (regaddr == RTXAGC_B_MCS07_MCS04) {
 371                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][11] =
 372                     data;
 373                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 374                          "MCSTxPowerLevelOriginalOffset[%d][11] = 0x%x\n",
 375                           rtlphy->pwrgroup_cnt,
 376                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 377                                                             pwrgroup_cnt][11]);
 378         }
 379         if (regaddr == RTXAGC_B_MCS11_MCS08) {
 380                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][12] =
 381                     data;
 382                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 383                          "MCSTxPowerLevelOriginalOffset[%d][12] = 0x%x\n",
 384                           rtlphy->pwrgroup_cnt,
 385                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 386                                                             pwrgroup_cnt][12]);
 387         }
 388         if (regaddr == RTXAGC_B_MCS15_MCS12) {
 389                 rtlphy->mcs_txpwrlevel_origoffset[rtlphy->pwrgroup_cnt][13] =
 390                     data;
 391                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 392                          "MCSTxPowerLevelOriginalOffset[%d][13] = 0x%x\n",
 393                           rtlphy->pwrgroup_cnt,
 394                           rtlphy->mcs_txpwrlevel_origoffset[rtlphy->
 395                                                             pwrgroup_cnt][13]);
 396
 397                 rtlphy->pwrgroup_cnt++;
 398         }
 399 }
 400 EXPORT_SYMBOL(_rtl92c_store_pwrIndex_diffrate_offset);
 401
 402 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw)
 403 {
 404         struct rtl_priv *rtlpriv = rtl_priv(hw);
 405         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 406
 407         rtlphy->default_initialgain[0] =
 408             (u8)rtl_get_bbreg(hw, ROFDM0_XAAGCCORE1, MASKBYTE0);
 409         rtlphy->default_initialgain[1] =
 410             (u8)rtl_get_bbreg(hw, ROFDM0_XBAGCCORE1, MASKBYTE0);
 411         rtlphy->default_initialgain[2] =
 412             (u8)rtl_get_bbreg(hw, ROFDM0_XCAGCCORE1, MASKBYTE0);
 413         rtlphy->default_initialgain[3] =
 414             (u8)rtl_get_bbreg(hw, ROFDM0_XDAGCCORE1, MASKBYTE0);
 415
 416         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 417                  "Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x\n",
 418                   rtlphy->default_initialgain[0],
 419                   rtlphy->default_initialgain[1],
 420                   rtlphy->default_initialgain[2],
 421                   rtlphy->default_initialgain[3]);
 422
 423         rtlphy->framesync = (u8)rtl_get_bbreg(hw,
 424                                                ROFDM0_RXDETECTOR3, MASKBYTE0);
 425         rtlphy->framesync_c34 = rtl_get_bbreg(hw,
 426                                               ROFDM0_RXDETECTOR2, MASKDWORD);
 427
 428         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
 429                  "Default framesync (0x%x) = 0x%x\n",
 430                   ROFDM0_RXDETECTOR3, rtlphy->framesync);
 431 }
 432
 433 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw *hw)
 434 {
 435         struct rtl_priv *rtlpriv = rtl_priv(hw);
 436         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 437
 438         rtlphy->phyreg_def[RF90_PATH_A].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 439         rtlphy->phyreg_def[RF90_PATH_B].rfintfs = RFPGA0_XAB_RFINTERFACESW;
 440         rtlphy->phyreg_def[RF90_PATH_C].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 441         rtlphy->phyreg_def[RF90_PATH_D].rfintfs = RFPGA0_XCD_RFINTERFACESW;
 442
 443         rtlphy->phyreg_def[RF90_PATH_A].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 444         rtlphy->phyreg_def[RF90_PATH_B].rfintfi = RFPGA0_XAB_RFINTERFACERB;
 445         rtlphy->phyreg_def[RF90_PATH_C].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 446         rtlphy->phyreg_def[RF90_PATH_D].rfintfi = RFPGA0_XCD_RFINTERFACERB;
 447
 448         rtlphy->phyreg_def[RF90_PATH_A].rfintfo = RFPGA0_XA_RFINTERFACEOE;
 449         rtlphy->phyreg_def[RF90_PATH_B].rfintfo = RFPGA0_XB_RFINTERFACEOE;
 450
 451         rtlphy->phyreg_def[RF90_PATH_A].rfintfe = RFPGA0_XA_RFINTERFACEOE;
 452         rtlphy->phyreg_def[RF90_PATH_B].rfintfe = RFPGA0_XB_RFINTERFACEOE;
 453
 454         rtlphy->phyreg_def[RF90_PATH_A].rf3wire_offset =
 455             RFPGA0_XA_LSSIPARAMETER;
 456         rtlphy->phyreg_def[RF90_PATH_B].rf3wire_offset =
 457             RFPGA0_XB_LSSIPARAMETER;
 458
 459         rtlphy->phyreg_def[RF90_PATH_A].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 460         rtlphy->phyreg_def[RF90_PATH_B].rflssi_select = rFPGA0_XAB_RFPARAMETER;
 461         rtlphy->phyreg_def[RF90_PATH_C].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 462         rtlphy->phyreg_def[RF90_PATH_D].rflssi_select = rFPGA0_XCD_RFPARAMETER;
 463
 464         rtlphy->phyreg_def[RF90_PATH_A].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 465         rtlphy->phyreg_def[RF90_PATH_B].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 466         rtlphy->phyreg_def[RF90_PATH_C].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 467         rtlphy->phyreg_def[RF90_PATH_D].rftxgain_stage = RFPGA0_TXGAINSTAGE;
 468
 469         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para1 = RFPGA0_XA_HSSIPARAMETER1;
 470         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para1 = RFPGA0_XB_HSSIPARAMETER1;
 471
 472         rtlphy->phyreg_def[RF90_PATH_A].rfhssi_para2 = RFPGA0_XA_HSSIPARAMETER2;
 473         rtlphy->phyreg_def[RF90_PATH_B].rfhssi_para2 = RFPGA0_XB_HSSIPARAMETER2;
 474
 475         rtlphy->phyreg_def[RF90_PATH_A].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 476         rtlphy->phyreg_def[RF90_PATH_B].rfsw_ctrl = RFPGA0_XAB_SWITCHCONTROL;
 477         rtlphy->phyreg_def[RF90_PATH_C].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 478         rtlphy->phyreg_def[RF90_PATH_D].rfsw_ctrl = RFPGA0_XCD_SWITCHCONTROL;
 479
 480         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control1 = ROFDM0_XAAGCCORE1;
 481         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control1 = ROFDM0_XBAGCCORE1;
 482         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control1 = ROFDM0_XCAGCCORE1;
 483         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control1 = ROFDM0_XDAGCCORE1;
 484
 485         rtlphy->phyreg_def[RF90_PATH_A].rfagc_control2 = ROFDM0_XAAGCCORE2;
 486         rtlphy->phyreg_def[RF90_PATH_B].rfagc_control2 = ROFDM0_XBAGCCORE2;
 487         rtlphy->phyreg_def[RF90_PATH_C].rfagc_control2 = ROFDM0_XCAGCCORE2;
 488         rtlphy->phyreg_def[RF90_PATH_D].rfagc_control2 = ROFDM0_XDAGCCORE2;
 489
 490         rtlphy->phyreg_def[RF90_PATH_A].rfrxiq_imbal = ROFDM0_XARXIQIMBALANCE;
 491         rtlphy->phyreg_def[RF90_PATH_B].rfrxiq_imbal = ROFDM0_XBRXIQIMBALANCE;
 492         rtlphy->phyreg_def[RF90_PATH_C].rfrxiq_imbal = ROFDM0_XCRXIQIMBANLANCE;
 493         rtlphy->phyreg_def[RF90_PATH_D].rfrxiq_imbal = ROFDM0_XDRXIQIMBALANCE;
 494
 495         rtlphy->phyreg_def[RF90_PATH_A].rfrx_afe = ROFDM0_XARXAFE;
 496         rtlphy->phyreg_def[RF90_PATH_B].rfrx_afe = ROFDM0_XBRXAFE;
 497         rtlphy->phyreg_def[RF90_PATH_C].rfrx_afe = ROFDM0_XCRXAFE;
 498         rtlphy->phyreg_def[RF90_PATH_D].rfrx_afe = ROFDM0_XDRXAFE;
 499
 500         rtlphy->phyreg_def[RF90_PATH_A].rftxiq_imbal = ROFDM0_XATXIQIMBALANCE;
 501         rtlphy->phyreg_def[RF90_PATH_B].rftxiq_imbal = ROFDM0_XBTXIQIMBALANCE;
 502         rtlphy->phyreg_def[RF90_PATH_C].rftxiq_imbal = ROFDM0_XCTXIQIMBALANCE;
 503         rtlphy->phyreg_def[RF90_PATH_D].rftxiq_imbal = ROFDM0_XDTXIQIMBALANCE;
 504
 505         rtlphy->phyreg_def[RF90_PATH_A].rftx_afe = ROFDM0_XATXAFE;
 506         rtlphy->phyreg_def[RF90_PATH_B].rftx_afe = ROFDM0_XBTXAFE;
 507         rtlphy->phyreg_def[RF90_PATH_C].rftx_afe = ROFDM0_XCTXAFE;
 508         rtlphy->phyreg_def[RF90_PATH_D].rftx_afe = ROFDM0_XDTXAFE;
 509
 510         rtlphy->phyreg_def[RF90_PATH_A].rf_rb = RFPGA0_XA_LSSIREADBACK;
 511         rtlphy->phyreg_def[RF90_PATH_B].rf_rb = RFPGA0_XB_LSSIREADBACK;
 512         rtlphy->phyreg_def[RF90_PATH_C].rf_rb = RFPGA0_XC_LSSIREADBACK;
 513         rtlphy->phyreg_def[RF90_PATH_D].rf_rb = RFPGA0_XD_LSSIREADBACK;
 514
 515         rtlphy->phyreg_def[RF90_PATH_A].rf_rbpi = TRANSCEIVEA_HSPI_READBACK;
 516         rtlphy->phyreg_def[RF90_PATH_B].rf_rbpi = TRANSCEIVEB_HSPI_READBACK;
 517
 518 }
 519 EXPORT_SYMBOL(_rtl92c_phy_init_bb_rf_register_definition);
 520
 521 void rtl92c_phy_get_txpower_level(struct ieee80211_hw *hw, long *powerlevel)
 522 {
 523         struct rtl_priv *rtlpriv = rtl_priv(hw);
 524         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 525         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 526         u8 txpwr_level;
 527         long txpwr_dbm;
 528
 529         txpwr_level = rtlphy->cur_cck_txpwridx;
 530         txpwr_dbm = _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_B,
 531                                                  txpwr_level);
 532         txpwr_level = rtlphy->cur_ofdm24g_txpwridx +
 533             rtlefuse->legacy_ht_txpowerdiff;
 534         if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 535                                          txpwr_level) > txpwr_dbm)
 536                 txpwr_dbm =
 537                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_G,
 538                                                  txpwr_level);
 539         txpwr_level = rtlphy->cur_ofdm24g_txpwridx;
 540         if (_rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 541                                          txpwr_level) > txpwr_dbm)
 542                 txpwr_dbm =
 543                     _rtl92c_phy_txpwr_idx_to_dbm(hw, WIRELESS_MODE_N_24G,
 544                                                  txpwr_level);
 545         *powerlevel = txpwr_dbm;
 546 }
 547
 548 static void _rtl92c_get_txpower_index(struct ieee80211_hw *hw, u8 channel,
 549                                       u8 *cckpowerlevel, u8 *ofdmpowerlevel)
 550 {
 551         struct rtl_priv *rtlpriv = rtl_priv(hw);
 552         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 553         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 554         u8 index = (channel - 1);
 555
 556         cckpowerlevel[RF90_PATH_A] =
 557             rtlefuse->txpwrlevel_cck[RF90_PATH_A][index];
 558         cckpowerlevel[RF90_PATH_B] =
 559             rtlefuse->txpwrlevel_cck[RF90_PATH_B][index];
 560         if (get_rf_type(rtlphy) == RF_1T2R || get_rf_type(rtlphy) == RF_1T1R) {
 561                 ofdmpowerlevel[RF90_PATH_A] =
 562                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_A][index];
 563                 ofdmpowerlevel[RF90_PATH_B] =
 564                     rtlefuse->txpwrlevel_ht40_1s[RF90_PATH_B][index];
 565         } else if (get_rf_type(rtlphy) == RF_2T2R) {
 566                 ofdmpowerlevel[RF90_PATH_A] =
 567                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_A][index];
 568                 ofdmpowerlevel[RF90_PATH_B] =
 569                     rtlefuse->txpwrlevel_ht40_2s[RF90_PATH_B][index];
 570         }
 571 }
 572
 573 static void _rtl92c_ccxpower_index_check(struct ieee80211_hw *hw,
 574                                          u8 channel, u8 *cckpowerlevel,
 575                                          u8 *ofdmpowerlevel)
 576 {
 577         struct rtl_priv *rtlpriv = rtl_priv(hw);
 578         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 579
 580         rtlphy->cur_cck_txpwridx = cckpowerlevel[0];
 581         rtlphy->cur_ofdm24g_txpwridx = ofdmpowerlevel[0];
 582 }
 583
 584 void rtl92c_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel)
 585 {
 586         struct rtl_priv *rtlpriv = rtl_priv(hw);
 587         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 588         u8 cckpowerlevel[2], ofdmpowerlevel[2];
 589
 590         if (!rtlefuse->txpwr_fromeprom)
 591                 return;
 592         _rtl92c_get_txpower_index(hw, channel,
 593                                   &cckpowerlevel[0], &ofdmpowerlevel[0]);
 594         _rtl92c_ccxpower_index_check(hw, channel, &cckpowerlevel[0],
 595                                      &ofdmpowerlevel[0]);
 596         rtlpriv->cfg->ops->phy_rf6052_set_cck_txpower(hw, &cckpowerlevel[0]);
 597         rtlpriv->cfg->ops->phy_rf6052_set_ofdm_txpower(hw, &ofdmpowerlevel[0],
 598                                                        channel);
 599 }
 600 EXPORT_SYMBOL(rtl92c_phy_set_txpower_level);
 601
 602 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw *hw, long power_indbm)
 603 {
 604         struct rtl_priv *rtlpriv = rtl_priv(hw);
 605         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 606         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 607         u8 idx;
 608         u8 rf_path;
 609         u8 ccktxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_B,
 610                                                       power_indbm);
 611         u8 ofdmtxpwridx = _rtl92c_phy_dbm_to_txpwr_idx(hw, WIRELESS_MODE_N_24G,
 612                                                        power_indbm);
 613         if (ofdmtxpwridx - rtlefuse->legacy_ht_txpowerdiff > 0)
 614                 ofdmtxpwridx -= rtlefuse->legacy_ht_txpowerdiff;
 615         else
 616                 ofdmtxpwridx = 0;
 617         RT_TRACE(rtlpriv, COMP_TXAGC, DBG_TRACE,
 618                  "%lx dBm, ccktxpwridx = %d, ofdmtxpwridx = %d\n",
 619                   power_indbm, ccktxpwridx, ofdmtxpwridx);
 620         for (idx = 0; idx < 14; idx++) {
 621                 for (rf_path = 0; rf_path < 2; rf_path++) {
 622                         rtlefuse->txpwrlevel_cck[rf_path][idx] = ccktxpwridx;
 623                         rtlefuse->txpwrlevel_ht40_1s[rf_path][idx] =
 624                             ofdmtxpwridx;
 625                         rtlefuse->txpwrlevel_ht40_2s[rf_path][idx] =
 626                             ofdmtxpwridx;
 627                 }
 628         }
 629         rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
 630         return true;
 631 }
 632 EXPORT_SYMBOL(rtl92c_phy_update_txpower_dbm);
 633
 634 u8 _rtl92c_phy_dbm_to_txpwr_idx(struct ieee80211_hw *hw,
 635                                 enum wireless_mode wirelessmode,
 636                                 long power_indbm)
 637 {
 638         u8 txpwridx;
 639         long offset;
 640
 641         switch (wirelessmode) {
 642         case WIRELESS_MODE_B:
 643                 offset = -7;
 644                 break;
 645         case WIRELESS_MODE_G:
 646         case WIRELESS_MODE_N_24G:
 647                 offset = -8;
 648                 break;
 649         default:
 650                 offset = -8;
 651                 break;
 652         }
 653
 654         if ((power_indbm - offset) > 0)
 655                 txpwridx = (u8)((power_indbm - offset) * 2);
 656         else
 657                 txpwridx = 0;
 658
 659         if (txpwridx > MAX_TXPWR_IDX_NMODE_92S)
 660                 txpwridx = MAX_TXPWR_IDX_NMODE_92S;
 661
 662         return txpwridx;
 663 }
 664 EXPORT_SYMBOL(_rtl92c_phy_dbm_to_txpwr_idx);
 665
 666 long _rtl92c_phy_txpwr_idx_to_dbm(struct ieee80211_hw *hw,
 667                                   enum wireless_mode wirelessmode,
 668                                   u8 txpwridx)
 669 {
 670         long offset;
 671         long pwrout_dbm;
 672
 673         switch (wirelessmode) {
 674         case WIRELESS_MODE_B:
 675                 offset = -7;
 676                 break;
 677         case WIRELESS_MODE_G:
 678         case WIRELESS_MODE_N_24G:
 679                 offset = -8;
 680                 break;
 681         default:
 682                 offset = -8;
 683                 break;
 684         }
 685         pwrout_dbm = txpwridx / 2 + offset;
 686         return pwrout_dbm;
 687 }
 688 EXPORT_SYMBOL(_rtl92c_phy_txpwr_idx_to_dbm);
 689
 690 void rtl92c_phy_set_bw_mode(struct ieee80211_hw *hw,
 691                             enum nl80211_channel_type ch_type)
 692 {
 693         struct rtl_priv *rtlpriv = rtl_priv(hw);
 694         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 695         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 696         u8 tmp_bw = rtlphy->current_chan_bw;
 697
 698         if (rtlphy->set_bwmode_inprogress)
 699                 return;
 700         rtlphy->set_bwmode_inprogress = true;
 701         if ((!is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 702                 rtlpriv->cfg->ops->phy_set_bw_mode_callback(hw);
 703         } else {
 704                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 705                          "false driver sleep or unload\n");
 706                 rtlphy->set_bwmode_inprogress = false;
 707                 rtlphy->current_chan_bw = tmp_bw;
 708         }
 709 }
 710 EXPORT_SYMBOL(rtl92c_phy_set_bw_mode);
 711
 712 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw *hw)
 713 {
 714         struct rtl_priv *rtlpriv = rtl_priv(hw);
 715         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 716         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 717         u32 delay;
 718
 719         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE,
 720                  "switch to channel%d\n", rtlphy->current_channel);
 721         if (is_hal_stop(rtlhal))
 722                 return;
 723         do {
 724                 if (!rtlphy->sw_chnl_inprogress)
 725                         break;
 726                 if (!_rtl92c_phy_sw_chnl_step_by_step
 727                     (hw, rtlphy->current_channel, &rtlphy->sw_chnl_stage,
 728                      &rtlphy->sw_chnl_step, &delay)) {
 729                         if (delay > 0)
 730                                 mdelay(delay);
 731                         else
 732                                 continue;
 733                 } else {
 734                         rtlphy->sw_chnl_inprogress = false;
 735                 }
 736                 break;
 737         } while (true);
 738         RT_TRACE(rtlpriv, COMP_SCAN, DBG_TRACE, "\n");
 739 }
 740 EXPORT_SYMBOL(rtl92c_phy_sw_chnl_callback);
 741
 742 u8 rtl92c_phy_sw_chnl(struct ieee80211_hw *hw)
 743 {
 744         struct rtl_priv *rtlpriv = rtl_priv(hw);
 745         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 746         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 747
 748         if (rtlphy->sw_chnl_inprogress)
 749                 return 0;
 750         if (rtlphy->set_bwmode_inprogress)
 751                 return 0;
 752         RT_ASSERT((rtlphy->current_channel <= 14),
 753                   "WIRELESS_MODE_G but channel>14");
 754         rtlphy->sw_chnl_inprogress = true;
 755         rtlphy->sw_chnl_stage = 0;
 756         rtlphy->sw_chnl_step = 0;
 757         if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
 758                 rtl92c_phy_sw_chnl_callback(hw);
 759                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
 760                          "sw_chnl_inprogress false schedule workitem\n");
 761                 rtlphy->sw_chnl_inprogress = false;
 762         } else {
 763                 RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD,
 764                          "sw_chnl_inprogress false driver sleep or unload\n");
 765                 rtlphy->sw_chnl_inprogress = false;
 766         }
 767         return 1;
 768 }
 769 EXPORT_SYMBOL(rtl92c_phy_sw_chnl);
 770
 771 static void _rtl92c_phy_sw_rf_seting(struct ieee80211_hw *hw, u8 channel)
 772 {
 773         struct rtl_priv *rtlpriv = rtl_priv(hw);
 774         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 775         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 776         if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
 777                 if (channel == 6 &&
 778                     rtlphy->current_chan_bw == HT_CHANNEL_WIDTH_20) {
 779                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 780                                       MASKDWORD, 0x00255);
 781                 } else {
 782                         u32 backuprf0x1A =
 783                           (u32)rtl_get_rfreg(hw, RF90_PATH_A, RF_RX_G1,
 784                                              RFREG_OFFSET_MASK);
 785                         rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD,
 786                                       backuprf0x1A);
 787                 }
 788         }
 789 }
 790
 791 static bool _rtl92c_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable,
 792                                              u32 cmdtableidx, u32 cmdtablesz,
 793                                              enum swchnlcmd_id cmdid,
 794                                              u32 para1, u32 para2, u32 msdelay)
 795 {
 796         struct swchnlcmd *pcmd;
 797
 798         if (cmdtable == NULL) {
 799                 RT_ASSERT(false, "cmdtable cannot be NULL.\n");
 800                 return false;
 801         }
 802
 803         if (cmdtableidx >= cmdtablesz)
 804                 return false;
 805
 806         pcmd = cmdtable + cmdtableidx;
 807         pcmd->cmdid = cmdid;
 808         pcmd->para1 = para1;
 809         pcmd->para2 = para2;
 810         pcmd->msdelay = msdelay;
 811         return true;
 812 }
 813
 814 bool _rtl92c_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw,
 815                                       u8 channel, u8 *stage, u8 *step,
 816                                       u32 *delay)
 817 {
 818         struct rtl_priv *rtlpriv = rtl_priv(hw);
 819         struct rtl_phy *rtlphy = &(rtlpriv->phy);
 820         struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
 821         u32 precommoncmdcnt;
 822         struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
 823         u32 postcommoncmdcnt;
 824         struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
 825         u32 rfdependcmdcnt;
 826         struct swchnlcmd *currentcmd = NULL;
 827         u8 rfpath;
 828         u8 num_total_rfpath = rtlphy->num_total_rfpath;
 829
 830         precommoncmdcnt = 0;
 831         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 832                                          MAX_PRECMD_CNT,
 833                                          CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
 834         _rtl92c_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++,
 835                                          MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
 836
 837         postcommoncmdcnt = 0;
 838
 839         _rtl92c_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++,
 840                                          MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
 841
 842         rfdependcmdcnt = 0;
 843
 844         RT_ASSERT((channel >= 1 && channel <= 14),
 845                   "illegal channel for Zebra: %d\n", channel);
 846
 847         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 848                                          MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG,
 849                                          RF_CHNLBW, channel, 10);
 850
 851         _rtl92c_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++,
 852                                          MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0,
 853                                          0);
 854
 855         do {
 856                 switch (*stage) {
 857                 case 0:
 858                         currentcmd = &precommoncmd[*step];
 859                         break;
 860                 case 1:
 861                         currentcmd = &rfdependcmd[*step];
 862                         break;
 863                 case 2:
 864                         currentcmd = &postcommoncmd[*step];
 865                         break;
 866                 default:
 867                         RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
 868                                  "Invalid 'stage' = %d, Check it!\n", *stage);
 869                         return true;
 870                 }
 871
 872                 if (currentcmd->cmdid == CMDID_END) {
 873                         if ((*stage) == 2) {
 874                                 return true;
 875                         } else {
 876                                 (*stage)++;
 877                                 (*step) = 0;
 878                                 continue;
 879                         }
 880                 }
 881
 882                 switch (currentcmd->cmdid) {
 883                 case CMDID_SET_TXPOWEROWER_LEVEL:
 884                         rtl92c_phy_set_txpower_level(hw, channel);
 885                         break;
 886                 case CMDID_WRITEPORT_ULONG:
 887                         rtl_write_dword(rtlpriv, currentcmd->para1,
 888                                         currentcmd->para2);
 889                         break;
 890                 case CMDID_WRITEPORT_USHORT:
 891                         rtl_write_word(rtlpriv, currentcmd->para1,
 892                                        (u16) currentcmd->para2);
 893                         break;
 894                 case CMDID_WRITEPORT_UCHAR:
 895                         rtl_write_byte(rtlpriv, currentcmd->para1,
 896                                        (u8)currentcmd->para2);
 897                         break;
 898                 case CMDID_RF_WRITEREG:
 899                         for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
 900                                 rtlphy->rfreg_chnlval[rfpath] =
 901                                     ((rtlphy->rfreg_chnlval[rfpath] &
 902                                       0xfffffc00) | currentcmd->para2);
 903
 904                                 rtl_set_rfreg(hw, (enum radio_path)rfpath,
 905                                               currentcmd->para1,
 906                                               RFREG_OFFSET_MASK,
 907                                               rtlphy->rfreg_chnlval[rfpath]);
 908                         }
 909                         _rtl92c_phy_sw_rf_seting(hw, channel);
 910                         break;
 911                 default:
 912                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
 913                                  "switch case %#x not processed\n",
 914                                  currentcmd->cmdid);
 915                         break;
 916                 }
 917
 918                 break;
 919         } while (true);
 920
 921         (*delay) = currentcmd->msdelay;
 922         (*step)++;
 923         return false;
 924 }
 925
 926 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw *hw, u32 rfpath)
 927 {
 928         return true;
 929 }
 930 EXPORT_SYMBOL(rtl8192_phy_check_is_legal_rfpath);
 931
 932 static u8 _rtl92c_phy_path_a_iqk(struct ieee80211_hw *hw, bool config_pathb)
 933 {
 934         u32 reg_eac, reg_e94, reg_e9c, reg_ea4;
 935         u8 result = 0x00;
 936
 937         rtl_set_bbreg(hw, 0xe30, MASKDWORD, 0x10008c1f);
 938         rtl_set_bbreg(hw, 0xe34, MASKDWORD, 0x10008c1f);
 939         rtl_set_bbreg(hw, 0xe38, MASKDWORD, 0x82140102);
 940         rtl_set_bbreg(hw, 0xe3c, MASKDWORD,
 941                       config_pathb ? 0x28160202 : 0x28160502);
 942
 943         if (config_pathb) {
 944                 rtl_set_bbreg(hw, 0xe50, MASKDWORD, 0x10008c22);
 945                 rtl_set_bbreg(hw, 0xe54, MASKDWORD, 0x10008c22);
 946                 rtl_set_bbreg(hw, 0xe58, MASKDWORD, 0x82140102);
 947                 rtl_set_bbreg(hw, 0xe5c, MASKDWORD, 0x28160202);
 948         }
 949
 950         rtl_set_bbreg(hw, 0xe4c, MASKDWORD, 0x001028d1);
 951         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf9000000);
 952         rtl_set_bbreg(hw, 0xe48, MASKDWORD, 0xf8000000);
 953
 954         mdelay(IQK_DELAY_TIME);
 955
 956         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 957         reg_e94 = rtl_get_bbreg(hw, 0xe94, MASKDWORD);
 958         reg_e9c = rtl_get_bbreg(hw, 0xe9c, MASKDWORD);
 959         reg_ea4 = rtl_get_bbreg(hw, 0xea4, MASKDWORD);
 960
 961         if (!(reg_eac & BIT(28)) &&
 962             (((reg_e94 & 0x03FF0000) >> 16) != 0x142) &&
 963             (((reg_e9c & 0x03FF0000) >> 16) != 0x42))
 964                 result |= 0x01;
 965         else
 966                 return result;
 967
 968         if (!(reg_eac & BIT(27)) &&
 969             (((reg_ea4 & 0x03FF0000) >> 16) != 0x132) &&
 970             (((reg_eac & 0x03FF0000) >> 16) != 0x36))
 971                 result |= 0x02;
 972         return result;
 973 }
 974
 975 static u8 _rtl92c_phy_path_b_iqk(struct ieee80211_hw *hw)
 976 {
 977         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
 978         u8 result = 0x00;
 979
 980         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000002);
 981         rtl_set_bbreg(hw, 0xe60, MASKDWORD, 0x00000000);
 982         mdelay(IQK_DELAY_TIME);
 983         reg_eac = rtl_get_bbreg(hw, 0xeac, MASKDWORD);
 984         reg_eb4 = rtl_get_bbreg(hw, 0xeb4, MASKDWORD);
 985         reg_ebc = rtl_get_bbreg(hw, 0xebc, MASKDWORD);
 986         reg_ec4 = rtl_get_bbreg(hw, 0xec4, MASKDWORD);
 987         reg_ecc = rtl_get_bbreg(hw, 0xecc, MASKDWORD);
 988
 989         if (!(reg_eac & BIT(31)) &&
 990             (((reg_eb4 & 0x03FF0000) >> 16) != 0x142) &&
 991             (((reg_ebc & 0x03FF0000) >> 16) != 0x42))
 992                 result |= 0x01;
 993         else
 994                 return result;
 995         if (!(reg_eac & BIT(30)) &&
 996             (((reg_ec4 & 0x03FF0000) >> 16) != 0x132) &&
 997             (((reg_ecc & 0x03FF0000) >> 16) != 0x36))
 998                 result |= 0x02;
 999         return result;
1000 }
1001
1002 static void _rtl92c_phy_path_a_fill_iqk_matrix(struct ieee80211_hw *hw,
1003                                                bool b_iqk_ok, long result[][8],
1004                                                u8 final_candidate, bool btxonly)
1005 {
1006         u32 oldval_0, x, tx0_a, reg;
1007         long y, tx0_c;
1008
1009         if (final_candidate == 0xFF) {
1010                 return;
1011         } else if (b_iqk_ok) {
1012                 oldval_0 = (rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
1013                                           MASKDWORD) >> 22) & 0x3FF;
1014                 x = result[final_candidate][0];
1015                 if ((x & 0x00000200) != 0)
1016                         x = x | 0xFFFFFC00;
1017                 tx0_a = (x * oldval_0) >> 8;
1018                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x3FF, tx0_a);
1019                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(31),
1020                               ((x * oldval_0 >> 7) & 0x1));
1021                 y = result[final_candidate][1];
1022                 if ((y & 0x00000200) != 0)
1023                         y = y | 0xFFFFFC00;
1024                 tx0_c = (y * oldval_0) >> 8;
1025                 rtl_set_bbreg(hw, ROFDM0_XCTXAFE, 0xF0000000,
1026                               ((tx0_c & 0x3C0) >> 6));
1027                 rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE, 0x003F0000,
1028                               (tx0_c & 0x3F));
1029                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(29),
1030                               ((y * oldval_0 >> 7) & 0x1));
1031                 if (btxonly)
1032                         return;
1033                 reg = result[final_candidate][2];
1034                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0x3FF, reg);
1035                 reg = result[final_candidate][3] & 0x3F;
1036                 rtl_set_bbreg(hw, ROFDM0_XARXIQIMBALANCE, 0xFC00, reg);
1037                 reg = (result[final_candidate][3] >> 6) & 0xF;
1038                 rtl_set_bbreg(hw, 0xca0, 0xF0000000, reg);
1039         }
1040 }
1041
1042 static void _rtl92c_phy_path_b_fill_iqk_matrix(struct ieee80211_hw *hw,
1043                                                bool b_iqk_ok, long result[][8],
1044                                                u8 final_candidate, bool btxonly)
1045 {
1046         u32 oldval_1, x, tx1_a, reg;
1047         long y, tx1_c;
1048
1049         if (final_candidate == 0xFF) {
1050                 return;
1051         } else if (b_iqk_ok) {
1052                 oldval_1 = (rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
1053                                           MASKDWORD) >> 22) & 0x3FF;
1054                 x = result[final_candidate][4];
1055                 if ((x & 0x00000200) != 0)
1056                         x = x | 0xFFFFFC00;
1057                 tx1_a = (x * oldval_1) >> 8;
1058                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x3FF, tx1_a);
1059                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(27),
1060                               ((x * oldval_1 >> 7) & 0x1));
1061                 y = result[final_candidate][5];
1062                 if ((y & 0x00000200) != 0)
1063                         y = y | 0xFFFFFC00;
1064                 tx1_c = (y * oldval_1) >> 8;
1065                 rtl_set_bbreg(hw, ROFDM0_XDTXAFE, 0xF0000000,
1066                               ((tx1_c & 0x3C0) >> 6));
1067                 rtl_set_bbreg(hw, ROFDM0_XBTXIQIMBALANCE, 0x003F0000,
1068                               (tx1_c & 0x3F));
1069                 rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD, BIT(25),
1070                               ((y * oldval_1 >> 7) & 0x1));
1071                 if (btxonly)
1072                         return;
1073                 reg = result[final_candidate][6];
1074                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0x3FF, reg);
1075                 reg = result[final_candidate][7] & 0x3F;
1076                 rtl_set_bbreg(hw, ROFDM0_XBRXIQIMBALANCE, 0xFC00, reg);
1077                 reg = (result[final_candidate][7] >> 6) & 0xF;
1078                 rtl_set_bbreg(hw, ROFDM0_AGCRSSITABLE, 0x0000F000, reg);
1079         }
1080 }
1081
1082 static void _rtl92c_phy_save_adda_registers(struct ieee80211_hw *hw,
1083                                             u32 *addareg, u32 *addabackup,
1084                                             u32 registernum)
1085 {
1086         u32 i;
1087
1088         for (i = 0; i < registernum; i++)
1089                 addabackup[i] = rtl_get_bbreg(hw, addareg[i], MASKDWORD);
1090 }
1091
1092 static void _rtl92c_phy_save_mac_registers(struct ieee80211_hw *hw,
1093                                            u32 *macreg, u32 *macbackup)
1094 {
1095         struct rtl_priv *rtlpriv = rtl_priv(hw);
1096         u32 i;
1097
1098         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1099                 macbackup[i] = rtl_read_byte(rtlpriv, macreg[i]);
1100         macbackup[i] = rtl_read_dword(rtlpriv, macreg[i]);
1101 }
1102
1103 static void _rtl92c_phy_reload_adda_registers(struct ieee80211_hw *hw,
1104                                               u32 *addareg, u32 *addabackup,
1105                                               u32 regiesternum)
1106 {
1107         u32 i;
1108
1109         for (i = 0; i < regiesternum; i++)
1110                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, addabackup[i]);
1111 }
1112
1113 static void _rtl92c_phy_reload_mac_registers(struct ieee80211_hw *hw,
1114                                              u32 *macreg, u32 *macbackup)
1115 {
1116         struct rtl_priv *rtlpriv = rtl_priv(hw);
1117         u32 i;
1118
1119         for (i = 0; i < (IQK_MAC_REG_NUM - 1); i++)
1120                 rtl_write_byte(rtlpriv, macreg[i], (u8)macbackup[i]);
1121         rtl_write_dword(rtlpriv, macreg[i], macbackup[i]);
1122 }
1123
1124 static void _rtl92c_phy_path_adda_on(struct ieee80211_hw *hw,
1125                                      u32 *addareg, bool is_patha_on, bool is2t)
1126 {
1127         u32 pathOn;
1128         u32 i;
1129
1130         pathOn = is_patha_on ? 0x04db25a4 : 0x0b1b25a4;
1131         if (false == is2t) {
1132                 pathOn = 0x0bdb25a0;
1133                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, 0x0b1b25a0);
1134         } else {
1135                 rtl_set_bbreg(hw, addareg[0], MASKDWORD, pathOn);
1136         }
1137
1138         for (i = 1; i < IQK_ADDA_REG_NUM; i++)
1139                 rtl_set_bbreg(hw, addareg[i], MASKDWORD, pathOn);
1140 }
1141
1142 static void _rtl92c_phy_mac_setting_calibration(struct ieee80211_hw *hw,
1143                                                 u32 *macreg, u32 *macbackup)
1144 {
1145         struct rtl_priv *rtlpriv = rtl_priv(hw);
1146         u32 i = 0;
1147
1148         rtl_write_byte(rtlpriv, macreg[i], 0x3F);
1149
1150         for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++)
1151                 rtl_write_byte(rtlpriv, macreg[i],
1152                                (u8)(macbackup[i] & (~BIT(3))));
1153         rtl_write_byte(rtlpriv, macreg[i], (u8)(macbackup[i] & (~BIT(5))));
1154 }
1155
1156 static void _rtl92c_phy_path_a_standby(struct ieee80211_hw *hw)
1157 {
1158         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x0);
1159         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1160         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1161 }
1162
1163 static void _rtl92c_phy_pi_mode_switch(struct ieee80211_hw *hw, bool pi_mode)
1164 {
1165         u32 mode;
1166
1167         mode = pi_mode ? 0x01000100 : 0x01000000;
1168         rtl_set_bbreg(hw, 0x820, MASKDWORD, mode);
1169         rtl_set_bbreg(hw, 0x828, MASKDWORD, mode);
1170 }
1171
1172 static bool _rtl92c_phy_simularity_compare(struct ieee80211_hw *hw,
1173                                            long result[][8], u8 c1, u8 c2)
1174 {
1175         u32 i, j, diff, simularity_bitmap, bound;
1176         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1177
1178         u8 final_candidate[2] = { 0xFF, 0xFF };
1179         bool bresult = true, is2t = IS_92C_SERIAL(rtlhal->version);
1180
1181         if (is2t)
1182                 bound = 8;
1183         else
1184                 bound = 4;
1185
1186         simularity_bitmap = 0;
1187
1188         for (i = 0; i < bound; i++) {
1189                 diff = (result[c1][i] > result[c2][i]) ?
1190                     (result[c1][i] - result[c2][i]) :
1191                     (result[c2][i] - result[c1][i]);
1192
1193                 if (diff > MAX_TOLERANCE) {
1194                         if ((i == 2 || i == 6) && !simularity_bitmap) {
1195                                 if (result[c1][i] + result[c1][i + 1] == 0)
1196                                         final_candidate[(i / 4)] = c2;
1197                                 else if (result[c2][i] + result[c2][i + 1] == 0)
1198                                         final_candidate[(i / 4)] = c1;
1199                                 else
1200                                         simularity_bitmap = simularity_bitmap |
1201                                             (1 << i);
1202                         } else
1203                                 simularity_bitmap =
1204                                     simularity_bitmap | (1 << i);
1205                 }
1206         }
1207
1208         if (simularity_bitmap == 0) {
1209                 for (i = 0; i < (bound / 4); i++) {
1210                         if (final_candidate[i] != 0xFF) {
1211                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
1212                                         result[3][j] =
1213                                             result[final_candidate[i]][j];
1214                                 bresult = false;
1215                         }
1216                 }
1217                 return bresult;
1218         } else if (!(simularity_bitmap & 0x0F)) {
1219                 for (i = 0; i < 4; i++)
1220                         result[3][i] = result[c1][i];
1221                 return false;
1222         } else if (!(simularity_bitmap & 0xF0) && is2t) {
1223                 for (i = 4; i < 8; i++)
1224                         result[3][i] = result[c1][i];
1225                 return false;
1226         } else {
1227                 return false;
1228         }
1229 }
1230
1231 static void _rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw,
1232                                      long result[][8], u8 t, bool is2t)
1233 {
1234         struct rtl_priv *rtlpriv = rtl_priv(hw);
1235         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1236         u32 i;
1237         u8 patha_ok, pathb_ok;
1238         u32 adda_reg[IQK_ADDA_REG_NUM] = {
1239                 0x85c, 0xe6c, 0xe70, 0xe74,
1240                 0xe78, 0xe7c, 0xe80, 0xe84,
1241                 0xe88, 0xe8c, 0xed0, 0xed4,
1242                 0xed8, 0xedc, 0xee0, 0xeec
1243         };
1244         u32 iqk_mac_reg[IQK_MAC_REG_NUM] = {
1245                 0x522, 0x550, 0x551, 0x040
1246         };
1247         const u32 retrycount = 2;
1248         u32 bbvalue;
1249
1250         if (t == 0) {
1251                 bbvalue = rtl_get_bbreg(hw, 0x800, MASKDWORD);
1252
1253                 _rtl92c_phy_save_adda_registers(hw, adda_reg,
1254                                                 rtlphy->adda_backup, 16);
1255                 _rtl92c_phy_save_mac_registers(hw, iqk_mac_reg,
1256                                                rtlphy->iqk_mac_backup);
1257         }
1258         _rtl92c_phy_path_adda_on(hw, adda_reg, true, is2t);
1259         if (t == 0) {
1260                 rtlphy->rfpi_enable =
1261                    (u8)rtl_get_bbreg(hw, RFPGA0_XA_HSSIPARAMETER1,
1262                                      BIT(8));
1263         }
1264
1265         if (!rtlphy->rfpi_enable)
1266                 _rtl92c_phy_pi_mode_switch(hw, true);
1267         if (t == 0) {
1268                 rtlphy->reg_c04 = rtl_get_bbreg(hw, 0xc04, MASKDWORD);
1269                 rtlphy->reg_c08 = rtl_get_bbreg(hw, 0xc08, MASKDWORD);
1270                 rtlphy->reg_874 = rtl_get_bbreg(hw, 0x874, MASKDWORD);
1271         }
1272         rtl_set_bbreg(hw, 0xc04, MASKDWORD, 0x03a05600);
1273         rtl_set_bbreg(hw, 0xc08, MASKDWORD, 0x000800e4);
1274         rtl_set_bbreg(hw, 0x874, MASKDWORD, 0x22204000);
1275         if (is2t) {
1276                 rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00010000);
1277                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00010000);
1278         }
1279         _rtl92c_phy_mac_setting_calibration(hw, iqk_mac_reg,
1280                                             rtlphy->iqk_mac_backup);
1281         rtl_set_bbreg(hw, 0xb68, MASKDWORD, 0x00080000);
1282         if (is2t)
1283                 rtl_set_bbreg(hw, 0xb6c, MASKDWORD, 0x00080000);
1284         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0x80800000);
1285         rtl_set_bbreg(hw, 0xe40, MASKDWORD, 0x01007c00);
1286         rtl_set_bbreg(hw, 0xe44, MASKDWORD, 0x01004800);
1287         for (i = 0; i < retrycount; i++) {
1288                 patha_ok = _rtl92c_phy_path_a_iqk(hw, is2t);
1289                 if (patha_ok == 0x03) {
1290                         result[t][0] = (rtl_get_bbreg(hw, 0xe94, MASKDWORD) &
1291                                         0x3FF0000) >> 16;
1292                         result[t][1] = (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) &
1293                                         0x3FF0000) >> 16;
1294                         result[t][2] = (rtl_get_bbreg(hw, 0xea4, MASKDWORD) &
1295                                         0x3FF0000) >> 16;
1296                         result[t][3] = (rtl_get_bbreg(hw, 0xeac, MASKDWORD) &
1297                                         0x3FF0000) >> 16;
1298                         break;
1299                 } else if (i == (retrycount - 1) && patha_ok == 0x01)
1300
1301                         result[t][0] = (rtl_get_bbreg(hw, 0xe94,
1302                                                       MASKDWORD) & 0x3FF0000) >>
1303                             16;
1304                 result[t][1] =
1305                     (rtl_get_bbreg(hw, 0xe9c, MASKDWORD) & 0x3FF0000) >> 16;
1306
1307         }
1308
1309         if (is2t) {
1310                 _rtl92c_phy_path_a_standby(hw);
1311                 _rtl92c_phy_path_adda_on(hw, adda_reg, false, is2t);
1312                 for (i = 0; i < retrycount; i++) {
1313                         pathb_ok = _rtl92c_phy_path_b_iqk(hw);
1314                         if (pathb_ok == 0x03) {
1315                                 result[t][4] = (rtl_get_bbreg(hw,
1316                                                               0xeb4,
1317                                                               MASKDWORD) &
1318                                                 0x3FF0000) >> 16;
1319                                 result[t][5] =
1320                                     (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1321                                      0x3FF0000) >> 16;
1322                                 result[t][6] =
1323                                     (rtl_get_bbreg(hw, 0xec4, MASKDWORD) &
1324                                      0x3FF0000) >> 16;
1325                                 result[t][7] =
1326                                     (rtl_get_bbreg(hw, 0xecc, MASKDWORD) &
1327                                      0x3FF0000) >> 16;
1328                                 break;
1329                         } else if (i == (retrycount - 1) && pathb_ok == 0x01) {
1330                                 result[t][4] = (rtl_get_bbreg(hw,
1331                                                               0xeb4,
1332                                                               MASKDWORD) &
1333                                                 0x3FF0000) >> 16;
1334                         }
1335                         result[t][5] = (rtl_get_bbreg(hw, 0xebc, MASKDWORD) &
1336                                         0x3FF0000) >> 16;
1337                 }
1338         }
1339         rtl_set_bbreg(hw, 0xc04, MASKDWORD, rtlphy->reg_c04);
1340         rtl_set_bbreg(hw, 0x874, MASKDWORD, rtlphy->reg_874);
1341         rtl_set_bbreg(hw, 0xc08, MASKDWORD, rtlphy->reg_c08);
1342         rtl_set_bbreg(hw, 0xe28, MASKDWORD, 0);
1343         rtl_set_bbreg(hw, 0x840, MASKDWORD, 0x00032ed3);
1344         if (is2t)
1345                 rtl_set_bbreg(hw, 0x844, MASKDWORD, 0x00032ed3);
1346         if (t != 0) {
1347                 if (!rtlphy->rfpi_enable)
1348                         _rtl92c_phy_pi_mode_switch(hw, false);
1349                 _rtl92c_phy_reload_adda_registers(hw, adda_reg,
1350                                                   rtlphy->adda_backup, 16);
1351                 _rtl92c_phy_reload_mac_registers(hw, iqk_mac_reg,
1352                                                  rtlphy->iqk_mac_backup);
1353         }
1354 }
1355
1356 static void _rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw,
1357                                      s8 delta, bool is2t)
1358 {
1359 }
1360
1361 static void _rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw,
1362                                           bool bmain, bool is2t)
1363 {
1364         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1365
1366         if (is_hal_stop(rtlhal)) {
1367                 rtl_set_bbreg(hw, REG_LEDCFG0, BIT(23), 0x01);
1368                 rtl_set_bbreg(hw, rFPGA0_XAB_RFPARAMETER, BIT(13), 0x01);
1369         }
1370         if (is2t) {
1371                 if (bmain)
1372                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1373                                       BIT(5) | BIT(6), 0x1);
1374                 else
1375                         rtl_set_bbreg(hw, RFPGA0_XB_RFINTERFACEOE,
1376                                       BIT(5) | BIT(6), 0x2);
1377         } else {
1378                 if (bmain)
1379                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x2);
1380                 else
1381                         rtl_set_bbreg(hw, RFPGA0_XA_RFINTERFACEOE, 0x300, 0x1);
1382         }
1383 }
1384
1385 #undef IQK_ADDA_REG_NUM
1386 #undef IQK_DELAY_TIME
1387
1388 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool b_recovery)
1389 {
1390         struct rtl_priv *rtlpriv = rtl_priv(hw);
1391         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1392         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1393
1394         long result[4][8];
1395         u8 i, final_candidate;
1396         bool b_patha_ok, b_pathb_ok;
1397         long reg_e94, reg_e9c, reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4,
1398             reg_ecc, reg_tmp = 0;
1399         bool is12simular, is13simular, is23simular;
1400         u32 iqk_bb_reg[10] = {
1401                 ROFDM0_XARXIQIMBALANCE,
1402                 ROFDM0_XBRXIQIMBALANCE,
1403                 ROFDM0_ECCATHRESHOLD,
1404                 ROFDM0_AGCRSSITABLE,
1405                 ROFDM0_XATXIQIMBALANCE,
1406                 ROFDM0_XBTXIQIMBALANCE,
1407                 ROFDM0_XCTXIQIMBALANCE,
1408                 ROFDM0_XCTXAFE,
1409                 ROFDM0_XDTXAFE,
1410                 ROFDM0_RXIQEXTANTA
1411         };
1412
1413         if (b_recovery) {
1414                 _rtl92c_phy_reload_adda_registers(hw,
1415                                                   iqk_bb_reg,
1416                                                   rtlphy->iqk_bb_backup, 10);
1417                 return;
1418         }
1419         for (i = 0; i < 8; i++) {
1420                 result[0][i] = 0;
1421                 result[1][i] = 0;
1422                 result[2][i] = 0;
1423                 result[3][i] = 0;
1424         }
1425         final_candidate = 0xff;
1426         b_patha_ok = false;
1427         b_pathb_ok = false;
1428         is12simular = false;
1429         is23simular = false;
1430         is13simular = false;
1431         for (i = 0; i < 3; i++) {
1432                 if (IS_92C_SERIAL(rtlhal->version))
1433                         _rtl92c_phy_iq_calibrate(hw, result, i, true);
1434                 else
1435                         _rtl92c_phy_iq_calibrate(hw, result, i, false);
1436                 if (i == 1) {
1437                         is12simular = _rtl92c_phy_simularity_compare(hw,
1438                                                                      result, 0,
1439                                                                      1);
1440                         if (is12simular) {
1441                                 final_candidate = 0;
1442                                 break;
1443                         }
1444                 }
1445                 if (i == 2) {
1446                         is13simular = _rtl92c_phy_simularity_compare(hw,
1447                                                                      result, 0,
1448                                                                      2);
1449                         if (is13simular) {
1450                                 final_candidate = 0;
1451                                 break;
1452                         }
1453                         is23simular = _rtl92c_phy_simularity_compare(hw,
1454                                                                      result, 1,
1455                                                                      2);
1456                         if (is23simular)
1457                                 final_candidate = 1;
1458                         else {
1459                                 for (i = 0; i < 8; i++)
1460                                         reg_tmp += result[3][i];
1461
1462                                 if (reg_tmp != 0)
1463                                         final_candidate = 3;
1464                                 else
1465                                         final_candidate = 0xFF;
1466                         }
1467                 }
1468         }
1469         for (i = 0; i < 4; i++) {
1470                 reg_e94 = result[i][0];
1471                 reg_e9c = result[i][1];
1472                 reg_ea4 = result[i][2];
1473                 reg_eac = result[i][3];
1474                 reg_eb4 = result[i][4];
1475                 reg_ebc = result[i][5];
1476                 reg_ec4 = result[i][6];
1477                 reg_ecc = result[i][7];
1478         }
1479         if (final_candidate != 0xff) {
1480                 rtlphy->reg_e94 = reg_e94 = result[final_candidate][0];
1481                 rtlphy->reg_e9c = reg_e9c = result[final_candidate][1];
1482                 reg_ea4 = result[final_candidate][2];
1483                 reg_eac = result[final_candidate][3];
1484                 rtlphy->reg_eb4 = reg_eb4 = result[final_candidate][4];
1485                 rtlphy->reg_ebc = reg_ebc = result[final_candidate][5];
1486                 reg_ec4 = result[final_candidate][6];
1487                 reg_ecc = result[final_candidate][7];
1488                 b_patha_ok = true;
1489                 b_pathb_ok = true;
1490         } else {
1491                 rtlphy->reg_e94 = rtlphy->reg_eb4 = 0x100;
1492                 rtlphy->reg_e9c = rtlphy->reg_ebc = 0x0;
1493         }
1494         if (reg_e94 != 0) /*&&(reg_ea4 != 0) */
1495                 _rtl92c_phy_path_a_fill_iqk_matrix(hw, b_patha_ok, result,
1496                                                    final_candidate,
1497                                                    (reg_ea4 == 0));
1498         if (IS_92C_SERIAL(rtlhal->version)) {
1499                 if (reg_eb4 != 0) /*&&(reg_ec4 != 0) */
1500                         _rtl92c_phy_path_b_fill_iqk_matrix(hw, b_pathb_ok,
1501                                                            result,
1502                                                            final_candidate,
1503                                                            (reg_ec4 == 0));
1504         }
1505         _rtl92c_phy_save_adda_registers(hw, iqk_bb_reg,
1506                                         rtlphy->iqk_bb_backup, 10);
1507 }
1508 EXPORT_SYMBOL(rtl92c_phy_iq_calibrate);
1509
1510 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw)
1511 {
1512         struct rtl_priv *rtlpriv = rtl_priv(hw);
1513         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1514
1515         if (IS_92C_SERIAL(rtlhal->version))
1516                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, true);
1517         else
1518                 rtlpriv->cfg->ops->phy_lc_calibrate(hw, false);
1519 }
1520 EXPORT_SYMBOL(rtl92c_phy_lc_calibrate);
1521
1522 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta)
1523 {
1524         struct rtl_priv *rtlpriv = rtl_priv(hw);
1525         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1526         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1527
1528         if (rtlphy->apk_done)
1529                 return;
1530         if (IS_92C_SERIAL(rtlhal->version))
1531                 _rtl92c_phy_ap_calibrate(hw, delta, true);
1532         else
1533                 _rtl92c_phy_ap_calibrate(hw, delta, false);
1534 }
1535 EXPORT_SYMBOL(rtl92c_phy_ap_calibrate);
1536
1537 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw *hw, bool bmain)
1538 {
1539         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1540
1541         if (IS_92C_SERIAL(rtlhal->version))
1542                 _rtl92c_phy_set_rfpath_switch(hw, bmain, true);
1543         else
1544                 _rtl92c_phy_set_rfpath_switch(hw, bmain, false);
1545 }
1546 EXPORT_SYMBOL(rtl92c_phy_set_rfpath_switch);
1547
1548 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype)
1549 {
1550         struct rtl_priv *rtlpriv = rtl_priv(hw);
1551         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1552         bool postprocessing = false;
1553
1554         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1555                  "-->IO Cmd(%#x), set_io_inprogress(%d)\n",
1556                   iotype, rtlphy->set_io_inprogress);
1557         do {
1558                 switch (iotype) {
1559                 case IO_CMD_RESUME_DM_BY_SCAN:
1560                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1561                                  "[IO CMD] Resume DM after scan.\n");
1562                         postprocessing = true;
1563                         break;
1564                 case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1565                         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1566                                  "[IO CMD] Pause DM before scan.\n");
1567                         postprocessing = true;
1568                         break;
1569                 default:
1570                         RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1571                                  "switch case %#x not processed\n", iotype);
1572                         break;
1573                 }
1574         } while (false);
1575         if (postprocessing && !rtlphy->set_io_inprogress) {
1576                 rtlphy->set_io_inprogress = true;
1577                 rtlphy->current_io_type = iotype;
1578         } else {
1579                 return false;
1580         }
1581         rtl92c_phy_set_io(hw);
1582         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE, "IO Type(%#x)\n", iotype);
1583         return true;
1584 }
1585 EXPORT_SYMBOL(rtl92c_phy_set_io_cmd);
1586
1587 void rtl92c_phy_set_io(struct ieee80211_hw *hw)
1588 {
1589         struct rtl_priv *rtlpriv = rtl_priv(hw);
1590         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1591         struct dig_t *dm_digtable = &rtlpriv->dm_digtable;
1592
1593         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1594                  "--->Cmd(%#x), set_io_inprogress(%d)\n",
1595                   rtlphy->current_io_type, rtlphy->set_io_inprogress);
1596         switch (rtlphy->current_io_type) {
1597         case IO_CMD_RESUME_DM_BY_SCAN:
1598                 dm_digtable->cur_igvalue = rtlphy->initgain_backup.xaagccore1;
1599                 rtl92c_dm_write_dig(hw);
1600                 rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
1601                 break;
1602         case IO_CMD_PAUSE_BAND0_DM_BY_SCAN:
1603                 rtlphy->initgain_backup.xaagccore1 = dm_digtable->cur_igvalue;
1604                 dm_digtable->cur_igvalue = 0x17;
1605                 rtl92c_dm_write_dig(hw);
1606                 break;
1607         default:
1608                 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1609                          "switch case %#x not processed\n",
1610                          rtlphy->current_io_type);
1611                 break;
1612         }
1613         rtlphy->set_io_inprogress = false;
1614         RT_TRACE(rtlpriv, COMP_CMD, DBG_TRACE,
1615                  "(%#x)\n", rtlphy->current_io_type);
1616 }
1617 EXPORT_SYMBOL(rtl92c_phy_set_io);
1618
1619 void rtl92ce_phy_set_rf_on(struct ieee80211_hw *hw)
1620 {
1621         struct rtl_priv *rtlpriv = rtl_priv(hw);
1622
1623         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
1624         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1625         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1626         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1627         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1628         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1629 }
1630 EXPORT_SYMBOL(rtl92ce_phy_set_rf_on);
1631
1632 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw *hw)
1633 {
1634         u32 u4b_tmp;
1635         u8 delay = 5;
1636         struct rtl_priv *rtlpriv = rtl_priv(hw);
1637
1638         rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1639         rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1640         rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1641         u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1642         while (u4b_tmp != 0 && delay > 0) {
1643                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x0);
1644                 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1645                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1646                 u4b_tmp = rtl_get_rfreg(hw, RF90_PATH_A, 0, RFREG_OFFSET_MASK);
1647                 delay--;
1648         }
1649         if (delay == 0) {
1650                 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x00);
1651                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1652                 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE3);
1653                 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0x00);
1654                 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
1655                          "Switch RF timeout !!!.\n");
1656                 return;
1657         }
1658         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1659         rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x22);
1660 }
1661 EXPORT_SYMBOL(_rtl92c_phy_set_rf_sleep);