GNU Linux-libre 4.14.328-gnu1
[releases.git] / drivers / net / wireless / realtek / rtlwifi / rtl8192c / dm_common.h
1 /******************************************************************************
2  *
3  * Copyright(c) 2009-2012  Realtek Corporation.
4  *
5  * This program is free software; you can redistribute it and/or modify it
6  * under the terms of version 2 of the GNU General Public License as
7  * published by the Free Software Foundation.
8  *
9  * This program is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
12  * more details.
13  *
14  * The full GNU General Public License is included in this distribution in the
15  * file called LICENSE.
16  *
17  * Contact Information:
18  * wlanfae <wlanfae@realtek.com>
19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20  * Hsinchu 300, Taiwan.
21  *
22  * Larry Finger <Larry.Finger@lwfinger.net>
23  *
24  *****************************************************************************/
25
26 #ifndef __RTL92COMMON_DM_H__
27 #define __RTL92COMMON_DM_H__
28
29 #include "../wifi.h"
30 #include "../rtl8192ce/def.h"
31 #include "../rtl8192ce/reg.h"
32 #include "fw_common.h"
33
34 #define HAL_DM_DIG_DISABLE                      BIT(0)
35 #define HAL_DM_HIPWR_DISABLE                    BIT(1)
36
37 #define OFDM_TABLE_LENGTH                       37
38 #define CCK_TABLE_LENGTH                        33
39
40 #define OFDM_TABLE_SIZE                         37
41 #define CCK_TABLE_SIZE                          33
42
43 #define BW_AUTO_SWITCH_HIGH_LOW                 25
44 #define BW_AUTO_SWITCH_LOW_HIGH                 30
45
46 #define DM_DIG_FA_UPPER                         0x32
47 #define DM_DIG_FA_LOWER                         0x20
48 #define DM_DIG_FA_TH0                           0x20
49 #define DM_DIG_FA_TH1                           0x100
50 #define DM_DIG_FA_TH2                           0x200
51
52 #define RXPATHSELECTION_SS_TH_lOW               30
53 #define RXPATHSELECTION_DIFF_TH                 18
54
55 #define DM_RATR_STA_INIT                        0
56 #define DM_RATR_STA_HIGH                        1
57 #define DM_RATR_STA_MIDDLE                      2
58 #define DM_RATR_STA_LOW                         3
59
60 #define CTS2SELF_THVAL                          30
61 #define REGC38_TH                               20
62
63 #define WAIOTTHVal                              25
64
65 #define TXHIGHPWRLEVEL_NORMAL                   0
66 #define TXHIGHPWRLEVEL_LEVEL1                   1
67 #define TXHIGHPWRLEVEL_LEVEL2                   2
68 #define TXHIGHPWRLEVEL_BT1                      3
69 #define TXHIGHPWRLEVEL_BT2                      4
70
71 #define DM_TYPE_BYFW                            0
72 #define DM_TYPE_BYDRIVER                        1
73
74 #define TX_POWER_NEAR_FIELD_THRESH_LVL2         74
75 #define TX_POWER_NEAR_FIELD_THRESH_LVL1         67
76
77 #define DYNAMIC_FUNC_DISABLE                    0x0
78 #define DYNAMIC_FUNC_DIG                        BIT(0)
79 #define DYNAMIC_FUNC_HP                         BIT(1)
80 #define DYNAMIC_FUNC_SS                         BIT(2) /*Tx Power Tracking*/
81 #define DYNAMIC_FUNC_BT                         BIT(3)
82 #define DYNAMIC_FUNC_ANT_DIV                    BIT(4)
83
84 #define RSSI_CCK                                0
85 #define RSSI_OFDM                               1
86 #define RSSI_DEFAULT                            2
87
88 struct swat_t {
89         u8 failure_cnt;
90         u8 try_flag;
91         u8 stop_trying;
92         long pre_rssi;
93         long trying_threshold;
94         u8 cur_antenna;
95         u8 pre_antenna;
96 };
97
98 enum tag_dynamic_init_gain_operation_type_definition {
99         DIG_TYPE_THRESH_HIGH = 0,
100         DIG_TYPE_THRESH_LOW = 1,
101         DIG_TYPE_BACKOFF = 2,
102         DIG_TYPE_RX_GAIN_MIN = 3,
103         DIG_TYPE_RX_GAIN_MAX = 4,
104         DIG_TYPE_ENABLE = 5,
105         DIG_TYPE_DISABLE = 6,
106         DIG_OP_TYPE_MAX
107 };
108
109 enum dm_1r_cca_e {
110         CCA_1R = 0,
111         CCA_2R = 1,
112         CCA_MAX = 2,
113 };
114
115 enum dm_rf_e {
116         RF_SAVE = 0,
117         RF_NORMAL = 1,
118         RF_MAX = 2,
119 };
120
121 enum dm_sw_ant_switch_e {
122         ANS_ANTENNA_B = 1,
123         ANS_ANTENNA_A = 2,
124         ANS_ANTENNA_MAX = 3,
125 };
126
127 void rtl92c_dm_init(struct ieee80211_hw *hw);
128 void rtl92c_dm_watchdog(struct ieee80211_hw *hw);
129 void rtl92c_dm_write_dig(struct ieee80211_hw *hw);
130 void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw);
131 void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw);
132 void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw);
133 void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal);
134 void rtl92c_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
135 void rtl92c_phy_lc_calibrate(struct ieee80211_hw *hw);
136 void rtl92c_phy_iq_calibrate(struct ieee80211_hw *hw, bool recovery);
137 void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw);
138 void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw);
139 void dm_savepowerindex(struct ieee80211_hw *hw);
140 void dm_writepowerindex(struct ieee80211_hw *hw, u8 value);
141 void dm_restorepowerindex(struct ieee80211_hw *hw);
142
143 #endif