drivers/net/wireless/realtek/rtlwifi/rtl8188ee/hw.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2013  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../wifi.h"
  27 #include "../efuse.h"
  28 #include "../base.h"
  29 #include "../regd.h"
  30 #include "../cam.h"
  31 #include "../ps.h"
  32 #include "../pci.h"
  33 #include "../pwrseqcmd.h"
  34 #include "reg.h"
  35 #include "def.h"
  36 #include "phy.h"
  37 #include "dm.h"
  38 #include "fw.h"
  39 #include "led.h"
  40 #include "hw.h"
  41 #include "pwrseq.h"
  42
  43 #define LLT_CONFIG              5
  44
  45 static void _rtl88ee_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
  46                                       u8 set_bits, u8 clear_bits)
  47 {
  48         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  49         struct rtl_priv *rtlpriv = rtl_priv(hw);
  50
  51         rtlpci->reg_bcn_ctrl_val |= set_bits;
  52         rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
  53
  54         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
  55 }
  56
  57 static void _rtl88ee_stop_tx_beacon(struct ieee80211_hw *hw)
  58 {
  59         struct rtl_priv *rtlpriv = rtl_priv(hw);
  60         u8 tmp1byte;
  61
  62         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  63         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
  64         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
  65         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  66         tmp1byte &= ~(BIT(0));
  67         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  68 }
  69
  70 static void _rtl88ee_resume_tx_beacon(struct ieee80211_hw *hw)
  71 {
  72         struct rtl_priv *rtlpriv = rtl_priv(hw);
  73         u8 tmp1byte;
  74
  75         tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
  76         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
  77         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
  78         tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
  79         tmp1byte |= BIT(0);
  80         rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
  81 }
  82
  83 static void _rtl88ee_enable_bcn_sub_func(struct ieee80211_hw *hw)
  84 {
  85         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(1));
  86 }
  87
  88 static void _rtl88ee_return_beacon_queue_skb(struct ieee80211_hw *hw)
  89 {
  90         struct rtl_priv *rtlpriv = rtl_priv(hw);
  91         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
  92         struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[BEACON_QUEUE];
  93         unsigned long flags;
  94
  95         spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
  96         while (skb_queue_len(&ring->queue)) {
  97                 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
  98                 struct sk_buff *skb = __skb_dequeue(&ring->queue);
  99
 100                 pci_unmap_single(rtlpci->pdev,
 101                                  rtlpriv->cfg->ops->get_desc(
 102                                  (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
 103                                  skb->len, PCI_DMA_TODEVICE);
 104                 kfree_skb(skb);
 105                 ring->idx = (ring->idx + 1) % ring->entries;
 106         }
 107         spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
 108 }
 109
 110 static void _rtl88ee_disable_bcn_sub_func(struct ieee80211_hw *hw)
 111 {
 112         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(1), 0);
 113 }
 114
 115 static void _rtl88ee_set_fw_clock_on(struct ieee80211_hw *hw,
 116                                      u8 rpwm_val, bool b_need_turn_off_ckk)
 117 {
 118         struct rtl_priv *rtlpriv = rtl_priv(hw);
 119         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 120         bool b_support_remote_wake_up;
 121         u32 count = 0, isr_regaddr, content;
 122         bool schedule_timer = b_need_turn_off_ckk;
 123         rtlpriv->cfg->ops->get_hw_reg(hw, HAL_DEF_WOWLAN,
 124                                         (u8 *)(&b_support_remote_wake_up));
 125
 126         if (!rtlhal->fw_ready)
 127                 return;
 128         if (!rtlpriv->psc.fw_current_inpsmode)
 129                 return;
 130
 131         while (1) {
 132                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 133                 if (rtlhal->fw_clk_change_in_progress) {
 134                         while (rtlhal->fw_clk_change_in_progress) {
 135                                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 136                                 count++;
 137                                 udelay(100);
 138                                 if (count > 1000)
 139                                         return;
 140                                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 141                         }
 142                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 143                 } else {
 144                         rtlhal->fw_clk_change_in_progress = false;
 145                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 146                         break;
 147                 }
 148         }
 149
 150         if (IS_IN_LOW_POWER_STATE_88E(rtlhal->fw_ps_state)) {
 151                 rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 152                 if (FW_PS_IS_ACK(rpwm_val)) {
 153                         isr_regaddr = REG_HISR;
 154                         content = rtl_read_dword(rtlpriv, isr_regaddr);
 155                         while (!(content & IMR_CPWM) && (count < 500)) {
 156                                 udelay(50);
 157                                 count++;
 158                                 content = rtl_read_dword(rtlpriv, isr_regaddr);
 159                         }
 160
 161                         if (content & IMR_CPWM) {
 162                                 rtl_write_word(rtlpriv, isr_regaddr, 0x0100);
 163                                 rtlhal->fw_ps_state = FW_PS_STATE_RF_ON_88E;
 164                                 RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
 165                                          "Receive CPWM INT!!! Set pHalData->FwPSState = %X\n",
 166                                          rtlhal->fw_ps_state);
 167                         }
 168                 }
 169
 170                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 171                 rtlhal->fw_clk_change_in_progress = false;
 172                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 173                 if (schedule_timer) {
 174                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 175                                   jiffies + MSECS(10));
 176                 }
 177
 178         } else  {
 179                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 180                 rtlhal->fw_clk_change_in_progress = false;
 181                 spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 182         }
 183 }
 184
 185 static void _rtl88ee_set_fw_clock_off(struct ieee80211_hw *hw,
 186                                       u8 rpwm_val)
 187 {
 188         struct rtl_priv *rtlpriv = rtl_priv(hw);
 189         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 190         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 191         struct rtl8192_tx_ring *ring;
 192         enum rf_pwrstate rtstate;
 193         bool schedule_timer = false;
 194         u8 queue;
 195
 196         if (!rtlhal->fw_ready)
 197                 return;
 198         if (!rtlpriv->psc.fw_current_inpsmode)
 199                 return;
 200         if (!rtlhal->allow_sw_to_change_hwclc)
 201                 return;
 202         rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_RF_STATE, (u8 *)(&rtstate));
 203         if (rtstate == ERFOFF || rtlpriv->psc.inactive_pwrstate == ERFOFF)
 204                 return;
 205
 206         for (queue = 0; queue < RTL_PCI_MAX_TX_QUEUE_COUNT; queue++) {
 207                 ring = &rtlpci->tx_ring[queue];
 208                 if (skb_queue_len(&ring->queue)) {
 209                         schedule_timer = true;
 210                         break;
 211                 }
 212         }
 213
 214         if (schedule_timer) {
 215                 mod_timer(&rtlpriv->works.fw_clockoff_timer,
 216                           jiffies + MSECS(10));
 217                 return;
 218         }
 219
 220         if (FW_PS_STATE(rtlhal->fw_ps_state) !=
 221             FW_PS_STATE_RF_OFF_LOW_PWR_88E) {
 222                 spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 223                 if (!rtlhal->fw_clk_change_in_progress) {
 224                         rtlhal->fw_clk_change_in_progress = true;
 225                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 226                         rtlhal->fw_ps_state = FW_PS_STATE(rpwm_val);
 227                         rtl_write_word(rtlpriv, REG_HISR, 0x0100);
 228                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM,
 229                                                       &rpwm_val);
 230                         spin_lock_bh(&rtlpriv->locks.fw_ps_lock);
 231                         rtlhal->fw_clk_change_in_progress = false;
 232                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 233                 } else {
 234                         spin_unlock_bh(&rtlpriv->locks.fw_ps_lock);
 235                         mod_timer(&rtlpriv->works.fw_clockoff_timer,
 236                                   jiffies + MSECS(10));
 237                 }
 238         }
 239 }
 240
 241 static void _rtl88ee_set_fw_ps_rf_on(struct ieee80211_hw *hw)
 242 {
 243         u8 rpwm_val = 0;
 244
 245         rpwm_val |= (FW_PS_STATE_RF_OFF_88E | FW_PS_ACK);
 246         _rtl88ee_set_fw_clock_on(hw, rpwm_val, true);
 247 }
 248
 249 static void _rtl88ee_set_fw_ps_rf_off_low_power(struct ieee80211_hw *hw)
 250 {
 251         u8 rpwm_val = 0;
 252         rpwm_val |= FW_PS_STATE_RF_OFF_LOW_PWR_88E;
 253         _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 254 }
 255 void rtl88ee_fw_clk_off_timer_callback(unsigned long data)
 256 {
 257         struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
 258
 259         _rtl88ee_set_fw_ps_rf_off_low_power(hw);
 260 }
 261
 262 static void _rtl88ee_fwlps_leave(struct ieee80211_hw *hw)
 263 {
 264         struct rtl_priv *rtlpriv = rtl_priv(hw);
 265         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 266         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 267         bool fw_current_inps = false;
 268         u8 rpwm_val = 0, fw_pwrmode = FW_PS_ACTIVE_MODE;
 269
 270         if (ppsc->low_power_enable) {
 271                 rpwm_val = (FW_PS_STATE_ALL_ON_88E|FW_PS_ACK);/* RF on */
 272                 _rtl88ee_set_fw_clock_on(hw, rpwm_val, false);
 273                 rtlhal->allow_sw_to_change_hwclc = false;
 274                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 275                                               &fw_pwrmode);
 276                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 277                                               (u8 *)(&fw_current_inps));
 278         } else {
 279                 rpwm_val = FW_PS_STATE_ALL_ON_88E;      /* RF on */
 280                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 281                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 282                                               &fw_pwrmode);
 283                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 284                                               (u8 *)(&fw_current_inps));
 285         }
 286 }
 287
 288 static void _rtl88ee_fwlps_enter(struct ieee80211_hw *hw)
 289 {
 290         struct rtl_priv *rtlpriv = rtl_priv(hw);
 291         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 292         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 293         bool fw_current_inps = true;
 294         u8 rpwm_val;
 295
 296         if (ppsc->low_power_enable) {
 297                 rpwm_val = FW_PS_STATE_RF_OFF_LOW_PWR_88E;      /* RF off */
 298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 299                                               (u8 *)(&fw_current_inps));
 300                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 301                                               &ppsc->fwctrl_psmode);
 302                 rtlhal->allow_sw_to_change_hwclc = true;
 303                 _rtl88ee_set_fw_clock_off(hw, rpwm_val);
 304         } else {
 305                 rpwm_val = FW_PS_STATE_RF_OFF_88E;      /* RF off */
 306                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
 307                                               (u8 *)(&fw_current_inps));
 308                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_H2C_FW_PWRMODE,
 309                                               &ppsc->fwctrl_psmode);
 310                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SET_RPWM, &rpwm_val);
 311         }
 312 }
 313
 314 void rtl88ee_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 315 {
 316         struct rtl_priv *rtlpriv = rtl_priv(hw);
 317         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 318         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 319
 320         switch (variable) {
 321         case HW_VAR_RCR:
 322                 *((u32 *)(val)) = rtlpci->receive_config;
 323                 break;
 324         case HW_VAR_RF_STATE:
 325                 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
 326                 break;
 327         case HW_VAR_FWLPS_RF_ON:{
 328                 enum rf_pwrstate rfstate;
 329                 u32 val_rcr;
 330
 331                 rtlpriv->cfg->ops->get_hw_reg(hw,
 332                                               HW_VAR_RF_STATE,
 333                                               (u8 *)(&rfstate));
 334                 if (rfstate == ERFOFF) {
 335                         *((bool *)(val)) = true;
 336                 } else {
 337                         val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
 338                         val_rcr &= 0x00070000;
 339                         if (val_rcr)
 340                                 *((bool *)(val)) = false;
 341                         else
 342                                 *((bool *)(val)) = true;
 343                 }
 344                 break; }
 345         case HW_VAR_FW_PSMODE_STATUS:
 346                 *((bool *)(val)) = ppsc->fw_current_inpsmode;
 347                 break;
 348         case HW_VAR_CORRECT_TSF:{
 349                 u64 tsf;
 350                 u32 *ptsf_low = (u32 *)&tsf;
 351                 u32 *ptsf_high = ((u32 *)&tsf) + 1;
 352
 353                 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
 354                 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
 355
 356                 *((u64 *)(val)) = tsf;
 357                 break; }
 358         case HAL_DEF_WOWLAN:
 359                 break;
 360         default:
 361                 pr_err("switch case %#x not processed\n", variable);
 362                 break;
 363         }
 364 }
 365
 366 void rtl88ee_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
 367 {
 368         struct rtl_priv *rtlpriv = rtl_priv(hw);
 369         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 370         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
 371         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
 372         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 373         u8 idx;
 374
 375         switch (variable) {
 376         case HW_VAR_ETHER_ADDR:
 377                 for (idx = 0; idx < ETH_ALEN; idx++) {
 378                         rtl_write_byte(rtlpriv, (REG_MACID + idx),
 379                                        val[idx]);
 380                 }
 381                 break;
 382         case HW_VAR_BASIC_RATE:{
 383                 u16 b_rate_cfg = ((u16 *)val)[0];
 384                 u8 rate_index = 0;
 385                 b_rate_cfg = b_rate_cfg & 0x15f;
 386                 b_rate_cfg |= 0x01;
 387                 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
 388                 rtl_write_byte(rtlpriv, REG_RRSR + 1,
 389                                (b_rate_cfg >> 8) & 0xff);
 390                 while (b_rate_cfg > 0x1) {
 391                         b_rate_cfg = (b_rate_cfg >> 1);
 392                         rate_index++;
 393                 }
 394                 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
 395                                rate_index);
 396                 break;
 397                 }
 398         case HW_VAR_BSSID:
 399                 for (idx = 0; idx < ETH_ALEN; idx++) {
 400                         rtl_write_byte(rtlpriv, (REG_BSSID + idx),
 401                                        val[idx]);
 402                 }
 403                 break;
 404         case HW_VAR_SIFS:
 405                 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
 406                 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
 407
 408                 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
 409                 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
 410
 411                 if (!mac->ht_enable)
 412                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 413                                        0x0e0e);
 414                 else
 415                         rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
 416                                        *((u16 *)val));
 417                 break;
 418         case HW_VAR_SLOT_TIME:{
 419                 u8 e_aci;
 420
 421                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 422                          "HW_VAR_SLOT_TIME %x\n", val[0]);
 423
 424                 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
 425
 426                 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
 427                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AC_PARAM,
 428                                                       &e_aci);
 429                 }
 430                 break;
 431                 }
 432         case HW_VAR_ACK_PREAMBLE:{
 433                 u8 reg_tmp;
 434                 u8 short_preamble = (bool)*val;
 435                 reg_tmp = rtl_read_byte(rtlpriv, REG_TRXPTCL_CTL+2);
 436                 if (short_preamble) {
 437                         reg_tmp |= 0x02;
 438                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 439                                        2, reg_tmp);
 440                 } else {
 441                         reg_tmp |= 0xFD;
 442                         rtl_write_byte(rtlpriv, REG_TRXPTCL_CTL +
 443                                        2, reg_tmp);
 444                 }
 445                 break; }
 446         case HW_VAR_WPA_CONFIG:
 447                 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
 448                 break;
 449         case HW_VAR_AMPDU_MIN_SPACE:{
 450                 u8 min_spacing_to_set;
 451                 u8 sec_min_space;
 452
 453                 min_spacing_to_set = *val;
 454                 if (min_spacing_to_set <= 7) {
 455                         sec_min_space = 0;
 456
 457                         if (min_spacing_to_set < sec_min_space)
 458                                 min_spacing_to_set = sec_min_space;
 459
 460                         mac->min_space_cfg = ((mac->min_space_cfg &
 461                                                0xf8) |
 462                                               min_spacing_to_set);
 463
 464                         *val = min_spacing_to_set;
 465
 466                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 467                                  "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
 468                                   mac->min_space_cfg);
 469
 470                         rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 471                                        mac->min_space_cfg);
 472                 }
 473                 break; }
 474         case HW_VAR_SHORTGI_DENSITY:{
 475                 u8 density_to_set;
 476
 477                 density_to_set = *val;
 478                 mac->min_space_cfg |= (density_to_set << 3);
 479
 480                 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 481                          "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
 482                           mac->min_space_cfg);
 483
 484                 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
 485                                mac->min_space_cfg);
 486                 break;
 487                 }
 488         case HW_VAR_AMPDU_FACTOR:{
 489                 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
 490                 u8 factor_toset;
 491                 u8 *p_regtoset = NULL;
 492                 u8 index = 0;
 493
 494                 p_regtoset = regtoset_normal;
 495
 496                 factor_toset = *val;
 497                 if (factor_toset <= 3) {
 498                         factor_toset = (1 << (factor_toset + 2));
 499                         if (factor_toset > 0xf)
 500                                 factor_toset = 0xf;
 501
 502                         for (index = 0; index < 4; index++) {
 503                                 if ((p_regtoset[index] & 0xf0) >
 504                                     (factor_toset << 4))
 505                                         p_regtoset[index] =
 506                                             (p_regtoset[index] & 0x0f) |
 507                                             (factor_toset << 4);
 508
 509                                 if ((p_regtoset[index] & 0x0f) >
 510                                     factor_toset)
 511                                         p_regtoset[index] =
 512                                             (p_regtoset[index] & 0xf0) |
 513                                             (factor_toset);
 514
 515                                 rtl_write_byte(rtlpriv,
 516                                                (REG_AGGLEN_LMT + index),
 517                                                p_regtoset[index]);
 518
 519                         }
 520
 521                         RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
 522                                  "Set HW_VAR_AMPDU_FACTOR: %#x\n",
 523                                   factor_toset);
 524                 }
 525                 break; }
 526         case HW_VAR_AC_PARAM:{
 527                 u8 e_aci = *val;
 528                 rtl88e_dm_init_edca_turbo(hw);
 529
 530                 if (rtlpci->acm_method != EACMWAY2_SW)
 531                         rtlpriv->cfg->ops->set_hw_reg(hw,
 532                                                       HW_VAR_ACM_CTRL,
 533                                                       &e_aci);
 534                 break; }
 535         case HW_VAR_ACM_CTRL:{
 536                 u8 e_aci = *val;
 537                 union aci_aifsn *p_aci_aifsn =
 538                     (union aci_aifsn *)(&(mac->ac[0].aifs));
 539                 u8 acm = p_aci_aifsn->f.acm;
 540                 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
 541
 542                 acm_ctrl = acm_ctrl |
 543                            ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
 544
 545                 if (acm) {
 546                         switch (e_aci) {
 547                         case AC0_BE:
 548                                 acm_ctrl |= ACMHW_BEQEN;
 549                                 break;
 550                         case AC2_VI:
 551                                 acm_ctrl |= ACMHW_VIQEN;
 552                                 break;
 553                         case AC3_VO:
 554                                 acm_ctrl |= ACMHW_VOQEN;
 555                                 break;
 556                         default:
 557                                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
 558                                          "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
 559                                          acm);
 560                                 break;
 561                         }
 562                 } else {
 563                         switch (e_aci) {
 564                         case AC0_BE:
 565                                 acm_ctrl &= (~ACMHW_BEQEN);
 566                                 break;
 567                         case AC2_VI:
 568                                 acm_ctrl &= (~ACMHW_VIQEN);
 569                                 break;
 570                         case AC3_VO:
 571                                 acm_ctrl &= (~ACMHW_VOQEN);
 572                                 break;
 573                         default:
 574                                 pr_err("switch case %#x not processed\n",
 575                                        e_aci);
 576                                 break;
 577                         }
 578                 }
 579
 580                 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
 581                          "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
 582                          acm_ctrl);
 583                 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
 584                 break; }
 585         case HW_VAR_RCR:
 586                 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
 587                 rtlpci->receive_config = ((u32 *)(val))[0];
 588                 break;
 589         case HW_VAR_RETRY_LIMIT:{
 590                 u8 retry_limit = *val;
 591
 592                 rtl_write_word(rtlpriv, REG_RL,
 593                                retry_limit << RETRY_LIMIT_SHORT_SHIFT |
 594                                retry_limit << RETRY_LIMIT_LONG_SHIFT);
 595                 break; }
 596         case HW_VAR_DUAL_TSF_RST:
 597                 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
 598                 break;
 599         case HW_VAR_EFUSE_BYTES:
 600                 rtlefuse->efuse_usedbytes = *((u16 *)val);
 601                 break;
 602         case HW_VAR_EFUSE_USAGE:
 603                 rtlefuse->efuse_usedpercentage = *val;
 604                 break;
 605         case HW_VAR_IO_CMD:
 606                 rtl88e_phy_set_io_cmd(hw, (*(enum io_type *)val));
 607                 break;
 608         case HW_VAR_SET_RPWM:{
 609                 u8 rpwm_val;
 610
 611                 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
 612                 udelay(1);
 613
 614                 if (rpwm_val & BIT(7)) {
 615                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
 616                 } else {
 617                         rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val | BIT(7));
 618                 }
 619                 break; }
 620         case HW_VAR_H2C_FW_PWRMODE:
 621                 rtl88e_set_fw_pwrmode_cmd(hw, *val);
 622                 break;
 623         case HW_VAR_FW_PSMODE_STATUS:
 624                 ppsc->fw_current_inpsmode = *((bool *)val);
 625                 break;
 626         case HW_VAR_RESUME_CLK_ON:
 627                 _rtl88ee_set_fw_ps_rf_on(hw);
 628                 break;
 629         case HW_VAR_FW_LPS_ACTION:{
 630                 bool enter_fwlps = *((bool *)val);
 631
 632                 if (enter_fwlps)
 633                         _rtl88ee_fwlps_enter(hw);
 634                  else
 635                         _rtl88ee_fwlps_leave(hw);
 636
 637                  break; }
 638         case HW_VAR_H2C_FW_JOINBSSRPT:{
 639                 u8 mstatus = *val;
 640                 u8 tmp_regcr, tmp_reg422, bcnvalid_reg;
 641                 u8 count = 0, dlbcn_count = 0;
 642                 bool b_recover = false;
 643
 644                 if (mstatus == RT_MEDIA_CONNECT) {
 645                         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
 646                                                       NULL);
 647
 648                         tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
 649                         rtl_write_byte(rtlpriv, REG_CR + 1,
 650                                        (tmp_regcr | BIT(0)));
 651
 652                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 653                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
 654
 655                         tmp_reg422 =
 656                             rtl_read_byte(rtlpriv,
 657                                           REG_FWHW_TXQ_CTRL + 2);
 658                         rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
 659                                        tmp_reg422 & (~BIT(6)));
 660                         if (tmp_reg422 & BIT(6))
 661                                 b_recover = true;
 662
 663                         do {
 664                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 665                                                              REG_TDECTRL+2);
 666                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2,
 667                                                (bcnvalid_reg | BIT(0)));
 668                                 _rtl88ee_return_beacon_queue_skb(hw);
 669
 670                                 rtl88e_set_fw_rsvdpagepkt(hw, 0);
 671                                 bcnvalid_reg = rtl_read_byte(rtlpriv,
 672                                                              REG_TDECTRL+2);
 673                                 count = 0;
 674                                 while (!(bcnvalid_reg & BIT(0)) && count < 20) {
 675                                         count++;
 676                                         udelay(10);
 677                                         bcnvalid_reg =
 678                                           rtl_read_byte(rtlpriv, REG_TDECTRL+2);
 679                                 }
 680                                 dlbcn_count++;
 681                         } while (!(bcnvalid_reg & BIT(0)) && dlbcn_count < 5);
 682
 683                         if (bcnvalid_reg & BIT(0))
 684                                 rtl_write_byte(rtlpriv, REG_TDECTRL+2, BIT(0));
 685
 686                         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 687                         _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
 688
 689                         if (b_recover) {
 690                                 rtl_write_byte(rtlpriv,
 691                                                REG_FWHW_TXQ_CTRL + 2,
 692                                                tmp_reg422);
 693                         }
 694
 695                         rtl_write_byte(rtlpriv, REG_CR + 1,
 696                                        (tmp_regcr & ~(BIT(0))));
 697                 }
 698                 rtl88e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
 699                 break; }
 700         case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
 701                 rtl88e_set_p2p_ps_offload_cmd(hw, *val);
 702                 break;
 703         case HW_VAR_AID:{
 704                 u16 u2btmp;
 705
 706                 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
 707                 u2btmp &= 0xC000;
 708                 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
 709                                mac->assoc_id));
 710                 break; }
 711         case HW_VAR_CORRECT_TSF:{
 712                 u8 btype_ibss = *val;
 713
 714                 if (btype_ibss)
 715                         _rtl88ee_stop_tx_beacon(hw);
 716
 717                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(3));
 718
 719                 rtl_write_dword(rtlpriv, REG_TSFTR,
 720                                 (u32)(mac->tsf & 0xffffffff));
 721                 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
 722                                 (u32)((mac->tsf >> 32) & 0xffffffff));
 723
 724                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
 725
 726                 if (btype_ibss)
 727                         _rtl88ee_resume_tx_beacon(hw);
 728                 break; }
 729         case HW_VAR_KEEP_ALIVE: {
 730                 u8 array[2];
 731
 732                 array[0] = 0xff;
 733                 array[1] = *((u8 *)val);
 734                 rtl88e_fill_h2c_cmd(hw, H2C_88E_KEEP_ALIVE_CTRL,
 735                                     2, array);
 736                 break; }
 737         default:
 738                 pr_err("switch case %#x not processed\n", variable);
 739                 break;
 740         }
 741 }
 742
 743 static bool _rtl88ee_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
 744 {
 745         struct rtl_priv *rtlpriv = rtl_priv(hw);
 746         bool status = true;
 747         long count = 0;
 748         u32 value = _LLT_INIT_ADDR(address) | _LLT_INIT_DATA(data) |
 749                     _LLT_OP(_LLT_WRITE_ACCESS);
 750
 751         rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
 752
 753         do {
 754                 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
 755                 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
 756                         break;
 757
 758                 if (count > POLLING_LLT_THRESHOLD) {
 759                         pr_err("Failed to polling write LLT done at address %d!\n",
 760                                address);
 761                         status = false;
 762                         break;
 763                 }
 764         } while (++count);
 765
 766         return status;
 767 }
 768
 769 static bool _rtl88ee_llt_table_init(struct ieee80211_hw *hw)
 770 {
 771         struct rtl_priv *rtlpriv = rtl_priv(hw);
 772         unsigned short i;
 773         u8 txpktbuf_bndy;
 774         u8 maxpage;
 775         bool status;
 776
 777         maxpage = 0xAF;
 778         txpktbuf_bndy = 0xAB;
 779
 780         rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x01);
 781         rtl_write_dword(rtlpriv, REG_RQPN, 0x80730d29);
 782
 783         /*0x2600   MaxRxBuff=10k-max(TxReportSize(64*8), WOLPattern(16*24)) */
 784         rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x25FF0000 | txpktbuf_bndy));
 785         rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
 786
 787         rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
 788         rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
 789
 790         rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
 791         rtl_write_byte(rtlpriv, REG_PBP, 0x11);
 792         rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
 793
 794         for (i = 0; i < (txpktbuf_bndy - 1); i++) {
 795                 status = _rtl88ee_llt_write(hw, i, i + 1);
 796                 if (true != status)
 797                         return status;
 798         }
 799
 800         status = _rtl88ee_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
 801         if (true != status)
 802                 return status;
 803
 804         for (i = txpktbuf_bndy; i < maxpage; i++) {
 805                 status = _rtl88ee_llt_write(hw, i, (i + 1));
 806                 if (true != status)
 807                         return status;
 808         }
 809
 810         status = _rtl88ee_llt_write(hw, maxpage, txpktbuf_bndy);
 811         if (true != status)
 812                 return status;
 813
 814         return true;
 815 }
 816
 817 static void _rtl88ee_gen_refresh_led_state(struct ieee80211_hw *hw)
 818 {
 819         struct rtl_priv *rtlpriv = rtl_priv(hw);
 820         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 821         struct rtl_led *pled0 = &rtlpriv->ledctl.sw_led0;
 822
 823         if (rtlpriv->rtlhal.up_first_time)
 824                 return;
 825
 826         if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
 827                 rtl88ee_sw_led_on(hw, pled0);
 828         else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
 829                 rtl88ee_sw_led_on(hw, pled0);
 830         else
 831                 rtl88ee_sw_led_off(hw, pled0);
 832 }
 833
 834 static bool _rtl88ee_init_mac(struct ieee80211_hw *hw)
 835 {
 836         struct rtl_priv *rtlpriv = rtl_priv(hw);
 837         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
 838         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
 839
 840         u8 bytetmp;
 841         u16 wordtmp;
 842
 843         /*Disable XTAL OUTPUT for power saving. YJ,add,111206. */
 844         bytetmp = rtl_read_byte(rtlpriv, REG_XCK_OUT_CTRL) & (~BIT(0));
 845         rtl_write_byte(rtlpriv, REG_XCK_OUT_CTRL, bytetmp);
 846         /*Auto Power Down to CHIP-off State*/
 847         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) & (~BIT(7));
 848         rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
 849
 850         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
 851         /* HW Power on sequence */
 852         if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK,
 853                                       PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK,
 854                                       RTL8188EE_NIC_ENABLE_FLOW)) {
 855                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 856                          "init MAC Fail as rtl_hal_pwrseqcmdparsing\n");
 857                 return false;
 858         }
 859
 860         bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO) | BIT(4);
 861         rtl_write_byte(rtlpriv, REG_APS_FSMCO, bytetmp);
 862
 863         bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
 864         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp|BIT(2));
 865
 866         bytetmp = rtl_read_byte(rtlpriv, REG_WATCH_DOG+1);
 867         rtl_write_byte(rtlpriv, REG_WATCH_DOG+1, bytetmp|BIT(7));
 868
 869         bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1);
 870         rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL_EXT+1, bytetmp|BIT(1));
 871
 872         bytetmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
 873         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, bytetmp|BIT(1)|BIT(0));
 874         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL+1, 2);
 875         rtl_write_word(rtlpriv, REG_TX_RPT_TIME, 0xcdf0);
 876
 877         /*Add for wake up online*/
 878         bytetmp = rtl_read_byte(rtlpriv, REG_SYS_CLKR);
 879
 880         rtl_write_byte(rtlpriv, REG_SYS_CLKR, bytetmp|BIT(3));
 881         bytetmp = rtl_read_byte(rtlpriv, REG_GPIO_MUXCFG+1);
 882         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG+1, (bytetmp & (~BIT(4))));
 883         rtl_write_byte(rtlpriv, 0x367, 0x80);
 884
 885         rtl_write_word(rtlpriv, REG_CR, 0x2ff);
 886         rtl_write_byte(rtlpriv, REG_CR+1, 0x06);
 887         rtl_write_byte(rtlpriv, MSR, 0x00);
 888
 889         if (!rtlhal->mac_func_enable) {
 890                 if (_rtl88ee_llt_table_init(hw) == false) {
 891                         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
 892                                  "LLT table init fail\n");
 893                         return false;
 894                 }
 895         }
 896         rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
 897         rtl_write_dword(rtlpriv, REG_HISRE, 0xffffffff);
 898
 899         wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
 900         wordtmp &= 0xf;
 901         wordtmp |= 0xE771;
 902         rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
 903
 904         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
 905         rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xffff);
 906         rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
 907
 908         rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
 909                         ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
 910                         DMA_BIT_MASK(32));
 911         rtl_write_dword(rtlpriv, REG_MGQ_DESA,
 912                         (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
 913                         DMA_BIT_MASK(32));
 914         rtl_write_dword(rtlpriv, REG_VOQ_DESA,
 915                         (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
 916         rtl_write_dword(rtlpriv, REG_VIQ_DESA,
 917                         (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
 918         rtl_write_dword(rtlpriv, REG_BEQ_DESA,
 919                         (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
 920         rtl_write_dword(rtlpriv, REG_BKQ_DESA,
 921                         (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
 922         rtl_write_dword(rtlpriv, REG_HQ_DESA,
 923                         (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
 924                         DMA_BIT_MASK(32));
 925         rtl_write_dword(rtlpriv, REG_RX_DESA,
 926                         (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
 927                         DMA_BIT_MASK(32));
 928
 929         /* if we want to support 64 bit DMA, we should set it here,
 930          * but now we do not support 64 bit DMA
 931          */
 932         rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
 933
 934         rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
 935         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0);/*Enable RX DMA */
 936
 937         if (rtlhal->earlymode_enable) {/*Early mode enable*/
 938                 bytetmp = rtl_read_byte(rtlpriv, REG_EARLY_MODE_CONTROL);
 939                 bytetmp |= 0x1f;
 940                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL, bytetmp);
 941                 rtl_write_byte(rtlpriv, REG_EARLY_MODE_CONTROL+3, 0x81);
 942         }
 943         _rtl88ee_gen_refresh_led_state(hw);
 944         return true;
 945 }
 946
 947 static void _rtl88ee_hw_configure(struct ieee80211_hw *hw)
 948 {
 949         struct rtl_priv *rtlpriv = rtl_priv(hw);
 950         u8 reg_bw_opmode;
 951         u32 reg_ratr, reg_prsr;
 952
 953         reg_bw_opmode = BW_OPMODE_20MHZ;
 954         reg_ratr = RATE_ALL_CCK | RATE_ALL_OFDM_AG |
 955             RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 956         reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 957
 958         rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
 959         rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
 960 }
 961
 962 static void _rtl88ee_enable_aspm_back_door(struct ieee80211_hw *hw)
 963 {
 964         struct rtl_priv *rtlpriv = rtl_priv(hw);
 965         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
 966         u8 tmp1byte = 0;
 967         u32 tmp4byte = 0, count = 0;
 968
 969         rtl_write_word(rtlpriv, 0x354, 0x8104);
 970         rtl_write_word(rtlpriv, 0x358, 0x24);
 971
 972         rtl_write_word(rtlpriv, 0x350, 0x70c);
 973         rtl_write_byte(rtlpriv, 0x352, 0x2);
 974         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 975         count = 0;
 976         while (tmp1byte && count < 20) {
 977                 udelay(10);
 978                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 979                 count++;
 980         }
 981         if (0 == tmp1byte) {
 982                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
 983                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(31));
 984                 rtl_write_word(rtlpriv, 0x350, 0xf70c);
 985                 rtl_write_byte(rtlpriv, 0x352, 0x1);
 986         }
 987
 988         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 989         count = 0;
 990         while (tmp1byte && count < 20) {
 991                 udelay(10);
 992                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 993                 count++;
 994         }
 995
 996         rtl_write_word(rtlpriv, 0x350, 0x718);
 997         rtl_write_byte(rtlpriv, 0x352, 0x2);
 998         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
 999         count = 0;
1000         while (tmp1byte && count < 20) {
1001                 udelay(10);
1002                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1003                 count++;
1004         }
1005
1006         if (ppsc->support_backdoor || (0 == tmp1byte)) {
1007                 tmp4byte = rtl_read_dword(rtlpriv, 0x34c);
1008                 rtl_write_dword(rtlpriv, 0x348, tmp4byte|BIT(11)|BIT(12));
1009                 rtl_write_word(rtlpriv, 0x350, 0xf718);
1010                 rtl_write_byte(rtlpriv, 0x352, 0x1);
1011         }
1012
1013         tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1014         count = 0;
1015         while (tmp1byte && count < 20) {
1016                 udelay(10);
1017                 tmp1byte = rtl_read_byte(rtlpriv, 0x352);
1018                 count++;
1019         }
1020 }
1021
1022 void rtl88ee_enable_hw_security_config(struct ieee80211_hw *hw)
1023 {
1024         struct rtl_priv *rtlpriv = rtl_priv(hw);
1025         u8 sec_reg_value;
1026
1027         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1028                  "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
1029                   rtlpriv->sec.pairwise_enc_algorithm,
1030                   rtlpriv->sec.group_enc_algorithm);
1031
1032         if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
1033                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1034                          "not open hw encryption\n");
1035                 return;
1036         }
1037
1038         sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
1039
1040         if (rtlpriv->sec.use_defaultkey) {
1041                 sec_reg_value |= SCR_TXUSEDK;
1042                 sec_reg_value |= SCR_RXUSEDK;
1043         }
1044
1045         sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
1046
1047         rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
1048
1049         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
1050                  "The SECR-value %x\n", sec_reg_value);
1051
1052         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
1053 }
1054
1055 int rtl88ee_hw_init(struct ieee80211_hw *hw)
1056 {
1057         struct rtl_priv *rtlpriv = rtl_priv(hw);
1058         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1059         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1060         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1061         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1062         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1063         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1064         bool rtstatus = true;
1065         int err = 0;
1066         u8 tmp_u1b, u1byte;
1067         unsigned long flags;
1068
1069         rtlpriv->rtlhal.being_init_adapter = true;
1070         /* As this function can take a very long time (up to 350 ms)
1071          * and can be called with irqs disabled, reenable the irqs
1072          * to let the other devices continue being serviced.
1073          *
1074          * It is safe doing so since our own interrupts will only be enabled
1075          * in a subsequent step.
1076          */
1077         local_save_flags(flags);
1078         local_irq_enable();
1079         rtlhal->fw_ready = false;
1080
1081         rtlpriv->intf_ops->disable_aspm(hw);
1082
1083         tmp_u1b = rtl_read_byte(rtlpriv, REG_SYS_CLKR+1);
1084         u1byte = rtl_read_byte(rtlpriv, REG_CR);
1085         if ((tmp_u1b & BIT(3)) && (u1byte != 0 && u1byte != 0xEA)) {
1086                 rtlhal->mac_func_enable = true;
1087         } else {
1088                 rtlhal->mac_func_enable = false;
1089                 rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1090         }
1091
1092         rtstatus = _rtl88ee_init_mac(hw);
1093         if (rtstatus != true) {
1094                 pr_info("Init MAC failed\n");
1095                 err = 1;
1096                 goto exit;
1097         }
1098
1099         err = rtl88e_download_fw(hw, false);
1100         if (err) {
1101                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1102                          "Failed to download FW. Init HW without FW now..\n");
1103                 err = 1;
1104                 goto exit;
1105         }
1106         rtlhal->fw_ready = true;
1107         /*fw related variable initialize */
1108         rtlhal->last_hmeboxnum = 0;
1109         rtlhal->fw_ps_state = FW_PS_STATE_ALL_ON_88E;
1110         rtlhal->fw_clk_change_in_progress = false;
1111         rtlhal->allow_sw_to_change_hwclc = false;
1112         ppsc->fw_current_inpsmode = false;
1113
1114         rtl88e_phy_mac_config(hw);
1115         /* because last function modify RCR, so we update
1116          * rcr var here, or TP will unstable for receive_config
1117          * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
1118          * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
1119          */
1120         rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
1121         rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
1122
1123         rtl88e_phy_bb_config(hw);
1124         rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
1125         rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
1126
1127         rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
1128         rtl88e_phy_rf_config(hw);
1129
1130         rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
1131                                                  RF_CHNLBW, RFREG_OFFSET_MASK);
1132         rtlphy->rfreg_chnlval[0] = rtlphy->rfreg_chnlval[0] & 0xfff00fff;
1133
1134         _rtl88ee_hw_configure(hw);
1135         rtl_cam_reset_all_entry(hw);
1136         rtl88ee_enable_hw_security_config(hw);
1137
1138         rtlhal->mac_func_enable = true;
1139         ppsc->rfpwr_state = ERFON;
1140
1141         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
1142         _rtl88ee_enable_aspm_back_door(hw);
1143         rtlpriv->intf_ops->enable_aspm(hw);
1144
1145         if (ppsc->rfpwr_state == ERFON) {
1146                 if ((rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV) ||
1147                     ((rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV) &&
1148                      (rtlhal->oem_id == RT_CID_819X_HP))) {
1149                         rtl88e_phy_set_rfpath_switch(hw, true);
1150                         rtlpriv->dm.fat_table.rx_idle_ant = MAIN_ANT;
1151                 } else {
1152                         rtl88e_phy_set_rfpath_switch(hw, false);
1153                         rtlpriv->dm.fat_table.rx_idle_ant = AUX_ANT;
1154                 }
1155                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "rx idle ant %s\n",
1156                          (rtlpriv->dm.fat_table.rx_idle_ant == MAIN_ANT) ?
1157                          ("MAIN_ANT") : ("AUX_ANT"));
1158
1159                 if (rtlphy->iqk_initialized) {
1160                         rtl88e_phy_iq_calibrate(hw, true);
1161                 } else {
1162                         rtl88e_phy_iq_calibrate(hw, false);
1163                         rtlphy->iqk_initialized = true;
1164                 }
1165
1166                 rtl88e_dm_check_txpower_tracking(hw);
1167                 rtl88e_phy_lc_calibrate(hw);
1168         }
1169
1170         tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1171         if (!(tmp_u1b & BIT(0))) {
1172                 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1173                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "PA BIAS path A\n");
1174         }
1175
1176         if (!(tmp_u1b & BIT(4))) {
1177                 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1178                 tmp_u1b &= 0x0F;
1179                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1180                 udelay(10);
1181                 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1182                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "under 1.5V\n");
1183         }
1184         rtl_write_byte(rtlpriv, REG_NAV_CTRL+2,  ((30000+127)/128));
1185         rtl88e_dm_init(hw);
1186 exit:
1187         local_irq_restore(flags);
1188         rtlpriv->rtlhal.being_init_adapter = false;
1189         return err;
1190 }
1191
1192 static enum version_8188e _rtl88ee_read_chip_version(struct ieee80211_hw *hw)
1193 {
1194         struct rtl_priv *rtlpriv = rtl_priv(hw);
1195         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1196         enum version_8188e version = VERSION_UNKNOWN;
1197         u32 value32;
1198
1199         value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1200         if (value32 & TRP_VAUX_EN) {
1201                 version = (enum version_8188e) VERSION_TEST_CHIP_88E;
1202         } else {
1203                 version = NORMAL_CHIP;
1204                 version = version | ((value32 & TYPE_ID) ? RF_TYPE_2T2R : 0);
1205                 version = version | ((value32 & VENDOR_ID) ?
1206                           CHIP_VENDOR_UMC : 0);
1207         }
1208
1209         rtlphy->rf_type = RF_1T1R;
1210         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1211                  "Chip RF Type: %s\n", (rtlphy->rf_type == RF_2T2R) ?
1212                  "RF_2T2R" : "RF_1T1R");
1213
1214         return version;
1215 }
1216
1217 static int _rtl88ee_set_media_status(struct ieee80211_hw *hw,
1218                                      enum nl80211_iftype type)
1219 {
1220         struct rtl_priv *rtlpriv = rtl_priv(hw);
1221         u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1222         enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1223         u8 mode = MSR_NOLINK;
1224
1225         switch (type) {
1226         case NL80211_IFTYPE_UNSPECIFIED:
1227                 mode = MSR_NOLINK;
1228                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1229                          "Set Network type to NO LINK!\n");
1230                 break;
1231         case NL80211_IFTYPE_ADHOC:
1232         case NL80211_IFTYPE_MESH_POINT:
1233                 mode = MSR_ADHOC;
1234                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1235                          "Set Network type to Ad Hoc!\n");
1236                 break;
1237         case NL80211_IFTYPE_STATION:
1238                 mode = MSR_INFRA;
1239                 ledaction = LED_CTL_LINK;
1240                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1241                          "Set Network type to STA!\n");
1242                 break;
1243         case NL80211_IFTYPE_AP:
1244                 mode = MSR_AP;
1245                 ledaction = LED_CTL_LINK;
1246                 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1247                          "Set Network type to AP!\n");
1248                 break;
1249         default:
1250                 pr_err("Network type %d not support!\n", type);
1251                 return 1;
1252                 break;
1253         }
1254
1255         /* MSR_INFRA == Link in infrastructure network;
1256          * MSR_ADHOC == Link in ad hoc network;
1257          * Therefore, check link state is necessary.
1258          *
1259          * MSR_AP == AP mode; link state is not cared here.
1260          */
1261         if (mode != MSR_AP && rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1262                 mode = MSR_NOLINK;
1263                 ledaction = LED_CTL_NO_LINK;
1264         }
1265
1266         if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1267                 _rtl88ee_stop_tx_beacon(hw);
1268                 _rtl88ee_enable_bcn_sub_func(hw);
1269         } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1270                 _rtl88ee_resume_tx_beacon(hw);
1271                 _rtl88ee_disable_bcn_sub_func(hw);
1272         } else {
1273                 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1274                          "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1275                          mode);
1276         }
1277
1278         rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1279         rtlpriv->cfg->ops->led_control(hw, ledaction);
1280         if (mode == MSR_AP)
1281                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1282         else
1283                 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1284         return 0;
1285 }
1286
1287 void rtl88ee_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1288 {
1289         struct rtl_priv *rtlpriv = rtl_priv(hw);
1290         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1291         u32 reg_rcr = rtlpci->receive_config;
1292
1293         if (rtlpriv->psc.rfpwr_state != ERFON)
1294                 return;
1295
1296         if (check_bssid == true) {
1297                 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1298                 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1299                                               (u8 *)(&reg_rcr));
1300                 _rtl88ee_set_bcn_ctrl_reg(hw, 0, BIT(4));
1301         } else if (check_bssid == false) {
1302                 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1303                 _rtl88ee_set_bcn_ctrl_reg(hw, BIT(4), 0);
1304                 rtlpriv->cfg->ops->set_hw_reg(hw,
1305                         HW_VAR_RCR, (u8 *)(&reg_rcr));
1306         }
1307
1308 }
1309
1310 int rtl88ee_set_network_type(struct ieee80211_hw *hw,
1311                              enum nl80211_iftype type)
1312 {
1313         struct rtl_priv *rtlpriv = rtl_priv(hw);
1314
1315         if (_rtl88ee_set_media_status(hw, type))
1316                 return -EOPNOTSUPP;
1317
1318         if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1319                 if (type != NL80211_IFTYPE_AP &&
1320                     type != NL80211_IFTYPE_MESH_POINT)
1321                         rtl88ee_set_check_bssid(hw, true);
1322         } else {
1323                 rtl88ee_set_check_bssid(hw, false);
1324         }
1325
1326         return 0;
1327 }
1328
1329 /* don't set REG_EDCA_BE_PARAM here
1330  * because mac80211 will send pkt when scan
1331  */
1332 void rtl88ee_set_qos(struct ieee80211_hw *hw, int aci)
1333 {
1334         struct rtl_priv *rtlpriv = rtl_priv(hw);
1335         rtl88e_dm_init_edca_turbo(hw);
1336         switch (aci) {
1337         case AC1_BK:
1338                 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1339                 break;
1340         case AC0_BE:
1341                 break;
1342         case AC2_VI:
1343                 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1344                 break;
1345         case AC3_VO:
1346                 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1347                 break;
1348         default:
1349                 WARN_ONCE(true, "rtl8188ee: invalid aci: %d !\n", aci);
1350                 break;
1351         }
1352 }
1353
1354 void rtl88ee_enable_interrupt(struct ieee80211_hw *hw)
1355 {
1356         struct rtl_priv *rtlpriv = rtl_priv(hw);
1357         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1358
1359         rtl_write_dword(rtlpriv, REG_HIMR,
1360                         rtlpci->irq_mask[0] & 0xFFFFFFFF);
1361         rtl_write_dword(rtlpriv, REG_HIMRE,
1362                         rtlpci->irq_mask[1] & 0xFFFFFFFF);
1363         rtlpci->irq_enabled = true;
1364         /* there are some C2H CMDs have been sent
1365          * before system interrupt is enabled, e.g., C2H, CPWM.
1366          * So we need to clear all C2H events that FW has notified,
1367          * otherwise FW won't schedule any commands anymore.
1368          */
1369         rtl_write_byte(rtlpriv, REG_C2HEVT_CLEAR, 0);
1370         /*enable system interrupt*/
1371         rtl_write_dword(rtlpriv, REG_HSIMR,
1372                         rtlpci->sys_irq_mask & 0xFFFFFFFF);
1373 }
1374
1375 void rtl88ee_disable_interrupt(struct ieee80211_hw *hw)
1376 {
1377         struct rtl_priv *rtlpriv = rtl_priv(hw);
1378         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1379
1380         rtl_write_dword(rtlpriv, REG_HIMR, IMR_DISABLED);
1381         rtl_write_dword(rtlpriv, REG_HIMRE, IMR_DISABLED);
1382         rtlpci->irq_enabled = false;
1383         /*synchronize_irq(rtlpci->pdev->irq);*/
1384 }
1385
1386 static void _rtl88ee_poweroff_adapter(struct ieee80211_hw *hw)
1387 {
1388         struct rtl_priv *rtlpriv = rtl_priv(hw);
1389         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1390         u8 u1b_tmp;
1391         u32 count = 0;
1392         rtlhal->mac_func_enable = false;
1393         rtlpriv->intf_ops->enable_aspm(hw);
1394
1395         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "POWER OFF adapter\n");
1396         u1b_tmp = rtl_read_byte(rtlpriv, REG_TX_RPT_CTRL);
1397         rtl_write_byte(rtlpriv, REG_TX_RPT_CTRL, u1b_tmp & (~BIT(1)));
1398
1399         u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1400         while (!(u1b_tmp & BIT(1)) && (count++ < 100)) {
1401                 udelay(10);
1402                 u1b_tmp = rtl_read_byte(rtlpriv, REG_RXDMA_CONTROL);
1403                 count++;
1404         }
1405         rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+1, 0xFF);
1406
1407         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1408                                  PWR_INTF_PCI_MSK,
1409                                  RTL8188EE_NIC_LPS_ENTER_FLOW);
1410
1411         rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1412
1413         if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) && rtlhal->fw_ready)
1414                 rtl88e_firmware_selfreset(hw);
1415
1416         u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1417         rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, (u1b_tmp & (~BIT(2))));
1418         rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1419
1420         u1b_tmp = rtl_read_byte(rtlpriv, REG_32K_CTRL);
1421         rtl_write_byte(rtlpriv, REG_32K_CTRL, (u1b_tmp & (~BIT(0))));
1422
1423         rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1424                                  PWR_INTF_PCI_MSK, RTL8188EE_NIC_DISABLE_FLOW);
1425
1426         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1427         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp & (~BIT(3))));
1428         u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL+1);
1429         rtl_write_byte(rtlpriv, REG_RSV_CTRL+1, (u1b_tmp | BIT(3)));
1430
1431         rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0E);
1432
1433         u1b_tmp = rtl_read_byte(rtlpriv, GPIO_IN);
1434         rtl_write_byte(rtlpriv, GPIO_OUT, u1b_tmp);
1435         rtl_write_byte(rtlpriv, GPIO_IO_SEL, 0x7F);
1436
1437         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
1438         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL, (u1b_tmp << 4) | u1b_tmp);
1439         u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL+1);
1440         rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL+1, u1b_tmp | 0x0F);
1441
1442         rtl_write_dword(rtlpriv, REG_GPIO_IO_SEL_2+2, 0x00080808);
1443 }
1444
1445 void rtl88ee_card_disable(struct ieee80211_hw *hw)
1446 {
1447         struct rtl_priv *rtlpriv = rtl_priv(hw);
1448         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1449         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1450         enum nl80211_iftype opmode;
1451
1452         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "RTL8188ee card disable\n");
1453
1454         mac->link_state = MAC80211_NOLINK;
1455         opmode = NL80211_IFTYPE_UNSPECIFIED;
1456
1457         _rtl88ee_set_media_status(hw, opmode);
1458
1459         if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1460             ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1461                 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1462
1463         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1464         _rtl88ee_poweroff_adapter(hw);
1465
1466         /* after power off we should do iqk again */
1467         rtlpriv->phy.iqk_initialized = false;
1468 }
1469
1470 void rtl88ee_interrupt_recognized(struct ieee80211_hw *hw,
1471                                   u32 *p_inta, u32 *p_intb)
1472 {
1473         struct rtl_priv *rtlpriv = rtl_priv(hw);
1474         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1475
1476         *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1477         rtl_write_dword(rtlpriv, ISR, *p_inta);
1478
1479         *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1480         rtl_write_dword(rtlpriv, REG_HISRE, *p_intb);
1481
1482 }
1483
1484 void rtl88ee_set_beacon_related_registers(struct ieee80211_hw *hw)
1485 {
1486         struct rtl_priv *rtlpriv = rtl_priv(hw);
1487         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1488         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1489         u16 bcn_interval, atim_window;
1490
1491         bcn_interval = mac->beacon_interval;
1492         atim_window = 2;        /*FIX MERGE */
1493         rtl88ee_disable_interrupt(hw);
1494         rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1495         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1496         rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1497         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1498         rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1499         rtl_write_byte(rtlpriv, 0x606, 0x30);
1500         rtlpci->reg_bcn_ctrl_val |= BIT(3);
1501         rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
1502         /*rtl88ee_enable_interrupt(hw);*/
1503 }
1504
1505 void rtl88ee_set_beacon_interval(struct ieee80211_hw *hw)
1506 {
1507         struct rtl_priv *rtlpriv = rtl_priv(hw);
1508         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1509         u16 bcn_interval = mac->beacon_interval;
1510
1511         RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1512                  "beacon_interval:%d\n", bcn_interval);
1513         /*rtl88ee_disable_interrupt(hw);*/
1514         rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1515         /*rtl88ee_enable_interrupt(hw);*/
1516 }
1517
1518 void rtl88ee_update_interrupt_mask(struct ieee80211_hw *hw,
1519                                    u32 add_msr, u32 rm_msr)
1520 {
1521         struct rtl_priv *rtlpriv = rtl_priv(hw);
1522         struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1523
1524         RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD,
1525                  "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1526
1527         if (add_msr)
1528                 rtlpci->irq_mask[0] |= add_msr;
1529         if (rm_msr)
1530                 rtlpci->irq_mask[0] &= (~rm_msr);
1531         rtl88ee_disable_interrupt(hw);
1532         rtl88ee_enable_interrupt(hw);
1533 }
1534
1535 static u8 _rtl88e_get_chnl_group(u8 chnl)
1536 {
1537         u8 group = 0;
1538
1539         if (chnl < 3)
1540                 group = 0;
1541         else if (chnl < 6)
1542                 group = 1;
1543         else if (chnl < 9)
1544                 group = 2;
1545         else if (chnl < 12)
1546                 group = 3;
1547         else if (chnl < 14)
1548                 group = 4;
1549         else if (chnl == 14)
1550                 group = 5;
1551
1552         return group;
1553 }
1554
1555 static void set_24g_base(struct txpower_info_2g *pwrinfo24g, u32 rfpath)
1556 {
1557         int group, txcnt;
1558
1559         for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1560                 pwrinfo24g->index_cck_base[rfpath][group] = 0x2D;
1561                 pwrinfo24g->index_bw40_base[rfpath][group] = 0x2D;
1562         }
1563         for (txcnt = 0; txcnt < MAX_TX_COUNT; txcnt++) {
1564                 if (txcnt == 0) {
1565                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1566                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1567                 } else {
1568                         pwrinfo24g->bw20_diff[rfpath][txcnt] = 0xFE;
1569                         pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1570                         pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1571                         pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1572                 }
1573         }
1574 }
1575
1576 static void read_power_value_fromprom(struct ieee80211_hw *hw,
1577                                       struct txpower_info_2g *pwrinfo24g,
1578                                       struct txpower_info_5g *pwrinfo5g,
1579                                       bool autoload_fail, u8 *hwinfo)
1580 {
1581         struct rtl_priv *rtlpriv = rtl_priv(hw);
1582         u32 rfpath, eeaddr = EEPROM_TX_PWR_INX, group, txcnt = 0;
1583
1584         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1585                  "hal_ReadPowerValueFromPROM88E():PROMContent[0x%x]=0x%x\n",
1586                  (eeaddr+1), hwinfo[eeaddr+1]);
1587         if (0xFF == hwinfo[eeaddr+1])  /*YJ,add,120316*/
1588                 autoload_fail = true;
1589
1590         if (autoload_fail) {
1591                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1592                          "auto load fail : Use Default value!\n");
1593                 for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1594                         /* 2.4G default value */
1595                         set_24g_base(pwrinfo24g, rfpath);
1596                 }
1597                 return;
1598         }
1599
1600         for (rfpath = 0 ; rfpath < MAX_RF_PATH ; rfpath++) {
1601                 /*2.4G default value*/
1602                 for (group = 0 ; group < MAX_CHNL_GROUP_24G; group++) {
1603                         pwrinfo24g->index_cck_base[rfpath][group] =
1604                           hwinfo[eeaddr++];
1605                         if (pwrinfo24g->index_cck_base[rfpath][group] == 0xFF)
1606                                 pwrinfo24g->index_cck_base[rfpath][group] =
1607                                   0x2D;
1608                 }
1609                 for (group = 0 ; group < MAX_CHNL_GROUP_24G-1; group++) {
1610                         pwrinfo24g->index_bw40_base[rfpath][group] =
1611                                 hwinfo[eeaddr++];
1612                         if (pwrinfo24g->index_bw40_base[rfpath][group] == 0xFF)
1613                                 pwrinfo24g->index_bw40_base[rfpath][group] =
1614                                         0x2D;
1615                 }
1616                 pwrinfo24g->bw40_diff[rfpath][0] = 0;
1617                 if (hwinfo[eeaddr] == 0xFF) {
1618                         pwrinfo24g->bw20_diff[rfpath][0] = 0x02;
1619                 } else {
1620                         pwrinfo24g->bw20_diff[rfpath][0] =
1621                                 (hwinfo[eeaddr]&0xf0)>>4;
1622                         /*bit sign number to 8 bit sign number*/
1623                         if (pwrinfo24g->bw20_diff[rfpath][0] & BIT(3))
1624                                 pwrinfo24g->bw20_diff[rfpath][0] |= 0xF0;
1625                 }
1626
1627                 if (hwinfo[eeaddr] == 0xFF) {
1628                         pwrinfo24g->ofdm_diff[rfpath][0] = 0x04;
1629                 } else {
1630                         pwrinfo24g->ofdm_diff[rfpath][0] =
1631                                 (hwinfo[eeaddr]&0x0f);
1632                                 /*bit sign number to 8 bit sign number*/
1633                         if (pwrinfo24g->ofdm_diff[rfpath][0] & BIT(3))
1634                                 pwrinfo24g->ofdm_diff[rfpath][0] |= 0xF0;
1635                 }
1636                 pwrinfo24g->cck_diff[rfpath][0] = 0;
1637                 eeaddr++;
1638                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1639                         if (hwinfo[eeaddr] == 0xFF) {
1640                                 pwrinfo24g->bw40_diff[rfpath][txcnt] = 0xFE;
1641                         } else {
1642                                 pwrinfo24g->bw40_diff[rfpath][txcnt] =
1643                                   (hwinfo[eeaddr]&0xf0)>>4;
1644                                 if (pwrinfo24g->bw40_diff[rfpath][txcnt] &
1645                                     BIT(3))
1646                                         pwrinfo24g->bw40_diff[rfpath][txcnt] |=
1647                                           0xF0;
1648                         }
1649
1650                         if (hwinfo[eeaddr] == 0xFF) {
1651                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1652                                         0xFE;
1653                         } else {
1654                                 pwrinfo24g->bw20_diff[rfpath][txcnt] =
1655                                   (hwinfo[eeaddr]&0x0f);
1656                                 if (pwrinfo24g->bw20_diff[rfpath][txcnt] &
1657                                     BIT(3))
1658                                         pwrinfo24g->bw20_diff[rfpath][txcnt] |=
1659                                           0xF0;
1660                         }
1661                         eeaddr++;
1662
1663                         if (hwinfo[eeaddr] == 0xFF) {
1664                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] = 0xFE;
1665                         } else {
1666                                 pwrinfo24g->ofdm_diff[rfpath][txcnt] =
1667                                   (hwinfo[eeaddr]&0xf0)>>4;
1668                                 if (pwrinfo24g->ofdm_diff[rfpath][txcnt] &
1669                                     BIT(3))
1670                                         pwrinfo24g->ofdm_diff[rfpath][txcnt] |=
1671                                           0xF0;
1672                         }
1673
1674                         if (hwinfo[eeaddr] == 0xFF) {
1675                                 pwrinfo24g->cck_diff[rfpath][txcnt] =   0xFE;
1676                         } else {
1677                                 pwrinfo24g->cck_diff[rfpath][txcnt] =
1678                                   (hwinfo[eeaddr]&0x0f);
1679                                 if (pwrinfo24g->cck_diff[rfpath][txcnt] &
1680                                     BIT(3))
1681                                         pwrinfo24g->cck_diff[rfpath][txcnt] |=
1682                                           0xF0;
1683                         }
1684                         eeaddr++;
1685                 }
1686
1687                 /*5G default value*/
1688                 for (group = 0 ; group < MAX_CHNL_GROUP_5G; group++) {
1689                         pwrinfo5g->index_bw40_base[rfpath][group] =
1690                                 hwinfo[eeaddr++];
1691                         if (pwrinfo5g->index_bw40_base[rfpath][group] == 0xFF)
1692                                 pwrinfo5g->index_bw40_base[rfpath][group] =
1693                                   0xFE;
1694                 }
1695
1696                 pwrinfo5g->bw40_diff[rfpath][0] = 0;
1697
1698                 if (hwinfo[eeaddr] == 0xFF) {
1699                         pwrinfo5g->bw20_diff[rfpath][0] = 0;
1700                 } else {
1701                         pwrinfo5g->bw20_diff[rfpath][0] =
1702                           (hwinfo[eeaddr]&0xf0)>>4;
1703                         if (pwrinfo5g->bw20_diff[rfpath][0] & BIT(3))
1704                                 pwrinfo5g->bw20_diff[rfpath][0] |= 0xF0;
1705                 }
1706
1707                 if (hwinfo[eeaddr] == 0xFF) {
1708                         pwrinfo5g->ofdm_diff[rfpath][0] = 0x04;
1709                 } else {
1710                         pwrinfo5g->ofdm_diff[rfpath][0] = (hwinfo[eeaddr]&0x0f);
1711                         if (pwrinfo5g->ofdm_diff[rfpath][0] & BIT(3))
1712                                 pwrinfo5g->ofdm_diff[rfpath][0] |= 0xF0;
1713                 }
1714                 eeaddr++;
1715                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1716                         if (hwinfo[eeaddr] == 0xFF) {
1717                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =   0xFE;
1718                         } else {
1719                                 pwrinfo5g->bw40_diff[rfpath][txcnt] =
1720                                   (hwinfo[eeaddr]&0xf0)>>4;
1721                                 if (pwrinfo5g->bw40_diff[rfpath][txcnt] &
1722                                     BIT(3))
1723                                         pwrinfo5g->bw40_diff[rfpath][txcnt] |=
1724                                           0xF0;
1725                         }
1726
1727                         if (hwinfo[eeaddr] == 0xFF) {
1728                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =   0xFE;
1729                         } else {
1730                                 pwrinfo5g->bw20_diff[rfpath][txcnt] =
1731                                   (hwinfo[eeaddr]&0x0f);
1732                                 if (pwrinfo5g->bw20_diff[rfpath][txcnt] &
1733                                     BIT(3))
1734                                         pwrinfo5g->bw20_diff[rfpath][txcnt] |=
1735                                           0xF0;
1736                         }
1737                         eeaddr++;
1738                 }
1739
1740                 if (hwinfo[eeaddr] == 0xFF) {
1741                         pwrinfo5g->ofdm_diff[rfpath][1] = 0xFE;
1742                         pwrinfo5g->ofdm_diff[rfpath][2] = 0xFE;
1743                 } else {
1744                         pwrinfo5g->ofdm_diff[rfpath][1] =
1745                                         (hwinfo[eeaddr]&0xf0)>>4;
1746                         pwrinfo5g->ofdm_diff[rfpath][2] =
1747                                         (hwinfo[eeaddr]&0x0f);
1748                 }
1749                 eeaddr++;
1750
1751                 if (hwinfo[eeaddr] == 0xFF)
1752                         pwrinfo5g->ofdm_diff[rfpath][3] = 0xFE;
1753                 else
1754                         pwrinfo5g->ofdm_diff[rfpath][3] = (hwinfo[eeaddr]&0x0f);
1755                 eeaddr++;
1756
1757                 for (txcnt = 1; txcnt < MAX_TX_COUNT; txcnt++) {
1758                         if (pwrinfo5g->ofdm_diff[rfpath][txcnt] == 0xFF)
1759                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] =   0xFE;
1760                         else if (pwrinfo5g->ofdm_diff[rfpath][txcnt] & BIT(3))
1761                                 pwrinfo5g->ofdm_diff[rfpath][txcnt] |= 0xF0;
1762                 }
1763         }
1764 }
1765
1766 static void _rtl88ee_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1767                                                  bool autoload_fail,
1768                                                  u8 *hwinfo)
1769 {
1770         struct rtl_priv *rtlpriv = rtl_priv(hw);
1771         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1772         struct txpower_info_2g pwrinfo24g;
1773         struct txpower_info_5g pwrinfo5g;
1774         u8 rf_path, index;
1775         u8 i;
1776
1777         read_power_value_fromprom(hw, &pwrinfo24g,
1778                                   &pwrinfo5g, autoload_fail, hwinfo);
1779
1780         for (rf_path = 0; rf_path < 2; rf_path++) {
1781                 for (i = 0; i < 14; i++) {
1782                         index = _rtl88e_get_chnl_group(i+1);
1783
1784                         rtlefuse->txpwrlevel_cck[rf_path][i] =
1785                                 pwrinfo24g.index_cck_base[rf_path][index];
1786                         rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1787                                 pwrinfo24g.index_bw40_base[rf_path][index];
1788                         rtlefuse->txpwr_ht20diff[rf_path][i] =
1789                                 pwrinfo24g.bw20_diff[rf_path][0];
1790                         rtlefuse->txpwr_legacyhtdiff[rf_path][i] =
1791                                 pwrinfo24g.ofdm_diff[rf_path][0];
1792                 }
1793
1794                 for (i = 0; i < 14; i++) {
1795                         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1796                                 "RF(%d)-Ch(%d) [CCK / HT40_1S ] = [0x%x / 0x%x ]\n",
1797                                 rf_path, i,
1798                                 rtlefuse->txpwrlevel_cck[rf_path][i],
1799                                 rtlefuse->txpwrlevel_ht40_1s[rf_path][i]);
1800                 }
1801         }
1802
1803         if (!autoload_fail)
1804                 rtlefuse->eeprom_thermalmeter =
1805                         hwinfo[EEPROM_THERMAL_METER_88E];
1806         else
1807                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1808
1809         if (rtlefuse->eeprom_thermalmeter == 0xff || autoload_fail) {
1810                 rtlefuse->apk_thermalmeterignore = true;
1811                 rtlefuse->eeprom_thermalmeter = EEPROM_DEFAULT_THERMALMETER;
1812         }
1813
1814         rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1815         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1816                 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1817
1818         if (!autoload_fail) {
1819                 rtlefuse->eeprom_regulatory =
1820                         hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x07;/*bit0~2*/
1821                 if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1822                         rtlefuse->eeprom_regulatory = 0;
1823         } else {
1824                 rtlefuse->eeprom_regulatory = 0;
1825         }
1826         RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1827                 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1828 }
1829
1830 static void _rtl88ee_read_adapter_info(struct ieee80211_hw *hw)
1831 {
1832         struct rtl_priv *rtlpriv = rtl_priv(hw);
1833         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1834         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1835         int params[] = {RTL8188E_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1836                         EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1837                         EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1838                         COUNTRY_CODE_WORLD_WIDE_13};
1839         u8 *hwinfo;
1840
1841         hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1842         if (!hwinfo)
1843                 return;
1844
1845         if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1846                 goto exit;
1847
1848         if (rtlefuse->eeprom_oemid == 0xFF)
1849                 rtlefuse->eeprom_oemid = 0;
1850
1851         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1852                  "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1853         /* set channel plan from efuse */
1854         rtlefuse->channel_plan = rtlefuse->eeprom_channelplan;
1855         /*tx power*/
1856         _rtl88ee_read_txpower_info_from_hwpg(hw,
1857                                              rtlefuse->autoload_failflag,
1858                                              hwinfo);
1859         rtlefuse->txpwr_fromeprom = true;
1860
1861         rtl8188ee_read_bt_coexist_info_from_hwpg(hw,
1862                                                  rtlefuse->autoload_failflag,
1863                                                  hwinfo);
1864
1865         /*board type*/
1866         rtlefuse->board_type =
1867                 ((hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0xE0) >> 5);
1868         rtlhal->board_type = rtlefuse->board_type;
1869         /*Wake on wlan*/
1870         rtlefuse->wowlan_enable =
1871                 ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0x40) >> 6);
1872         /*parse xtal*/
1873         rtlefuse->crystalcap = hwinfo[EEPROM_XTAL_88E];
1874         if (hwinfo[EEPROM_XTAL_88E])
1875                 rtlefuse->crystalcap = 0x20;
1876         /*antenna diversity*/
1877         rtlefuse->antenna_div_cfg =
1878                 (hwinfo[EEPROM_RF_BOARD_OPTION_88E] & 0x18) >> 3;
1879         if (hwinfo[EEPROM_RF_BOARD_OPTION_88E] == 0xFF)
1880                 rtlefuse->antenna_div_cfg = 0;
1881         if (rtlpriv->btcoexist.eeprom_bt_coexist != 0 &&
1882             rtlpriv->btcoexist.eeprom_bt_ant_num == ANT_X1)
1883                 rtlefuse->antenna_div_cfg = 0;
1884
1885         rtlefuse->antenna_div_type = hwinfo[EEPROM_RF_ANTENNA_OPT_88E];
1886         if (rtlefuse->antenna_div_type == 0xFF)
1887                 rtlefuse->antenna_div_type = 0x01;
1888         if (rtlefuse->antenna_div_type == CG_TRX_HW_ANTDIV ||
1889                 rtlefuse->antenna_div_type == CGCS_RX_HW_ANTDIV)
1890                 rtlefuse->antenna_div_cfg = 1;
1891
1892         if (rtlhal->oem_id == RT_CID_DEFAULT) {
1893                 switch (rtlefuse->eeprom_oemid) {
1894                 case EEPROM_CID_DEFAULT:
1895                         if (rtlefuse->eeprom_did == 0x8179) {
1896                                 if (rtlefuse->eeprom_svid == 0x1025) {
1897                                         rtlhal->oem_id = RT_CID_819X_ACER;
1898                                 } else if ((rtlefuse->eeprom_svid == 0x10EC &&
1899                                      rtlefuse->eeprom_smid == 0x0179) ||
1900                                      (rtlefuse->eeprom_svid == 0x17AA &&
1901                                      rtlefuse->eeprom_smid == 0x0179)) {
1902                                         rtlhal->oem_id = RT_CID_819X_LENOVO;
1903                                 } else if (rtlefuse->eeprom_svid == 0x103c &&
1904                                            rtlefuse->eeprom_smid == 0x197d) {
1905                                         rtlhal->oem_id = RT_CID_819X_HP;
1906                                 } else {
1907                                         rtlhal->oem_id = RT_CID_DEFAULT;
1908                                 }
1909                         } else {
1910                                 rtlhal->oem_id = RT_CID_DEFAULT;
1911                         }
1912                         break;
1913                 case EEPROM_CID_TOSHIBA:
1914                         rtlhal->oem_id = RT_CID_TOSHIBA;
1915                         break;
1916                 case EEPROM_CID_QMI:
1917                         rtlhal->oem_id = RT_CID_819X_QMI;
1918                         break;
1919                 case EEPROM_CID_WHQL:
1920                 default:
1921                         rtlhal->oem_id = RT_CID_DEFAULT;
1922                         break;
1923
1924                 }
1925         }
1926 exit:
1927         kfree(hwinfo);
1928 }
1929
1930 static void _rtl88ee_hal_customized_behavior(struct ieee80211_hw *hw)
1931 {
1932         struct rtl_priv *rtlpriv = rtl_priv(hw);
1933         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1934
1935         rtlpriv->ledctl.led_opendrain = true;
1936
1937         switch (rtlhal->oem_id) {
1938         case RT_CID_819X_HP:
1939                 rtlpriv->ledctl.led_opendrain = true;
1940                 break;
1941         case RT_CID_819X_LENOVO:
1942         case RT_CID_DEFAULT:
1943         case RT_CID_TOSHIBA:
1944         case RT_CID_CCX:
1945         case RT_CID_819X_ACER:
1946         case RT_CID_WHQL:
1947         default:
1948                 break;
1949         }
1950         RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1951                  "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1952 }
1953
1954 void rtl88ee_read_eeprom_info(struct ieee80211_hw *hw)
1955 {
1956         struct rtl_priv *rtlpriv = rtl_priv(hw);
1957         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1958         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1959         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1960         u8 tmp_u1b;
1961
1962         rtlhal->version = _rtl88ee_read_chip_version(hw);
1963         if (get_rf_type(rtlphy) == RF_1T1R)
1964                 rtlpriv->dm.rfpath_rxenable[0] = true;
1965         else
1966                 rtlpriv->dm.rfpath_rxenable[0] =
1967                     rtlpriv->dm.rfpath_rxenable[1] = true;
1968         RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1969                                                 rtlhal->version);
1970         tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1971         if (tmp_u1b & BIT(4)) {
1972                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1973                 rtlefuse->epromtype = EEPROM_93C46;
1974         } else {
1975                 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1976                 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1977         }
1978         if (tmp_u1b & BIT(5)) {
1979                 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1980                 rtlefuse->autoload_failflag = false;
1981                 _rtl88ee_read_adapter_info(hw);
1982         } else {
1983                 pr_err("Autoload ERR!!\n");
1984         }
1985         _rtl88ee_hal_customized_behavior(hw);
1986 }
1987
1988 static void rtl88ee_update_hal_rate_table(struct ieee80211_hw *hw,
1989                 struct ieee80211_sta *sta)
1990 {
1991         struct rtl_priv *rtlpriv = rtl_priv(hw);
1992         struct rtl_phy *rtlphy = &(rtlpriv->phy);
1993         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1994         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1995         u32 ratr_value;
1996         u8 ratr_index = 0;
1997         u8 b_nmode = mac->ht_enable;
1998         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1999         u16 shortgi_rate;
2000         u32 tmp_ratr_value;
2001         u8 curtxbw_40mhz = mac->bw_40;
2002         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2003                                 1 : 0;
2004         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2005                                 1 : 0;
2006         enum wireless_mode wirelessmode = mac->mode;
2007         u32 ratr_mask;
2008
2009         if (rtlhal->current_bandtype == BAND_ON_5G)
2010                 ratr_value = sta->supp_rates[1] << 4;
2011         else
2012                 ratr_value = sta->supp_rates[0];
2013         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2014                 ratr_value = 0xfff;
2015         ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2016                        sta->ht_cap.mcs.rx_mask[0] << 12);
2017         switch (wirelessmode) {
2018         case WIRELESS_MODE_B:
2019                 if (ratr_value & 0x0000000c)
2020                         ratr_value &= 0x0000000d;
2021                 else
2022                         ratr_value &= 0x0000000f;
2023                 break;
2024         case WIRELESS_MODE_G:
2025                 ratr_value &= 0x00000FF5;
2026                 break;
2027         case WIRELESS_MODE_N_24G:
2028         case WIRELESS_MODE_N_5G:
2029                 b_nmode = 1;
2030                 if (get_rf_type(rtlphy) == RF_1T2R ||
2031                     get_rf_type(rtlphy) == RF_1T1R)
2032                         ratr_mask = 0x000ff005;
2033                 else
2034                         ratr_mask = 0x0f0ff005;
2035
2036                 ratr_value &= ratr_mask;
2037                 break;
2038         default:
2039                 if (rtlphy->rf_type == RF_1T2R)
2040                         ratr_value &= 0x000ff0ff;
2041                 else
2042                         ratr_value &= 0x0f0ff0ff;
2043
2044                 break;
2045         }
2046
2047         if ((rtlpriv->btcoexist.bt_coexistence) &&
2048             (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
2049             (rtlpriv->btcoexist.bt_cur_state) &&
2050             (rtlpriv->btcoexist.bt_ant_isolation) &&
2051             ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
2052              (rtlpriv->btcoexist.bt_service == BT_BUSY)))
2053                 ratr_value &= 0x0fffcfc0;
2054         else
2055                 ratr_value &= 0x0FFFFFFF;
2056
2057         if (b_nmode &&
2058             ((curtxbw_40mhz && curshortgi_40mhz) ||
2059              (!curtxbw_40mhz && curshortgi_20mhz))) {
2060                 ratr_value |= 0x10000000;
2061                 tmp_ratr_value = (ratr_value >> 12);
2062
2063                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
2064                         if ((1 << shortgi_rate) & tmp_ratr_value)
2065                                 break;
2066                 }
2067
2068                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
2069                     (shortgi_rate << 4) | (shortgi_rate);
2070         }
2071
2072         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
2073
2074         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2075                  "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
2076 }
2077
2078 static void rtl88ee_update_hal_rate_mask(struct ieee80211_hw *hw,
2079                 struct ieee80211_sta *sta, u8 rssi_level)
2080 {
2081         struct rtl_priv *rtlpriv = rtl_priv(hw);
2082         struct rtl_phy *rtlphy = &(rtlpriv->phy);
2083         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2084         struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
2085         struct rtl_sta_info *sta_entry = NULL;
2086         u32 ratr_bitmap;
2087         u8 ratr_index;
2088         u8 curtxbw_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
2089                                 ? 1 : 0;
2090         u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
2091                                 1 : 0;
2092         u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
2093                                 1 : 0;
2094         enum wireless_mode wirelessmode = 0;
2095         bool b_shortgi = false;
2096         u8 rate_mask[5];
2097         u8 macid = 0;
2098         /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2099
2100         sta_entry = (struct rtl_sta_info *)sta->drv_priv;
2101         wirelessmode = sta_entry->wireless_mode;
2102         if (mac->opmode == NL80211_IFTYPE_STATION ||
2103                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2104                 curtxbw_40mhz = mac->bw_40;
2105         else if (mac->opmode == NL80211_IFTYPE_AP ||
2106                 mac->opmode == NL80211_IFTYPE_ADHOC)
2107                 macid = sta->aid + 1;
2108
2109         if (rtlhal->current_bandtype == BAND_ON_5G)
2110                 ratr_bitmap = sta->supp_rates[1] << 4;
2111         else
2112                 ratr_bitmap = sta->supp_rates[0];
2113         if (mac->opmode == NL80211_IFTYPE_ADHOC)
2114                 ratr_bitmap = 0xfff;
2115         ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
2116                         sta->ht_cap.mcs.rx_mask[0] << 12);
2117         switch (wirelessmode) {
2118         case WIRELESS_MODE_B:
2119                 ratr_index = RATR_INX_WIRELESS_B;
2120                 if (ratr_bitmap & 0x0000000c)
2121                         ratr_bitmap &= 0x0000000d;
2122                 else
2123                         ratr_bitmap &= 0x0000000f;
2124                 break;
2125         case WIRELESS_MODE_G:
2126                 ratr_index = RATR_INX_WIRELESS_GB;
2127
2128                 if (rssi_level == 1)
2129                         ratr_bitmap &= 0x00000f00;
2130                 else if (rssi_level == 2)
2131                         ratr_bitmap &= 0x00000ff0;
2132                 else
2133                         ratr_bitmap &= 0x00000ff5;
2134                 break;
2135         case WIRELESS_MODE_N_24G:
2136         case WIRELESS_MODE_N_5G:
2137                 ratr_index = RATR_INX_WIRELESS_NGB;
2138                 if (rtlphy->rf_type == RF_1T2R ||
2139                     rtlphy->rf_type == RF_1T1R) {
2140                         if (curtxbw_40mhz) {
2141                                 if (rssi_level == 1)
2142                                         ratr_bitmap &= 0x000f0000;
2143                                 else if (rssi_level == 2)
2144                                         ratr_bitmap &= 0x000ff000;
2145                                 else
2146                                         ratr_bitmap &= 0x000ff015;
2147                         } else {
2148                                 if (rssi_level == 1)
2149                                         ratr_bitmap &= 0x000f0000;
2150                                 else if (rssi_level == 2)
2151                                         ratr_bitmap &= 0x000ff000;
2152                                 else
2153                                         ratr_bitmap &= 0x000ff005;
2154                         }
2155                 } else {
2156                         if (curtxbw_40mhz) {
2157                                 if (rssi_level == 1)
2158                                         ratr_bitmap &= 0x0f8f0000;
2159                                 else if (rssi_level == 2)
2160                                         ratr_bitmap &= 0x0f8ff000;
2161                                 else
2162                                         ratr_bitmap &= 0x0f8ff015;
2163                         } else {
2164                                 if (rssi_level == 1)
2165                                         ratr_bitmap &= 0x0f8f0000;
2166                                 else if (rssi_level == 2)
2167                                         ratr_bitmap &= 0x0f8ff000;
2168                                 else
2169                                         ratr_bitmap &= 0x0f8ff005;
2170                         }
2171                 }
2172                 /*}*/
2173
2174                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2175                     (!curtxbw_40mhz && curshortgi_20mhz)) {
2176
2177                         if (macid == 0)
2178                                 b_shortgi = true;
2179                         else if (macid == 1)
2180                                 b_shortgi = false;
2181                 }
2182                 break;
2183         default:
2184                 ratr_index = RATR_INX_WIRELESS_NGB;
2185
2186                 if (rtlphy->rf_type == RF_1T2R)
2187                         ratr_bitmap &= 0x000ff0ff;
2188                 else
2189                         ratr_bitmap &= 0x0f0ff0ff;
2190                 break;
2191         }
2192         sta_entry->ratr_index = ratr_index;
2193
2194         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2195                  "ratr_bitmap :%x\n", ratr_bitmap);
2196         *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2197                              (ratr_index << 28);
2198         rate_mask[4] = macid | (b_shortgi ? 0x20 : 0x00) | 0x80;
2199         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2200                  "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2201                  ratr_index, ratr_bitmap,
2202                  rate_mask[0], rate_mask[1],
2203                  rate_mask[2], rate_mask[3],
2204                  rate_mask[4]);
2205         rtl88e_fill_h2c_cmd(hw, H2C_88E_RA_MASK, 5, rate_mask);
2206         _rtl88ee_set_bcn_ctrl_reg(hw, BIT(3), 0);
2207 }
2208
2209 void rtl88ee_update_hal_rate_tbl(struct ieee80211_hw *hw,
2210                 struct ieee80211_sta *sta, u8 rssi_level)
2211 {
2212         struct rtl_priv *rtlpriv = rtl_priv(hw);
2213
2214         if (rtlpriv->dm.useramask)
2215                 rtl88ee_update_hal_rate_mask(hw, sta, rssi_level);
2216         else
2217                 rtl88ee_update_hal_rate_table(hw, sta);
2218 }
2219
2220 void rtl88ee_update_channel_access_setting(struct ieee80211_hw *hw)
2221 {
2222         struct rtl_priv *rtlpriv = rtl_priv(hw);
2223         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2224         u16 sifs_timer;
2225
2226         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2227         if (!mac->ht_enable)
2228                 sifs_timer = 0x0a0a;
2229         else
2230                 sifs_timer = 0x0e0e;
2231         rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2232 }
2233
2234 bool rtl88ee_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2235 {
2236         struct rtl_priv *rtlpriv = rtl_priv(hw);
2237         struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2238         enum rf_pwrstate e_rfpowerstate_toset, cur_rfstate;
2239         u32 u4tmp;
2240         bool b_actuallyset = false;
2241
2242         if (rtlpriv->rtlhal.being_init_adapter)
2243                 return false;
2244
2245         if (ppsc->swrf_processing)
2246                 return false;
2247
2248         spin_lock(&rtlpriv->locks.rf_ps_lock);
2249         if (ppsc->rfchange_inprogress) {
2250                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2251                 return false;
2252         } else {
2253                 ppsc->rfchange_inprogress = true;
2254                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2255         }
2256
2257         cur_rfstate = ppsc->rfpwr_state;
2258
2259         u4tmp = rtl_read_dword(rtlpriv, REG_GPIO_OUTPUT);
2260         e_rfpowerstate_toset = (u4tmp & BIT(31)) ? ERFON : ERFOFF;
2261
2262         if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2263                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2264                          "GPIOChangeRF  - HW Radio ON, RF ON\n");
2265
2266                 e_rfpowerstate_toset = ERFON;
2267                 ppsc->hwradiooff = false;
2268                 b_actuallyset = true;
2269         } else if ((!ppsc->hwradiooff) &&
2270                    (e_rfpowerstate_toset == ERFOFF)) {
2271                 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2272                          "GPIOChangeRF  - HW Radio OFF, RF OFF\n");
2273
2274                 e_rfpowerstate_toset = ERFOFF;
2275                 ppsc->hwradiooff = true;
2276                 b_actuallyset = true;
2277         }
2278
2279         if (b_actuallyset) {
2280                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2281                 ppsc->rfchange_inprogress = false;
2282                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2283         } else {
2284                 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2285                         RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2286
2287                 spin_lock(&rtlpriv->locks.rf_ps_lock);
2288                 ppsc->rfchange_inprogress = false;
2289                 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2290         }
2291
2292         *valid = 1;
2293         return !ppsc->hwradiooff;
2294
2295 }
2296
2297 void rtl88ee_set_key(struct ieee80211_hw *hw, u32 key_index,
2298                      u8 *p_macaddr, bool is_group, u8 enc_algo,
2299                      bool is_wepkey, bool clear_all)
2300 {
2301         struct rtl_priv *rtlpriv = rtl_priv(hw);
2302         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2303         struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2304         u8 *macaddr = p_macaddr;
2305         u32 entry_id = 0;
2306         bool is_pairwise = false;
2307         static u8 cam_const_addr[4][6] = {
2308                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2309                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2310                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2311                 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2312         };
2313         static u8 cam_const_broad[] = {
2314                 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2315         };
2316
2317         if (clear_all) {
2318                 u8 idx = 0;
2319                 u8 cam_offset = 0;
2320                 u8 clear_number = 5;
2321
2322                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2323
2324                 for (idx = 0; idx < clear_number; idx++) {
2325                         rtl_cam_mark_invalid(hw, cam_offset + idx);
2326                         rtl_cam_empty_entry(hw, cam_offset + idx);
2327
2328                         if (idx < 5) {
2329                                 memset(rtlpriv->sec.key_buf[idx], 0,
2330                                        MAX_KEY_LEN);
2331                                 rtlpriv->sec.key_len[idx] = 0;
2332                         }
2333                 }
2334
2335         } else {
2336                 switch (enc_algo) {
2337                 case WEP40_ENCRYPTION:
2338                         enc_algo = CAM_WEP40;
2339                         break;
2340                 case WEP104_ENCRYPTION:
2341                         enc_algo = CAM_WEP104;
2342                         break;
2343                 case TKIP_ENCRYPTION:
2344                         enc_algo = CAM_TKIP;
2345                         break;
2346                 case AESCCMP_ENCRYPTION:
2347                         enc_algo = CAM_AES;
2348                         break;
2349                 default:
2350                         pr_err("switch case %#x not processed\n",
2351                                enc_algo);
2352                         enc_algo = CAM_TKIP;
2353                         break;
2354                 }
2355
2356                 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2357                         macaddr = cam_const_addr[key_index];
2358                         entry_id = key_index;
2359                 } else {
2360                         if (is_group) {
2361                                 macaddr = cam_const_broad;
2362                                 entry_id = key_index;
2363                         } else {
2364                                 if (mac->opmode == NL80211_IFTYPE_AP ||
2365                                     mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2366                                         entry_id =
2367                                           rtl_cam_get_free_entry(hw, p_macaddr);
2368                                         if (entry_id >=  TOTAL_CAM_ENTRY) {
2369                                                 pr_err("Can not find free hw security cam entry\n");
2370                                                 return;
2371                                         }
2372                                 } else {
2373                                         entry_id = CAM_PAIRWISE_KEY_POSITION;
2374                                 }
2375                                 key_index = PAIRWISE_KEYIDX;
2376                                 is_pairwise = true;
2377                         }
2378                 }
2379
2380                 if (rtlpriv->sec.key_len[key_index] == 0) {
2381                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2382                                  "delete one entry, entry_id is %d\n",
2383                                  entry_id);
2384                         if (mac->opmode == NL80211_IFTYPE_AP ||
2385                                 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2386                                 rtl_cam_del_entry(hw, p_macaddr);
2387                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2388                 } else {
2389                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2390                                  "add one entry\n");
2391                         if (is_pairwise) {
2392                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2393                                          "set Pairwise key\n");
2394
2395                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2396                                                       entry_id, enc_algo,
2397                                                       CAM_CONFIG_NO_USEDK,
2398                                                       rtlpriv->sec.key_buf[key_index]);
2399                         } else {
2400                                 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2401                                          "set group key\n");
2402
2403                                 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2404                                         rtl_cam_add_one_entry(hw,
2405                                                         rtlefuse->dev_addr,
2406                                                         PAIRWISE_KEYIDX,
2407                                                         CAM_PAIRWISE_KEY_POSITION,
2408                                                         enc_algo,
2409                                                         CAM_CONFIG_NO_USEDK,
2410                                                         rtlpriv->sec.key_buf
2411                                                         [entry_id]);
2412                                 }
2413
2414                                 rtl_cam_add_one_entry(hw, macaddr, key_index,
2415                                                       entry_id, enc_algo,
2416                                                       CAM_CONFIG_NO_USEDK,
2417                                                       rtlpriv->sec.key_buf[entry_id]);
2418                         }
2419
2420                 }
2421         }
2422 }
2423
2424 static void rtl8188ee_bt_var_init(struct ieee80211_hw *hw)
2425 {
2426         struct rtl_priv *rtlpriv = rtl_priv(hw);
2427
2428         rtlpriv->btcoexist.bt_coexistence =
2429                 rtlpriv->btcoexist.eeprom_bt_coexist;
2430         rtlpriv->btcoexist.bt_ant_num = rtlpriv->btcoexist.eeprom_bt_ant_num;
2431         rtlpriv->btcoexist.bt_coexist_type = rtlpriv->btcoexist.eeprom_bt_type;
2432
2433         if (rtlpriv->btcoexist.reg_bt_iso == 2)
2434                 rtlpriv->btcoexist.bt_ant_isolation =
2435                                 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2436         else
2437                 rtlpriv->btcoexist.bt_ant_isolation =
2438                                 rtlpriv->btcoexist.reg_bt_iso;
2439
2440         rtlpriv->btcoexist.bt_radio_shared_type =
2441                 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2442
2443         if (rtlpriv->btcoexist.bt_coexistence) {
2444                 if (rtlpriv->btcoexist.reg_bt_sco == 1)
2445                         rtlpriv->btcoexist.bt_service = BT_OTHER_ACTION;
2446                 else if (rtlpriv->btcoexist.reg_bt_sco == 2)
2447                         rtlpriv->btcoexist.bt_service = BT_SCO;
2448                 else if (rtlpriv->btcoexist.reg_bt_sco == 4)
2449                         rtlpriv->btcoexist.bt_service = BT_BUSY;
2450                 else if (rtlpriv->btcoexist.reg_bt_sco == 5)
2451                         rtlpriv->btcoexist.bt_service = BT_OTHERBUSY;
2452                 else
2453                         rtlpriv->btcoexist.bt_service = BT_IDLE;
2454
2455                 rtlpriv->btcoexist.bt_edca_ul = 0;
2456                 rtlpriv->btcoexist.bt_edca_dl = 0;
2457                 rtlpriv->btcoexist.bt_rssi_state = 0xff;
2458         }
2459 }
2460
2461 void rtl8188ee_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2462                                               bool auto_load_fail, u8 *hwinfo)
2463 {
2464         struct rtl_priv *rtlpriv = rtl_priv(hw);
2465         u8 value;
2466
2467         if (!auto_load_fail) {
2468                 rtlpriv->btcoexist.eeprom_bt_coexist =
2469                         ((hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & 0xe0) >> 5);
2470                 if (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] == 0xFF)
2471                         rtlpriv->btcoexist.eeprom_bt_coexist  = 0;
2472                 value = hwinfo[EEPROM_RF_BT_SETTING_88E];
2473                 rtlpriv->btcoexist.eeprom_bt_type = ((value & 0xe) >> 1);
2474                 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2475                 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2476                 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2477                                  ((value & 0x20) >> 5);
2478         } else {
2479                 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2480                 rtlpriv->btcoexist.eeprom_bt_type = BT_2WIRE;
2481                 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2482                 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2483                 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2484         }
2485
2486         rtl8188ee_bt_var_init(hw);
2487 }
2488
2489 void rtl8188ee_bt_reg_init(struct ieee80211_hw *hw)
2490 {
2491         struct rtl_priv *rtlpriv = rtl_priv(hw);
2492
2493         /* 0:Low, 1:High, 2:From Efuse. */
2494         rtlpriv->btcoexist.reg_bt_iso = 2;
2495         /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2496         rtlpriv->btcoexist.reg_bt_sco = 3;
2497         /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2498         rtlpriv->btcoexist.reg_bt_sco = 0;
2499 }
2500
2501 void rtl8188ee_bt_hw_init(struct ieee80211_hw *hw)
2502 {
2503         struct rtl_priv *rtlpriv = rtl_priv(hw);
2504         struct rtl_phy *rtlphy = &rtlpriv->phy;
2505         u8 u1_tmp;
2506
2507         if (rtlpriv->btcoexist.bt_coexistence &&
2508             ((rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) ||
2509               rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC8)) {
2510                 if (rtlpriv->btcoexist.bt_ant_isolation)
2511                         rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2512
2513                 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2514                          BIT_OFFSET_LEN_MASK_32(0, 1);
2515                 u1_tmp = u1_tmp |
2516                          ((rtlpriv->btcoexist.bt_ant_isolation == 1) ?
2517                          0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2518                          ((rtlpriv->btcoexist.bt_service == BT_SCO) ?
2519                          0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2520                 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2521
2522                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2523                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2524                 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2525
2526                 /* Config to 1T1R. */
2527                 if (rtlphy->rf_type == RF_1T1R) {
2528                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2529                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2530                         rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2531
2532                         u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2533                         u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2534                         rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2535                 }
2536         }
2537 }
2538
2539 void rtl88ee_suspend(struct ieee80211_hw *hw)
2540 {
2541 }
2542
2543 void rtl88ee_resume(struct ieee80211_hw *hw)
2544 {
2545 }