1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
5 * Register definitions taken from original Realtek rtl8723au driver
8 /* 0x0000 ~ 0x00FF System Configuration */
9 #define REG_SYS_ISO_CTRL 0x0000
10 #define SYS_ISO_MD2PP BIT(0)
11 #define SYS_ISO_ANALOG_IPS BIT(5)
12 #define SYS_ISO_DIOR BIT(9)
13 #define SYS_ISO_PWC_EV25V BIT(14)
14 #define SYS_ISO_PWC_EV12V BIT(15)
16 #define REG_SYS_FUNC 0x0002
17 #define SYS_FUNC_BBRSTB BIT(0)
18 #define SYS_FUNC_BB_GLB_RSTN BIT(1)
19 #define SYS_FUNC_USBA BIT(2)
20 #define SYS_FUNC_UPLL BIT(3)
21 #define SYS_FUNC_USBD BIT(4)
22 #define SYS_FUNC_DIO_PCIE BIT(5)
23 #define SYS_FUNC_PCIEA BIT(6)
24 #define SYS_FUNC_PPLL BIT(7)
25 #define SYS_FUNC_PCIED BIT(8)
26 #define SYS_FUNC_DIOE BIT(9)
27 #define SYS_FUNC_CPU_ENABLE BIT(10)
28 #define SYS_FUNC_DCORE BIT(11)
29 #define SYS_FUNC_ELDR BIT(12)
30 #define SYS_FUNC_DIO_RF BIT(13)
31 #define SYS_FUNC_HWPDN BIT(14)
32 #define SYS_FUNC_MREGEN BIT(15)
34 #define REG_APS_FSMCO 0x0004
35 #define APS_FSMCO_PFM_ALDN BIT(1)
36 #define APS_FSMCO_PFM_WOWL BIT(3)
37 #define APS_FSMCO_ENABLE_POWERDOWN BIT(4)
38 #define APS_FSMCO_MAC_ENABLE BIT(8)
39 #define APS_FSMCO_MAC_OFF BIT(9)
40 #define APS_FSMCO_SW_LPS BIT(10)
41 #define APS_FSMCO_HW_SUSPEND BIT(11)
42 #define APS_FSMCO_PCIE BIT(12)
43 #define APS_FSMCO_HW_POWERDOWN BIT(15)
44 #define APS_FSMCO_WLON_RESET BIT(16)
46 #define REG_SYS_CLKR 0x0008
47 #define SYS_CLK_ANAD16V_ENABLE BIT(0)
48 #define SYS_CLK_ANA8M BIT(1)
49 #define SYS_CLK_MACSLP BIT(4)
50 #define SYS_CLK_LOADER_ENABLE BIT(5)
51 #define SYS_CLK_80M_SSC_DISABLE BIT(7)
52 #define SYS_CLK_80M_SSC_ENABLE_HO BIT(8)
53 #define SYS_CLK_PHY_SSC_RSTB BIT(9)
54 #define SYS_CLK_SEC_CLK_ENABLE BIT(10)
55 #define SYS_CLK_MAC_CLK_ENABLE BIT(11)
56 #define SYS_CLK_ENABLE BIT(12)
57 #define SYS_CLK_RING_CLK_ENABLE BIT(13)
59 #define REG_9346CR 0x000a
60 #define EEPROM_BOOT BIT(4)
61 #define EEPROM_ENABLE BIT(5)
63 #define REG_EE_VPD 0x000c
64 #define REG_AFE_MISC 0x0010
65 #define AFE_MISC_WL_XTAL_CTRL BIT(6)
67 #define REG_SPS0_CTRL 0x0011
68 #define REG_SPS_OCP_CFG 0x0018
69 #define REG_8192E_LDOV12_CTRL 0x0014
70 #define REG_SYS_SWR_CTRL2 0x0014
71 #define REG_RSV_CTRL 0x001c
72 #define RSV_CTRL_WLOCK_1C BIT(5)
73 #define RSV_CTRL_DIS_PRST BIT(6)
75 #define REG_RF_CTRL 0x001f
76 #define RF_ENABLE BIT(0)
77 #define RF_RSTB BIT(1)
78 #define RF_SDMRSTB BIT(2)
80 #define REG_LDOA15_CTRL 0x0020
81 #define LDOA15_ENABLE BIT(0)
82 #define LDOA15_STANDBY BIT(1)
83 #define LDOA15_OBUF BIT(2)
84 #define LDOA15_REG_VOS BIT(3)
85 #define LDOA15_VOADJ_SHIFT 4
87 #define REG_LDOV12D_CTRL 0x0021
88 #define LDOV12D_ENABLE BIT(0)
89 #define LDOV12D_STANDBY BIT(1)
90 #define LDOV12D_VADJ_SHIFT 4
92 #define REG_LDOHCI12_CTRL 0x0022
94 #define REG_LPLDO_CTRL 0x0023
95 #define LPLDO_HSM BIT(2)
96 #define LPLDO_LSM_DIS BIT(3)
98 #define REG_AFE_XTAL_CTRL 0x0024
99 #define AFE_XTAL_ENABLE BIT(0)
100 #define AFE_XTAL_B_SELECT BIT(1)
101 #define AFE_XTAL_GATE_USB BIT(8)
102 #define AFE_XTAL_GATE_AFE BIT(11)
103 #define AFE_XTAL_RF_GATE BIT(14)
104 #define AFE_XTAL_GATE_DIG BIT(17)
105 #define AFE_XTAL_BT_GATE BIT(20)
108 * 0x0028 is also known as REG_AFE_CTRL2 on 8723bu/8192eu
110 #define REG_AFE_PLL_CTRL 0x0028
111 #define AFE_PLL_ENABLE BIT(0)
112 #define AFE_PLL_320_ENABLE BIT(1)
113 #define APE_PLL_FREF_SELECT BIT(2)
114 #define AFE_PLL_EDGE_SELECT BIT(3)
115 #define AFE_PLL_WDOGB BIT(4)
116 #define AFE_PLL_LPF_ENABLE BIT(5)
118 #define REG_MAC_PHY_CTRL 0x002c
120 #define REG_EFUSE_CTRL 0x0030
121 #define REG_EFUSE_TEST 0x0034
122 #define EFUSE_TRPT BIT(7)
123 /* 00: Wifi Efuse, 01: BT Efuse0, 10: BT Efuse1, 11: BT Efuse2 */
124 #define EFUSE_CELL_SEL (BIT(8) | BIT(9))
125 #define EFUSE_LDOE25_ENABLE BIT(31)
126 #define EFUSE_SELECT_MASK 0x0300
127 #define EFUSE_WIFI_SELECT 0x0000
128 #define EFUSE_BT0_SELECT 0x0100
129 #define EFUSE_BT1_SELECT 0x0200
130 #define EFUSE_BT2_SELECT 0x0300
132 #define EFUSE_ACCESS_ENABLE 0x69 /* RTL8723 only */
133 #define EFUSE_ACCESS_DISABLE 0x00 /* RTL8723 only */
135 #define REG_PWR_DATA 0x0038
136 #define PWR_DATA_EEPRPAD_RFE_CTRL_EN BIT(11)
138 #define REG_CAL_TIMER 0x003c
139 #define REG_ACLK_MON 0x003e
140 #define REG_GPIO_MUXCFG 0x0040
141 #define GPIO_MUXCFG_IO_SEL_ENBT BIT(5)
142 #define REG_GPIO_IO_SEL 0x0042
143 #define REG_MAC_PINMUX_CFG 0x0043
144 #define REG_GPIO_PIN_CTRL 0x0044
145 #define REG_GPIO_INTM 0x0048
146 #define GPIO_INTM_EDGE_TRIG_IRQ BIT(9)
148 #define REG_LEDCFG0 0x004c
149 #define LEDCFG0_DPDT_SELECT BIT(23)
150 #define REG_LEDCFG1 0x004d
151 #define LEDCFG1_HW_LED_CONTROL BIT(1)
152 #define LEDCFG1_LED_DISABLE BIT(7)
153 #define REG_LEDCFG2 0x004e
154 #define LEDCFG2_HW_LED_CONTROL BIT(1)
155 #define LEDCFG2_HW_LED_ENABLE BIT(5)
156 #define LEDCFG2_SW_LED_DISABLE BIT(3)
157 #define LEDCFG2_SW_LED_CONTROL BIT(5)
158 #define LEDCFG2_DPDT_SELECT BIT(7)
159 #define REG_LEDCFG3 0x004f
160 #define REG_LEDCFG REG_LEDCFG2
161 #define REG_FSIMR 0x0050
162 #define REG_FSISR 0x0054
163 #define REG_HSIMR 0x0058
164 #define REG_HSISR 0x005c
165 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */
166 #define REG_GPIO_PIN_CTRL_2 0x0060
167 /* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */
168 #define REG_GPIO_IO_SEL_2 0x0062
169 #define GPIO_IO_SEL_2_GPIO09_INPUT BIT(1)
170 #define GPIO_IO_SEL_2_GPIO09_IRQ BIT(9)
173 #define REG_PAD_CTRL1 0x0064
174 #define PAD_CTRL1_SW_DPDT_SEL_DATA BIT(0)
176 /* RTL8723 only WIFI/BT/GPS Multi-Function control source. */
177 #define REG_MULTI_FUNC_CTRL 0x0068
179 #define MULTI_FN_WIFI_HW_PWRDOWN_EN BIT(0) /* Enable GPIO[9] as WiFi HW
181 #define MULTI_FN_WIFI_HW_PWRDOWN_SL BIT(1) /* WiFi HW powerdown polarity
183 #define MULTI_WIFI_FUNC_EN BIT(2) /* WiFi function enable */
185 #define MULTI_WIFI_HW_ROF_EN BIT(3) /* Enable GPIO[9] as WiFi RF HW
187 #define MULTI_BT_HW_PWRDOWN_EN BIT(16) /* Enable GPIO[11] as BT HW
189 #define MULTI_BT_HW_PWRDOWN_SL BIT(17) /* BT HW powerdown polarity
191 #define MULTI_BT_FUNC_EN BIT(18) /* BT function enable */
192 #define MULTI_BT_HW_ROF_EN BIT(19) /* Enable GPIO[11] as BT/GPS
193 RF HW powerdown source */
194 #define MULTI_GPS_HW_PWRDOWN_EN BIT(20) /* Enable GPIO[10] as GPS HW
196 #define MULTI_GPS_HW_PWRDOWN_SL BIT(21) /* GPS HW powerdown polarity
198 #define MULTI_GPS_FUNC_EN BIT(22) /* GPS function enable */
200 #define REG_AFE_CTRL4 0x0078 /* 8192eu/8723bu */
201 #define REG_LDO_SW_CTRL 0x007c /* 8192eu */
203 #define REG_MCU_FW_DL 0x0080
204 #define MCU_FW_DL_ENABLE BIT(0)
205 #define MCU_FW_DL_READY BIT(1)
206 #define MCU_FW_DL_CSUM_REPORT BIT(2)
207 #define MCU_MAC_INIT_READY BIT(3)
208 #define MCU_BB_INIT_READY BIT(4)
209 #define MCU_RF_INIT_READY BIT(5)
210 #define MCU_WINT_INIT_READY BIT(6)
211 #define MCU_FW_RAM_SEL BIT(7) /* 1: RAM, 0:ROM */
212 #define MCU_CP_RESET BIT(23)
214 #define REG_HMBOX_EXT_0 0x0088
215 #define REG_HMBOX_EXT_1 0x008a
216 #define REG_HMBOX_EXT_2 0x008c
217 #define REG_HMBOX_EXT_3 0x008e
219 #define REG_RSVD_1 0x0097
221 /* Interrupt registers for 8192e/8723bu/8812 */
222 #define REG_HIMR0 0x00b0
223 #define IMR0_TXCCK BIT(30) /* TXRPT interrupt when CCX bit
224 of the packet is set */
225 #define IMR0_PSTIMEOUT BIT(29) /* Power Save Time Out Int */
226 #define IMR0_GTINT4 BIT(28) /* Set when GTIMER4 expires */
227 #define IMR0_GTINT3 BIT(27) /* Set when GTIMER3 expires */
228 #define IMR0_TBDER BIT(26) /* Transmit Beacon0 Error */
229 #define IMR0_TBDOK BIT(25) /* Transmit Beacon0 OK */
230 #define IMR0_TSF_BIT32_TOGGLE BIT(24) /* TSF Timer BIT32 toggle
231 indication interrupt */
232 #define IMR0_BCNDMAINT0 BIT(20) /* Beacon DMA Interrupt 0 */
233 #define IMR0_BCNDERR0 BIT(16) /* Beacon Queue DMA Error 0 */
234 #define IMR0_HSISR_IND_ON_INT BIT(15) /* HSISR Indicator (HSIMR &
236 #define IMR0_BCNDMAINT_E BIT(14) /* Beacon DMA Interrupt
237 Extension for Win7 */
238 #define IMR0_ATIMEND BIT(12) /* CTWidnow End or
240 #define IMR0_HISR1_IND_INT BIT(11) /* HISR1 Indicator
241 (HISR1 & HIMR1 is true) */
242 #define IMR0_C2HCMD BIT(10) /* CPU to Host Command INT
243 Status, Write 1 to clear */
244 #define IMR0_CPWM2 BIT(9) /* CPU power Mode exchange INT
245 Status, Write 1 to clear */
246 #define IMR0_CPWM BIT(8) /* CPU power Mode exchange INT
247 Status, Write 1 to clear */
248 #define IMR0_HIGHDOK BIT(7) /* High Queue DMA OK */
249 #define IMR0_MGNTDOK BIT(6) /* Management Queue DMA OK */
250 #define IMR0_BKDOK BIT(5) /* AC_BK DMA OK */
251 #define IMR0_BEDOK BIT(4) /* AC_BE DMA OK */
252 #define IMR0_VIDOK BIT(3) /* AC_VI DMA OK */
253 #define IMR0_VODOK BIT(2) /* AC_VO DMA OK */
254 #define IMR0_RDU BIT(1) /* Rx Descriptor Unavailable */
255 #define IMR0_ROK BIT(0) /* Receive DMA OK */
256 #define REG_HISR0 0x00b4
257 #define REG_HIMR1 0x00b8
258 #define IMR1_BCNDMAINT7 BIT(27) /* Beacon DMA Interrupt 7 */
259 #define IMR1_BCNDMAINT6 BIT(26) /* Beacon DMA Interrupt 6 */
260 #define IMR1_BCNDMAINT5 BIT(25) /* Beacon DMA Interrupt 5 */
261 #define IMR1_BCNDMAINT4 BIT(24) /* Beacon DMA Interrupt 4 */
262 #define IMR1_BCNDMAINT3 BIT(23) /* Beacon DMA Interrupt 3 */
263 #define IMR1_BCNDMAINT2 BIT(22) /* Beacon DMA Interrupt 2 */
264 #define IMR1_BCNDMAINT1 BIT(21) /* Beacon DMA Interrupt 1 */
265 #define IMR1_BCNDERR7 BIT(20) /* Beacon Queue DMA Err Int 7 */
266 #define IMR1_BCNDERR6 BIT(19) /* Beacon Queue DMA Err Int 6 */
267 #define IMR1_BCNDERR5 BIT(18) /* Beacon Queue DMA Err Int 5 */
268 #define IMR1_BCNDERR4 BIT(17) /* Beacon Queue DMA Err Int 4 */
269 #define IMR1_BCNDERR3 BIT(16) /* Beacon Queue DMA Err Int 3 */
270 #define IMR1_BCNDERR2 BIT(15) /* Beacon Queue DMA Err Int 2 */
271 #define IMR1_BCNDERR1 BIT(14) /* Beacon Queue DMA Err Int 1 */
272 #define IMR1_ATIMEND_E BIT(13) /* ATIM Window End Extension
274 #define IMR1_TXERR BIT(11) /* Tx Error Flag Int Status,
276 #define IMR1_RXERR BIT(10) /* Rx Error Flag Int Status,
278 #define IMR1_TXFOVW BIT(9) /* Transmit FIFO Overflow */
279 #define IMR1_RXFOVW BIT(8) /* Receive FIFO Overflow */
280 #define REG_HISR1 0x00bc
282 /* Host suspend counter on FPGA platform */
283 #define REG_HOST_SUSP_CNT 0x00bc
284 /* Efuse access protection for RTL8723 */
285 #define REG_EFUSE_ACCESS 0x00cf
286 #define REG_BIST_SCAN 0x00d0
287 #define REG_BIST_RPT 0x00d4
288 #define REG_BIST_ROM_RPT 0x00d8
289 #define REG_RSVD_4 0x00dc
290 #define REG_USB_SIE_INTF 0x00e0
291 #define REG_PCIE_MIO_INTF 0x00e4
292 #define REG_PCIE_MIO_INTD 0x00e8
293 #define REG_HPON_FSM 0x00ec
294 #define HPON_FSM_BONDING_MASK (BIT(22) | BIT(23))
295 #define HPON_FSM_BONDING_1T2R BIT(22)
296 #define REG_SYS_CFG 0x00f0
297 #define SYS_CFG_XCLK_VLD BIT(0)
298 #define SYS_CFG_ACLK_VLD BIT(1)
299 #define SYS_CFG_UCLK_VLD BIT(2)
300 #define SYS_CFG_PCLK_VLD BIT(3)
301 #define SYS_CFG_PCIRSTB BIT(4)
302 #define SYS_CFG_V15_VLD BIT(5)
303 #define SYS_CFG_TRP_B15V_EN BIT(7)
304 #define SYS_CFG_SW_OFFLOAD_EN BIT(7) /* For chips with IOL support */
305 #define SYS_CFG_SIC_IDLE BIT(8)
306 #define SYS_CFG_BD_MAC2 BIT(9)
307 #define SYS_CFG_BD_MAC1 BIT(10)
308 #define SYS_CFG_IC_MACPHY_MODE BIT(11)
309 #define SYS_CFG_CHIP_VER (BIT(12) | BIT(13) | BIT(14) | BIT(15))
310 #define SYS_CFG_BT_FUNC BIT(16)
311 #define SYS_CFG_VENDOR_ID BIT(19)
312 #define SYS_CFG_VENDOR_EXT_MASK (BIT(18) | BIT(19))
313 #define SYS_CFG_VENDOR_ID_TSMC 0
314 #define SYS_CFG_VENDOR_ID_SMIC BIT(18)
315 #define SYS_CFG_VENDOR_ID_UMC BIT(19)
316 #define SYS_CFG_PAD_HWPD_IDN BIT(22)
317 #define SYS_CFG_TRP_VAUX_EN BIT(23)
318 #define SYS_CFG_TRP_BT_EN BIT(24)
319 #define SYS_CFG_SPS_LDO_SEL BIT(24) /* 8192eu */
320 #define SYS_CFG_BD_PKG_SEL BIT(25)
321 #define SYS_CFG_BD_HCI_SEL BIT(26)
322 #define SYS_CFG_TYPE_ID BIT(27)
323 #define SYS_CFG_RTL_ID BIT(23) /* TestChip ID,
324 1:Test(RLE); 0:MP(RL) */
325 #define SYS_CFG_SPS_SEL BIT(24) /* 1:LDO regulator mode;
326 0:Switching regulator mode*/
327 #define SYS_CFG_CHIP_VERSION_MASK 0xf000 /* Bit 12 - 15 */
329 #define REG_GPIO_OUTSTS 0x00f4 /* For RTL8723 only. */
330 #define GPIO_EFS_HCI_SEL (BIT(0) | BIT(1))
331 #define GPIO_PAD_HCI_SEL (BIT(2) | BIT(3))
332 #define GPIO_HCI_SEL (BIT(4) | BIT(5))
333 #define GPIO_PKG_SEL_HCI BIT(6)
334 #define GPIO_FEN_GPS BIT(7)
335 #define GPIO_FEN_BT BIT(8)
336 #define GPIO_FEN_WL BIT(9)
337 #define GPIO_FEN_PCI BIT(10)
338 #define GPIO_FEN_USB BIT(11)
339 #define GPIO_BTRF_HWPDN_N BIT(12)
340 #define GPIO_WLRF_HWPDN_N BIT(13)
341 #define GPIO_PDN_BT_N BIT(14)
342 #define GPIO_PDN_GPS_N BIT(15)
343 #define GPIO_BT_CTL_HWPDN BIT(16)
344 #define GPIO_GPS_CTL_HWPDN BIT(17)
345 #define GPIO_PPHY_SUSB BIT(20)
346 #define GPIO_UPHY_SUSB BIT(21)
347 #define GPIO_PCI_SUSEN BIT(22)
348 #define GPIO_USB_SUSEN BIT(23)
349 #define GPIO_RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28))
351 #define REG_SYS_CFG2 0x00fc /* 8192eu */
353 /* 0x0100 ~ 0x01FF MACTOP General Configuration */
354 #define REG_CR 0x0100
355 #define CR_HCI_TXDMA_ENABLE BIT(0)
356 #define CR_HCI_RXDMA_ENABLE BIT(1)
357 #define CR_TXDMA_ENABLE BIT(2)
358 #define CR_RXDMA_ENABLE BIT(3)
359 #define CR_PROTOCOL_ENABLE BIT(4)
360 #define CR_SCHEDULE_ENABLE BIT(5)
361 #define CR_MAC_TX_ENABLE BIT(6)
362 #define CR_MAC_RX_ENABLE BIT(7)
363 #define CR_SW_BEACON_ENABLE BIT(8)
364 #define CR_SECURITY_ENABLE BIT(9)
365 #define CR_CALTIMER_ENABLE BIT(10)
367 /* Media Status Register */
368 #define REG_MSR 0x0102
369 #define MSR_LINKTYPE_MASK 0x3
370 #define MSR_LINKTYPE_NONE 0x0
371 #define MSR_LINKTYPE_ADHOC 0x1
372 #define MSR_LINKTYPE_STATION 0x2
373 #define MSR_LINKTYPE_AP 0x3
375 #define REG_PBP 0x0104
376 #define PBP_PAGE_SIZE_RX_SHIFT 0
377 #define PBP_PAGE_SIZE_TX_SHIFT 4
378 #define PBP_PAGE_SIZE_64 0x0
379 #define PBP_PAGE_SIZE_128 0x1
380 #define PBP_PAGE_SIZE_256 0x2
381 #define PBP_PAGE_SIZE_512 0x3
382 #define PBP_PAGE_SIZE_1024 0x4
384 /* 8188eu IOL magic */
385 #define REG_PKT_BUF_ACCESS_CTRL 0x0106
386 #define PKT_BUF_ACCESS_CTRL_TX 0x69
387 #define PKT_BUF_ACCESS_CTRL_RX 0xa5
389 #define REG_TRXDMA_CTRL 0x010c
390 #define TRXDMA_CTRL_RXDMA_AGG_EN BIT(2)
391 #define TRXDMA_CTRL_VOQ_SHIFT 4
392 #define TRXDMA_CTRL_VIQ_SHIFT 6
393 #define TRXDMA_CTRL_BEQ_SHIFT 8
394 #define TRXDMA_CTRL_BKQ_SHIFT 10
395 #define TRXDMA_CTRL_MGQ_SHIFT 12
396 #define TRXDMA_CTRL_HIQ_SHIFT 14
397 #define TRXDMA_CTRL_VOQ_SHIFT_8192F 4
398 #define TRXDMA_CTRL_VIQ_SHIFT_8192F 7
399 #define TRXDMA_CTRL_BEQ_SHIFT_8192F 10
400 #define TRXDMA_CTRL_BKQ_SHIFT_8192F 13
401 #define TRXDMA_CTRL_MGQ_SHIFT_8192F 16
402 #define TRXDMA_CTRL_HIQ_SHIFT_8192F 19
403 #define TRXDMA_QUEUE_LOW 1
404 #define TRXDMA_QUEUE_NORMAL 2
405 #define TRXDMA_QUEUE_HIGH 3
407 #define REG_TRXFF_BNDY 0x0114
408 #define REG_TRXFF_STATUS 0x0118
409 #define REG_RXFF_PTR 0x011c
410 #define REG_HIMR 0x0120
411 #define REG_HISR 0x0124
412 #define REG_HIMRE 0x0128
413 #define REG_HISRE 0x012c
414 #define REG_CPWM 0x012f
415 #define REG_FWIMR 0x0130
416 #define REG_FWISR 0x0134
417 #define REG_FTIMR 0x0138
418 #define REG_PKTBUF_DBG_CTRL 0x0140
419 #define REG_PKTBUF_DBG_DATA_L 0x0144
420 #define REG_PKTBUF_DBG_DATA_H 0x0148
422 #define REG_TC0_CTRL 0x0150
423 #define REG_TC1_CTRL 0x0154
424 #define REG_TC2_CTRL 0x0158
425 #define REG_TC3_CTRL 0x015c
426 #define REG_TC4_CTRL 0x0160
427 #define REG_TCUNIT_BASE 0x0164
428 #define REG_MBIST_START 0x0174
429 #define REG_MBIST_DONE 0x0178
430 #define REG_MBIST_FAIL 0x017c
432 #define REG_32K_CTRL 0x0194
433 #define REG_C2HEVT_MSG_NORMAL 0x01a0
434 /* 8192EU/8723BU/8812 */
435 #define REG_C2HEVT_CMD_ID_8723B 0x01ae
436 #define REG_C2HEVT_CLEAR 0x01af
437 #define REG_C2HEVT_MSG_TEST 0x01b8
438 #define REG_MCUTST_1 0x01c0
439 #define REG_FMTHR 0x01c8
440 #define REG_HMTFR 0x01cc
441 #define REG_HMBOX_0 0x01d0
442 #define REG_HMBOX_1 0x01d4
443 #define REG_HMBOX_2 0x01d8
444 #define REG_HMBOX_3 0x01dc
446 #define REG_LLT_INIT 0x01e0
447 #define LLT_OP_INACTIVE 0x0
448 #define LLT_OP_WRITE (0x1 << 30)
449 #define LLT_OP_READ (0x2 << 30)
450 #define LLT_OP_MASK (0x3 << 30)
452 #define REG_BB_ACCESS_CTRL 0x01e8
453 #define REG_BB_ACCESS_DATA 0x01ec
455 #define REG_HMBOX_EXT0_8723B 0x01f0
456 #define REG_HMBOX_EXT1_8723B 0x01f4
457 #define REG_HMBOX_EXT2_8723B 0x01f8
458 #define REG_HMBOX_EXT3_8723B 0x01fc
460 /* 0x0200 ~ 0x027F TXDMA Configuration */
461 #define REG_RQPN 0x0200
462 #define RQPN_HI_PQ_SHIFT 0
463 #define RQPN_LO_PQ_SHIFT 8
464 #define RQPN_PUB_PQ_SHIFT 16
465 #define RQPN_LOAD BIT(31)
467 #define REG_FIFOPAGE 0x0204
468 #define REG_TDECTRL 0x0208
469 #define BIT_BCN_VALID BIT(16)
471 #define REG_DWBCN0_CTRL_8188F REG_TDECTRL
473 #define REG_TXDMA_OFFSET_CHK 0x020c
474 #define TXDMA_OFFSET_DROP_DATA_EN BIT(9)
475 #define REG_TXDMA_STATUS 0x0210
476 #define REG_RQPN_NPQ 0x0214
477 #define RQPN_NPQ_SHIFT 0
478 #define RQPN_EPQ_SHIFT 16
480 #define REG_AUTO_LLT 0x0224
481 #define AUTO_LLT_INIT_LLT BIT(16)
483 #define REG_DWBCN1_CTRL_8723B 0x0228
484 #define BIT_SW_BCN_SEL BIT(20)
486 /* 0x0280 ~ 0x02FF RXDMA Configuration */
487 #define REG_RXDMA_AGG_PG_TH 0x0280 /* 0-7 : USB DMA size bits
488 8-14: USB DMA timeout
489 15 : Aggregation enable
490 Only seems to be used
492 #define RXDMA_USB_AGG_ENABLE BIT(31)
493 #define REG_RXPKT_NUM 0x0284
494 #define RXPKT_NUM_RXDMA_IDLE BIT(17)
495 #define RXPKT_NUM_RW_RELEASE_EN BIT(18)
496 #define REG_RXDMA_STATUS 0x0288
498 /* Presumably only found on newer chips such as 8723bu */
499 #define REG_RX_DMA_CTRL_8723B 0x0286
500 #define REG_RXDMA_PRO_8723B 0x0290
501 #define RXDMA_PRO_DMA_MODE BIT(1) /* Set to 0x1. */
502 #define RXDMA_PRO_DMA_BURST_CNT GENMASK(3, 2) /* Set to 0x3. */
503 #define RXDMA_PRO_DMA_BURST_SIZE GENMASK(5, 4) /* Set to 0x1. */
505 #define REG_EARLY_MODE_CONTROL_8710B 0x02bc
507 #define REG_RF_BB_CMD_ADDR 0x02c0
508 #define REG_RF_BB_CMD_DATA 0x02c4
510 /* spec version 11 */
511 /* 0x0400 ~ 0x047F Protocol Configuration */
513 #define REG_VOQ_INFO 0x0400
514 #define REG_VIQ_INFO 0x0404
515 #define REG_BEQ_INFO 0x0408
516 #define REG_BKQ_INFO 0x040c
517 /* 8188e, 8723a, 8812a, 8821a, 8192e, 8723b */
518 #define REG_Q0_INFO 0x400
519 #define REG_Q1_INFO 0x404
520 #define REG_Q2_INFO 0x408
521 #define REG_Q3_INFO 0x40c
523 #define REG_MGQ_INFO 0x0410
524 #define REG_HGQ_INFO 0x0414
525 #define REG_BCNQ_INFO 0x0418
527 #define REG_CPU_MGQ_INFORMATION 0x041c
528 #define REG_FWHW_TXQ_CTRL 0x0420
529 #define FWHW_TXQ_CTRL_AMPDU_RETRY BIT(7)
530 #define FWHW_TXQ_CTRL_XMIT_MGMT_ACK BIT(12)
531 #define EN_BCNQ_DL BIT(22)
533 #define REG_HWSEQ_CTRL 0x0423
534 #define REG_TXPKTBUF_BCNQ_BDNY 0x0424
535 #define REG_TXPKTBUF_MGQ_BDNY 0x0425
536 #define REG_LIFETIME_EN 0x0426
537 #define REG_MULTI_BCNQ_OFFSET 0x0427
539 #define REG_SPEC_SIFS 0x0428
540 #define SPEC_SIFS_CCK_MASK 0x00ff
541 #define SPEC_SIFS_CCK_SHIFT 0
542 #define SPEC_SIFS_OFDM_MASK 0xff00
543 #define SPEC_SIFS_OFDM_SHIFT 8
545 #define REG_RETRY_LIMIT 0x042a
546 #define RETRY_LIMIT_LONG_SHIFT 0
547 #define RETRY_LIMIT_LONG_MASK 0x003f
548 #define RETRY_LIMIT_SHORT_SHIFT 8
549 #define RETRY_LIMIT_SHORT_MASK 0x3f00
551 #define REG_DARFRC 0x0430
552 #define REG_RARFRC 0x0438
553 #define REG_RESPONSE_RATE_SET 0x0440
554 #define RESPONSE_RATE_BITMAP_ALL 0xfffff
555 #define RESPONSE_RATE_RRSR_CCK_ONLY_1M 0xffff1
556 #define RESPONSE_RATE_RRSR_INIT_2G 0x15f
557 #define RESPONSE_RATE_RRSR_INIT_5G 0x150
558 #define RSR_1M BIT(0)
559 #define RSR_2M BIT(1)
560 #define RSR_5_5M BIT(2)
561 #define RSR_11M BIT(3)
562 #define RSR_6M BIT(4)
563 #define RSR_9M BIT(5)
564 #define RSR_12M BIT(6)
565 #define RSR_18M BIT(7)
566 #define RSR_24M BIT(8)
567 #define RSR_36M BIT(9)
568 #define RSR_48M BIT(10)
569 #define RSR_54M BIT(11)
570 #define RSR_MCS0 BIT(12)
571 #define RSR_MCS1 BIT(13)
572 #define RSR_MCS2 BIT(14)
573 #define RSR_MCS3 BIT(15)
574 #define RSR_MCS4 BIT(16)
575 #define RSR_MCS5 BIT(17)
576 #define RSR_MCS6 BIT(18)
577 #define RSR_MCS7 BIT(19)
578 #define RSR_RSC_LOWER_SUB_CHANNEL BIT(21) /* 0x200000 */
579 #define RSR_RSC_UPPER_SUB_CHANNEL BIT(22) /* 0x400000 */
580 #define RSR_RSC_BANDWIDTH_40M (RSR_RSC_UPPER_SUB_CHANNEL | \
581 RSR_RSC_LOWER_SUB_CHANNEL)
582 #define RSR_ACK_SHORT_PREAMBLE BIT(23)
584 #define REG_ARFR0 0x0444
585 #define REG_ARFR1 0x0448
586 #define REG_ARFR2 0x044c
587 #define REG_ARFR3 0x0450
588 #define REG_CCK_CHECK 0x0454
589 #define BIT_BCN_PORT_SEL BIT(5)
590 #define REG_AMPDU_MAX_TIME_8723B 0x0456
591 #define REG_AGGLEN_LMT 0x0458
592 #define REG_AMPDU_MIN_SPACE 0x045c
593 #define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045d
594 #define REG_FAST_EDCA_CTRL 0x0460
595 #define REG_RD_RESP_PKT_TH 0x0463
596 #define REG_INIRTS_RATE_SEL 0x0480
598 #define REG_DATA_SUBCHANNEL 0x0483
600 #define REG_INIDATA_RATE_SEL 0x0484
601 /* MACID_SLEEP_1/3 for 8723b, 8192e, 8812a, 8821a */
602 #define REG_MACID_SLEEP_3_8732B 0x0484
603 #define REG_MACID_SLEEP_1_8732B 0x0488
605 #define REG_POWER_STATUS 0x04a4
606 #define REG_POWER_STAGE1 0x04b4
607 #define REG_POWER_STAGE2 0x04b8
608 #define REG_AMPDU_BURST_MODE_8723B 0x04bc
609 #define REG_PKT_VO_VI_LIFE_TIME 0x04c0
610 #define REG_PKT_BE_BK_LIFE_TIME 0x04c2
611 #define REG_STBC_SETTING 0x04c4
612 #define REG_QUEUE_CTRL 0x04c6
613 #define REG_HT_SINGLE_AMPDU_8723B 0x04c7
614 #define HT_SINGLE_AMPDU_ENABLE BIT(7)
615 #define REG_PROT_MODE_CTRL 0x04c8
616 #define REG_MAX_AGGR_NUM 0x04ca
617 #define REG_RTS_MAX_AGGR_NUM 0x04cb
618 #define REG_BAR_MODE_CTRL 0x04cc
619 #define REG_RA_TRY_RATE_AGG_LMT 0x04cf
620 /* MACID_DROP for 8723a */
621 #define REG_MACID_DROP_8732A 0x04d0
622 /* EARLY_MODE_CONTROL 8188e */
623 #define REG_EARLY_MODE_CONTROL_8188E 0x04d0
624 /* MACID_SLEEP_2 for 8723b, 8192e, 8812a, 8821a */
625 #define REG_MACID_SLEEP_2_8732B 0x04d0
626 #define REG_MACID_SLEEP 0x04d4
627 #define REG_NQOS_SEQ 0x04dc
628 #define REG_QOS_SEQ 0x04de
629 #define REG_NEED_CPU_HANDLE 0x04e0
630 #define REG_PKT_LOSE_RPT 0x04e1
631 #define REG_PTCL_ERR_STATUS 0x04e2
632 #define REG_TX_REPORT_CTRL 0x04ec
633 #define TX_REPORT_CTRL_TIMER_ENABLE BIT(1)
635 #define REG_TX_REPORT_TIME 0x04f0
636 #define REG_DUMMY 0x04fc
638 /* 0x0500 ~ 0x05FF EDCA Configuration */
639 #define REG_EDCA_VO_PARAM 0x0500
640 #define REG_EDCA_VI_PARAM 0x0504
641 #define REG_EDCA_BE_PARAM 0x0508
642 #define REG_EDCA_BK_PARAM 0x050c
643 #define EDCA_PARAM_ECW_MIN_SHIFT 8
644 #define EDCA_PARAM_ECW_MAX_SHIFT 12
645 #define EDCA_PARAM_TXOP_SHIFT 16
646 #define REG_BEACON_TCFG 0x0510
647 #define REG_PIFS 0x0512
648 #define REG_RDG_PIFS 0x0513
649 #define REG_SIFS_CCK 0x0514
650 #define REG_SIFS_OFDM 0x0516
651 #define REG_TSFTR_SYN_OFFSET 0x0518
652 #define REG_AGGR_BREAK_TIME 0x051a
653 #define REG_SLOT 0x051b
654 #define REG_TX_PTCL_CTRL 0x0520
655 #define REG_TXPAUSE 0x0522
656 #define REG_DIS_TXREQ_CLR 0x0523
657 #define REG_RD_CTRL 0x0524
658 #define REG_TBTT_PROHIBIT 0x0540
659 #define REG_RD_NAV_NXT 0x0544
660 #define REG_NAV_PROT_LEN 0x0546
662 #define REG_BEACON_CTRL 0x0550
663 #define REG_BEACON_CTRL_1 0x0551
664 #define BEACON_ATIM BIT(0)
665 #define BEACON_CTRL_MBSSID BIT(1)
666 #define BEACON_CTRL_TX_BEACON_RPT BIT(2)
667 #define BEACON_FUNCTION_ENABLE BIT(3)
668 #define BEACON_DISABLE_TSF_UPDATE BIT(4)
670 #define REG_MBID_NUM 0x0552
671 #define REG_DUAL_TSF_RST 0x0553
672 #define DUAL_TSF_RESET_TSF0 BIT(0)
673 #define DUAL_TSF_RESET_TSF1 BIT(1)
674 #define DUAL_TSF_RESET_P2P BIT(4)
675 #define DUAL_TSF_TX_OK BIT(5)
677 /* The same as REG_MBSSID_BCN_SPACE */
678 #define REG_BCN_INTERVAL 0x0554
679 #define REG_MBSSID_BCN_SPACE 0x0554
681 #define REG_DRIVER_EARLY_INT 0x0558
682 #define DRIVER_EARLY_INT_TIME 5
684 #define REG_BEACON_DMA_TIME 0x0559
685 #define BEACON_DMA_ATIME_INT_TIME 2
687 #define REG_ATIMWND 0x055a
688 #define REG_USTIME_TSF_8723B 0x055c
689 #define REG_BCN_MAX_ERR 0x055d
690 #define REG_RXTSF_OFFSET_CCK 0x055e
691 #define REG_RXTSF_OFFSET_OFDM 0x055f
692 #define REG_TSFTR 0x0560
693 #define REG_TSFTR1 0x0568
694 #define REG_INIT_TSFTR 0x0564
695 #define REG_ATIMWND_1 0x0570
696 #define REG_PSTIMER 0x0580
697 #define REG_TIMER0 0x0584
698 #define REG_TIMER1 0x0588
699 #define REG_ACM_HW_CTRL 0x05c0
700 #define ACM_HW_CTRL_BK BIT(0)
701 #define ACM_HW_CTRL_BE BIT(1)
702 #define ACM_HW_CTRL_VI BIT(2)
703 #define ACM_HW_CTRL_VO BIT(3)
704 #define REG_ACM_RST_CTRL 0x05c1
705 #define REG_ACMAVG 0x05c2
706 #define REG_VO_ADMTIME 0x05c4
707 #define REG_VI_ADMTIME 0x05c6
708 #define REG_BE_ADMTIME 0x05c8
709 #define REG_EDCA_RANDOM_GEN 0x05cc
710 #define REG_SCH_TXCMD 0x05d0
712 /* define REG_FW_TSF_SYNC_CNT 0x04a0 */
713 #define REG_SCH_TX_CMD 0x05f8
714 #define REG_FW_RESET_TSF_CNT_1 0x05fc
715 #define REG_FW_RESET_TSF_CNT_0 0x05fd
716 #define REG_FW_BCN_DIS_CNT 0x05fe
718 /* 0x0600 ~ 0x07FF WMAC Configuration */
719 #define REG_APSD_CTRL 0x0600
720 #define APSD_CTRL_OFF BIT(6)
721 #define APSD_CTRL_OFF_STATUS BIT(7)
722 #define REG_BW_OPMODE 0x0603
723 #define BW_OPMODE_20MHZ BIT(2)
724 #define BW_OPMODE_5G BIT(1)
725 #define BW_OPMODE_11J BIT(0)
727 #define REG_TCR 0x0604
729 /* Receive Configuration Register */
730 #define REG_RCR 0x0608
731 #define RCR_ACCEPT_AP BIT(0) /* Accept all unicast packet */
732 #define RCR_ACCEPT_PHYS_MATCH BIT(1) /* Accept phys match packet */
733 #define RCR_ACCEPT_MCAST BIT(2)
734 #define RCR_ACCEPT_BCAST BIT(3)
735 #define RCR_ACCEPT_ADDR3 BIT(4) /* Accept address 3 match
737 #define RCR_ACCEPT_PM BIT(5) /* Accept power management
739 #define RCR_CHECK_BSSID_MATCH BIT(6) /* Accept BSSID match packet */
740 #define RCR_CHECK_BSSID_BEACON BIT(7) /* Accept BSSID match packet
741 (Rx beacon, probe rsp) */
742 #define RCR_ACCEPT_CRC32 BIT(8) /* Accept CRC32 error packet */
743 #define RCR_ACCEPT_ICV BIT(9) /* Accept ICV error packet */
744 #define RCR_ACCEPT_DATA_FRAME BIT(11) /* Accept all data pkt or use
746 #define RCR_ACCEPT_CTRL_FRAME BIT(12) /* Accept all control pkt or use
748 #define RCR_ACCEPT_MGMT_FRAME BIT(13) /* Accept all mgmt pkt or use
750 #define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
751 #define RCR_UC_DATA_PKT_INT_ENABLE BIT(16) /* Enable unicast data packet
753 #define RCR_BM_DATA_PKT_INT_ENABLE BIT(17) /* Enable broadcast data packet
755 #define RCR_TIM_PARSER_ENABLE BIT(18) /* Enable RX beacon TIM parser*/
756 #define RCR_MFBEN BIT(22)
757 #define RCR_LSIG_ENABLE BIT(23) /* Enable LSIG TXOP Protection
758 function. Search KEYCAM for
759 each rx packet to check if
760 LSIGEN bit is set. */
761 #define RCR_MULTI_BSSID_ENABLE BIT(24) /* Enable Multiple BssId */
762 #define RCR_FORCE_ACK BIT(26)
763 #define RCR_ACCEPT_BA_SSN BIT(27) /* Accept BA SSN */
764 #define RCR_APPEND_PHYSTAT BIT(28)
765 #define RCR_APPEND_ICV BIT(29)
766 #define RCR_APPEND_MIC BIT(30)
767 #define RCR_APPEND_FCS BIT(31) /* WMAC append FCS after */
769 #define REG_RX_PKT_LIMIT 0x060c
770 #define REG_RX_DLK_TIME 0x060d
771 #define REG_RX_DRVINFO_SZ 0x060f
773 #define REG_MACID 0x0610
774 #define REG_BSSID 0x0618
775 #define REG_MAR 0x0620
776 #define REG_MBIDCAMCFG 0x0628
778 #define REG_USTIME_EDCA 0x0638
779 #define REG_MAC_SPEC_SIFS 0x063a
781 /* 20100719 Joseph: Hardware register definition change. (HW datasheet v54) */
782 /* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */
783 #define REG_R2T_SIFS 0x063c
784 /* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */
785 #define REG_T2T_SIFS 0x063e
786 #define REG_ACKTO 0x0640
787 #define REG_CTS2TO 0x0641
788 #define REG_EIFS 0x0642
791 #define REG_NAV_CTRL 0x0650
792 /* In units of 128us */
793 #define REG_NAV_UPPER 0x0652
794 #define NAV_UPPER_UNIT 128
796 #define REG_BACAMCMD 0x0654
797 #define REG_BACAMCONTENT 0x0658
798 #define REG_LBDLY 0x0660
799 #define REG_FWDLY 0x0661
800 #define REG_RXERR_RPT 0x0664
801 #define REG_WMAC_TRXPTCL_CTL 0x0668
802 #define WMAC_TRXPTCL_CTL_BW_MASK (BIT(7) | BIT(8))
803 #define WMAC_TRXPTCL_CTL_BW_20 0
804 #define WMAC_TRXPTCL_CTL_BW_40 BIT(7)
805 #define WMAC_TRXPTCL_CTL_BW_80 BIT(8)
808 #define REG_CAM_CMD 0x0670
809 #define CAM_CMD_POLLING BIT(31)
810 #define CAM_CMD_WRITE BIT(16)
811 #define CAM_CMD_KEY_SHIFT 3
812 #define REG_CAM_WRITE 0x0674
813 #define CAM_WRITE_VALID BIT(15)
814 #define REG_CAM_READ 0x0678
815 #define REG_CAM_DEBUG 0x067c
816 #define REG_SECURITY_CFG 0x0680
817 #define SEC_CFG_TX_USE_DEFKEY BIT(0)
818 #define SEC_CFG_RX_USE_DEFKEY BIT(1)
819 #define SEC_CFG_TX_SEC_ENABLE BIT(2)
820 #define SEC_CFG_RX_SEC_ENABLE BIT(3)
821 #define SEC_CFG_SKBYA2 BIT(4)
822 #define SEC_CFG_NO_SKMC BIT(5)
823 #define SEC_CFG_TXBC_USE_DEFKEY BIT(6)
824 #define SEC_CFG_RXBC_USE_DEFKEY BIT(7)
827 #define REG_WOW_CTRL 0x0690
828 #define REG_PSSTATUS 0x0691
829 #define REG_PS_RX_INFO 0x0692
830 #define REG_LPNAV_CTRL 0x0694
831 #define REG_WKFMCAM_CMD 0x0698
832 #define REG_WKFMCAM_RWD 0x069c
835 * RX Filters: each bit corresponds to the numerical value of the subtype.
836 * If it is set the subtype frame type is passed. The filter is only used when
837 * the RCR_ACCEPT_DATA_FRAME, RCR_ACCEPT_CTRL_FRAME, RCR_ACCEPT_MGMT_FRAME bit
838 * in the RCR are low.
840 * Example: Beacon subtype is binary 1000 which is decimal 8 so we have to set
841 * bit 8 (0x100) in REG_RXFLTMAP0 to enable reception.
843 #define REG_RXFLTMAP0 0x06a0 /* Management frames */
844 #define REG_RXFLTMAP1 0x06a2 /* Control frames */
845 #define REG_RXFLTMAP2 0x06a4 /* Data frames */
847 #define REG_BCN_PSR_RPT 0x06a8
848 #define REG_CALB32K_CTRL 0x06ac
849 #define REG_PKT_MON_CTRL 0x06b4
850 #define REG_BT_COEX_TABLE1 0x06c0
851 #define REG_BT_COEX_TABLE2 0x06c4
852 #define REG_BT_COEX_TABLE3 0x06c8
853 #define REG_BT_COEX_TABLE4 0x06cc
854 #define REG_WMAC_RESP_TXINFO 0x06d8
856 #define REG_MACID1 0x0700
857 #define REG_BSSID1 0x0708
860 * This seems to be 8723bu specific
862 #define REG_BT_CONTROL_8723BU 0x0764
863 #define BT_CONTROL_BT_GRANT BIT(12)
865 #define REG_PORT_CONTROL_8710B 0x076d
866 #define REG_WLAN_ACT_CONTROL_8723B 0x076e
868 #define REG_FPGA0_RF_MODE 0x0800
869 #define FPGA_RF_MODE BIT(0)
870 #define FPGA_RF_MODE_JAPAN BIT(1)
871 #define FPGA_RF_MODE_CCK BIT(24)
872 #define FPGA_RF_MODE_OFDM BIT(25)
874 #define REG_FPGA0_TX_INFO 0x0804
875 #define FPGA0_TX_INFO_OFDM_PATH_A BIT(0)
876 #define FPGA0_TX_INFO_OFDM_PATH_B BIT(1)
877 #define FPGA0_TX_INFO_OFDM_PATH_C BIT(2)
878 #define FPGA0_TX_INFO_OFDM_PATH_D BIT(3)
879 #define REG_FPGA0_PSD_FUNC 0x0808
880 #define REG_FPGA0_TX_GAIN 0x080c
881 #define REG_FPGA0_RF_TIMING1 0x0810
882 #define REG_FPGA0_RF_TIMING2 0x0814
883 #define REG_FPGA0_POWER_SAVE 0x0818
884 #define FPGA0_PS_LOWER_CHANNEL BIT(26)
885 #define FPGA0_PS_UPPER_CHANNEL BIT(27)
887 #define REG_FPGA0_XA_HSSI_PARM1 0x0820 /* RF 3 wire register */
888 #define FPGA0_HSSI_PARM1_PI BIT(8)
889 #define REG_FPGA0_XA_HSSI_PARM2 0x0824
890 #define REG_FPGA0_XB_HSSI_PARM1 0x0828
891 #define REG_FPGA0_XB_HSSI_PARM2 0x082c
892 #define FPGA0_HSSI_3WIRE_DATA_LEN 0x800
893 #define FPGA0_HSSI_3WIRE_ADDR_LEN 0x400
894 #define FPGA0_HSSI_PARM2_ADDR_SHIFT 23
895 #define FPGA0_HSSI_PARM2_ADDR_MASK 0x7f800000 /* 0xff << 23 */
896 #define FPGA0_HSSI_PARM2_CCK_HIGH_PWR BIT(9)
897 #define FPGA0_HSSI_PARM2_EDGE_READ BIT(31)
899 #define REG_TX_AGC_B_RATE18_06 0x0830
900 #define REG_TX_AGC_B_RATE54_24 0x0834
901 #define REG_TX_AGC_B_CCK1_55_MCS32 0x0838
902 #define REG_TX_AGC_B_MCS03_MCS00 0x083c
904 #define REG_FPGA0_XA_LSSI_PARM 0x0840
905 #define REG_FPGA0_XB_LSSI_PARM 0x0844
906 #define FPGA0_LSSI_PARM_ADDR_SHIFT 20
907 #define FPGA0_LSSI_PARM_ADDR_MASK 0x0ff00000
908 #define FPGA0_LSSI_PARM_DATA_MASK 0x000fffff
910 #define REG_TX_AGC_B_MCS07_MCS04 0x0848
911 #define REG_TX_AGC_B_MCS11_MCS08 0x084c
913 #define REG_FPGA0_XCD_SWITCH_CTRL 0x085c
915 #define REG_FPGA0_XA_RF_INT_OE 0x0860 /* RF Channel switch */
916 #define REG_FPGA0_XB_RF_INT_OE 0x0864
917 #define FPGA0_INT_OE_ANTENNA_AB_OPEN 0x000
918 #define FPGA0_INT_OE_ANTENNA_A BIT(8)
919 #define FPGA0_INT_OE_ANTENNA_B BIT(9)
920 #define FPGA0_INT_OE_ANTENNA_MASK (FPGA0_INT_OE_ANTENNA_A | \
921 FPGA0_INT_OE_ANTENNA_B)
923 #define REG_TX_AGC_B_MCS15_MCS12 0x0868
924 #define REG_TX_AGC_B_CCK11_A_CCK2_11 0x086c
926 #define REG_FPGA0_XAB_RF_SW_CTRL 0x0870
927 #define REG_FPGA0_XA_RF_SW_CTRL 0x0870 /* 16 bit */
928 #define REG_FPGA0_XB_RF_SW_CTRL 0x0872 /* 16 bit */
929 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874
930 #define REG_FPGA0_XC_RF_SW_CTRL 0x0874 /* 16 bit */
931 #define REG_FPGA0_XD_RF_SW_CTRL 0x0876 /* 16 bit */
932 #define FPGA0_RF_3WIRE_DATA BIT(0)
933 #define FPGA0_RF_3WIRE_CLOC BIT(1)
934 #define FPGA0_RF_3WIRE_LOAD BIT(2)
935 #define FPGA0_RF_3WIRE_RW BIT(3)
936 #define FPGA0_RF_3WIRE_MASK 0xf
937 #define FPGA0_RF_RFENV BIT(4)
938 #define FPGA0_RF_TRSW BIT(5) /* Useless now */
939 #define FPGA0_RF_TRSWB BIT(6)
940 #define FPGA0_RF_ANTSW BIT(8)
941 #define FPGA0_RF_ANTSWB BIT(9)
942 #define FPGA0_RF_PAPE BIT(10)
943 #define FPGA0_RF_PAPE5G BIT(11)
944 #define FPGA0_RF_BD_CTRL_SHIFT 16
946 #define REG_FPGA0_XAB_RF_PARM 0x0878 /* Antenna select path in ODM */
947 #define REG_FPGA0_XA_RF_PARM 0x0878 /* 16 bit */
948 #define REG_FPGA0_XB_RF_PARM 0x087a /* 16 bit */
949 #define REG_FPGA0_XCD_RF_PARM 0x087c
950 #define REG_FPGA0_XC_RF_PARM 0x087c /* 16 bit */
951 #define REG_FPGA0_XD_RF_PARM 0x087e /* 16 bit */
952 #define FPGA0_RF_PARM_RFA_ENABLE BIT(1)
953 #define FPGA0_RF_PARM_RFB_ENABLE BIT(17)
954 #define FPGA0_RF_PARM_CLK_GATE BIT(31)
956 #define REG_FPGA0_ANALOG1 0x0880
957 #define REG_FPGA0_ANALOG2 0x0884
958 #define FPGA0_ANALOG2_20MHZ BIT(10)
959 #define REG_FPGA0_ANALOG3 0x0888
960 #define REG_FPGA0_ANALOG4 0x088c
962 #define REG_NHM_TH9_TH10_8723B 0x0890
963 #define REG_NHM_TIMER_8723B 0x0894
964 #define REG_NHM_TH3_TO_TH0_8723B 0x0898
965 #define REG_NHM_TH7_TO_TH4_8723B 0x089c
967 #define REG_FPGA0_XA_LSSI_READBACK 0x08a0 /* Tranceiver LSSI Readback */
968 #define REG_FPGA0_XB_LSSI_READBACK 0x08a4
969 #define REG_FPGA0_PSD_REPORT 0x08b4
970 #define REG_HSPI_XA_READBACK 0x08b8 /* Transceiver A HSPI read */
971 #define REG_HSPI_XB_READBACK 0x08bc /* Transceiver B HSPI read */
973 #define REG_FPGA1_RF_MODE 0x0900
975 #define REG_FPGA1_TX_INFO 0x090c
976 #define FPGA1_TX_ANT_MASK 0x0000000f
977 #define FPGA1_TX_ANT_L_MASK 0x000000f0
978 #define FPGA1_TX_ANT_NON_HT_MASK 0x00000f00
979 #define FPGA1_TX_ANT_HT1_MASK 0x0000f000
980 #define FPGA1_TX_ANT_HT2_MASK 0x000f0000
981 #define FPGA1_TX_ANT_HT_S1_MASK 0x00f00000
982 #define FPGA1_TX_ANT_NON_HT_S1_MASK 0x0f000000
983 #define FPGA1_TX_OFDM_TXSC_MASK 0x30000000
985 #define REG_ANT_MAPPING1 0x0914
986 #define REG_RFE_OPT 0x0920
987 #define REG_DPDT_CTRL 0x092c /* 8723BU */
988 #define REG_RFE_CTRL_ANTA_SRC 0x0930 /* 8723BU */
989 #define REG_RFE_CTRL_ANT_SRC1 0x0934
990 #define REG_RFE_CTRL_ANT_SRC2 0x0938
991 #define REG_RFE_CTRL_ANT_SRC3 0x093c
992 #define REG_RFE_PATH_SELECT 0x0940 /* 8723BU */
993 #define REG_RFE_BUFFER 0x0944 /* 8723BU */
994 #define REG_S0S1_PATH_SWITCH 0x0948 /* 8723BU */
995 #define REG_RX_DFIR_MOD_97F 0x0948
996 #define REG_OFDM_RX_DFIR 0x954
997 #define REG_RFE_OPT62 0x0968
999 #define REG_CCK0_SYSTEM 0x0a00
1000 #define CCK0_SIDEBAND BIT(4)
1002 #define REG_CCK0_AFE_SETTING 0x0a04
1003 #define CCK0_AFE_RX_MASK 0x0f000000
1004 #define CCK0_AFE_TX_MASK 0xf0000000
1005 #define CCK0_AFE_RX_ANT_A 0
1006 #define CCK0_AFE_RX_ANT_B BIT(26)
1007 #define CCK0_AFE_RX_ANT_C BIT(27)
1008 #define CCK0_AFE_RX_ANT_D (BIT(26) | BIT(27))
1009 #define CCK0_AFE_RX_ANT_OPTION_A 0
1010 #define CCK0_AFE_RX_ANT_OPTION_B BIT(24)
1011 #define CCK0_AFE_RX_ANT_OPTION_C BIT(25)
1012 #define CCK0_AFE_RX_ANT_OPTION_D (BIT(24) | BIT(25))
1013 #define CCK0_AFE_TX_ANT_A BIT(31)
1014 #define CCK0_AFE_TX_ANT_B BIT(30)
1016 #define REG_CCK_ANTDIV_PARA2 0x0a04
1017 #define REG_BB_POWER_SAVE4 0x0a74
1020 #define REG_LNA_SWITCH 0x0b2c
1021 #define LNA_SWITCH_DISABLE_CSCG BIT(22)
1022 #define LNA_SWITCH_OUTPUT_CG BIT(31)
1024 #define REG_CCK_PD_THRESH 0x0a0a
1025 #define CCK_PD_TYPE1_LV0_TH 0x40
1026 #define CCK_PD_TYPE1_LV1_TH 0x83
1027 #define CCK_PD_TYPE1_LV2_TH 0xcd
1028 #define CCK_PD_TYPE1_LV3_TH 0xdd
1029 #define CCK_PD_TYPE1_LV4_TH 0xed
1031 #define REG_CCK0_TX_FILTER1 0x0a20
1032 #define REG_CCK0_TX_FILTER2 0x0a24
1033 #define REG_CCK0_DEBUG_PORT 0x0a28 /* debug port and Tx filter3 */
1034 #define REG_AGC_RPT 0xa80
1035 #define AGC_RPT_CCK BIT(7)
1036 #define REG_CCK0_TX_FILTER3 0x0aac
1038 #define REG_CONFIG_ANT_A 0x0b68
1039 #define REG_CONFIG_ANT_B 0x0b6c
1041 #define REG_OFDM0_TRX_PATH_ENABLE 0x0c04
1042 #define OFDM_RF_PATH_RX_MASK 0x0f
1043 #define OFDM_RF_PATH_RX_A BIT(0)
1044 #define OFDM_RF_PATH_RX_B BIT(1)
1045 #define OFDM_RF_PATH_RX_C BIT(2)
1046 #define OFDM_RF_PATH_RX_D BIT(3)
1047 #define OFDM_RF_PATH_TX_MASK 0xf0
1048 #define OFDM_RF_PATH_TX_A BIT(4)
1049 #define OFDM_RF_PATH_TX_B BIT(5)
1050 #define OFDM_RF_PATH_TX_C BIT(6)
1051 #define OFDM_RF_PATH_TX_D BIT(7)
1053 #define REG_OFDM0_TR_MUX_PAR 0x0c08
1055 #define REG_OFDM0_FA_RSTC 0x0c0c
1057 #define REG_DOWNSAM_FACTOR 0x0c10
1059 #define REG_OFDM0_XA_RX_AFE 0x0c10
1060 #define REG_OFDM0_XA_RX_IQ_IMBALANCE 0x0c14
1061 #define REG_OFDM0_XB_RX_IQ_IMBALANCE 0x0c1c
1063 #define REG_OFDM0_ENERGY_CCA_THRES 0x0c4c
1065 #define REG_OFDM0_RX_D_SYNC_PATH 0x0c40
1066 #define OFDM0_SYNC_PATH_NOTCH_FILTER BIT(1)
1068 #define REG_OFDM0_XA_AGC_CORE1 0x0c50
1069 #define REG_OFDM0_XA_AGC_CORE2 0x0c54
1070 #define REG_OFDM0_XB_AGC_CORE1 0x0c58
1071 #define REG_OFDM0_XB_AGC_CORE2 0x0c5c
1072 #define REG_OFDM0_XC_AGC_CORE1 0x0c60
1073 #define REG_OFDM0_XC_AGC_CORE2 0x0c64
1074 #define REG_OFDM0_XD_AGC_CORE1 0x0c68
1075 #define REG_OFDM0_XD_AGC_CORE2 0x0c6c
1076 #define OFDM0_X_AGC_CORE1_IGI_MASK 0x0000007F
1078 #define REG_OFDM0_AGC_PARM1 0x0c70
1080 #define REG_OFDM0_AGC_RSSI_TABLE 0x0c78
1082 #define REG_OFDM0_XA_TX_IQ_IMBALANCE 0x0c80
1083 #define REG_OFDM0_XB_TX_IQ_IMBALANCE 0x0c88
1084 #define REG_OFDM0_XC_TX_IQ_IMBALANCE 0x0c90
1085 #define REG_OFDM0_XD_TX_IQ_IMBALANCE 0x0c98
1087 #define REG_OFDM0_XC_TX_AFE 0x0c94
1088 #define REG_OFDM0_XD_TX_AFE 0x0c9c
1090 #define REG_OFDM0_RX_IQ_EXT_ANTA 0x0ca0
1093 #define REG_ANTDIV_PARA1 0x0ca4
1095 #define REG_RXIQB_EXT 0x0ca8
1098 #define REG_OFDM0_TX_PSDO_NOISE_WEIGHT 0x0ce4
1100 #define REG_OFDM1_LSTF 0x0d00
1101 #define OFDM_LSTF_PRIME_CH_LOW BIT(10)
1102 #define OFDM_LSTF_PRIME_CH_HIGH BIT(11)
1103 #define OFDM_LSTF_PRIME_CH_MASK (OFDM_LSTF_PRIME_CH_LOW | \
1104 OFDM_LSTF_PRIME_CH_HIGH)
1105 #define OFDM_LSTF_CONTINUE_TX BIT(28)
1106 #define OFDM_LSTF_SINGLE_CARRIER BIT(29)
1107 #define OFDM_LSTF_SINGLE_TONE BIT(30)
1108 #define OFDM_LSTF_MASK 0x70000000
1110 #define REG_OFDM1_TRX_PATH_ENABLE 0x0d04
1111 #define REG_OFDM1_CFO_TRACKING 0x0d2c
1112 #define CFO_TRACKING_ATC_STATUS BIT(11)
1113 #define REG_OFDM1_CSI_FIX_MASK1 0x0d40
1114 #define REG_OFDM1_CSI_FIX_MASK2 0x0d44
1116 #define REG_ANAPWR1 0x0d94
1118 #define REG_TX_AGC_A_RATE18_06 0x0e00
1119 #define REG_TX_AGC_A_RATE54_24 0x0e04
1120 #define REG_TX_AGC_A_CCK1_MCS32 0x0e08
1121 #define REG_TX_AGC_A_MCS03_MCS00 0x0e10
1122 #define REG_TX_AGC_A_MCS07_MCS04 0x0e14
1123 #define REG_TX_AGC_A_MCS11_MCS08 0x0e18
1124 #define REG_TX_AGC_A_MCS15_MCS12 0x0e1c
1126 #define REG_NP_ANTA 0x0e20
1128 #define REG_TAP_UPD_97F 0x0e24
1130 #define REG_FPGA0_IQK 0x0e28
1132 #define REG_TX_IQK_TONE_A 0x0e30
1133 #define REG_RX_IQK_TONE_A 0x0e34
1134 #define REG_TX_IQK_PI_A 0x0e38
1135 #define REG_RX_IQK_PI_A 0x0e3c
1137 #define REG_TX_IQK 0x0e40
1138 #define REG_RX_IQK 0x0e44
1139 #define REG_IQK_AGC_PTS 0x0e48
1140 #define REG_IQK_AGC_RSP 0x0e4c
1141 #define REG_TX_IQK_TONE_B 0x0e50
1142 #define REG_RX_IQK_TONE_B 0x0e54
1143 #define REG_TX_IQK_PI_B 0x0e58
1144 #define REG_RX_IQK_PI_B 0x0e5c
1145 #define REG_IQK_AGC_CONT 0x0e60
1147 #define REG_BLUETOOTH 0x0e6c
1148 #define REG_RX_WAIT_CCA 0x0e70
1149 #define REG_TX_CCK_RFON 0x0e74
1150 #define REG_TX_CCK_BBON 0x0e78
1151 #define REG_TX_OFDM_RFON 0x0e7c
1152 #define REG_TX_OFDM_BBON 0x0e80
1153 #define REG_TX_TO_RX 0x0e84
1154 #define REG_TX_TO_TX 0x0e88
1155 #define REG_RX_CCK 0x0e8c
1157 #define REG_TX_POWER_BEFORE_IQK_A 0x0e94
1158 #define REG_IQK_RPT_TXA 0x0e98
1159 #define REG_TX_POWER_AFTER_IQK_A 0x0e9c
1161 #define REG_RX_POWER_BEFORE_IQK_A 0x0ea0
1162 #define REG_RX_POWER_BEFORE_IQK_A_2 0x0ea4
1163 #define REG_RX_POWER_AFTER_IQK_A 0x0ea8
1164 #define REG_IQK_RPT_RXA 0x0ea8
1165 #define REG_RX_POWER_AFTER_IQK_A_2 0x0eac
1167 #define REG_TX_POWER_BEFORE_IQK_B 0x0eb4
1168 #define REG_IQK_RPT_TXB 0x0eb8
1169 #define REG_TX_POWER_AFTER_IQK_B 0x0ebc
1171 #define REG_RX_POWER_BEFORE_IQK_B 0x0ec0
1172 #define REG_RX_POWER_BEFORE_IQK_B_2 0x0ec4
1173 #define REG_RX_POWER_AFTER_IQK_B 0x0ec8
1174 #define REG_IQK_RPT_RXB 0x0ec8
1175 #define REG_RX_POWER_AFTER_IQK_B_2 0x0ecc
1177 #define REG_RX_OFDM 0x0ed0
1178 #define REG_RX_WAIT_RIFS 0x0ed4
1179 #define REG_RX_TO_RX 0x0ed8
1180 #define REG_STANDBY 0x0edc
1181 #define REG_SLEEP 0x0ee0
1182 #define REG_PMPD_ANAEN 0x0eec
1184 #define REG_FW_START_ADDRESS 0x1000
1185 #define REG_FW_START_ADDRESS_8192F 0x4000
1187 #define REG_SW_GPIO_SHARE_CTRL_0 0x1038
1188 #define REG_SW_GPIO_SHARE_CTRL_1 0x103c
1189 #define REG_GPIO_A0 0x1050
1190 #define REG_GPIO_B0 0x105b
1192 #define REG_USB_INFO 0xfe17
1193 #define REG_USB_HIMR 0xfe38
1194 #define USB_HIMR_TIMEOUT2 BIT(31)
1195 #define USB_HIMR_TIMEOUT1 BIT(30)
1196 #define USB_HIMR_PSTIMEOUT BIT(29)
1197 #define USB_HIMR_GTINT4 BIT(28)
1198 #define USB_HIMR_GTINT3 BIT(27)
1199 #define USB_HIMR_TXBCNERR BIT(26)
1200 #define USB_HIMR_TXBCNOK BIT(25)
1201 #define USB_HIMR_TSF_BIT32_TOGGLE BIT(24)
1202 #define USB_HIMR_BCNDMAINT3 BIT(23)
1203 #define USB_HIMR_BCNDMAINT2 BIT(22)
1204 #define USB_HIMR_BCNDMAINT1 BIT(21)
1205 #define USB_HIMR_BCNDMAINT0 BIT(20)
1206 #define USB_HIMR_BCNDOK3 BIT(19)
1207 #define USB_HIMR_BCNDOK2 BIT(18)
1208 #define USB_HIMR_BCNDOK1 BIT(17)
1209 #define USB_HIMR_BCNDOK0 BIT(16)
1210 #define USB_HIMR_HSISR_IND BIT(15)
1211 #define USB_HIMR_BCNDMAINT_E BIT(14)
1213 #define USB_HIMR_CTW_END BIT(12)
1215 #define USB_HIMR_C2HCMD BIT(10)
1216 #define USB_HIMR_CPWM2 BIT(9)
1217 #define USB_HIMR_CPWM BIT(8)
1218 #define USB_HIMR_HIGHDOK BIT(7) /* High Queue DMA OK
1220 #define USB_HIMR_MGNTDOK BIT(6) /* Management Queue DMA OK
1222 #define USB_HIMR_BKDOK BIT(5) /* AC_BK DMA OK Interrupt */
1223 #define USB_HIMR_BEDOK BIT(4) /* AC_BE DMA OK Interrupt */
1224 #define USB_HIMR_VIDOK BIT(3) /* AC_VI DMA OK Interrupt */
1225 #define USB_HIMR_VODOK BIT(2) /* AC_VO DMA Interrupt */
1226 #define USB_HIMR_RDU BIT(1) /* Receive Descriptor
1228 #define USB_HIMR_ROK BIT(0) /* Receive DMA OK Interrupt */
1230 #define REG_USB_ACCESS_TIMEOUT 0xfe4c
1232 #define REG_USB_SPECIAL_OPTION 0xfe55
1233 #define USB_SPEC_USB_AGG_ENABLE BIT(3) /* Enable USB aggregation */
1234 #define USB_SPEC_INT_BULK_SELECT BIT(4) /* Use interrupt endpoint to
1235 deliver interrupt packet.
1236 0: Use int, 1: use bulk */
1237 #define REG_USB_HRPWM 0xfe58
1238 #define REG_USB_DMA_AGG_TO 0xfe5b
1239 #define REG_USB_AGG_TIMEOUT 0xfe5c
1240 #define REG_USB_AGG_THRESH 0xfe5d
1242 #define REG_NORMAL_SIE_VID 0xfe60 /* 0xfe60 - 0xfe61 */
1243 #define REG_NORMAL_SIE_PID 0xfe62 /* 0xfe62 - 0xfe63 */
1244 #define REG_NORMAL_SIE_OPTIONAL 0xfe64
1245 #define REG_NORMAL_SIE_EP 0xfe65 /* 0xfe65 - 0xfe67 */
1246 #define REG_NORMAL_SIE_EP_TX 0xfe66
1247 #define NORMAL_SIE_EP_TX_HIGH_MASK 0x000f
1248 #define NORMAL_SIE_EP_TX_NORMAL_MASK 0x00f0
1249 #define NORMAL_SIE_EP_TX_LOW_MASK 0x0f00
1251 #define REG_NORMAL_SIE_PHY 0xfe68 /* 0xfe68 - 0xfe6b */
1252 #define REG_NORMAL_SIE_OPTIONAL2 0xfe6c
1253 #define REG_NORMAL_SIE_GPS_EP 0xfe6d /* RTL8723 only */
1254 #define REG_NORMAL_SIE_MAC_ADDR 0xfe70 /* 0xfe70 - 0xfe75 */
1255 #define REG_NORMAL_SIE_STRING 0xfe80 /* 0xfe80 - 0xfedf */
1258 * 8710B register addresses between 0x00 and 0xff must have 0x8000
1259 * added to them. We take care of that in the rtl8xxxu_read{8,16,32}
1260 * and rtl8xxxu_write{8,16,32} functions.
1262 #define REG_SYS_FUNC_8710B 0x0004
1263 #define REG_AFE_CTRL_8710B 0x0050
1264 #define REG_WL_RF_PSS_8710B 0x005c
1265 #define REG_EFUSE_INDIRECT_CTRL_8710B 0x006c
1266 #define NORMAL_REG_READ_OFFSET 0x83000000
1267 #define NORMAL_REG_WRITE_OFFSET 0x84000000
1268 #define EFUSE_READ_OFFSET 0x85000000
1269 #define EFUSE_WRITE_OFFSET 0x86000000
1270 #define REG_HIMR0_8710B 0x0080
1271 #define REG_HISR0_8710B 0x0084
1273 * 8710B uses this instead of REG_MCU_FW_DL, but at least bits
1274 * 0-7 have the same meaning.
1276 #define REG_8051FW_CTRL_V1_8710B 0x0090
1277 #define REG_USB_HOST_INDIRECT_DATA_8710B 0x009c
1278 #define REG_WL_STATUS_8710B 0x00f0
1279 #define REG_USB_HOST_INDIRECT_ADDR_8710B 0x00f8
1282 * 8710B registers which must be accessed through rtl8710b_read_syson_reg
1283 * and rtl8710b_write_syson_reg.
1285 #define SYSON_REG_BASE_ADDR_8710B 0x40000000
1286 #define REG_SYS_XTAL_CTRL0_8710B 0x060
1287 #define REG_SYS_EEPROM_CTRL0_8710B 0x0e0
1288 #define REG_SYS_SYSTEM_CFG0_8710B 0x1f0
1289 #define REG_SYS_SYSTEM_CFG1_8710B 0x1f4
1290 #define REG_SYS_SYSTEM_CFG2_8710B 0x1f8
1292 /* RF6052 registers */
1293 #define RF6052_REG_AC 0x00
1294 #define RF6052_REG_IQADJ_G1 0x01
1295 #define RF6052_REG_IQADJ_G2 0x02
1296 #define RF6052_REG_BS_PA_APSET_G1_G4 0x03
1297 #define RF6052_REG_BS_PA_APSET_G5_G8 0x04
1298 #define RF6052_REG_POW_TRSW 0x05
1299 #define RF6052_REG_GAIN_RX 0x06
1300 #define RF6052_REG_GAIN_TX 0x07
1301 #define RF6052_REG_TXM_IDAC 0x08
1302 #define RF6052_REG_IPA_G 0x09
1303 #define RF6052_REG_TXBIAS_G 0x0a
1304 #define RF6052_REG_TXPA_AG 0x0b
1305 #define RF6052_REG_IPA_A 0x0c
1306 #define RF6052_REG_TXBIAS_A 0x0d
1307 #define RF6052_REG_BS_PA_APSET_G9_G11 0x0e
1308 #define RF6052_REG_BS_IQGEN 0x0f
1309 #define RF6052_REG_MODE1 0x10
1310 #define RF6052_REG_MODE2 0x11
1311 #define RF6052_REG_RX_AGC_HP 0x12
1312 #define RF6052_REG_TX_AGC 0x13
1313 #define RF6052_REG_BIAS 0x14
1314 #define RF6052_REG_IPA 0x15
1315 #define RF6052_REG_TXBIAS 0x16
1316 #define RF6052_REG_POW_ABILITY 0x17
1317 #define RF6052_REG_MODE_AG 0x18 /* RF channel and BW switch */
1318 #define MODE_AG_CHANNEL_MASK 0x3ff
1319 #define MODE_AG_CHANNEL_20MHZ BIT(10)
1320 #define MODE_AG_BW_MASK (BIT(10) | BIT(11))
1321 #define MODE_AG_BW_20MHZ_8723B (BIT(10) | BIT(11))
1322 #define MODE_AG_BW_40MHZ_8723B BIT(10)
1323 #define MODE_AG_BW_80MHZ_8723B 0
1325 #define RF6052_REG_TOP 0x19
1326 #define RF6052_REG_RX_G1 0x1a
1327 #define RF6052_REG_RX_G2 0x1b
1328 #define RF6052_REG_RX_BB2 0x1c
1329 #define RF6052_REG_RX_BB1 0x1d
1330 #define RF6052_REG_RCK1 0x1e
1331 #define RF6052_REG_RCK2 0x1f
1332 #define RF6052_REG_TX_G1 0x20
1333 #define RF6052_REG_TX_G2 0x21
1334 #define RF6052_REG_TX_G3 0x22
1335 #define RF6052_REG_TX_BB1 0x23
1336 #define RF6052_REG_T_METER 0x24
1337 #define RF6052_REG_SYN_G1 0x25 /* RF TX Power control */
1338 #define RF6052_REG_SYN_G2 0x26 /* RF TX Power control */
1339 #define RF6052_REG_SYN_G3 0x27 /* RF TX Power control */
1340 #define RF6052_REG_SYN_G4 0x28 /* RF TX Power control */
1341 #define RF6052_REG_SYN_G5 0x29 /* RF TX Power control */
1342 #define RF6052_REG_SYN_G6 0x2a /* RF TX Power control */
1343 #define RF6052_REG_SYN_G7 0x2b /* RF TX Power control */
1344 #define RF6052_REG_SYN_G8 0x2c /* RF TX Power control */
1346 #define RF6052_REG_RCK_OS 0x30 /* RF TX PA control */
1348 #define RF6052_REG_TXPA_G1 0x31 /* RF TX PA control */
1349 #define RF6052_REG_TXPA_G2 0x32 /* RF TX PA control */
1350 #define RF6052_REG_TXPA_G3 0x33 /* RF TX PA control */
1353 * NextGen regs: 8723BU
1355 #define RF6052_REG_GAIN_P1 0x35
1356 #define RF6052_REG_T_METER_8723B 0x42
1357 #define RF6052_REG_UNKNOWN_43 0x43
1358 #define RF6052_REG_UNKNOWN_55 0x55
1359 #define RF6052_REG_PAD_TXG 0x56
1360 #define RF6052_REG_TXMOD 0x58
1361 #define RF6052_REG_RXG_MIX_SWBW 0x87
1362 #define RF6052_REG_S0S1 0xb0
1363 #define RF6052_REG_GAIN_CCA 0xdf
1364 #define RF6052_REG_UNKNOWN_ED 0xed
1365 #define RF6052_REG_WE_LUT 0xef
1366 #define RF6052_REG_GAIN_CTRL 0xf5
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