2 * RTL8XXXU mac80211 USB driver
4 * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
24 #include <linux/init.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <linux/errno.h>
28 #include <linux/slab.h>
29 #include <linux/module.h>
30 #include <linux/spinlock.h>
31 #include <linux/list.h>
32 #include <linux/usb.h>
33 #include <linux/netdevice.h>
34 #include <linux/etherdevice.h>
35 #include <linux/ethtool.h>
36 #include <linux/wireless.h>
37 #include <linux/firmware.h>
38 #include <linux/moduleparam.h>
39 #include <net/mac80211.h>
41 #include "rtl8xxxu_regs.h"
43 #define DRIVER_NAME "rtl8xxxu"
45 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46 static bool rtl8xxxu_ht40_2g;
47 static bool rtl8xxxu_dma_aggregation;
48 static int rtl8xxxu_dma_agg_timeout = -1;
49 static int rtl8xxxu_dma_agg_pages = -1;
51 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
52 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
53 MODULE_LICENSE("GPL");
56 module_param_named(debug, rtl8xxxu_debug, int, 0600);
57 MODULE_PARM_DESC(debug, "Set debug mask");
58 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
59 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
60 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
61 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
62 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
63 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
64 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
65 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
67 #define USB_VENDOR_ID_REALTEK 0x0bda
68 #define RTL8XXXU_RX_URBS 32
69 #define RTL8XXXU_RX_URB_PENDING_WATER 8
70 #define RTL8XXXU_TX_URBS 64
71 #define RTL8XXXU_TX_URB_LOW_WATER 25
72 #define RTL8XXXU_TX_URB_HIGH_WATER 32
74 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
75 struct rtl8xxxu_rx_urb *rx_urb);
77 static struct ieee80211_rate rtl8xxxu_rates[] = {
78 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
79 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
80 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
81 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
82 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
83 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
84 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
85 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
86 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
87 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
88 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
89 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
92 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
93 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
94 .hw_value = 1, .max_power = 30 },
95 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
96 .hw_value = 2, .max_power = 30 },
97 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
98 .hw_value = 3, .max_power = 30 },
99 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
100 .hw_value = 4, .max_power = 30 },
101 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
102 .hw_value = 5, .max_power = 30 },
103 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
104 .hw_value = 6, .max_power = 30 },
105 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
106 .hw_value = 7, .max_power = 30 },
107 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
108 .hw_value = 8, .max_power = 30 },
109 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
110 .hw_value = 9, .max_power = 30 },
111 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
112 .hw_value = 10, .max_power = 30 },
113 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
114 .hw_value = 11, .max_power = 30 },
115 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
116 .hw_value = 12, .max_power = 30 },
117 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
118 .hw_value = 13, .max_power = 30 },
119 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
120 .hw_value = 14, .max_power = 30 }
123 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
124 .channels = rtl8xxxu_channels_2g,
125 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
126 .bitrates = rtl8xxxu_rates,
127 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
130 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
131 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
132 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
133 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
134 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
135 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
136 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
137 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
138 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
139 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
140 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
141 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
142 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
143 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
144 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
145 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
146 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
147 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
148 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
149 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
150 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
151 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
152 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
155 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
156 {0x800, 0x80040000}, {0x804, 0x00000003},
157 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
158 {0x810, 0x10001331}, {0x814, 0x020c3d10},
159 {0x818, 0x02200385}, {0x81c, 0x00000000},
160 {0x820, 0x01000100}, {0x824, 0x00390004},
161 {0x828, 0x00000000}, {0x82c, 0x00000000},
162 {0x830, 0x00000000}, {0x834, 0x00000000},
163 {0x838, 0x00000000}, {0x83c, 0x00000000},
164 {0x840, 0x00010000}, {0x844, 0x00000000},
165 {0x848, 0x00000000}, {0x84c, 0x00000000},
166 {0x850, 0x00000000}, {0x854, 0x00000000},
167 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
168 {0x860, 0x66f60110}, {0x864, 0x061f0130},
169 {0x868, 0x00000000}, {0x86c, 0x32323200},
170 {0x870, 0x07000760}, {0x874, 0x22004000},
171 {0x878, 0x00000808}, {0x87c, 0x00000000},
172 {0x880, 0xc0083070}, {0x884, 0x000004d5},
173 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
174 {0x890, 0x00000800}, {0x894, 0xfffffffe},
175 {0x898, 0x40302010}, {0x89c, 0x00706050},
176 {0x900, 0x00000000}, {0x904, 0x00000023},
177 {0x908, 0x00000000}, {0x90c, 0x81121111},
178 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
179 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
180 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
181 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
182 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
183 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
184 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
186 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
187 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
188 {0xc10, 0x08800000}, {0xc14, 0x40000100},
189 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
190 {0xc20, 0x00000000}, {0xc24, 0x00000000},
191 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
192 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
193 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
194 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
195 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
196 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
197 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
198 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
199 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
200 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
201 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
202 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
203 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
204 {0xc90, 0x00121820}, {0xc94, 0x00000000},
205 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
206 {0xca0, 0x00000000}, {0xca4, 0x00000080},
207 {0xca8, 0x00000000}, {0xcac, 0x00000000},
208 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
209 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
210 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
211 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
212 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
213 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
214 {0xce0, 0x00222222}, {0xce4, 0x00000000},
215 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
216 {0xd00, 0x00080740}, {0xd04, 0x00020401},
217 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
218 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
219 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
220 {0xd30, 0x00000000}, {0xd34, 0x80608000},
221 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
222 {0xd40, 0x00000000}, {0xd44, 0x00000000},
223 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
224 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
225 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
226 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
227 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
228 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
229 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
230 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
231 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
232 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
233 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
234 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
235 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
236 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
237 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
238 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
239 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
240 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
241 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
242 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
243 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
244 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
245 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
246 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
247 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
248 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
250 {0xffff, 0xffffffff},
253 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
254 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
255 {0x800, 0x80040002}, {0x804, 0x00000003},
256 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
257 {0x810, 0x10000330}, {0x814, 0x020c3d10},
258 {0x818, 0x02200385}, {0x81c, 0x00000000},
259 {0x820, 0x01000100}, {0x824, 0x00390004},
260 {0x828, 0x01000100}, {0x82c, 0x00390004},
261 {0x830, 0x27272727}, {0x834, 0x27272727},
262 {0x838, 0x27272727}, {0x83c, 0x27272727},
263 {0x840, 0x00010000}, {0x844, 0x00010000},
264 {0x848, 0x27272727}, {0x84c, 0x27272727},
265 {0x850, 0x00000000}, {0x854, 0x00000000},
266 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
267 {0x860, 0x66e60230}, {0x864, 0x061f0130},
268 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
269 {0x870, 0x07000700}, {0x874, 0x22184000},
270 {0x878, 0x08080808}, {0x87c, 0x00000000},
271 {0x880, 0xc0083070}, {0x884, 0x000004d5},
272 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
273 {0x890, 0x00000800}, {0x894, 0xfffffffe},
274 {0x898, 0x40302010}, {0x89c, 0x00706050},
275 {0x900, 0x00000000}, {0x904, 0x00000023},
276 {0x908, 0x00000000}, {0x90c, 0x81121313},
277 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
278 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
279 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
280 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
281 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
282 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
283 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
284 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
285 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
286 {0xc10, 0x08800000}, {0xc14, 0x40000100},
287 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
288 {0xc20, 0x00000000}, {0xc24, 0x00000000},
289 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
290 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
291 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
292 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
293 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
294 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
295 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
296 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
297 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
298 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
299 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
300 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
301 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
302 {0xc90, 0x00121820}, {0xc94, 0x00000000},
303 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
304 {0xca0, 0x00000000}, {0xca4, 0x00000080},
305 {0xca8, 0x00000000}, {0xcac, 0x00000000},
306 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
307 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
308 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
309 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
310 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
311 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
312 {0xce0, 0x00222222}, {0xce4, 0x00000000},
313 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
314 {0xd00, 0x00080740}, {0xd04, 0x00020403},
315 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
316 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
317 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
318 {0xd30, 0x00000000}, {0xd34, 0x80608000},
319 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
320 {0xd40, 0x00000000}, {0xd44, 0x00000000},
321 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
322 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
323 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
324 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
325 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
326 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
327 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
328 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
329 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
330 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
331 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
332 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
333 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
334 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
335 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
336 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
337 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
338 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
339 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
340 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
341 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
342 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
343 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
344 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
345 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
346 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
348 {0xffff, 0xffffffff},
351 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
352 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
353 {0x040, 0x000c0004}, {0x800, 0x80040000},
354 {0x804, 0x00000001}, {0x808, 0x0000fc00},
355 {0x80c, 0x0000000a}, {0x810, 0x10005388},
356 {0x814, 0x020c3d10}, {0x818, 0x02200385},
357 {0x81c, 0x00000000}, {0x820, 0x01000100},
358 {0x824, 0x00390204}, {0x828, 0x00000000},
359 {0x82c, 0x00000000}, {0x830, 0x00000000},
360 {0x834, 0x00000000}, {0x838, 0x00000000},
361 {0x83c, 0x00000000}, {0x840, 0x00010000},
362 {0x844, 0x00000000}, {0x848, 0x00000000},
363 {0x84c, 0x00000000}, {0x850, 0x00000000},
364 {0x854, 0x00000000}, {0x858, 0x569a569a},
365 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
366 {0x864, 0x061f0130}, {0x868, 0x00000000},
367 {0x86c, 0x20202000}, {0x870, 0x03000300},
368 {0x874, 0x22004000}, {0x878, 0x00000808},
369 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
370 {0x884, 0x000004d5}, {0x888, 0x00000000},
371 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
372 {0x894, 0xfffffffe}, {0x898, 0x40302010},
373 {0x89c, 0x00706050}, {0x900, 0x00000000},
374 {0x904, 0x00000023}, {0x908, 0x00000000},
375 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
376 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
377 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
378 {0xa14, 0x11144028}, {0xa18, 0x00881117},
379 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
380 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
381 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
382 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
383 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
384 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
385 {0xc14, 0x40000100}, {0xc18, 0x08800000},
386 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
387 {0xc24, 0x00000000}, {0xc28, 0x00000000},
388 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
389 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
390 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
391 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
392 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
393 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
394 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
395 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
396 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
397 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
398 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
399 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
400 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
401 {0xc94, 0x00000000}, {0xc98, 0x00121820},
402 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
403 {0xca4, 0x00000080}, {0xca8, 0x00000000},
404 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
405 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
406 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
407 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
408 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
409 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
410 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
411 {0xce4, 0x00000000}, {0xce8, 0x37644302},
412 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
413 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
414 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
415 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
416 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
417 {0xd34, 0x80608000}, {0xd38, 0x00000000},
418 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
419 {0xd44, 0x00000000}, {0xd48, 0x00000000},
420 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
421 {0xd54, 0x00000000}, {0xd58, 0x00000000},
422 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
423 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
424 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
425 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
426 {0xe00, 0x24242424}, {0xe04, 0x24242424},
427 {0xe08, 0x03902024}, {0xe10, 0x24242424},
428 {0xe14, 0x24242424}, {0xe18, 0x24242424},
429 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
430 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
431 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
432 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
433 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
434 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
435 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
436 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
437 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
438 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
439 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
440 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
441 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
442 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
443 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
444 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
445 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
447 {0xffff, 0xffffffff},
450 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
451 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
452 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
453 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
454 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
455 {0xc78, 0x78080001}, {0xc78, 0x77090001},
456 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
457 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
458 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
459 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
460 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
461 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
462 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
463 {0xc78, 0x68180001}, {0xc78, 0x67190001},
464 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
465 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
466 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
467 {0xc78, 0x60200001}, {0xc78, 0x49210001},
468 {0xc78, 0x48220001}, {0xc78, 0x47230001},
469 {0xc78, 0x46240001}, {0xc78, 0x45250001},
470 {0xc78, 0x44260001}, {0xc78, 0x43270001},
471 {0xc78, 0x42280001}, {0xc78, 0x41290001},
472 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
473 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
474 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
475 {0xc78, 0x21300001}, {0xc78, 0x20310001},
476 {0xc78, 0x06320001}, {0xc78, 0x05330001},
477 {0xc78, 0x04340001}, {0xc78, 0x03350001},
478 {0xc78, 0x02360001}, {0xc78, 0x01370001},
479 {0xc78, 0x00380001}, {0xc78, 0x00390001},
480 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
481 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
482 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
483 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
484 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
485 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
486 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
487 {0xc78, 0x78480001}, {0xc78, 0x77490001},
488 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
489 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
490 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
491 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
492 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
493 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
494 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
495 {0xc78, 0x68580001}, {0xc78, 0x67590001},
496 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
497 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
498 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
499 {0xc78, 0x60600001}, {0xc78, 0x49610001},
500 {0xc78, 0x48620001}, {0xc78, 0x47630001},
501 {0xc78, 0x46640001}, {0xc78, 0x45650001},
502 {0xc78, 0x44660001}, {0xc78, 0x43670001},
503 {0xc78, 0x42680001}, {0xc78, 0x41690001},
504 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
505 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
506 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
507 {0xc78, 0x21700001}, {0xc78, 0x20710001},
508 {0xc78, 0x06720001}, {0xc78, 0x05730001},
509 {0xc78, 0x04740001}, {0xc78, 0x03750001},
510 {0xc78, 0x02760001}, {0xc78, 0x01770001},
511 {0xc78, 0x00780001}, {0xc78, 0x00790001},
512 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
513 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
514 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
515 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
516 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
517 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
518 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
519 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
520 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
521 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
522 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
523 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
524 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
525 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
526 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
527 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
528 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
529 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
530 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
534 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
535 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
536 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
537 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
538 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
539 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
540 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
541 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
542 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
543 {0xc78, 0x73100001}, {0xc78, 0x72110001},
544 {0xc78, 0x71120001}, {0xc78, 0x70130001},
545 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
546 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
547 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
548 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
549 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
550 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
551 {0xc78, 0x63200001}, {0xc78, 0x62210001},
552 {0xc78, 0x61220001}, {0xc78, 0x60230001},
553 {0xc78, 0x46240001}, {0xc78, 0x45250001},
554 {0xc78, 0x44260001}, {0xc78, 0x43270001},
555 {0xc78, 0x42280001}, {0xc78, 0x41290001},
556 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
557 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
558 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
559 {0xc78, 0x21300001}, {0xc78, 0x20310001},
560 {0xc78, 0x06320001}, {0xc78, 0x05330001},
561 {0xc78, 0x04340001}, {0xc78, 0x03350001},
562 {0xc78, 0x02360001}, {0xc78, 0x01370001},
563 {0xc78, 0x00380001}, {0xc78, 0x00390001},
564 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
565 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
566 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
567 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
568 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
569 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
570 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
571 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
572 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
573 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
574 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
575 {0xc78, 0x73500001}, {0xc78, 0x72510001},
576 {0xc78, 0x71520001}, {0xc78, 0x70530001},
577 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
578 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
579 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
580 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
581 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
582 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
583 {0xc78, 0x63600001}, {0xc78, 0x62610001},
584 {0xc78, 0x61620001}, {0xc78, 0x60630001},
585 {0xc78, 0x46640001}, {0xc78, 0x45650001},
586 {0xc78, 0x44660001}, {0xc78, 0x43670001},
587 {0xc78, 0x42680001}, {0xc78, 0x41690001},
588 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
589 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
590 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
591 {0xc78, 0x21700001}, {0xc78, 0x20710001},
592 {0xc78, 0x06720001}, {0xc78, 0x05730001},
593 {0xc78, 0x04740001}, {0xc78, 0x03750001},
594 {0xc78, 0x02760001}, {0xc78, 0x01770001},
595 {0xc78, 0x00780001}, {0xc78, 0x00790001},
596 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
597 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
598 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
599 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
600 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
601 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
602 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
603 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
604 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
605 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
606 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
607 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
608 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
609 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
610 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
611 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
612 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
613 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
614 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
618 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
620 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
621 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
622 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
623 .hspiread = REG_HSPI_XA_READBACK,
624 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
625 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
628 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
629 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
630 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
631 .hspiread = REG_HSPI_XB_READBACK,
632 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
633 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
637 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
638 REG_OFDM0_XA_RX_IQ_IMBALANCE,
639 REG_OFDM0_XB_RX_IQ_IMBALANCE,
640 REG_OFDM0_ENERGY_CCA_THRES,
641 REG_OFDM0_AGCR_SSI_TABLE,
642 REG_OFDM0_XA_TX_IQ_IMBALANCE,
643 REG_OFDM0_XB_TX_IQ_IMBALANCE,
646 REG_OFDM0_RX_IQ_EXT_ANTA
649 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
651 struct usb_device *udev = priv->udev;
655 mutex_lock(&priv->usb_buf_mutex);
656 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
657 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
658 addr, 0, &priv->usb_buf.val8, sizeof(u8),
659 RTW_USB_CONTROL_MSG_TIMEOUT);
660 data = priv->usb_buf.val8;
661 mutex_unlock(&priv->usb_buf_mutex);
663 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
664 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
665 __func__, addr, data, len);
669 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
671 struct usb_device *udev = priv->udev;
675 mutex_lock(&priv->usb_buf_mutex);
676 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
677 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
678 addr, 0, &priv->usb_buf.val16, sizeof(u16),
679 RTW_USB_CONTROL_MSG_TIMEOUT);
680 data = le16_to_cpu(priv->usb_buf.val16);
681 mutex_unlock(&priv->usb_buf_mutex);
683 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
684 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
685 __func__, addr, data, len);
689 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
691 struct usb_device *udev = priv->udev;
695 mutex_lock(&priv->usb_buf_mutex);
696 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
697 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
698 addr, 0, &priv->usb_buf.val32, sizeof(u32),
699 RTW_USB_CONTROL_MSG_TIMEOUT);
700 data = le32_to_cpu(priv->usb_buf.val32);
701 mutex_unlock(&priv->usb_buf_mutex);
703 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
704 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
705 __func__, addr, data, len);
709 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
711 struct usb_device *udev = priv->udev;
714 mutex_lock(&priv->usb_buf_mutex);
715 priv->usb_buf.val8 = val;
716 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
717 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
718 addr, 0, &priv->usb_buf.val8, sizeof(u8),
719 RTW_USB_CONTROL_MSG_TIMEOUT);
721 mutex_unlock(&priv->usb_buf_mutex);
723 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
724 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
725 __func__, addr, val);
729 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
731 struct usb_device *udev = priv->udev;
734 mutex_lock(&priv->usb_buf_mutex);
735 priv->usb_buf.val16 = cpu_to_le16(val);
736 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
737 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
738 addr, 0, &priv->usb_buf.val16, sizeof(u16),
739 RTW_USB_CONTROL_MSG_TIMEOUT);
740 mutex_unlock(&priv->usb_buf_mutex);
742 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
743 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
744 __func__, addr, val);
748 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
750 struct usb_device *udev = priv->udev;
753 mutex_lock(&priv->usb_buf_mutex);
754 priv->usb_buf.val32 = cpu_to_le32(val);
755 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
756 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
757 addr, 0, &priv->usb_buf.val32, sizeof(u32),
758 RTW_USB_CONTROL_MSG_TIMEOUT);
759 mutex_unlock(&priv->usb_buf_mutex);
761 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
762 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
763 __func__, addr, val);
768 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
770 struct usb_device *udev = priv->udev;
771 int blocksize = priv->fops->writeN_block_size;
772 int ret, i, count, remainder;
774 count = len / blocksize;
775 remainder = len % blocksize;
777 for (i = 0; i < count; i++) {
778 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
779 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
780 addr, 0, buf, blocksize,
781 RTW_USB_CONTROL_MSG_TIMEOUT);
782 if (ret != blocksize)
790 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
791 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
792 addr, 0, buf, remainder,
793 RTW_USB_CONTROL_MSG_TIMEOUT);
794 if (ret != remainder)
802 "%s: Failed to write block at addr: %04x size: %04x\n",
803 __func__, addr, blocksize);
807 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
808 enum rtl8xxxu_rfpath path, u8 reg)
810 u32 hssia, val32, retval;
812 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
814 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
818 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
819 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
820 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
821 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
822 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
826 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
829 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
833 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
834 if (val32 & FPGA0_HSSI_PARM1_PI)
835 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
837 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
841 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
842 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
843 __func__, reg, retval);
848 * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
849 * have write issues in high temperature conditions. We may have to
850 * retry writing them.
852 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
853 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
858 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
859 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
860 __func__, reg, data);
862 data &= FPGA0_LSSI_PARM_DATA_MASK;
863 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
865 if (priv->rtl_chip == RTL8192E) {
866 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
868 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
871 /* Use XB for path B */
872 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
873 if (ret != sizeof(dataaddr))
880 if (priv->rtl_chip == RTL8192E) {
881 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
883 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
890 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
892 struct device *dev = &priv->udev->dev;
893 int mbox_nr, retry, retval = 0;
894 int mbox_reg, mbox_ext_reg;
897 mutex_lock(&priv->h2c_mutex);
899 mbox_nr = priv->next_mbox;
900 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
901 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
908 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
909 if (!(val8 & BIT(mbox_nr)))
914 dev_info(dev, "%s: Mailbox busy\n", __func__);
920 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
922 if (len > sizeof(u32)) {
923 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
924 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
925 dev_info(dev, "H2C_EXT %04x\n",
926 le16_to_cpu(h2c->raw.ext));
928 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
929 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
930 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
932 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
935 mutex_unlock(&priv->h2c_mutex);
940 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
942 struct device *dev = &priv->udev->dev;
943 int mbox_nr, retry, retval = 0;
944 int mbox_reg, mbox_ext_reg;
947 mutex_lock(&priv->h2c_mutex);
949 mbox_nr = priv->next_mbox;
950 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
951 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
958 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
959 if (!(val8 & BIT(mbox_nr)))
964 dev_info(dev, "%s: Mailbox busy\n", __func__);
970 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
972 if (len > sizeof(u32)) {
973 rtl8xxxu_write32(priv, mbox_ext_reg,
974 le32_to_cpu(h2c->raw_wide.ext));
975 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
976 dev_info(dev, "H2C_EXT %08x\n",
977 le32_to_cpu(h2c->raw_wide.ext));
979 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
980 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
981 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
983 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
986 mutex_unlock(&priv->h2c_mutex);
990 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
995 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
996 val8 |= BIT(0) | BIT(3);
997 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
999 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1000 val32 &= ~(BIT(4) | BIT(5));
1002 if (priv->rf_paths == 2) {
1003 val32 &= ~(BIT(20) | BIT(21));
1006 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1008 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1009 val32 &= ~OFDM_RF_PATH_TX_MASK;
1010 if (priv->tx_paths == 2)
1011 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1012 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1013 val32 |= OFDM_RF_PATH_TX_B;
1015 val32 |= OFDM_RF_PATH_TX_A;
1016 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1018 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1019 val32 &= ~FPGA_RF_MODE_JAPAN;
1020 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1022 if (priv->rf_paths == 2)
1023 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1025 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1027 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1028 if (priv->rf_paths == 2)
1029 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1031 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1034 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1039 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1041 /* RF RX code for preamble power saving */
1042 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1043 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1044 if (priv->rf_paths == 2)
1045 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1046 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1048 /* Disable TX for four paths */
1049 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1050 val32 &= ~OFDM_RF_PATH_TX_MASK;
1051 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1053 /* Enable power saving */
1054 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1055 val32 |= FPGA_RF_MODE_JAPAN;
1056 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1058 /* AFE control register to power down bits [30:22] */
1059 if (priv->rf_paths == 2)
1060 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1062 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1064 /* Power down RF module */
1065 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1066 if (priv->rf_paths == 2)
1067 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1069 sps0 &= ~(BIT(0) | BIT(3));
1070 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1073 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1077 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1079 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1081 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1082 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1084 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1089 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1090 * supports the 2.4GHz band, so channels 1 - 14:
1091 * group 0: channels 1 - 3
1092 * group 1: channels 4 - 9
1093 * group 2: channels 10 - 14
1095 * Note: We index from 0 in the code
1097 static int rtl8xxxu_gen1_channel_to_group(int channel)
1103 else if (channel < 10)
1112 * Valid for rtl8723bu and rtl8192eu
1114 int rtl8xxxu_gen2_channel_to_group(int channel)
1120 else if (channel < 6)
1122 else if (channel < 9)
1124 else if (channel < 12)
1132 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1134 struct rtl8xxxu_priv *priv = hw->priv;
1138 int sec_ch_above, channel;
1141 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1142 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1143 channel = hw->conf.chandef.chan->hw_value;
1145 switch (hw->conf.chandef.width) {
1146 case NL80211_CHAN_WIDTH_20_NOHT:
1148 case NL80211_CHAN_WIDTH_20:
1149 opmode |= BW_OPMODE_20MHZ;
1150 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1152 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1153 val32 &= ~FPGA_RF_MODE;
1154 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1156 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1157 val32 &= ~FPGA_RF_MODE;
1158 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1160 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1161 val32 |= FPGA0_ANALOG2_20MHZ;
1162 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1164 case NL80211_CHAN_WIDTH_40:
1165 if (hw->conf.chandef.center_freq1 >
1166 hw->conf.chandef.chan->center_freq) {
1174 opmode &= ~BW_OPMODE_20MHZ;
1175 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1176 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1178 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1180 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1181 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1183 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1184 val32 |= FPGA_RF_MODE;
1185 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1187 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1188 val32 |= FPGA_RF_MODE;
1189 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1192 * Set Control channel to upper or lower. These settings
1193 * are required only for 40MHz
1195 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1196 val32 &= ~CCK0_SIDEBAND;
1198 val32 |= CCK0_SIDEBAND;
1199 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1201 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1202 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1204 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1206 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1207 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1209 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1210 val32 &= ~FPGA0_ANALOG2_20MHZ;
1211 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1213 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1214 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1216 val32 |= FPGA0_PS_UPPER_CHANNEL;
1218 val32 |= FPGA0_PS_LOWER_CHANNEL;
1219 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1226 for (i = RF_A; i < priv->rf_paths; i++) {
1227 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1228 val32 &= ~MODE_AG_CHANNEL_MASK;
1230 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1238 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1239 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1241 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1242 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1244 for (i = RF_A; i < priv->rf_paths; i++) {
1245 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1246 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1247 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1249 val32 |= MODE_AG_CHANNEL_20MHZ;
1250 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1254 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1256 struct rtl8xxxu_priv *priv = hw->priv;
1258 u8 val8, subchannel;
1261 int sec_ch_above, channel;
1264 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1265 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1266 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1267 channel = hw->conf.chandef.chan->hw_value;
1272 switch (hw->conf.chandef.width) {
1273 case NL80211_CHAN_WIDTH_20_NOHT:
1275 case NL80211_CHAN_WIDTH_20:
1276 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1279 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1280 val32 &= ~FPGA_RF_MODE;
1281 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1283 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1284 val32 &= ~FPGA_RF_MODE;
1285 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1287 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1288 val32 &= ~(BIT(30) | BIT(31));
1289 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1292 case NL80211_CHAN_WIDTH_40:
1293 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1295 if (hw->conf.chandef.center_freq1 >
1296 hw->conf.chandef.chan->center_freq) {
1304 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1305 val32 |= FPGA_RF_MODE;
1306 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1308 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1309 val32 |= FPGA_RF_MODE;
1310 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1313 * Set Control channel to upper or lower. These settings
1314 * are required only for 40MHz
1316 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1317 val32 &= ~CCK0_SIDEBAND;
1319 val32 |= CCK0_SIDEBAND;
1320 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1322 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1323 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1325 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1327 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1328 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1330 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1331 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1333 val32 |= FPGA0_PS_UPPER_CHANNEL;
1335 val32 |= FPGA0_PS_LOWER_CHANNEL;
1336 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1338 case NL80211_CHAN_WIDTH_80:
1339 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1345 for (i = RF_A; i < priv->rf_paths; i++) {
1346 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1347 val32 &= ~MODE_AG_CHANNEL_MASK;
1349 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1352 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1353 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1360 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1361 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1363 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1364 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1366 for (i = RF_A; i < priv->rf_paths; i++) {
1367 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1368 val32 &= ~MODE_AG_BW_MASK;
1369 switch(hw->conf.chandef.width) {
1370 case NL80211_CHAN_WIDTH_80:
1371 val32 |= MODE_AG_BW_80MHZ_8723B;
1373 case NL80211_CHAN_WIDTH_40:
1374 val32 |= MODE_AG_BW_40MHZ_8723B;
1377 val32 |= MODE_AG_BW_20MHZ_8723B;
1380 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1385 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1387 struct rtl8xxxu_power_base *power_base = priv->power_base;
1388 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1389 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1390 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1394 group = rtl8xxxu_gen1_channel_to_group(channel);
1396 cck[0] = priv->cck_tx_power_index_A[group] - 1;
1397 cck[1] = priv->cck_tx_power_index_B[group] - 1;
1406 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1407 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1413 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1414 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1416 mcsbase[0] = ofdm[0];
1417 mcsbase[1] = ofdm[1];
1419 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1420 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1423 if (priv->tx_paths > 1) {
1424 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1425 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1426 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1427 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1430 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1431 dev_info(&priv->udev->dev,
1432 "%s: Setting TX power CCK A: %02x, "
1433 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1434 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1436 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1437 if (cck[i] > RF6052_MAX_TX_PWR)
1438 cck[i] = RF6052_MAX_TX_PWR;
1439 if (ofdm[i] > RF6052_MAX_TX_PWR)
1440 ofdm[i] = RF6052_MAX_TX_PWR;
1443 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1444 val32 &= 0xffff00ff;
1445 val32 |= (cck[0] << 8);
1446 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1448 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1450 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1451 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1453 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1454 val32 &= 0xffffff00;
1456 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1458 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1460 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1461 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1463 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1464 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1465 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1466 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1468 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1469 ofdm_a + power_base->reg_0e00);
1470 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1471 ofdm_b + power_base->reg_0830);
1473 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1474 ofdm_a + power_base->reg_0e04);
1475 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1476 ofdm_b + power_base->reg_0834);
1478 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1479 mcsbase[0] << 16 | mcsbase[0] << 24;
1480 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1481 mcsbase[1] << 16 | mcsbase[1] << 24;
1483 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1484 mcs_a + power_base->reg_0e10);
1485 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1486 mcs_b + power_base->reg_083c);
1488 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1489 mcs_a + power_base->reg_0e14);
1490 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1491 mcs_b + power_base->reg_0848);
1493 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1494 mcs_a + power_base->reg_0e18);
1495 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1496 mcs_b + power_base->reg_084c);
1498 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1499 mcs_a + power_base->reg_0e1c);
1500 for (i = 0; i < 3; i++) {
1502 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1504 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1505 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1507 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1508 mcs_b + power_base->reg_0868);
1509 for (i = 0; i < 3; i++) {
1511 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1513 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1514 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1518 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1519 enum nl80211_iftype linktype)
1523 val8 = rtl8xxxu_read8(priv, REG_MSR);
1524 val8 &= ~MSR_LINKTYPE_MASK;
1527 case NL80211_IFTYPE_UNSPECIFIED:
1528 val8 |= MSR_LINKTYPE_NONE;
1530 case NL80211_IFTYPE_ADHOC:
1531 val8 |= MSR_LINKTYPE_ADHOC;
1533 case NL80211_IFTYPE_STATION:
1534 val8 |= MSR_LINKTYPE_STATION;
1536 case NL80211_IFTYPE_AP:
1537 val8 |= MSR_LINKTYPE_AP;
1543 rtl8xxxu_write8(priv, REG_MSR, val8);
1549 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1553 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1554 RETRY_LIMIT_SHORT_MASK) |
1555 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1556 RETRY_LIMIT_LONG_MASK);
1558 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1562 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1566 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1567 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1569 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1572 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1574 struct device *dev = &priv->udev->dev;
1577 switch (priv->chip_cut) {
1598 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1599 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1600 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1601 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1603 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1606 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1608 struct device *dev = &priv->udev->dev;
1612 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1613 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1614 SYS_CFG_CHIP_VERSION_SHIFT;
1615 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1616 dev_info(dev, "Unsupported test chip\n");
1620 if (val32 & SYS_CFG_BT_FUNC) {
1621 if (priv->chip_cut >= 3) {
1622 sprintf(priv->chip_name, "8723BU");
1623 priv->rtl_chip = RTL8723B;
1625 sprintf(priv->chip_name, "8723AU");
1626 priv->usb_interrupts = 1;
1627 priv->rtl_chip = RTL8723A;
1634 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1635 if (val32 & MULTI_WIFI_FUNC_EN)
1637 if (val32 & MULTI_BT_FUNC_EN)
1638 priv->has_bluetooth = 1;
1639 if (val32 & MULTI_GPS_FUNC_EN)
1641 priv->is_multi_func = 1;
1642 } else if (val32 & SYS_CFG_TYPE_ID) {
1643 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1644 bonding &= HPON_FSM_BONDING_MASK;
1645 if (priv->fops->tx_desc_size ==
1646 sizeof(struct rtl8xxxu_txdesc40)) {
1647 if (bonding == HPON_FSM_BONDING_1T2R) {
1648 sprintf(priv->chip_name, "8191EU");
1652 priv->rtl_chip = RTL8191E;
1654 sprintf(priv->chip_name, "8192EU");
1658 priv->rtl_chip = RTL8192E;
1660 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1661 sprintf(priv->chip_name, "8191CU");
1665 priv->usb_interrupts = 1;
1666 priv->rtl_chip = RTL8191C;
1668 sprintf(priv->chip_name, "8192CU");
1672 priv->usb_interrupts = 1;
1673 priv->rtl_chip = RTL8192C;
1677 sprintf(priv->chip_name, "8188CU");
1681 priv->rtl_chip = RTL8188C;
1682 priv->usb_interrupts = 1;
1686 switch (priv->rtl_chip) {
1690 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1691 case SYS_CFG_VENDOR_ID_TSMC:
1692 sprintf(priv->chip_vendor, "TSMC");
1694 case SYS_CFG_VENDOR_ID_SMIC:
1695 sprintf(priv->chip_vendor, "SMIC");
1696 priv->vendor_smic = 1;
1698 case SYS_CFG_VENDOR_ID_UMC:
1699 sprintf(priv->chip_vendor, "UMC");
1700 priv->vendor_umc = 1;
1703 sprintf(priv->chip_vendor, "unknown");
1707 if (val32 & SYS_CFG_VENDOR_ID) {
1708 sprintf(priv->chip_vendor, "UMC");
1709 priv->vendor_umc = 1;
1711 sprintf(priv->chip_vendor, "TSMC");
1715 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1716 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1718 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1719 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1720 priv->ep_tx_high_queue = 1;
1721 priv->ep_tx_count++;
1724 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1725 priv->ep_tx_normal_queue = 1;
1726 priv->ep_tx_count++;
1729 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1730 priv->ep_tx_low_queue = 1;
1731 priv->ep_tx_count++;
1735 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1737 if (!priv->ep_tx_count) {
1738 switch (priv->nr_out_eps) {
1741 priv->ep_tx_low_queue = 1;
1742 priv->ep_tx_count++;
1744 priv->ep_tx_normal_queue = 1;
1745 priv->ep_tx_count++;
1747 priv->ep_tx_high_queue = 1;
1748 priv->ep_tx_count++;
1751 dev_info(dev, "Unsupported USB TX end-points\n");
1760 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1767 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1768 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1770 val8 |= (offset >> 8) & 0x03;
1771 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1773 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1774 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1776 /* Poll for data read */
1777 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1778 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1779 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1780 if (val32 & BIT(31))
1784 if (i == RTL8XXXU_MAX_REG_POLL)
1788 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1790 *data = val32 & 0xff;
1794 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1796 struct device *dev = &priv->udev->dev;
1798 u8 val8, word_mask, header, extheader;
1799 u16 val16, efuse_addr, offset;
1802 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1803 if (val16 & EEPROM_ENABLE)
1804 priv->has_eeprom = 1;
1805 if (val16 & EEPROM_BOOT)
1806 priv->boot_eeprom = 1;
1808 if (priv->is_multi_func) {
1809 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1810 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1811 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1814 dev_dbg(dev, "Booting from %s\n",
1815 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1817 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1819 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1820 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1821 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1822 val16 |= SYS_ISO_PWC_EV12V;
1823 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1825 /* Reset: 0x0000[28], default valid */
1826 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1827 if (!(val16 & SYS_FUNC_ELDR)) {
1828 val16 |= SYS_FUNC_ELDR;
1829 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1833 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1835 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1836 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1837 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1838 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1841 /* Default value is 0xff */
1842 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1845 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1848 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1849 if (ret || header == 0xff)
1852 if ((header & 0x1f) == 0x0f) { /* extended header */
1853 offset = (header & 0xe0) >> 5;
1855 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1859 /* All words disabled */
1860 if ((extheader & 0x0f) == 0x0f)
1863 offset |= ((extheader & 0xf0) >> 1);
1864 word_mask = extheader & 0x0f;
1866 offset = (header >> 4) & 0x0f;
1867 word_mask = header & 0x0f;
1870 /* Get word enable value from PG header */
1872 /* We have 8 bits to indicate validity */
1873 map_addr = offset * 8;
1874 if (map_addr >= EFUSE_MAP_LEN) {
1875 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1877 __func__, map_addr);
1881 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1882 /* Check word enable condition in the section */
1883 if (word_mask & BIT(i)) {
1888 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1891 priv->efuse_wifi.raw[map_addr++] = val8;
1893 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1896 priv->efuse_wifi.raw[map_addr++] = val8;
1901 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1906 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1911 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1913 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1915 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1916 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1917 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1919 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1921 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1923 sys_func |= SYS_FUNC_CPU_ENABLE;
1924 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1927 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1929 struct device *dev = &priv->udev->dev;
1933 /* Poll checksum report */
1934 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1935 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1936 if (val32 & MCU_FW_DL_CSUM_REPORT)
1940 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1941 dev_warn(dev, "Firmware checksum poll timed out\n");
1946 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1947 val32 |= MCU_FW_DL_READY;
1948 val32 &= ~MCU_WINT_INIT_READY;
1949 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1952 * Reset the 8051 in order for the firmware to start running,
1953 * otherwise it won't come up on the 8192eu
1955 priv->fops->reset_8051(priv);
1957 /* Wait for firmware to become ready */
1958 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1959 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1960 if (val32 & MCU_WINT_INIT_READY)
1966 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1967 dev_warn(dev, "Firmware failed to start\n");
1975 if (priv->rtl_chip == RTL8723B)
1976 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1981 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1983 int pages, remainder, i, ret;
1989 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1991 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
1994 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1995 val16 |= SYS_FUNC_CPU_ENABLE;
1996 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1998 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
1999 if (val8 & MCU_FW_RAM_SEL) {
2000 pr_info("do the RAM reset\n");
2001 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2002 priv->fops->reset_8051(priv);
2005 /* MCU firmware download enable */
2006 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2007 val8 |= MCU_FW_DL_ENABLE;
2008 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2011 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2013 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2015 /* Reset firmware download checksum */
2016 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2017 val8 |= MCU_FW_DL_CSUM_REPORT;
2018 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2020 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2021 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2023 fwptr = priv->fw_data->data;
2025 for (i = 0; i < pages; i++) {
2026 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2028 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2030 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2031 fwptr, RTL_FW_PAGE_SIZE);
2032 if (ret != RTL_FW_PAGE_SIZE) {
2037 fwptr += RTL_FW_PAGE_SIZE;
2041 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2043 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2044 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2046 if (ret != remainder) {
2054 /* MCU firmware download disable */
2055 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2056 val16 &= ~MCU_FW_DL_ENABLE;
2057 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2062 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2064 struct device *dev = &priv->udev->dev;
2065 const struct firmware *fw;
2069 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2070 if (reject_firmware(&fw, fw_name, &priv->udev->dev)) {
2071 dev_warn(dev, "reject_firmware(%s) failed\n", fw_name);
2076 dev_warn(dev, "Firmware data not available\n");
2081 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2082 if (!priv->fw_data) {
2086 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2088 signature = le16_to_cpu(priv->fw_data->signature);
2089 switch (signature & 0xfff0) {
2098 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2099 __func__, signature);
2102 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2103 le16_to_cpu(priv->fw_data->major_version),
2104 priv->fw_data->minor_version, signature);
2107 release_firmware(fw);
2111 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2116 /* Inform 8051 to perform reset */
2117 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2119 for (i = 100; i > 0; i--) {
2120 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2122 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2123 dev_dbg(&priv->udev->dev,
2124 "%s: Firmware self reset success!\n", __func__);
2131 /* Force firmware reset */
2132 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2133 val16 &= ~SYS_FUNC_CPU_ENABLE;
2134 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2139 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2141 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2146 for (i = 0; ; i++) {
2150 if (reg == 0xffff && val == 0xff)
2153 ret = rtl8xxxu_write8(priv, reg, val);
2155 dev_warn(&priv->udev->dev,
2156 "Failed to initialize MAC "
2157 "(reg: %04x, val %02x)\n", reg, val);
2162 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
2163 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2168 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2169 struct rtl8xxxu_reg32val *array)
2175 for (i = 0; ; i++) {
2179 if (reg == 0xffff && val == 0xffffffff)
2182 ret = rtl8xxxu_write32(priv, reg, val);
2183 if (ret != sizeof(val)) {
2184 dev_warn(&priv->udev->dev,
2185 "Failed to initialize PHY\n");
2194 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2196 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2200 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2202 val8 |= AFE_PLL_320_ENABLE;
2203 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2206 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2209 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2210 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2211 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2213 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2214 val32 &= ~AFE_XTAL_RF_GATE;
2215 if (priv->has_bluetooth)
2216 val32 &= ~AFE_XTAL_BT_GATE;
2217 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2219 /* 6. 0x1f[7:0] = 0x07 */
2220 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2221 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2224 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2225 else if (priv->tx_paths == 2)
2226 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2228 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2230 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2231 priv->vendor_umc && priv->chip_cut == 1)
2232 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2235 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2237 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2239 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2240 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2243 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2244 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2248 * Most of this is black magic retrieved from the old rtl8723au driver
2250 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2255 priv->fops->init_phy_bb(priv);
2257 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2259 * For 1T2R boards, patch the registers.
2261 * It looks like 8191/2 1T2R boards use path B for TX
2263 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2264 val32 &= ~(BIT(0) | BIT(1));
2266 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2268 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2271 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2273 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2274 val32 &= ~CCK0_AFE_RX_MASK;
2275 val32 &= 0x00ffffff;
2276 val32 |= 0x40000000;
2277 val32 |= CCK0_AFE_RX_ANT_B;
2278 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2280 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2281 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2282 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2284 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2286 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2287 val32 &= ~(BIT(4) | BIT(5));
2289 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2291 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2292 val32 &= ~(BIT(27) | BIT(26));
2294 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2296 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2297 val32 &= ~(BIT(27) | BIT(26));
2299 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2301 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2302 val32 &= ~(BIT(27) | BIT(26));
2304 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2306 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2307 val32 &= ~(BIT(27) | BIT(26));
2309 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2311 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2312 val32 &= ~(BIT(27) | BIT(26));
2314 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2317 if (priv->has_xtalk) {
2318 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2321 val32 &= 0xff000fff;
2322 val32 |= ((val8 | (val8 << 6)) << 12);
2324 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2327 if (priv->rtl_chip == RTL8192E)
2328 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2333 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2334 struct rtl8xxxu_rfregval *array,
2335 enum rtl8xxxu_rfpath path)
2341 for (i = 0; ; i++) {
2345 if (reg == 0xff && val == 0xffffffff)
2369 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2371 dev_warn(&priv->udev->dev,
2372 "Failed to initialize RF\n");
2381 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2382 struct rtl8xxxu_rfregval *table,
2383 enum rtl8xxxu_rfpath path)
2386 u16 val16, rfsi_rfenv;
2387 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2391 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2392 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2393 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2396 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2397 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2398 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2401 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2402 __func__, path + 'A');
2405 /* For path B, use XB */
2406 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2407 rfsi_rfenv &= FPGA0_RF_RFENV;
2410 * These two we might be able to optimize into one
2412 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2413 val32 |= BIT(20); /* 0x10 << 16 */
2414 rtl8xxxu_write32(priv, reg_int_oe, val32);
2417 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2419 rtl8xxxu_write32(priv, reg_int_oe, val32);
2423 * These two we might be able to optimize into one
2425 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2426 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2427 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2430 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2431 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2432 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2435 rtl8xxxu_init_rf_regs(priv, table, path);
2437 /* For path B, use XB */
2438 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2439 val16 &= ~FPGA0_RF_RFENV;
2440 val16 |= rfsi_rfenv;
2441 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2446 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2452 value = LLT_OP_WRITE | address << 8 | data;
2454 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2457 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2458 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2462 } while (count++ < 20);
2467 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2473 last_tx_page = priv->fops->total_page_num;
2475 for (i = 0; i < last_tx_page; i++) {
2476 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2481 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2485 /* Mark remaining pages as a ring buffer */
2486 for (i = last_tx_page + 1; i < 0xff; i++) {
2487 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2492 /* Let last entry point to the start entry of ring buffer */
2493 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2501 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2507 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2508 val32 |= AUTO_LLT_INIT_LLT;
2509 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2511 for (i = 500; i; i--) {
2512 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2513 if (!(val32 & AUTO_LLT_INIT_LLT))
2520 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2526 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2529 u16 hiq, mgq, bkq, beq, viq, voq;
2530 int hip, mgp, bkp, bep, vip, vop;
2533 switch (priv->ep_tx_count) {
2535 if (priv->ep_tx_high_queue) {
2536 hi = TRXDMA_QUEUE_HIGH;
2537 } else if (priv->ep_tx_low_queue) {
2538 hi = TRXDMA_QUEUE_LOW;
2539 } else if (priv->ep_tx_normal_queue) {
2540 hi = TRXDMA_QUEUE_NORMAL;
2561 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2562 hi = TRXDMA_QUEUE_HIGH;
2563 lo = TRXDMA_QUEUE_LOW;
2564 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2565 hi = TRXDMA_QUEUE_NORMAL;
2566 lo = TRXDMA_QUEUE_LOW;
2567 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2568 hi = TRXDMA_QUEUE_HIGH;
2569 lo = TRXDMA_QUEUE_NORMAL;
2591 beq = TRXDMA_QUEUE_LOW;
2592 bkq = TRXDMA_QUEUE_LOW;
2593 viq = TRXDMA_QUEUE_NORMAL;
2594 voq = TRXDMA_QUEUE_HIGH;
2595 mgq = TRXDMA_QUEUE_HIGH;
2596 hiq = TRXDMA_QUEUE_HIGH;
2610 * None of the vendor drivers are configuring the beacon
2611 * queue here .... why?
2614 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2616 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2617 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2618 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2619 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2620 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2621 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2622 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2624 priv->pipe_out[TXDESC_QUEUE_VO] =
2625 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2626 priv->pipe_out[TXDESC_QUEUE_VI] =
2627 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2628 priv->pipe_out[TXDESC_QUEUE_BE] =
2629 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2630 priv->pipe_out[TXDESC_QUEUE_BK] =
2631 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2632 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2633 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2634 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2635 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2636 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2637 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2638 priv->pipe_out[TXDESC_QUEUE_CMD] =
2639 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2645 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2646 int result[][8], int candidate, bool tx_only)
2648 u32 oldval, x, tx0_a, reg;
2655 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2656 oldval = val32 >> 22;
2658 x = result[candidate][0];
2659 if ((x & 0x00000200) != 0)
2661 tx0_a = (x * oldval) >> 8;
2663 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2666 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2668 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2670 if ((x * oldval >> 7) & 0x1)
2672 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2674 y = result[candidate][1];
2675 if ((y & 0x00000200) != 0)
2677 tx0_c = (y * oldval) >> 8;
2679 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2680 val32 &= ~0xf0000000;
2681 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2682 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2684 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2685 val32 &= ~0x003f0000;
2686 val32 |= ((tx0_c & 0x3f) << 16);
2687 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2689 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2691 if ((y * oldval >> 7) & 0x1)
2693 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2696 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2700 reg = result[candidate][2];
2702 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2704 val32 |= (reg & 0x3ff);
2705 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2707 reg = result[candidate][3] & 0x3F;
2709 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2711 val32 |= ((reg << 10) & 0xfc00);
2712 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2714 reg = (result[candidate][3] >> 6) & 0xF;
2716 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2717 val32 &= ~0xf0000000;
2718 val32 |= (reg << 28);
2719 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2722 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2723 int result[][8], int candidate, bool tx_only)
2725 u32 oldval, x, tx1_a, reg;
2732 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2733 oldval = val32 >> 22;
2735 x = result[candidate][4];
2736 if ((x & 0x00000200) != 0)
2738 tx1_a = (x * oldval) >> 8;
2740 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2743 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2745 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2747 if ((x * oldval >> 7) & 0x1)
2749 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2751 y = result[candidate][5];
2752 if ((y & 0x00000200) != 0)
2754 tx1_c = (y * oldval) >> 8;
2756 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2757 val32 &= ~0xf0000000;
2758 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2759 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2761 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2762 val32 &= ~0x003f0000;
2763 val32 |= ((tx1_c & 0x3f) << 16);
2764 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2766 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2768 if ((y * oldval >> 7) & 0x1)
2770 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2773 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2777 reg = result[candidate][6];
2779 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2781 val32 |= (reg & 0x3ff);
2782 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2784 reg = result[candidate][7] & 0x3f;
2786 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2788 val32 |= ((reg << 10) & 0xfc00);
2789 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2791 reg = (result[candidate][7] >> 6) & 0xf;
2793 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2794 val32 &= ~0x0000f000;
2795 val32 |= (reg << 12);
2796 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2799 #define MAX_TOLERANCE 5
2801 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2802 int result[][8], int c1, int c2)
2804 u32 i, j, diff, simubitmap, bound = 0;
2805 int candidate[2] = {-1, -1}; /* for path A and path B */
2808 if (priv->tx_paths > 1)
2815 for (i = 0; i < bound; i++) {
2816 diff = (result[c1][i] > result[c2][i]) ?
2817 (result[c1][i] - result[c2][i]) :
2818 (result[c2][i] - result[c1][i]);
2819 if (diff > MAX_TOLERANCE) {
2820 if ((i == 2 || i == 6) && !simubitmap) {
2821 if (result[c1][i] + result[c1][i + 1] == 0)
2822 candidate[(i / 4)] = c2;
2823 else if (result[c2][i] + result[c2][i + 1] == 0)
2824 candidate[(i / 4)] = c1;
2826 simubitmap = simubitmap | (1 << i);
2828 simubitmap = simubitmap | (1 << i);
2833 if (simubitmap == 0) {
2834 for (i = 0; i < (bound / 4); i++) {
2835 if (candidate[i] >= 0) {
2836 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2837 result[3][j] = result[candidate[i]][j];
2842 } else if (!(simubitmap & 0x0f)) {
2844 for (i = 0; i < 4; i++)
2845 result[3][i] = result[c1][i];
2846 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2848 for (i = 4; i < 8; i++)
2849 result[3][i] = result[c1][i];
2855 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2856 int result[][8], int c1, int c2)
2858 u32 i, j, diff, simubitmap, bound = 0;
2859 int candidate[2] = {-1, -1}; /* for path A and path B */
2863 if (priv->tx_paths > 1)
2870 for (i = 0; i < bound; i++) {
2872 if ((result[c1][i] & 0x00000200))
2873 tmp1 = result[c1][i] | 0xfffffc00;
2875 tmp1 = result[c1][i];
2877 if ((result[c2][i]& 0x00000200))
2878 tmp2 = result[c2][i] | 0xfffffc00;
2880 tmp2 = result[c2][i];
2882 tmp1 = result[c1][i];
2883 tmp2 = result[c2][i];
2886 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2888 if (diff > MAX_TOLERANCE) {
2889 if ((i == 2 || i == 6) && !simubitmap) {
2890 if (result[c1][i] + result[c1][i + 1] == 0)
2891 candidate[(i / 4)] = c2;
2892 else if (result[c2][i] + result[c2][i + 1] == 0)
2893 candidate[(i / 4)] = c1;
2895 simubitmap = simubitmap | (1 << i);
2897 simubitmap = simubitmap | (1 << i);
2902 if (simubitmap == 0) {
2903 for (i = 0; i < (bound / 4); i++) {
2904 if (candidate[i] >= 0) {
2905 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2906 result[3][j] = result[candidate[i]][j];
2912 if (!(simubitmap & 0x03)) {
2914 for (i = 0; i < 2; i++)
2915 result[3][i] = result[c1][i];
2918 if (!(simubitmap & 0x0c)) {
2920 for (i = 2; i < 4; i++)
2921 result[3][i] = result[c1][i];
2924 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2926 for (i = 4; i < 6; i++)
2927 result[3][i] = result[c1][i];
2930 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2932 for (i = 6; i < 8; i++)
2933 result[3][i] = result[c1][i];
2941 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2945 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2946 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2948 backup[i] = rtl8xxxu_read32(priv, reg[i]);
2951 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2952 const u32 *reg, u32 *backup)
2956 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2957 rtl8xxxu_write8(priv, reg[i], backup[i]);
2959 rtl8xxxu_write32(priv, reg[i], backup[i]);
2962 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2963 u32 *backup, int count)
2967 for (i = 0; i < count; i++)
2968 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2971 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2972 u32 *backup, int count)
2976 for (i = 0; i < count; i++)
2977 rtl8xxxu_write32(priv, regs[i], backup[i]);
2981 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2987 if (priv->tx_paths == 1) {
2988 path_on = priv->fops->adda_1t_path_on;
2989 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
2991 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
2992 priv->fops->adda_2t_path_on_b;
2994 rtl8xxxu_write32(priv, regs[0], path_on);
2997 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
2998 rtl8xxxu_write32(priv, regs[i], path_on);
3001 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3002 const u32 *regs, u32 *backup)
3006 rtl8xxxu_write8(priv, regs[i], 0x3f);
3008 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3009 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3011 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3014 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3016 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3019 /* path-A IQK setting */
3020 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3021 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3022 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3024 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3025 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3027 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3029 /* path-B IQK setting */
3030 if (priv->rf_paths > 1) {
3031 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3032 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3033 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3034 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3037 /* LO calibration setting */
3038 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3040 /* One shot, path A LOK & IQK */
3041 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3042 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3047 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3048 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3049 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3050 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3052 if (!(reg_eac & BIT(28)) &&
3053 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3054 ((reg_e9c & 0x03ff0000) != 0x00420000))
3056 else /* If TX not OK, ignore RX */
3059 /* If TX is OK, check whether RX is OK */
3060 if (!(reg_eac & BIT(27)) &&
3061 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3062 ((reg_eac & 0x03ff0000) != 0x00360000))
3065 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3071 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3073 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3076 /* One shot, path B LOK & IQK */
3077 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3078 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3083 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3084 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3085 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3086 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3087 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3089 if (!(reg_eac & BIT(31)) &&
3090 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3091 ((reg_ebc & 0x03ff0000) != 0x00420000))
3096 if (!(reg_eac & BIT(30)) &&
3097 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3098 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3101 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3107 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3108 int result[][8], int t)
3110 struct device *dev = &priv->udev->dev;
3112 int path_a_ok, path_b_ok;
3114 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3115 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3116 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3117 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3118 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3119 REG_TX_TO_TX, REG_RX_CCK,
3120 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3121 REG_RX_TO_RX, REG_STANDBY,
3122 REG_SLEEP, REG_PMPD_ANAEN
3124 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3125 REG_TXPAUSE, REG_BEACON_CTRL,
3126 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3128 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3129 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3130 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3131 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3132 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3136 * Note: IQ calibration must be performed after loading
3137 * PHY_REG.txt , and radio_a, radio_b.txt
3141 /* Save ADDA parameters, turn Path A ADDA on */
3142 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3143 RTL8XXXU_ADDA_REGS);
3144 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3145 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3146 priv->bb_backup, RTL8XXXU_BB_REGS);
3149 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3152 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3153 if (val32 & FPGA0_HSSI_PARM1_PI)
3154 priv->pi_enabled = 1;
3157 if (!priv->pi_enabled) {
3158 /* Switch BB to PI mode to do IQ Calibration. */
3159 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3160 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3163 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3164 val32 &= ~FPGA_RF_MODE_CCK;
3165 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3167 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3168 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3169 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3171 if (!priv->no_pape) {
3172 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3173 val32 |= (FPGA0_RF_PAPE |
3174 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3175 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3178 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3180 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3181 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3183 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3185 if (priv->tx_paths > 1) {
3186 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3187 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3191 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3194 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3196 if (priv->tx_paths > 1)
3197 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3199 /* IQ calibration setting */
3200 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3201 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3202 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3204 for (i = 0; i < retry; i++) {
3205 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3206 if (path_a_ok == 0x03) {
3207 val32 = rtl8xxxu_read32(priv,
3208 REG_TX_POWER_BEFORE_IQK_A);
3209 result[t][0] = (val32 >> 16) & 0x3ff;
3210 val32 = rtl8xxxu_read32(priv,
3211 REG_TX_POWER_AFTER_IQK_A);
3212 result[t][1] = (val32 >> 16) & 0x3ff;
3213 val32 = rtl8xxxu_read32(priv,
3214 REG_RX_POWER_BEFORE_IQK_A_2);
3215 result[t][2] = (val32 >> 16) & 0x3ff;
3216 val32 = rtl8xxxu_read32(priv,
3217 REG_RX_POWER_AFTER_IQK_A_2);
3218 result[t][3] = (val32 >> 16) & 0x3ff;
3220 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3222 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3225 val32 = rtl8xxxu_read32(priv,
3226 REG_TX_POWER_BEFORE_IQK_A);
3227 result[t][0] = (val32 >> 16) & 0x3ff;
3228 val32 = rtl8xxxu_read32(priv,
3229 REG_TX_POWER_AFTER_IQK_A);
3230 result[t][1] = (val32 >> 16) & 0x3ff;
3235 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3237 if (priv->tx_paths > 1) {
3239 * Path A into standby
3241 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3242 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3243 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3245 /* Turn Path B ADDA on */
3246 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3248 for (i = 0; i < retry; i++) {
3249 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3250 if (path_b_ok == 0x03) {
3251 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3252 result[t][4] = (val32 >> 16) & 0x3ff;
3253 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3254 result[t][5] = (val32 >> 16) & 0x3ff;
3255 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3256 result[t][6] = (val32 >> 16) & 0x3ff;
3257 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3258 result[t][7] = (val32 >> 16) & 0x3ff;
3260 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3262 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3263 result[t][4] = (val32 >> 16) & 0x3ff;
3264 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3265 result[t][5] = (val32 >> 16) & 0x3ff;
3270 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3273 /* Back to BB mode, load original value */
3274 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3277 if (!priv->pi_enabled) {
3279 * Switch back BB to SI mode after finishing
3283 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3284 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3287 /* Reload ADDA power saving parameters */
3288 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3289 RTL8XXXU_ADDA_REGS);
3291 /* Reload MAC parameters */
3292 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3294 /* Reload BB parameters */
3295 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3296 priv->bb_backup, RTL8XXXU_BB_REGS);
3298 /* Restore RX initial gain */
3299 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3301 if (priv->tx_paths > 1) {
3302 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3306 /* Load 0xe30 IQC default value */
3307 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3308 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3312 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3316 memset(&h2c, 0, sizeof(struct h2c_cmd));
3317 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3318 h2c.bt_wlan_calibration.data = start;
3320 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3323 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3325 struct device *dev = &priv->udev->dev;
3326 int result[4][8]; /* last is final result */
3328 bool path_a_ok, path_b_ok;
3329 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3330 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3334 memset(result, 0, sizeof(result));
3340 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3342 for (i = 0; i < 3; i++) {
3343 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3346 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3354 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3360 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3364 for (i = 0; i < 8; i++)
3365 reg_tmp += result[3][i];
3375 for (i = 0; i < 4; i++) {
3376 reg_e94 = result[i][0];
3377 reg_e9c = result[i][1];
3378 reg_ea4 = result[i][2];
3379 reg_eac = result[i][3];
3380 reg_eb4 = result[i][4];
3381 reg_ebc = result[i][5];
3382 reg_ec4 = result[i][6];
3383 reg_ecc = result[i][7];
3386 if (candidate >= 0) {
3387 reg_e94 = result[candidate][0];
3388 priv->rege94 = reg_e94;
3389 reg_e9c = result[candidate][1];
3390 priv->rege9c = reg_e9c;
3391 reg_ea4 = result[candidate][2];
3392 reg_eac = result[candidate][3];
3393 reg_eb4 = result[candidate][4];
3394 priv->regeb4 = reg_eb4;
3395 reg_ebc = result[candidate][5];
3396 priv->regebc = reg_ebc;
3397 reg_ec4 = result[candidate][6];
3398 reg_ecc = result[candidate][7];
3399 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3401 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3402 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3403 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3407 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3408 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3411 if (reg_e94 && candidate >= 0)
3412 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3413 candidate, (reg_ea4 == 0));
3415 if (priv->tx_paths > 1 && reg_eb4)
3416 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3417 candidate, (reg_ec4 == 0));
3419 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3420 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3423 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3426 u32 rf_amode, rf_bmode = 0, lstf;
3428 /* Check continuous TX and Packet TX */
3429 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3431 if (lstf & OFDM_LSTF_MASK) {
3432 /* Disable all continuous TX */
3433 val32 = lstf & ~OFDM_LSTF_MASK;
3434 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3436 /* Read original RF mode Path A */
3437 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3439 /* Set RF mode to standby Path A */
3440 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3441 (rf_amode & 0x8ffff) | 0x10000);
3444 if (priv->tx_paths > 1) {
3445 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3448 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3449 (rf_bmode & 0x8ffff) | 0x10000);
3452 /* Deal with Packet TX case */
3453 /* block all queues */
3454 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3457 /* Start LC calibration */
3458 if (priv->fops->has_s0s1)
3459 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3460 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3462 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3466 if (priv->fops->has_s0s1)
3467 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3469 /* Restore original parameters */
3470 if (lstf & OFDM_LSTF_MASK) {
3472 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3473 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3476 if (priv->tx_paths > 1)
3477 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3479 } else /* Deal with Packet TX case */
3480 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3483 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3490 for (i = 0; i < ETH_ALEN; i++)
3491 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3496 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3501 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3505 for (i = 0; i < ETH_ALEN; i++)
3506 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3512 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3514 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3518 ampdu_factor = 1 << (ampdu_factor + 2);
3519 if (ampdu_factor > max_agg)
3520 ampdu_factor = max_agg;
3522 for (i = 0; i < 4; i++) {
3523 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3524 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3526 if ((vals[i] & 0x0f) > ampdu_factor)
3527 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3529 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3533 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3537 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3540 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3543 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3548 /* Start of rtl8723AU_card_enable_flow */
3549 /* Act to Cardemu sequence*/
3551 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3553 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3554 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3555 val8 &= ~LEDCFG2_DPDT_SELECT;
3556 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3558 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3559 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3561 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3563 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3564 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3565 if ((val8 & BIT(1)) == 0)
3571 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3577 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3578 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3579 val8 |= SYS_ISO_ANALOG_IPS;
3580 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3582 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3583 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3584 val8 &= ~LDOA15_ENABLE;
3585 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3591 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3597 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3600 * Poll - wait for RX packet to complete
3602 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3603 val32 = rtl8xxxu_read32(priv, 0x5f8);
3610 dev_warn(&priv->udev->dev,
3611 "%s: RX poll timed out (0x05f8)\n", __func__);
3616 /* Disable CCK and OFDM, clock gated */
3617 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3618 val8 &= ~SYS_FUNC_BBRSTB;
3619 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3623 /* Reset baseband */
3624 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3625 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3626 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3629 val8 = rtl8xxxu_read8(priv, REG_CR);
3630 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3631 rtl8xxxu_write8(priv, REG_CR, val8);
3634 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3635 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3636 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3638 /* Respond TX OK to scheduler */
3639 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3640 val8 |= DUAL_TSF_TX_OK;
3641 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3647 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3651 /* Clear suspend enable and power down enable*/
3652 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3653 val8 &= ~(BIT(3) | BIT(7));
3654 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3656 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3657 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3659 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3661 /* 0x04[12:11] = 11 enable WL suspend*/
3662 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3663 val8 &= ~(BIT(3) | BIT(4));
3664 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3667 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3671 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3672 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3674 /* 0x04[12:11] = 01 enable WL suspend */
3675 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3678 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3680 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3682 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3684 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3685 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3687 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3692 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3694 struct device *dev = &priv->udev->dev;
3698 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3700 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3701 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3702 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3708 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3709 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3715 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3716 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3720 dev_warn(dev, "Failed to flush FIFO\n");
3725 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3727 /* Fix USB interface interference issue */
3728 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3729 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3730 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3732 * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3733 * 8 and 5, for which I have found no documentation.
3735 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3738 * Solve too many protocol error on USB bus.
3739 * Can't do this for 8188/8192 UMC A cut parts
3741 if (!(!priv->chip_cut && priv->vendor_umc)) {
3742 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3743 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3744 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3746 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3747 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3748 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3750 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3751 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3752 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3754 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3755 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3756 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3760 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3764 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3765 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3766 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3769 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3776 * Workaround for 8188RU LNA power leakage problem.
3778 if (priv->rtl_chip == RTL8188R) {
3779 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3781 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3784 rtl8xxxu_flush_fifo(priv);
3786 rtl8xxxu_active_to_lps(priv);
3789 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3791 /* Reset Firmware if running in RAM */
3792 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3793 rtl8xxxu_firmware_self_reset(priv);
3796 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3797 val16 &= ~SYS_FUNC_CPU_ENABLE;
3798 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3800 /* Reset MCU ready status */
3801 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3803 rtl8xxxu_active_to_emu(priv);
3804 rtl8xxxu_emu_to_disabled(priv);
3806 /* Reset MCU IO Wrapper */
3807 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3809 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3811 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3813 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3815 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
3816 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3820 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3821 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3825 memset(&h2c, 0, sizeof(struct h2c_cmd));
3826 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3827 h2c.b_type_dma.data1 = arg1;
3828 h2c.b_type_dma.data2 = arg2;
3829 h2c.b_type_dma.data3 = arg3;
3830 h2c.b_type_dma.data4 = arg4;
3831 h2c.b_type_dma.data5 = arg5;
3832 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3836 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3840 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3841 val32 &= ~(BIT(22) | BIT(23));
3842 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3845 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3847 struct rtl8xxxu_fileops *fops = priv->fops;
3848 u32 hq, lq, nq, eq, pubq;
3857 if (priv->ep_tx_high_queue)
3858 hq = fops->page_num_hi;
3859 if (priv->ep_tx_low_queue)
3860 lq = fops->page_num_lo;
3861 if (priv->ep_tx_normal_queue)
3862 nq = fops->page_num_norm;
3864 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3865 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3867 pubq = fops->total_page_num - hq - lq - nq - 1;
3870 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3871 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3872 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3874 rtl8xxxu_write32(priv, REG_RQPN, val32);
3877 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3879 struct rtl8xxxu_priv *priv = hw->priv;
3880 struct device *dev = &priv->udev->dev;
3881 struct rtl8xxxu_fileops *fops = priv->fops;
3888 /* Check if MAC is already powered on */
3889 val8 = rtl8xxxu_read8(priv, REG_CR);
3892 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3893 * initialized. First MAC returns 0xea, second MAC returns 0x00
3900 if (fops->needs_full_init)
3903 ret = fops->power_on(priv);
3905 dev_warn(dev, "%s: Failed power on\n", __func__);
3910 rtl8xxxu_init_queue_reserved_page(priv);
3912 ret = rtl8xxxu_init_queue_priority(priv);
3913 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3918 * Set RX page boundary
3920 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
3922 ret = rtl8xxxu_download_firmware(priv);
3923 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
3926 ret = rtl8xxxu_start_firmware(priv);
3927 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
3931 if (fops->phy_init_antenna_selection)
3932 fops->phy_init_antenna_selection(priv);
3934 ret = rtl8xxxu_init_mac(priv);
3936 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3940 ret = rtl8xxxu_init_phy_bb(priv);
3941 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3945 ret = fops->init_phy_rf(priv);
3949 /* RFSW Control - clear bit 14 ?? */
3950 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
3951 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
3953 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
3955 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3956 if (!priv->no_pape) {
3957 val32 |= (FPGA0_RF_PAPE |
3958 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3960 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3962 /* 0x860[6:5]= 00 - why? - this sets antenna B */
3963 if (priv->rtl_chip != RTL8192E)
3964 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3968 * Set TX buffer boundary
3970 val8 = fops->total_page_num + 1;
3972 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3973 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3974 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3975 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3976 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3980 * The vendor drivers set PBP for all devices, except 8192e.
3981 * There is no explanation for this in any of the sources.
3983 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3984 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
3985 if (priv->rtl_chip != RTL8192E)
3986 rtl8xxxu_write8(priv, REG_PBP, val8);
3988 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3990 ret = fops->llt_init(priv);
3992 dev_warn(dev, "%s: LLT table init failed\n", __func__);
3997 * Chip specific quirks
3999 fops->usb_quirks(priv);
4002 * Enable TX report and TX report timer for 8723bu/8188eu/...
4004 if (fops->has_tx_report) {
4005 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4006 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4007 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4008 /* Set MAX RPT MACID */
4009 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4010 /* TX report Timer. Unit: 32us */
4011 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4014 val8 = rtl8xxxu_read8(priv, 0xa3);
4016 rtl8xxxu_write8(priv, 0xa3, val8);
4021 * Unit in 8 bytes, not obvious what it is used for
4023 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4025 if (priv->rtl_chip == RTL8192E) {
4026 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4027 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4030 * Enable all interrupts - not obvious USB needs to do this
4032 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4033 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4036 rtl8xxxu_set_mac(priv);
4037 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4040 * Configure initial WMAC settings
4042 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4043 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4044 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4045 rtl8xxxu_write32(priv, REG_RCR, val32);
4048 * Accept all multicast
4050 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4051 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4054 * Init adaptive controls
4056 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4057 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4058 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4059 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4061 /* CCK = 0x0a, OFDM = 0x10 */
4062 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4063 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4064 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4069 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4072 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4075 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4078 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4079 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4080 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4081 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4083 /* Set data auto rate fallback retry count */
4084 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4085 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4086 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4087 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4089 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4090 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4091 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4093 /* Set ACK timeout */
4094 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4097 * Initialize beacon parameters
4099 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4100 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4101 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4102 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4103 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4104 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4107 * Initialize burst parameters
4109 if (priv->rtl_chip == RTL8723B) {
4111 * For USB high speed set 512B packets
4113 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4114 val8 &= ~(BIT(4) | BIT(5));
4116 val8 |= BIT(1) | BIT(2) | BIT(3);
4117 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4120 * For USB high speed set 512B packets
4122 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4124 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4126 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4127 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4128 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4129 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4130 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4131 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4132 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4134 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4135 val8 |= BIT(5) | BIT(6);
4136 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4139 if (fops->init_aggregation)
4140 fops->init_aggregation(priv);
4143 * Enable CCK and OFDM block
4145 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4146 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4147 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4150 * Invalidate all CAM entries - bit 30 is undocumented
4152 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4155 * Start out with default power levels for channel 6, 20MHz
4157 fops->set_tx_power(priv, 1, false);
4159 /* Let the 8051 take control of antenna setting */
4160 if (priv->rtl_chip != RTL8192E) {
4161 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4162 val8 |= LEDCFG2_DPDT_SELECT;
4163 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4166 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4168 /* Disable BAR - not sure if this has any effect on USB */
4169 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4171 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4173 if (fops->init_statistics)
4174 fops->init_statistics(priv);
4176 if (priv->rtl_chip == RTL8192E) {
4178 * 0x4c6[3] 1: RTS BW = Data BW
4179 * 0: RTS BW depends on CCA / secondary CCA result.
4181 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4183 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4185 * Reset USB mode switch setting
4187 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4190 rtl8723a_phy_lc_calibrate(priv);
4192 fops->phy_iq_calibrate(priv);
4195 * This should enable thermal meter
4197 if (fops->gen2_thermal_meter)
4198 rtl8xxxu_write_rfreg(priv,
4199 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4201 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4203 /* Set NAV_UPPER to 30000us */
4204 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4205 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4207 if (priv->rtl_chip == RTL8723A) {
4209 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4210 * but we need to find root cause.
4211 * This is 8723au only.
4213 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4214 if ((val32 & 0xff000000) != 0x83000000) {
4215 val32 |= FPGA_RF_MODE_CCK;
4216 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4218 } else if (priv->rtl_chip == RTL8192E) {
4219 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4222 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4223 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4224 /* ack for xmit mgmt frames. */
4225 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4227 if (priv->rtl_chip == RTL8192E) {
4229 * Fix LDPC rx hang issue.
4231 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4232 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4233 val32 &= 0xfff00fff;
4234 val32 |= 0x0007e000;
4235 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4241 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4242 struct ieee80211_key_conf *key, const u8 *mac)
4244 u32 cmd, val32, addr, ctrl;
4245 int j, i, tmp_debug;
4247 tmp_debug = rtl8xxxu_debug;
4248 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4249 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4252 * This is a bit of a hack - the lower bits of the cipher
4253 * suite selector happens to match the cipher index in the CAM
4255 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4256 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4258 for (j = 5; j >= 0; j--) {
4261 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4264 val32 = mac[2] | (mac[3] << 8) |
4265 (mac[4] << 16) | (mac[5] << 24);
4269 val32 = key->key[i] | (key->key[i + 1] << 8) |
4270 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4274 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4275 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4276 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4280 rtl8xxxu_debug = tmp_debug;
4283 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4284 struct ieee80211_vif *vif, const u8 *mac)
4286 struct rtl8xxxu_priv *priv = hw->priv;
4289 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4290 val8 |= BEACON_DISABLE_TSF_UPDATE;
4291 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4294 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4295 struct ieee80211_vif *vif)
4297 struct rtl8xxxu_priv *priv = hw->priv;
4300 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4301 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4302 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4305 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi)
4309 memset(&h2c, 0, sizeof(struct h2c_cmd));
4311 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4312 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4313 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4315 h2c.ramask.arg = 0x80;
4317 h2c.ramask.arg |= 0x20;
4319 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4320 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4321 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4324 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4325 u32 ramask, int sgi)
4330 memset(&h2c, 0, sizeof(struct h2c_cmd));
4332 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4333 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4334 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4335 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4336 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4338 h2c.ramask.arg = 0x80;
4339 h2c.b_macid_cfg.data1 = 0;
4341 h2c.b_macid_cfg.data1 |= BIT(7);
4343 h2c.b_macid_cfg.data2 = bw;
4345 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4346 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
4347 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4350 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4351 u8 macid, bool connect)
4355 memset(&h2c, 0, sizeof(struct h2c_cmd));
4357 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4360 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4362 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4364 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4367 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4368 u8 macid, bool connect)
4370 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT
4372 * Barry Day reports this causes issues with 8192eu and 8723bu
4373 * devices reconnecting. The reason for this is unclear, but
4374 * until it is better understood, leave the code in place but
4375 * disabled, so it is not lost.
4379 memset(&h2c, 0, sizeof(struct h2c_cmd));
4381 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4383 h2c.media_status_rpt.parm |= BIT(0);
4385 h2c.media_status_rpt.parm &= ~BIT(0);
4387 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4391 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4393 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4395 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4396 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4397 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4399 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4400 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4402 if (!rtl8xxxu_dma_aggregation) {
4403 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4407 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4408 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4411 * The number of packets we can take looks to be buffer size / 512
4412 * which matches the 512 byte rounding we have to do when de-muxing
4415 * Sample numbers from the vendor driver:
4416 * USB High-Speed mode values:
4417 * RxAggBlockCount = 8 : 512 byte unit
4418 * RxAggBlockTimeout = 6
4419 * RxAggPageCount = 48 : 128 byte unit
4420 * RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4423 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4424 if (rtl8xxxu_dma_agg_pages >= 0) {
4425 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4426 timeout = page_thresh;
4427 else if (rtl8xxxu_dma_agg_pages <= 6)
4428 dev_err(&priv->udev->dev,
4429 "%s: dma_agg_pages=%i too small, minium is 6\n",
4430 __func__, rtl8xxxu_dma_agg_pages);
4432 dev_err(&priv->udev->dev,
4433 "%s: dma_agg_pages=%i larger than limit %i\n",
4434 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4436 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4438 * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4439 * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4440 * don't set it, so better set both.
4444 if (rtl8xxxu_dma_agg_timeout >= 0) {
4445 if (rtl8xxxu_dma_agg_timeout <= 127)
4446 timeout = rtl8xxxu_dma_agg_timeout;
4448 dev_err(&priv->udev->dev,
4449 "%s: Invalid dma_agg_timeout: %i\n",
4450 __func__, rtl8xxxu_dma_agg_timeout);
4453 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4454 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4455 priv->rx_buf_aggregation = 1;
4458 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4463 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4465 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4466 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4468 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4470 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4473 rate_cfg = (rate_cfg >> 1);
4476 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4480 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4481 struct ieee80211_bss_conf *bss_conf, u32 changed)
4483 struct rtl8xxxu_priv *priv = hw->priv;
4484 struct device *dev = &priv->udev->dev;
4485 struct ieee80211_sta *sta;
4489 if (changed & BSS_CHANGED_ASSOC) {
4490 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4492 rtl8xxxu_set_linktype(priv, vif->type);
4494 if (bss_conf->assoc) {
4499 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4501 dev_info(dev, "%s: ASSOC no sta found\n",
4507 if (sta->ht_cap.ht_supported)
4508 dev_info(dev, "%s: HT supported\n", __func__);
4509 if (sta->vht_cap.vht_supported)
4510 dev_info(dev, "%s: VHT supported\n", __func__);
4512 /* TODO: Set bits 28-31 for rate adaptive id */
4513 ramask = (sta->supp_rates[0] & 0xfff) |
4514 sta->ht_cap.mcs.rx_mask[0] << 12 |
4515 sta->ht_cap.mcs.rx_mask[1] << 20;
4516 if (sta->ht_cap.cap &
4517 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4521 priv->fops->update_rate_mask(priv, ramask, sgi);
4523 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4525 rtl8xxxu_stop_tx_beacon(priv);
4527 /* joinbss sequence */
4528 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4529 0xc000 | bss_conf->aid);
4531 priv->fops->report_connect(priv, 0, true);
4533 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4534 val8 |= BEACON_DISABLE_TSF_UPDATE;
4535 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4537 priv->fops->report_connect(priv, 0, false);
4541 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4542 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4543 bss_conf->use_short_preamble);
4544 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4545 if (bss_conf->use_short_preamble)
4546 val32 |= RSR_ACK_SHORT_PREAMBLE;
4548 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4549 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4552 if (changed & BSS_CHANGED_ERP_SLOT) {
4553 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4554 bss_conf->use_short_slot);
4556 if (bss_conf->use_short_slot)
4560 rtl8xxxu_write8(priv, REG_SLOT, val8);
4563 if (changed & BSS_CHANGED_BSSID) {
4564 dev_dbg(dev, "Changed BSSID!\n");
4565 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4568 if (changed & BSS_CHANGED_BASIC_RATES) {
4569 dev_dbg(dev, "Changed BASIC_RATES!\n");
4570 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4576 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4581 case IEEE80211_AC_VO:
4582 rtlqueue = TXDESC_QUEUE_VO;
4584 case IEEE80211_AC_VI:
4585 rtlqueue = TXDESC_QUEUE_VI;
4587 case IEEE80211_AC_BE:
4588 rtlqueue = TXDESC_QUEUE_BE;
4590 case IEEE80211_AC_BK:
4591 rtlqueue = TXDESC_QUEUE_BK;
4594 rtlqueue = TXDESC_QUEUE_BE;
4600 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4602 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4605 if (ieee80211_is_mgmt(hdr->frame_control))
4606 queue = TXDESC_QUEUE_MGNT;
4608 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4614 * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
4615 * format. The descriptor checksum is still only calculated over the
4616 * initial 32 bytes of the descriptor!
4618 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
4620 __le16 *ptr = (__le16 *)tx_desc;
4625 * Clear csum field before calculation, as the csum field is
4626 * in the middle of the struct.
4628 tx_desc->csum = cpu_to_le16(0);
4630 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
4631 csum = csum ^ le16_to_cpu(ptr[i]);
4633 tx_desc->csum |= cpu_to_le16(csum);
4636 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4638 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4639 unsigned long flags;
4641 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4642 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4643 list_del(&tx_urb->list);
4644 priv->tx_urb_free_count--;
4645 usb_free_urb(&tx_urb->urb);
4647 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4650 static struct rtl8xxxu_tx_urb *
4651 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4653 struct rtl8xxxu_tx_urb *tx_urb;
4654 unsigned long flags;
4656 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4657 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4658 struct rtl8xxxu_tx_urb, list);
4660 list_del(&tx_urb->list);
4661 priv->tx_urb_free_count--;
4662 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4663 !priv->tx_stopped) {
4664 priv->tx_stopped = true;
4665 ieee80211_stop_queues(priv->hw);
4669 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4674 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4675 struct rtl8xxxu_tx_urb *tx_urb)
4677 unsigned long flags;
4679 INIT_LIST_HEAD(&tx_urb->list);
4681 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4683 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4684 priv->tx_urb_free_count++;
4685 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4687 priv->tx_stopped = false;
4688 ieee80211_wake_queues(priv->hw);
4691 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4694 static void rtl8xxxu_tx_complete(struct urb *urb)
4696 struct sk_buff *skb = (struct sk_buff *)urb->context;
4697 struct ieee80211_tx_info *tx_info;
4698 struct ieee80211_hw *hw;
4699 struct rtl8xxxu_priv *priv;
4700 struct rtl8xxxu_tx_urb *tx_urb =
4701 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4703 tx_info = IEEE80211_SKB_CB(skb);
4704 hw = tx_info->rate_driver_data[0];
4707 skb_pull(skb, priv->fops->tx_desc_size);
4709 ieee80211_tx_info_clear_status(tx_info);
4710 tx_info->status.rates[0].idx = -1;
4711 tx_info->status.rates[0].count = 0;
4714 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4716 ieee80211_tx_status_irqsafe(hw, skb);
4718 rtl8xxxu_free_tx_urb(priv, tx_urb);
4721 static void rtl8xxxu_dump_action(struct device *dev,
4722 struct ieee80211_hdr *hdr)
4724 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4727 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4730 switch (mgmt->u.action.u.addba_resp.action_code) {
4731 case WLAN_ACTION_ADDBA_RESP:
4732 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4733 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4734 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4735 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4738 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4739 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4741 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4743 case WLAN_ACTION_ADDBA_REQ:
4744 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4745 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4746 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4747 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4749 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4750 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4754 dev_info(dev, "action frame %02x\n",
4755 mgmt->u.action.u.addba_resp.action_code);
4761 * Fill in v1 (gen1) specific TX descriptor bits.
4762 * This format is used on 8188cu/8192cu/8723au
4765 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hdr *hdr,
4766 struct rtl8xxxu_txdesc32 *tx_desc, u32 rate,
4767 u16 rate_flag, bool sgi, bool short_preamble,
4772 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4774 tx_desc->txdw5 = cpu_to_le32(rate);
4776 if (ieee80211_is_data(hdr->frame_control))
4777 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4779 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4782 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4784 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4786 if (ieee80211_is_mgmt(hdr->frame_control)) {
4787 tx_desc->txdw5 = cpu_to_le32(rate);
4788 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4789 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4790 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4793 if (ieee80211_is_data_qos(hdr->frame_control))
4794 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4797 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4800 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4802 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4804 * Use RTS rate 24M - does the mac80211 tell
4807 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M <<
4808 TXDESC32_RTS_RATE_SHIFT);
4809 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4810 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4815 * Fill in v2 (gen2) specific TX descriptor bits.
4816 * This format is used on 8192eu/8723bu
4819 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hdr *hdr,
4820 struct rtl8xxxu_txdesc32 *tx_desc32, u32 rate,
4821 u16 rate_flag, bool sgi, bool short_preamble,
4824 struct rtl8xxxu_txdesc40 *tx_desc40;
4827 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4829 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4831 tx_desc40->txdw4 = cpu_to_le32(rate);
4832 if (ieee80211_is_data(hdr->frame_control)) {
4833 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4834 TXDESC40_DATA_RATE_FB_SHIFT);
4837 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4840 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4842 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4844 if (ieee80211_is_mgmt(hdr->frame_control)) {
4845 tx_desc40->txdw4 = cpu_to_le32(rate);
4846 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4848 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4849 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4853 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4855 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4857 * Use RTS rate 24M - does the mac80211 tell
4860 tx_desc40->txdw4 |= cpu_to_le32(DESC_RATE_24M <<
4861 TXDESC40_RTS_RATE_SHIFT);
4862 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
4863 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4867 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4868 struct ieee80211_tx_control *control,
4869 struct sk_buff *skb)
4871 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4872 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4873 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4874 struct rtl8xxxu_priv *priv = hw->priv;
4875 struct rtl8xxxu_txdesc32 *tx_desc;
4876 struct rtl8xxxu_tx_urb *tx_urb;
4877 struct ieee80211_sta *sta = NULL;
4878 struct ieee80211_vif *vif = tx_info->control.vif;
4879 struct device *dev = &priv->udev->dev;
4881 u16 pktlen = skb->len;
4883 u16 rate_flag = tx_info->control.rates[0].flags;
4884 int tx_desc_size = priv->fops->tx_desc_size;
4886 bool usedesc40, ampdu_enable, sgi = false, short_preamble = false;
4888 if (skb_headroom(skb) < tx_desc_size) {
4890 "%s: Not enough headroom (%i) for tx descriptor\n",
4891 __func__, skb_headroom(skb));
4895 if (unlikely(skb->len > (65535 - tx_desc_size))) {
4896 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4897 __func__, skb->len);
4901 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4903 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4907 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4908 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4909 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4911 if (ieee80211_is_action(hdr->frame_control))
4912 rtl8xxxu_dump_action(dev, hdr);
4914 usedesc40 = (tx_desc_size == 40);
4915 tx_info->rate_driver_data[0] = hw;
4917 if (control && control->sta)
4920 tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size);
4922 memset(tx_desc, 0, tx_desc_size);
4923 tx_desc->pkt_size = cpu_to_le16(pktlen);
4924 tx_desc->pkt_offset = tx_desc_size;
4927 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4928 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4929 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4930 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4932 queue = rtl8xxxu_queue_select(hw, skb);
4933 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4935 if (tx_info->control.hw_key) {
4936 switch (tx_info->control.hw_key->cipher) {
4937 case WLAN_CIPHER_SUITE_WEP40:
4938 case WLAN_CIPHER_SUITE_WEP104:
4939 case WLAN_CIPHER_SUITE_TKIP:
4940 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4942 case WLAN_CIPHER_SUITE_CCMP:
4943 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4950 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4951 ampdu_enable = false;
4952 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4953 if (sta->ht_cap.ht_supported) {
4956 ampdu = (u32)sta->ht_cap.ampdu_density;
4957 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4958 tx_desc->txdw2 |= cpu_to_le32(val32);
4960 ampdu_enable = true;
4964 if (rate_flag & IEEE80211_TX_RC_MCS &&
4965 !ieee80211_is_mgmt(hdr->frame_control))
4966 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4968 rate = tx_rate->hw_value;
4970 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4971 (ieee80211_is_data_qos(hdr->frame_control) &&
4972 sta && sta->ht_cap.cap &
4973 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
4976 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4977 (sta && vif && vif->bss_conf.use_short_preamble))
4978 short_preamble = true;
4980 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4982 priv->fops->fill_txdesc(hdr, tx_desc, rate, rate_flag,
4983 sgi, short_preamble, ampdu_enable);
4985 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4987 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4988 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4990 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4991 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4993 usb_unanchor_urb(&tx_urb->urb);
4994 rtl8xxxu_free_tx_urb(priv, tx_urb);
5002 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5003 struct ieee80211_rx_status *rx_status,
5004 struct rtl8723au_phy_stats *phy_stats,
5007 if (phy_stats->sgi_en)
5008 rx_status->flag |= RX_FLAG_SHORT_GI;
5010 if (rxmcs < DESC_RATE_6M) {
5012 * Handle PHY stats for CCK rates
5014 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5016 switch (cck_agc_rpt & 0xc0) {
5018 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5021 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5024 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5027 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5032 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5036 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5038 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5039 unsigned long flags;
5041 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5043 list_for_each_entry_safe(rx_urb, tmp,
5044 &priv->rx_urb_pending_list, list) {
5045 list_del(&rx_urb->list);
5046 priv->rx_urb_pending_count--;
5047 usb_free_urb(&rx_urb->urb);
5050 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5053 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5054 struct rtl8xxxu_rx_urb *rx_urb)
5056 struct sk_buff *skb;
5057 unsigned long flags;
5060 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5062 if (!priv->shutdown) {
5063 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5064 priv->rx_urb_pending_count++;
5065 pending = priv->rx_urb_pending_count;
5067 skb = (struct sk_buff *)rx_urb->urb.context;
5069 usb_free_urb(&rx_urb->urb);
5072 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5074 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5075 schedule_work(&priv->rx_urb_wq);
5078 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5080 struct rtl8xxxu_priv *priv;
5081 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5082 struct list_head local;
5083 struct sk_buff *skb;
5084 unsigned long flags;
5087 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5088 INIT_LIST_HEAD(&local);
5090 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5092 list_splice_init(&priv->rx_urb_pending_list, &local);
5093 priv->rx_urb_pending_count = 0;
5095 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5097 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5098 list_del_init(&rx_urb->list);
5099 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5101 * If out of memory or temporary error, put it back on the
5102 * queue and try again. Otherwise the device is dead/gone
5103 * and we should drop it.
5110 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5113 pr_info("failed to requeue urb %i\n", ret);
5114 skb = (struct sk_buff *)rx_urb->urb.context;
5116 usb_free_urb(&rx_urb->urb);
5121 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5122 struct sk_buff *skb)
5124 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5125 struct device *dev = &priv->udev->dev;
5130 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5131 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5134 case C2H_8723B_BT_INFO:
5135 if (c2h->bt_info.response_source >
5136 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5137 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5139 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5141 if (c2h->bt_info.bt_has_reset)
5142 dev_dbg(dev, "BT has been reset\n");
5143 if (c2h->bt_info.tx_rx_mask)
5144 dev_dbg(dev, "BT TRx mask\n");
5147 case C2H_8723B_BT_MP_INFO:
5148 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5149 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5151 case C2H_8723B_RA_REPORT:
5153 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5154 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
5155 c2h->ra_report.macid, c2h->ra_report.noisy_state);
5158 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5160 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5161 16, 1, c2h->raw.payload, len, false);
5166 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5168 struct ieee80211_hw *hw = priv->hw;
5169 struct ieee80211_rx_status *rx_status;
5170 struct rtl8xxxu_rxdesc16 *rx_desc;
5171 struct rtl8723au_phy_stats *phy_stats;
5172 struct sk_buff *next_skb = NULL;
5173 __le32 *_rx_desc_le;
5175 int drvinfo_sz, desc_shift;
5176 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
5182 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5183 _rx_desc_le = (__le32 *)skb->data;
5184 _rx_desc = (u32 *)skb->data;
5187 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5188 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5191 * Only read pkt_cnt from the header if we're parsing the
5195 pkt_cnt = rx_desc->pkt_cnt;
5196 pkt_len = rx_desc->pktlen;
5198 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5199 desc_shift = rx_desc->shift;
5200 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5201 sizeof(struct rtl8xxxu_rxdesc16), 128);
5204 * Only clone the skb if there's enough data at the end to
5205 * at least cover the rx descriptor
5208 urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
5209 next_skb = skb_clone(skb, GFP_ATOMIC);
5211 rx_status = IEEE80211_SKB_RXCB(skb);
5212 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5214 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
5216 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5218 skb_pull(skb, drvinfo_sz + desc_shift);
5220 skb_trim(skb, pkt_len);
5222 if (rx_desc->phy_stats)
5223 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5226 rx_status->mactime = rx_desc->tsfl;
5227 rx_status->flag |= RX_FLAG_MACTIME_START;
5229 if (!rx_desc->swdec)
5230 rx_status->flag |= RX_FLAG_DECRYPTED;
5232 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5234 rx_status->flag |= RX_FLAG_40MHZ;
5236 if (rx_desc->rxht) {
5237 rx_status->flag |= RX_FLAG_HT;
5238 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5240 rx_status->rate_idx = rx_desc->rxmcs;
5243 rx_status->freq = hw->conf.chandef.chan->center_freq;
5244 rx_status->band = hw->conf.chandef.chan->band;
5246 ieee80211_rx_irqsafe(hw, skb);
5250 skb_pull(next_skb, pkt_offset);
5253 urb_len -= pkt_offset;
5254 } while (skb && urb_len > 0 && pkt_cnt > 0);
5256 return RX_TYPE_DATA_PKT;
5259 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5261 struct ieee80211_hw *hw = priv->hw;
5262 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5263 struct rtl8xxxu_rxdesc24 *rx_desc =
5264 (struct rtl8xxxu_rxdesc24 *)skb->data;
5265 struct rtl8723au_phy_stats *phy_stats;
5266 __le32 *_rx_desc_le = (__le32 *)skb->data;
5267 u32 *_rx_desc = (u32 *)skb->data;
5268 int drvinfo_sz, desc_shift;
5271 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
5272 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5274 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5276 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
5278 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5280 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5281 desc_shift = rx_desc->shift;
5282 skb_pull(skb, drvinfo_sz + desc_shift);
5284 if (rx_desc->rpt_sel) {
5285 struct device *dev = &priv->udev->dev;
5286 dev_dbg(dev, "%s: C2H packet\n", __func__);
5287 rtl8723bu_handle_c2h(priv, skb);
5292 if (rx_desc->phy_stats)
5293 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5296 rx_status->mactime = rx_desc->tsfl;
5297 rx_status->flag |= RX_FLAG_MACTIME_START;
5299 if (!rx_desc->swdec)
5300 rx_status->flag |= RX_FLAG_DECRYPTED;
5302 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5304 rx_status->flag |= RX_FLAG_40MHZ;
5306 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5307 rx_status->flag |= RX_FLAG_HT;
5308 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5310 rx_status->rate_idx = rx_desc->rxmcs;
5313 rx_status->freq = hw->conf.chandef.chan->center_freq;
5314 rx_status->band = hw->conf.chandef.chan->band;
5316 ieee80211_rx_irqsafe(hw, skb);
5317 return RX_TYPE_DATA_PKT;
5320 static void rtl8xxxu_rx_complete(struct urb *urb)
5322 struct rtl8xxxu_rx_urb *rx_urb =
5323 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5324 struct ieee80211_hw *hw = rx_urb->hw;
5325 struct rtl8xxxu_priv *priv = hw->priv;
5326 struct sk_buff *skb = (struct sk_buff *)urb->context;
5327 struct device *dev = &priv->udev->dev;
5329 skb_put(skb, urb->actual_length);
5331 if (urb->status == 0) {
5332 priv->fops->parse_rx_desc(priv, skb);
5335 rx_urb->urb.context = NULL;
5336 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5338 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5349 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5350 struct rtl8xxxu_rx_urb *rx_urb)
5352 struct rtl8xxxu_fileops *fops = priv->fops;
5353 struct sk_buff *skb;
5355 int ret, rx_desc_sz;
5357 rx_desc_sz = fops->rx_desc_size;
5359 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
5360 skb_size = fops->rx_agg_buf_size;
5361 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5363 skb_size = IEEE80211_MAX_FRAME_LEN;
5366 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5370 memset(skb->data, 0, rx_desc_sz);
5371 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5372 skb_size, rtl8xxxu_rx_complete, skb);
5373 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5374 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5376 usb_unanchor_urb(&rx_urb->urb);
5380 static void rtl8xxxu_int_complete(struct urb *urb)
5382 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5383 struct device *dev = &priv->udev->dev;
5386 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
5387 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5388 if (urb->status == 0) {
5389 usb_anchor_urb(urb, &priv->int_anchor);
5390 ret = usb_submit_urb(urb, GFP_ATOMIC);
5392 usb_unanchor_urb(urb);
5394 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
5399 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5401 struct rtl8xxxu_priv *priv = hw->priv;
5406 urb = usb_alloc_urb(0, GFP_KERNEL);
5410 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5411 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5412 rtl8xxxu_int_complete, priv, 1);
5413 usb_anchor_urb(urb, &priv->int_anchor);
5414 ret = usb_submit_urb(urb, GFP_KERNEL);
5416 usb_unanchor_urb(urb);
5420 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5421 val32 |= USB_HIMR_CPWM;
5422 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5429 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5430 struct ieee80211_vif *vif)
5432 struct rtl8xxxu_priv *priv = hw->priv;
5436 switch (vif->type) {
5437 case NL80211_IFTYPE_STATION:
5438 rtl8xxxu_stop_tx_beacon(priv);
5440 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5441 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5442 BEACON_DISABLE_TSF_UPDATE;
5443 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5450 rtl8xxxu_set_linktype(priv, vif->type);
5455 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5456 struct ieee80211_vif *vif)
5458 struct rtl8xxxu_priv *priv = hw->priv;
5460 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5463 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5465 struct rtl8xxxu_priv *priv = hw->priv;
5466 struct device *dev = &priv->udev->dev;
5468 int ret = 0, channel;
5471 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5473 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5474 __func__, hw->conf.chandef.chan->hw_value,
5475 changed, hw->conf.chandef.width);
5477 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5478 val16 = ((hw->conf.long_frame_max_tx_count <<
5479 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5480 ((hw->conf.short_frame_max_tx_count <<
5481 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5482 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5485 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5486 switch (hw->conf.chandef.width) {
5487 case NL80211_CHAN_WIDTH_20_NOHT:
5488 case NL80211_CHAN_WIDTH_20:
5491 case NL80211_CHAN_WIDTH_40:
5499 channel = hw->conf.chandef.chan->hw_value;
5501 priv->fops->set_tx_power(priv, channel, ht40);
5503 priv->fops->config_channel(hw);
5510 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5511 struct ieee80211_vif *vif, u16 queue,
5512 const struct ieee80211_tx_queue_params *param)
5514 struct rtl8xxxu_priv *priv = hw->priv;
5515 struct device *dev = &priv->udev->dev;
5517 u8 aifs, acm_ctrl, acm_bit;
5522 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5523 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5524 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5526 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5528 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5529 __func__, queue, val32, param->acm, acm_ctrl);
5532 case IEEE80211_AC_VO:
5533 acm_bit = ACM_HW_CTRL_VO;
5534 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5536 case IEEE80211_AC_VI:
5537 acm_bit = ACM_HW_CTRL_VI;
5538 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5540 case IEEE80211_AC_BE:
5541 acm_bit = ACM_HW_CTRL_BE;
5542 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5544 case IEEE80211_AC_BK:
5545 acm_bit = ACM_HW_CTRL_BK;
5546 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5554 acm_ctrl |= acm_bit;
5556 acm_ctrl &= ~acm_bit;
5557 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5562 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5563 unsigned int changed_flags,
5564 unsigned int *total_flags, u64 multicast)
5566 struct rtl8xxxu_priv *priv = hw->priv;
5567 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5569 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5570 __func__, changed_flags, *total_flags);
5573 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5576 if (*total_flags & FIF_FCSFAIL)
5577 rcr |= RCR_ACCEPT_CRC32;
5579 rcr &= ~RCR_ACCEPT_CRC32;
5582 * FIF_PLCPFAIL not supported?
5585 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5586 rcr &= ~RCR_CHECK_BSSID_BEACON;
5588 rcr |= RCR_CHECK_BSSID_BEACON;
5590 if (*total_flags & FIF_CONTROL)
5591 rcr |= RCR_ACCEPT_CTRL_FRAME;
5593 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5595 if (*total_flags & FIF_OTHER_BSS) {
5596 rcr |= RCR_ACCEPT_AP;
5597 rcr &= ~RCR_CHECK_BSSID_MATCH;
5599 rcr &= ~RCR_ACCEPT_AP;
5600 rcr |= RCR_CHECK_BSSID_MATCH;
5603 if (*total_flags & FIF_PSPOLL)
5604 rcr |= RCR_ACCEPT_PM;
5606 rcr &= ~RCR_ACCEPT_PM;
5609 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5612 rtl8xxxu_write32(priv, REG_RCR, rcr);
5614 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5615 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5619 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5627 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5628 struct ieee80211_vif *vif,
5629 struct ieee80211_sta *sta,
5630 struct ieee80211_key_conf *key)
5632 struct rtl8xxxu_priv *priv = hw->priv;
5633 struct device *dev = &priv->udev->dev;
5634 u8 mac_addr[ETH_ALEN];
5638 int retval = -EOPNOTSUPP;
5640 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5641 __func__, cmd, key->cipher, key->keyidx);
5643 if (vif->type != NL80211_IFTYPE_STATION)
5646 if (key->keyidx > 3)
5649 switch (key->cipher) {
5650 case WLAN_CIPHER_SUITE_WEP40:
5651 case WLAN_CIPHER_SUITE_WEP104:
5654 case WLAN_CIPHER_SUITE_CCMP:
5655 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5657 case WLAN_CIPHER_SUITE_TKIP:
5658 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5664 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5665 dev_dbg(dev, "%s: pairwise key\n", __func__);
5666 ether_addr_copy(mac_addr, sta->addr);
5668 dev_dbg(dev, "%s: group key\n", __func__);
5669 eth_broadcast_addr(mac_addr);
5672 val16 = rtl8xxxu_read16(priv, REG_CR);
5673 val16 |= CR_SECURITY_ENABLE;
5674 rtl8xxxu_write16(priv, REG_CR, val16);
5676 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5677 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5678 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5679 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5683 key->hw_key_idx = key->keyidx;
5684 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5685 rtl8xxxu_cam_write(priv, key, mac_addr);
5689 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5690 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5691 key->keyidx << CAM_CMD_KEY_SHIFT;
5692 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5696 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5703 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5704 struct ieee80211_ampdu_params *params)
5706 struct rtl8xxxu_priv *priv = hw->priv;
5707 struct device *dev = &priv->udev->dev;
5708 u8 ampdu_factor, ampdu_density;
5709 struct ieee80211_sta *sta = params->sta;
5710 enum ieee80211_ampdu_mlme_action action = params->action;
5713 case IEEE80211_AMPDU_TX_START:
5714 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5715 ampdu_factor = sta->ht_cap.ampdu_factor;
5716 ampdu_density = sta->ht_cap.ampdu_density;
5717 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5718 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5720 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5721 ampdu_factor, ampdu_density);
5723 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5724 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5725 rtl8xxxu_set_ampdu_factor(priv, 0);
5726 rtl8xxxu_set_ampdu_min_space(priv, 0);
5728 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5729 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5731 rtl8xxxu_set_ampdu_factor(priv, 0);
5732 rtl8xxxu_set_ampdu_min_space(priv, 0);
5734 case IEEE80211_AMPDU_RX_START:
5735 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5737 case IEEE80211_AMPDU_RX_STOP:
5738 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5746 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5748 struct rtl8xxxu_priv *priv = hw->priv;
5749 struct rtl8xxxu_rx_urb *rx_urb;
5750 struct rtl8xxxu_tx_urb *tx_urb;
5751 struct sk_buff *skb;
5752 unsigned long flags;
5757 init_usb_anchor(&priv->rx_anchor);
5758 init_usb_anchor(&priv->tx_anchor);
5759 init_usb_anchor(&priv->int_anchor);
5761 priv->fops->enable_rf(priv);
5762 if (priv->usb_interrupts) {
5763 ret = rtl8xxxu_submit_int_urb(hw);
5768 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5769 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5776 usb_init_urb(&tx_urb->urb);
5777 INIT_LIST_HEAD(&tx_urb->list);
5779 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5780 priv->tx_urb_free_count++;
5783 priv->tx_stopped = false;
5785 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5786 priv->shutdown = false;
5787 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5789 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5790 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5797 usb_init_urb(&rx_urb->urb);
5798 INIT_LIST_HEAD(&rx_urb->list);
5801 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5803 if (ret != -ENOMEM) {
5804 skb = (struct sk_buff *)rx_urb->urb.context;
5807 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5812 * Accept all data and mgmt frames
5814 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5815 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5817 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5822 rtl8xxxu_free_tx_resources(priv);
5824 * Disable all data and mgmt frames
5826 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5827 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5832 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5834 struct rtl8xxxu_priv *priv = hw->priv;
5835 unsigned long flags;
5837 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5839 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5840 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5842 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5843 priv->shutdown = true;
5844 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5846 usb_kill_anchored_urbs(&priv->rx_anchor);
5847 usb_kill_anchored_urbs(&priv->tx_anchor);
5848 if (priv->usb_interrupts)
5849 usb_kill_anchored_urbs(&priv->int_anchor);
5851 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5853 priv->fops->disable_rf(priv);
5856 * Disable interrupts
5858 if (priv->usb_interrupts)
5859 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5861 rtl8xxxu_free_rx_resources(priv);
5862 rtl8xxxu_free_tx_resources(priv);
5865 static const struct ieee80211_ops rtl8xxxu_ops = {
5867 .add_interface = rtl8xxxu_add_interface,
5868 .remove_interface = rtl8xxxu_remove_interface,
5869 .config = rtl8xxxu_config,
5870 .conf_tx = rtl8xxxu_conf_tx,
5871 .bss_info_changed = rtl8xxxu_bss_info_changed,
5872 .configure_filter = rtl8xxxu_configure_filter,
5873 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5874 .start = rtl8xxxu_start,
5875 .stop = rtl8xxxu_stop,
5876 .sw_scan_start = rtl8xxxu_sw_scan_start,
5877 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5878 .set_key = rtl8xxxu_set_key,
5879 .ampdu_action = rtl8xxxu_ampdu_action,
5882 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5883 struct usb_interface *interface)
5885 struct usb_interface_descriptor *interface_desc;
5886 struct usb_host_interface *host_interface;
5887 struct usb_endpoint_descriptor *endpoint;
5888 struct device *dev = &priv->udev->dev;
5889 int i, j = 0, endpoints;
5893 host_interface = interface->cur_altsetting;
5894 interface_desc = &host_interface->desc;
5895 endpoints = interface_desc->bNumEndpoints;
5897 for (i = 0; i < endpoints; i++) {
5898 endpoint = &host_interface->endpoint[i].desc;
5900 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5901 num = usb_endpoint_num(endpoint);
5902 xtype = usb_endpoint_type(endpoint);
5903 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5905 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5906 __func__, dir, num, xtype);
5907 if (usb_endpoint_dir_in(endpoint) &&
5908 usb_endpoint_xfer_bulk(endpoint)) {
5909 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5910 dev_dbg(dev, "%s: in endpoint num %i\n",
5913 if (priv->pipe_in) {
5915 "%s: Too many IN pipes\n", __func__);
5920 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5923 if (usb_endpoint_dir_in(endpoint) &&
5924 usb_endpoint_xfer_int(endpoint)) {
5925 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5926 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5929 if (priv->pipe_interrupt) {
5930 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5936 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5939 if (usb_endpoint_dir_out(endpoint) &&
5940 usb_endpoint_xfer_bulk(endpoint)) {
5941 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5942 dev_dbg(dev, "%s: out endpoint num %i\n",
5944 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5946 "%s: Too many OUT pipes\n", __func__);
5950 priv->out_ep[j++] = num;
5954 priv->nr_out_eps = j;
5958 static int rtl8xxxu_probe(struct usb_interface *interface,
5959 const struct usb_device_id *id)
5961 struct rtl8xxxu_priv *priv;
5962 struct ieee80211_hw *hw;
5963 struct usb_device *udev;
5964 struct ieee80211_supported_band *sband;
5968 udev = usb_get_dev(interface_to_usbdev(interface));
5970 switch (id->idVendor) {
5971 case USB_VENDOR_ID_REALTEK:
5972 switch(id->idProduct) {
5982 if (id->idProduct == 0x7811)
5986 if (id->idProduct == 0x1004)
5990 if (id->idProduct == 0x648b)
5994 if (id->idProduct == 0x3308)
5998 if (id->idProduct == 0x0109)
6006 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
6007 dev_info(&udev->dev,
6008 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6009 id->idVendor, id->idProduct);
6010 dev_info(&udev->dev,
6011 "Please report results to Jes.Sorensen@gmail.com\n");
6014 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6024 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6025 mutex_init(&priv->usb_buf_mutex);
6026 mutex_init(&priv->h2c_mutex);
6027 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6028 spin_lock_init(&priv->tx_urb_lock);
6029 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6030 spin_lock_init(&priv->rx_urb_lock);
6031 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6033 usb_set_intfdata(interface, hw);
6035 ret = rtl8xxxu_parse_usb(priv, interface);
6039 ret = rtl8xxxu_identify_chip(priv);
6041 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6045 ret = rtl8xxxu_read_efuse(priv);
6047 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6051 ret = priv->fops->parse_efuse(priv);
6053 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6057 rtl8xxxu_print_chipinfo(priv);
6059 ret = priv->fops->load_firmware(priv);
6061 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6065 ret = rtl8xxxu_init_device(hw);
6069 hw->wiphy->max_scan_ssids = 1;
6070 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6071 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6074 sband = &rtl8xxxu_supported_band;
6075 sband->ht_cap.ht_supported = true;
6076 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6077 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6078 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6079 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6080 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6081 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6082 if (priv->rf_paths > 1) {
6083 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6084 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6086 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6088 * Some APs will negotiate HT20_40 in a noisy environment leading
6089 * to miserable performance. Rather than defaulting to this, only
6090 * enable it if explicitly requested at module load time.
6092 if (rtl8xxxu_ht40_2g) {
6093 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6094 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6096 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6098 hw->wiphy->rts_threshold = 2347;
6100 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6101 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6103 hw->extra_tx_headroom = priv->fops->tx_desc_size;
6104 ieee80211_hw_set(hw, SIGNAL_DBM);
6106 * The firmware handles rate control
6108 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6109 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6111 ret = ieee80211_register_hw(priv->hw);
6113 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6121 usb_set_intfdata(interface, NULL);
6124 kfree(priv->fw_data);
6125 mutex_destroy(&priv->usb_buf_mutex);
6126 mutex_destroy(&priv->h2c_mutex);
6130 ieee80211_free_hw(hw);
6135 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6137 struct rtl8xxxu_priv *priv;
6138 struct ieee80211_hw *hw;
6140 hw = usb_get_intfdata(interface);
6143 ieee80211_unregister_hw(hw);
6145 priv->fops->power_off(priv);
6147 usb_set_intfdata(interface, NULL);
6149 dev_info(&priv->udev->dev, "disconnecting\n");
6151 kfree(priv->fw_data);
6152 mutex_destroy(&priv->usb_buf_mutex);
6153 mutex_destroy(&priv->h2c_mutex);
6155 if (priv->udev->state != USB_STATE_NOTATTACHED) {
6156 dev_info(&priv->udev->dev,
6157 "Device still attached, trying to reset\n");
6158 usb_reset_device(priv->udev);
6160 usb_put_dev(priv->udev);
6161 ieee80211_free_hw(hw);
6164 static struct usb_device_id dev_table[] = {
6165 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6166 .driver_info = (unsigned long)&rtl8723au_fops},
6167 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6168 .driver_info = (unsigned long)&rtl8723au_fops},
6169 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6170 .driver_info = (unsigned long)&rtl8723au_fops},
6171 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6172 .driver_info = (unsigned long)&rtl8192eu_fops},
6173 /* Tested by Myckel Habets */
6174 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6175 .driver_info = (unsigned long)&rtl8192eu_fops},
6176 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6177 .driver_info = (unsigned long)&rtl8723bu_fops},
6178 #ifdef CONFIG_RTL8XXXU_UNTESTED
6179 /* Still supported by rtlwifi */
6180 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6181 .driver_info = (unsigned long)&rtl8192cu_fops},
6182 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6183 .driver_info = (unsigned long)&rtl8192cu_fops},
6184 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6185 .driver_info = (unsigned long)&rtl8192cu_fops},
6186 /* Tested by Larry Finger */
6187 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6188 .driver_info = (unsigned long)&rtl8192cu_fops},
6189 /* Tested by Andrea Merello */
6190 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6191 .driver_info = (unsigned long)&rtl8192cu_fops},
6192 /* Tested by Jocelyn Mayer */
6193 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6194 .driver_info = (unsigned long)&rtl8192cu_fops},
6195 /* Tested by Stefano Bravi */
6196 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6197 .driver_info = (unsigned long)&rtl8192cu_fops},
6198 /* Currently untested 8188 series devices */
6199 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6200 .driver_info = (unsigned long)&rtl8192cu_fops},
6201 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6202 .driver_info = (unsigned long)&rtl8192cu_fops},
6203 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6204 .driver_info = (unsigned long)&rtl8192cu_fops},
6205 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6206 .driver_info = (unsigned long)&rtl8192cu_fops},
6207 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6208 .driver_info = (unsigned long)&rtl8192cu_fops},
6209 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6210 .driver_info = (unsigned long)&rtl8192cu_fops},
6211 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6212 .driver_info = (unsigned long)&rtl8192cu_fops},
6213 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6214 .driver_info = (unsigned long)&rtl8192cu_fops},
6215 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6216 .driver_info = (unsigned long)&rtl8192cu_fops},
6217 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6218 .driver_info = (unsigned long)&rtl8192cu_fops},
6219 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6220 .driver_info = (unsigned long)&rtl8192cu_fops},
6221 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6222 .driver_info = (unsigned long)&rtl8192cu_fops},
6223 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6224 .driver_info = (unsigned long)&rtl8192cu_fops},
6225 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6226 .driver_info = (unsigned long)&rtl8192cu_fops},
6227 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6228 .driver_info = (unsigned long)&rtl8192cu_fops},
6229 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6230 .driver_info = (unsigned long)&rtl8192cu_fops},
6231 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6232 .driver_info = (unsigned long)&rtl8192cu_fops},
6233 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6234 .driver_info = (unsigned long)&rtl8192cu_fops},
6235 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6236 .driver_info = (unsigned long)&rtl8192cu_fops},
6237 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6238 .driver_info = (unsigned long)&rtl8192cu_fops},
6239 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6240 .driver_info = (unsigned long)&rtl8192cu_fops},
6241 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6242 .driver_info = (unsigned long)&rtl8192cu_fops},
6243 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6244 .driver_info = (unsigned long)&rtl8192cu_fops},
6245 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6246 .driver_info = (unsigned long)&rtl8192cu_fops},
6247 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6248 .driver_info = (unsigned long)&rtl8192cu_fops},
6249 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6250 .driver_info = (unsigned long)&rtl8192cu_fops},
6251 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6252 .driver_info = (unsigned long)&rtl8192cu_fops},
6253 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6254 .driver_info = (unsigned long)&rtl8192cu_fops},
6255 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6256 .driver_info = (unsigned long)&rtl8192cu_fops},
6257 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6258 .driver_info = (unsigned long)&rtl8192cu_fops},
6259 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6260 .driver_info = (unsigned long)&rtl8192cu_fops},
6261 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6262 .driver_info = (unsigned long)&rtl8192cu_fops},
6263 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6264 .driver_info = (unsigned long)&rtl8192cu_fops},
6265 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6266 .driver_info = (unsigned long)&rtl8192cu_fops},
6267 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6268 .driver_info = (unsigned long)&rtl8192cu_fops},
6269 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6270 .driver_info = (unsigned long)&rtl8192cu_fops},
6271 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6272 .driver_info = (unsigned long)&rtl8192cu_fops},
6273 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6274 .driver_info = (unsigned long)&rtl8192cu_fops},
6275 /* Currently untested 8192 series devices */
6276 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6277 .driver_info = (unsigned long)&rtl8192cu_fops},
6278 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6279 .driver_info = (unsigned long)&rtl8192cu_fops},
6280 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6281 .driver_info = (unsigned long)&rtl8192cu_fops},
6282 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6283 .driver_info = (unsigned long)&rtl8192cu_fops},
6284 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6285 .driver_info = (unsigned long)&rtl8192cu_fops},
6286 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6287 .driver_info = (unsigned long)&rtl8192cu_fops},
6288 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6289 .driver_info = (unsigned long)&rtl8192cu_fops},
6290 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6291 .driver_info = (unsigned long)&rtl8192cu_fops},
6292 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6293 .driver_info = (unsigned long)&rtl8192cu_fops},
6294 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6295 .driver_info = (unsigned long)&rtl8192cu_fops},
6296 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6297 .driver_info = (unsigned long)&rtl8192cu_fops},
6298 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6299 .driver_info = (unsigned long)&rtl8192cu_fops},
6300 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6301 .driver_info = (unsigned long)&rtl8192cu_fops},
6302 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6303 .driver_info = (unsigned long)&rtl8192cu_fops},
6304 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6305 .driver_info = (unsigned long)&rtl8192cu_fops},
6306 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6307 .driver_info = (unsigned long)&rtl8192cu_fops},
6308 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6309 .driver_info = (unsigned long)&rtl8192cu_fops},
6310 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6311 .driver_info = (unsigned long)&rtl8192cu_fops},
6312 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6313 .driver_info = (unsigned long)&rtl8192cu_fops},
6314 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6315 .driver_info = (unsigned long)&rtl8192cu_fops},
6316 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6317 .driver_info = (unsigned long)&rtl8192cu_fops},
6318 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6319 .driver_info = (unsigned long)&rtl8192cu_fops},
6320 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6321 .driver_info = (unsigned long)&rtl8192cu_fops},
6322 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6323 .driver_info = (unsigned long)&rtl8192cu_fops},
6324 /* found in rtl8192eu vendor driver */
6325 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
6326 .driver_info = (unsigned long)&rtl8192eu_fops},
6327 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
6328 .driver_info = (unsigned long)&rtl8192eu_fops},
6329 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
6330 .driver_info = (unsigned long)&rtl8192eu_fops},
6335 static struct usb_driver rtl8xxxu_driver = {
6336 .name = DRIVER_NAME,
6337 .probe = rtl8xxxu_probe,
6338 .disconnect = rtl8xxxu_disconnect,
6339 .id_table = dev_table,
6341 .disable_hub_initiated_lpm = 1,
6344 static int __init rtl8xxxu_module_init(void)
6348 res = usb_register(&rtl8xxxu_driver);
6350 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6355 static void __exit rtl8xxxu_module_exit(void)
6357 usb_deregister(&rtl8xxxu_driver);
6361 MODULE_DEVICE_TABLE(usb, dev_table);
6363 module_init(rtl8xxxu_module_init);
6364 module_exit(rtl8xxxu_module_exit);