drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
  46 static bool rtl8xxxu_ht40_2g;
  47 static bool rtl8xxxu_dma_aggregation;
  48 static int rtl8xxxu_dma_agg_timeout = -1;
  49 static int rtl8xxxu_dma_agg_pages = -1;
  50
  51 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
  52 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  53 MODULE_LICENSE("GPL");
  54 /*(DEBLOBBED)*/
  55
  56 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  57 MODULE_PARM_DESC(debug, "Set debug mask");
  58 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  59 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  60 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
  61 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
  62 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
  63 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
  64 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
  65 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
  66
  67 #define USB_VENDOR_ID_REALTEK           0x0bda
  68 #define RTL8XXXU_RX_URBS                32
  69 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  70 #define RTL8XXXU_TX_URBS                64
  71 #define RTL8XXXU_TX_URB_LOW_WATER       25
  72 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  73
  74 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  75                                   struct rtl8xxxu_rx_urb *rx_urb);
  76
  77 static struct ieee80211_rate rtl8xxxu_rates[] = {
  78         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  79         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  80         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  81         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  82         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  83         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  84         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  85         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  86         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  87         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  88         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  89         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  90 };
  91
  92 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  93         { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
  94           .hw_value = 1, .max_power = 30 },
  95         { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
  96           .hw_value = 2, .max_power = 30 },
  97         { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
  98           .hw_value = 3, .max_power = 30 },
  99         { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
 100           .hw_value = 4, .max_power = 30 },
 101         { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
 102           .hw_value = 5, .max_power = 30 },
 103         { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
 104           .hw_value = 6, .max_power = 30 },
 105         { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
 106           .hw_value = 7, .max_power = 30 },
 107         { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
 108           .hw_value = 8, .max_power = 30 },
 109         { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
 110           .hw_value = 9, .max_power = 30 },
 111         { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
 112           .hw_value = 10, .max_power = 30 },
 113         { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
 114           .hw_value = 11, .max_power = 30 },
 115         { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
 116           .hw_value = 12, .max_power = 30 },
 117         { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
 118           .hw_value = 13, .max_power = 30 },
 119         { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
 120           .hw_value = 14, .max_power = 30 }
 121 };
 122
 123 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 124         .channels = rtl8xxxu_channels_2g,
 125         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 126         .bitrates = rtl8xxxu_rates,
 127         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 128 };
 129
 130 struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
 131         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 132         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 133         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 134         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 135         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 136         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 137         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 138         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 139         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 140         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 141         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 142         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 143         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 144         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 145         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 146         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 147         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 148         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 149         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 150         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 151         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 152         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 153 };
 154
 155 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 156         {0x800, 0x80040000}, {0x804, 0x00000003},
 157         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 158         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 159         {0x818, 0x02200385}, {0x81c, 0x00000000},
 160         {0x820, 0x01000100}, {0x824, 0x00390004},
 161         {0x828, 0x00000000}, {0x82c, 0x00000000},
 162         {0x830, 0x00000000}, {0x834, 0x00000000},
 163         {0x838, 0x00000000}, {0x83c, 0x00000000},
 164         {0x840, 0x00010000}, {0x844, 0x00000000},
 165         {0x848, 0x00000000}, {0x84c, 0x00000000},
 166         {0x850, 0x00000000}, {0x854, 0x00000000},
 167         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 168         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 169         {0x868, 0x00000000}, {0x86c, 0x32323200},
 170         {0x870, 0x07000760}, {0x874, 0x22004000},
 171         {0x878, 0x00000808}, {0x87c, 0x00000000},
 172         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 173         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 174         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 175         {0x898, 0x40302010}, {0x89c, 0x00706050},
 176         {0x900, 0x00000000}, {0x904, 0x00000023},
 177         {0x908, 0x00000000}, {0x90c, 0x81121111},
 178         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 179         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 180         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 181         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 182         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 183         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 184         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 185         {0xa78, 0x00000900},
 186         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 187         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 188         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 189         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 190         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 191         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 192         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 193         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 194         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 195         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 196         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 197         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 198         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 199         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 200         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 201         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 202         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 203         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 204         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 205         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 206         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 207         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 208         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 209         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 210         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 211         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 212         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 213         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 214         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 215         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 216         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 217         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 218         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 219         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 220         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 221         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 222         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 223         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 224         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 225         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 226         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 227         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 228         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 229         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 230         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 231         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 232         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 233         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 234         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 235         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 236         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 237         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 238         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 239         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 240         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 241         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 242         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 243         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 244         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 245         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 246         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 247         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 248         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 249         {0xf00, 0x00000300},
 250         {0xffff, 0xffffffff},
 251 };
 252
 253 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 254         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 255         {0x800, 0x80040002}, {0x804, 0x00000003},
 256         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 257         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 258         {0x818, 0x02200385}, {0x81c, 0x00000000},
 259         {0x820, 0x01000100}, {0x824, 0x00390004},
 260         {0x828, 0x01000100}, {0x82c, 0x00390004},
 261         {0x830, 0x27272727}, {0x834, 0x27272727},
 262         {0x838, 0x27272727}, {0x83c, 0x27272727},
 263         {0x840, 0x00010000}, {0x844, 0x00010000},
 264         {0x848, 0x27272727}, {0x84c, 0x27272727},
 265         {0x850, 0x00000000}, {0x854, 0x00000000},
 266         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 267         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 268         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 269         {0x870, 0x07000700}, {0x874, 0x22184000},
 270         {0x878, 0x08080808}, {0x87c, 0x00000000},
 271         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 272         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 273         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 274         {0x898, 0x40302010}, {0x89c, 0x00706050},
 275         {0x900, 0x00000000}, {0x904, 0x00000023},
 276         {0x908, 0x00000000}, {0x90c, 0x81121313},
 277         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 278         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 279         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 280         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 281         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 282         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 283         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 284         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 285         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 286         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 287         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 288         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 289         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 290         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 291         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 292         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 293         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 294         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 295         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 296         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 297         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 298         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 299         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 300         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 301         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 302         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 303         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 304         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 305         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 306         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 307         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 308         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 309         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 310         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 311         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 312         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 313         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 314         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 315         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 316         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 317         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 318         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 319         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 320         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 321         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 322         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 323         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 324         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 325         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 326         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 327         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 328         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 329         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 330         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 331         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 332         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 333         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 334         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 335         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 336         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 337         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 338         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 339         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 340         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 341         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 342         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 343         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 344         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 345         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 346         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 347         {0xf00, 0x00000300},
 348         {0xffff, 0xffffffff},
 349 };
 350
 351 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 352         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 353         {0x040, 0x000c0004}, {0x800, 0x80040000},
 354         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 355         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 356         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 357         {0x81c, 0x00000000}, {0x820, 0x01000100},
 358         {0x824, 0x00390204}, {0x828, 0x00000000},
 359         {0x82c, 0x00000000}, {0x830, 0x00000000},
 360         {0x834, 0x00000000}, {0x838, 0x00000000},
 361         {0x83c, 0x00000000}, {0x840, 0x00010000},
 362         {0x844, 0x00000000}, {0x848, 0x00000000},
 363         {0x84c, 0x00000000}, {0x850, 0x00000000},
 364         {0x854, 0x00000000}, {0x858, 0x569a569a},
 365         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 366         {0x864, 0x061f0130}, {0x868, 0x00000000},
 367         {0x86c, 0x20202000}, {0x870, 0x03000300},
 368         {0x874, 0x22004000}, {0x878, 0x00000808},
 369         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 370         {0x884, 0x000004d5}, {0x888, 0x00000000},
 371         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 372         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 373         {0x89c, 0x00706050}, {0x900, 0x00000000},
 374         {0x904, 0x00000023}, {0x908, 0x00000000},
 375         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 376         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 377         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 378         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 379         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 380         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 381         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 382         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 383         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 384         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 385         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 386         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 387         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 388         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 389         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 390         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 391         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 392         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 393         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 394         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 395         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 396         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 397         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 398         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 399         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 400         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 401         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 402         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 403         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 404         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 405         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 406         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 407         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 408         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 409         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 410         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 411         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 412         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 413         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 414         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 415         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 416         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 417         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 418         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 419         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 420         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 421         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 422         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 423         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 424         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 425         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 426         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 427         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 428         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 429         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 430         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 431         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 432         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 433         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 434         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 435         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 436         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 437         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 438         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 439         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 440         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 441         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 442         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 443         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 444         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 445         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 446         {0xf00, 0x00000300},
 447         {0xffff, 0xffffffff},
 448 };
 449
 450 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 451         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 452         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 453         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 454         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 455         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 456         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 457         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 458         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 459         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 460         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 461         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 462         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 463         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 464         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 465         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 466         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 467         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 468         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 469         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 470         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 471         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 472         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 473         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 474         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 475         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 476         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 477         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 478         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 479         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 480         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 481         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 482         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 483         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 484         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 485         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 486         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 487         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 488         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 489         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 490         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 491         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 492         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 493         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 494         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 495         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 496         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 497         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 498         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 499         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 500         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 501         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 502         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 503         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 504         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 505         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 506         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 507         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 508         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 509         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 510         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 511         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 512         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 513         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 514         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 515         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 516         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 517         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 518         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 519         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 520         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 521         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 522         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 523         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 524         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 525         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 526         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 527         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 528         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 529         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 530         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 531         {0xffff, 0xffffffff}
 532 };
 533
 534 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 535         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 536         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 537         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 538         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 539         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 540         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 541         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 542         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 543         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 544         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 545         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 546         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 547         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 548         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 549         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 550         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 551         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 552         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 553         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 554         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 555         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 556         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 557         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 558         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 559         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 560         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 561         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 562         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 563         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 564         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 565         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 566         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 567         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 568         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 569         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 570         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 571         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 572         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 573         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 574         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 575         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 576         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 577         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 578         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 579         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 580         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 581         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 582         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 583         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 584         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 585         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 586         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 587         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 588         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 589         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 590         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 591         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 592         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 593         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 594         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 595         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 596         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 597         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 598         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 599         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 600         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 601         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 602         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 603         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 604         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 605         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 606         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 607         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 608         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 609         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 610         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 611         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 612         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 613         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 614         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 615         {0xffff, 0xffffffff}
 616 };
 617
 618 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 619         {       /* RF_A */
 620                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 621                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 622                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 623                 .hspiread = REG_HSPI_XA_READBACK,
 624                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 625                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 626         },
 627         {       /* RF_B */
 628                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 629                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 630                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 631                 .hspiread = REG_HSPI_XB_READBACK,
 632                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 633                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 634         },
 635 };
 636
 637 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 638         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 639         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 640         REG_OFDM0_ENERGY_CCA_THRES,
 641         REG_OFDM0_AGCR_SSI_TABLE,
 642         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 643         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 644         REG_OFDM0_XC_TX_AFE,
 645         REG_OFDM0_XD_TX_AFE,
 646         REG_OFDM0_RX_IQ_EXT_ANTA
 647 };
 648
 649 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 650 {
 651         struct usb_device *udev = priv->udev;
 652         int len;
 653         u8 data;
 654
 655         mutex_lock(&priv->usb_buf_mutex);
 656         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 657                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 658                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 659                               RTW_USB_CONTROL_MSG_TIMEOUT);
 660         data = priv->usb_buf.val8;
 661         mutex_unlock(&priv->usb_buf_mutex);
 662
 663         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 664                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 665                          __func__, addr, data, len);
 666         return data;
 667 }
 668
 669 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 670 {
 671         struct usb_device *udev = priv->udev;
 672         int len;
 673         u16 data;
 674
 675         mutex_lock(&priv->usb_buf_mutex);
 676         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 677                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 678                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
 679                               RTW_USB_CONTROL_MSG_TIMEOUT);
 680         data = le16_to_cpu(priv->usb_buf.val16);
 681         mutex_unlock(&priv->usb_buf_mutex);
 682
 683         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 684                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
 685                          __func__, addr, data, len);
 686         return data;
 687 }
 688
 689 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
 690 {
 691         struct usb_device *udev = priv->udev;
 692         int len;
 693         u32 data;
 694
 695         mutex_lock(&priv->usb_buf_mutex);
 696         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 697                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 698                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
 699                               RTW_USB_CONTROL_MSG_TIMEOUT);
 700         data = le32_to_cpu(priv->usb_buf.val32);
 701         mutex_unlock(&priv->usb_buf_mutex);
 702
 703         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 704                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
 705                          __func__, addr, data, len);
 706         return data;
 707 }
 708
 709 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
 710 {
 711         struct usb_device *udev = priv->udev;
 712         int ret;
 713
 714         mutex_lock(&priv->usb_buf_mutex);
 715         priv->usb_buf.val8 = val;
 716         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 717                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 718                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 719                               RTW_USB_CONTROL_MSG_TIMEOUT);
 720
 721         mutex_unlock(&priv->usb_buf_mutex);
 722
 723         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 724                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
 725                          __func__, addr, val);
 726         return ret;
 727 }
 728
 729 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
 730 {
 731         struct usb_device *udev = priv->udev;
 732         int ret;
 733
 734         mutex_lock(&priv->usb_buf_mutex);
 735         priv->usb_buf.val16 = cpu_to_le16(val);
 736         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 737                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 738                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
 739                               RTW_USB_CONTROL_MSG_TIMEOUT);
 740         mutex_unlock(&priv->usb_buf_mutex);
 741
 742         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 743                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
 744                          __func__, addr, val);
 745         return ret;
 746 }
 747
 748 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
 749 {
 750         struct usb_device *udev = priv->udev;
 751         int ret;
 752
 753         mutex_lock(&priv->usb_buf_mutex);
 754         priv->usb_buf.val32 = cpu_to_le32(val);
 755         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 756                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 757                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
 758                               RTW_USB_CONTROL_MSG_TIMEOUT);
 759         mutex_unlock(&priv->usb_buf_mutex);
 760
 761         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 762                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
 763                          __func__, addr, val);
 764         return ret;
 765 }
 766
 767 static int
 768 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
 769 {
 770         struct usb_device *udev = priv->udev;
 771         int blocksize = priv->fops->writeN_block_size;
 772         int ret, i, count, remainder;
 773
 774         count = len / blocksize;
 775         remainder = len % blocksize;
 776
 777         for (i = 0; i < count; i++) {
 778                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 779                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 780                                       addr, 0, buf, blocksize,
 781                                       RTW_USB_CONTROL_MSG_TIMEOUT);
 782                 if (ret != blocksize)
 783                         goto write_error;
 784
 785                 addr += blocksize;
 786                 buf += blocksize;
 787         }
 788
 789         if (remainder) {
 790                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 791                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 792                                       addr, 0, buf, remainder,
 793                                       RTW_USB_CONTROL_MSG_TIMEOUT);
 794                 if (ret != remainder)
 795                         goto write_error;
 796         }
 797
 798         return len;
 799
 800 write_error:
 801         dev_info(&udev->dev,
 802                  "%s: Failed to write block at addr: %04x size: %04x\n",
 803                  __func__, addr, blocksize);
 804         return -EAGAIN;
 805 }
 806
 807 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
 808                         enum rtl8xxxu_rfpath path, u8 reg)
 809 {
 810         u32 hssia, val32, retval;
 811
 812         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
 813         if (path != RF_A)
 814                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
 815         else
 816                 val32 = hssia;
 817
 818         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
 819         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
 820         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
 821         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
 822         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
 823
 824         udelay(10);
 825
 826         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
 827         udelay(100);
 828
 829         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
 830         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
 831         udelay(10);
 832
 833         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
 834         if (val32 & FPGA0_HSSI_PARM1_PI)
 835                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
 836         else
 837                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
 838
 839         retval &= 0xfffff;
 840
 841         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
 842                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
 843                          __func__, reg, retval);
 844         return retval;
 845 }
 846
 847 /*
 848  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
 849  * have write issues in high temperature conditions. We may have to
 850  * retry writing them.
 851  */
 852 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
 853                          enum rtl8xxxu_rfpath path, u8 reg, u32 data)
 854 {
 855         int ret, retval;
 856         u32 dataaddr, val32;
 857
 858         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
 859                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
 860                          __func__, reg, data);
 861
 862         data &= FPGA0_LSSI_PARM_DATA_MASK;
 863         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
 864
 865         if (priv->rtl_chip == RTL8192E) {
 866                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
 867                 val32 &= ~0x20000;
 868                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
 869         }
 870
 871         /* Use XB for path B */
 872         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
 873         if (ret != sizeof(dataaddr))
 874                 retval = -EIO;
 875         else
 876                 retval = 0;
 877
 878         udelay(1);
 879
 880         if (priv->rtl_chip == RTL8192E) {
 881                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
 882                 val32 |= 0x20000;
 883                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
 884         }
 885
 886         return retval;
 887 }
 888
 889 static int
 890 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
 891 {
 892         struct device *dev = &priv->udev->dev;
 893         int mbox_nr, retry, retval = 0;
 894         int mbox_reg, mbox_ext_reg;
 895         u8 val8;
 896
 897         mutex_lock(&priv->h2c_mutex);
 898
 899         mbox_nr = priv->next_mbox;
 900         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
 901         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
 902
 903         /*
 904          * MBOX ready?
 905          */
 906         retry = 100;
 907         do {
 908                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
 909                 if (!(val8 & BIT(mbox_nr)))
 910                         break;
 911         } while (retry--);
 912
 913         if (!retry) {
 914                 dev_info(dev, "%s: Mailbox busy\n", __func__);
 915                 retval = -EBUSY;
 916                 goto error;
 917         }
 918
 919         /*
 920          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
 921          */
 922         if (len > sizeof(u32)) {
 923                 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
 924                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
 925                         dev_info(dev, "H2C_EXT %04x\n",
 926                                  le16_to_cpu(h2c->raw.ext));
 927         }
 928         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
 929         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
 930                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
 931
 932         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
 933
 934 error:
 935         mutex_unlock(&priv->h2c_mutex);
 936         return retval;
 937 }
 938
 939 int
 940 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
 941 {
 942         struct device *dev = &priv->udev->dev;
 943         int mbox_nr, retry, retval = 0;
 944         int mbox_reg, mbox_ext_reg;
 945         u8 val8;
 946
 947         mutex_lock(&priv->h2c_mutex);
 948
 949         mbox_nr = priv->next_mbox;
 950         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
 951         mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
 952
 953         /*
 954          * MBOX ready?
 955          */
 956         retry = 100;
 957         do {
 958                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
 959                 if (!(val8 & BIT(mbox_nr)))
 960                         break;
 961         } while (retry--);
 962
 963         if (!retry) {
 964                 dev_info(dev, "%s: Mailbox busy\n", __func__);
 965                 retval = -EBUSY;
 966                 goto error;
 967         }
 968
 969         /*
 970          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
 971          */
 972         if (len > sizeof(u32)) {
 973                 rtl8xxxu_write32(priv, mbox_ext_reg,
 974                                  le32_to_cpu(h2c->raw_wide.ext));
 975                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
 976                         dev_info(dev, "H2C_EXT %08x\n",
 977                                  le32_to_cpu(h2c->raw_wide.ext));
 978         }
 979         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
 980         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
 981                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
 982
 983         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
 984
 985 error:
 986         mutex_unlock(&priv->h2c_mutex);
 987         return retval;
 988 }
 989
 990 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
 991 {
 992         u8 val8;
 993         u32 val32;
 994
 995         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
 996         val8 |= BIT(0) | BIT(3);
 997         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
 998
 999         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1000         val32 &= ~(BIT(4) | BIT(5));
1001         val32 |= BIT(3);
1002         if (priv->rf_paths == 2) {
1003                 val32 &= ~(BIT(20) | BIT(21));
1004                 val32 |= BIT(19);
1005         }
1006         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1007
1008         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1009         val32 &= ~OFDM_RF_PATH_TX_MASK;
1010         if (priv->tx_paths == 2)
1011                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1012         else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1013                 val32 |= OFDM_RF_PATH_TX_B;
1014         else
1015                 val32 |= OFDM_RF_PATH_TX_A;
1016         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1017
1018         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1019         val32 &= ~FPGA_RF_MODE_JAPAN;
1020         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1021
1022         if (priv->rf_paths == 2)
1023                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1024         else
1025                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1026
1027         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1028         if (priv->rf_paths == 2)
1029                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1030
1031         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1032 }
1033
1034 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1035 {
1036         u8 sps0;
1037         u32 val32;
1038
1039         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1040
1041         /* RF RX code for preamble power saving */
1042         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1043         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1044         if (priv->rf_paths == 2)
1045                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1046         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1047
1048         /* Disable TX for four paths */
1049         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1050         val32 &= ~OFDM_RF_PATH_TX_MASK;
1051         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1052
1053         /* Enable power saving */
1054         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1055         val32 |= FPGA_RF_MODE_JAPAN;
1056         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1057
1058         /* AFE control register to power down bits [30:22] */
1059         if (priv->rf_paths == 2)
1060                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1061         else
1062                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1063
1064         /* Power down RF module */
1065         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1066         if (priv->rf_paths == 2)
1067                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1068
1069         sps0 &= ~(BIT(0) | BIT(3));
1070         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1071 }
1072
1073 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1074 {
1075         u8 val8;
1076
1077         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1078         val8 &= ~BIT(6);
1079         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1080
1081         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1082         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1083         val8 &= ~BIT(0);
1084         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1085 }
1086
1087
1088 /*
1089  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1090  * supports the 2.4GHz band, so channels 1 - 14:
1091  *  group 0: channels 1 - 3
1092  *  group 1: channels 4 - 9
1093  *  group 2: channels 10 - 14
1094  *
1095  * Note: We index from 0 in the code
1096  */
1097 static int rtl8xxxu_gen1_channel_to_group(int channel)
1098 {
1099         int group;
1100
1101         if (channel < 4)
1102                 group = 0;
1103         else if (channel < 10)
1104                 group = 1;
1105         else
1106                 group = 2;
1107
1108         return group;
1109 }
1110
1111 /*
1112  * Valid for rtl8723bu and rtl8192eu
1113  */
1114 int rtl8xxxu_gen2_channel_to_group(int channel)
1115 {
1116         int group;
1117
1118         if (channel < 3)
1119                 group = 0;
1120         else if (channel < 6)
1121                 group = 1;
1122         else if (channel < 9)
1123                 group = 2;
1124         else if (channel < 12)
1125                 group = 3;
1126         else
1127                 group = 4;
1128
1129         return group;
1130 }
1131
1132 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1133 {
1134         struct rtl8xxxu_priv *priv = hw->priv;
1135         u32 val32, rsr;
1136         u8 val8, opmode;
1137         bool ht = true;
1138         int sec_ch_above, channel;
1139         int i;
1140
1141         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1142         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1143         channel = hw->conf.chandef.chan->hw_value;
1144
1145         switch (hw->conf.chandef.width) {
1146         case NL80211_CHAN_WIDTH_20_NOHT:
1147                 ht = false;
1148         case NL80211_CHAN_WIDTH_20:
1149                 opmode |= BW_OPMODE_20MHZ;
1150                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1151
1152                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1153                 val32 &= ~FPGA_RF_MODE;
1154                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1155
1156                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1157                 val32 &= ~FPGA_RF_MODE;
1158                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1159
1160                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1161                 val32 |= FPGA0_ANALOG2_20MHZ;
1162                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1163                 break;
1164         case NL80211_CHAN_WIDTH_40:
1165                 if (hw->conf.chandef.center_freq1 >
1166                     hw->conf.chandef.chan->center_freq) {
1167                         sec_ch_above = 1;
1168                         channel += 2;
1169                 } else {
1170                         sec_ch_above = 0;
1171                         channel -= 2;
1172                 }
1173
1174                 opmode &= ~BW_OPMODE_20MHZ;
1175                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1176                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1177                 if (sec_ch_above)
1178                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1179                 else
1180                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1181                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1182
1183                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1184                 val32 |= FPGA_RF_MODE;
1185                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1186
1187                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1188                 val32 |= FPGA_RF_MODE;
1189                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1190
1191                 /*
1192                  * Set Control channel to upper or lower. These settings
1193                  * are required only for 40MHz
1194                  */
1195                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1196                 val32 &= ~CCK0_SIDEBAND;
1197                 if (!sec_ch_above)
1198                         val32 |= CCK0_SIDEBAND;
1199                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1200
1201                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1202                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1203                 if (sec_ch_above)
1204                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1205                 else
1206                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1207                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1208
1209                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1210                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1211                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1212
1213                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1214                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1215                 if (sec_ch_above)
1216                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1217                 else
1218                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1219                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1220                 break;
1221
1222         default:
1223                 break;
1224         }
1225
1226         for (i = RF_A; i < priv->rf_paths; i++) {
1227                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1228                 val32 &= ~MODE_AG_CHANNEL_MASK;
1229                 val32 |= channel;
1230                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1231         }
1232
1233         if (ht)
1234                 val8 = 0x0e;
1235         else
1236                 val8 = 0x0a;
1237
1238         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1239         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1240
1241         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1242         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1243
1244         for (i = RF_A; i < priv->rf_paths; i++) {
1245                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1246                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1247                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1248                 else
1249                         val32 |= MODE_AG_CHANNEL_20MHZ;
1250                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1251         }
1252 }
1253
1254 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1255 {
1256         struct rtl8xxxu_priv *priv = hw->priv;
1257         u32 val32, rsr;
1258         u8 val8, subchannel;
1259         u16 rf_mode_bw;
1260         bool ht = true;
1261         int sec_ch_above, channel;
1262         int i;
1263
1264         rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1265         rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1266         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1267         channel = hw->conf.chandef.chan->hw_value;
1268
1269 /* Hack */
1270         subchannel = 0;
1271
1272         switch (hw->conf.chandef.width) {
1273         case NL80211_CHAN_WIDTH_20_NOHT:
1274                 ht = false;
1275         case NL80211_CHAN_WIDTH_20:
1276                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1277                 subchannel = 0;
1278
1279                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1280                 val32 &= ~FPGA_RF_MODE;
1281                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1282
1283                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1284                 val32 &= ~FPGA_RF_MODE;
1285                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1286
1287                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1288                 val32 &= ~(BIT(30) | BIT(31));
1289                 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1290
1291                 break;
1292         case NL80211_CHAN_WIDTH_40:
1293                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1294
1295                 if (hw->conf.chandef.center_freq1 >
1296                     hw->conf.chandef.chan->center_freq) {
1297                         sec_ch_above = 1;
1298                         channel += 2;
1299                 } else {
1300                         sec_ch_above = 0;
1301                         channel -= 2;
1302                 }
1303
1304                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1305                 val32 |= FPGA_RF_MODE;
1306                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1307
1308                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1309                 val32 |= FPGA_RF_MODE;
1310                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1311
1312                 /*
1313                  * Set Control channel to upper or lower. These settings
1314                  * are required only for 40MHz
1315                  */
1316                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1317                 val32 &= ~CCK0_SIDEBAND;
1318                 if (!sec_ch_above)
1319                         val32 |= CCK0_SIDEBAND;
1320                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1321
1322                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1323                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1324                 if (sec_ch_above)
1325                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1326                 else
1327                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1328                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1329
1330                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1331                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1332                 if (sec_ch_above)
1333                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1334                 else
1335                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1336                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1337                 break;
1338         case NL80211_CHAN_WIDTH_80:
1339                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1340                 break;
1341         default:
1342                 break;
1343         }
1344
1345         for (i = RF_A; i < priv->rf_paths; i++) {
1346                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1347                 val32 &= ~MODE_AG_CHANNEL_MASK;
1348                 val32 |= channel;
1349                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1350         }
1351
1352         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1353         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1354
1355         if (ht)
1356                 val8 = 0x0e;
1357         else
1358                 val8 = 0x0a;
1359
1360         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1361         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1362
1363         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1364         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1365
1366         for (i = RF_A; i < priv->rf_paths; i++) {
1367                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1368                 val32 &= ~MODE_AG_BW_MASK;
1369                 switch(hw->conf.chandef.width) {
1370                 case NL80211_CHAN_WIDTH_80:
1371                         val32 |= MODE_AG_BW_80MHZ_8723B;
1372                         break;
1373                 case NL80211_CHAN_WIDTH_40:
1374                         val32 |= MODE_AG_BW_40MHZ_8723B;
1375                         break;
1376                 default:
1377                         val32 |= MODE_AG_BW_20MHZ_8723B;
1378                         break;
1379                 }
1380                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1381         }
1382 }
1383
1384 void
1385 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1386 {
1387         struct rtl8xxxu_power_base *power_base = priv->power_base;
1388         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1389         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1390         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1391         u8 val8;
1392         int group, i;
1393
1394         group = rtl8xxxu_gen1_channel_to_group(channel);
1395
1396         cck[0] = priv->cck_tx_power_index_A[group] - 1;
1397         cck[1] = priv->cck_tx_power_index_B[group] - 1;
1398
1399         if (priv->hi_pa) {
1400                 if (cck[0] > 0x20)
1401                         cck[0] = 0x20;
1402                 if (cck[1] > 0x20)
1403                         cck[1] = 0x20;
1404         }
1405
1406         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1407         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1408         if (ofdm[0])
1409                 ofdm[0] -= 1;
1410         if (ofdm[1])
1411                 ofdm[1] -= 1;
1412
1413         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1414         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1415
1416         mcsbase[0] = ofdm[0];
1417         mcsbase[1] = ofdm[1];
1418         if (!ht40) {
1419                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1420                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1421         }
1422
1423         if (priv->tx_paths > 1) {
1424                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1425                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1426                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1427                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1428         }
1429
1430         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1431                 dev_info(&priv->udev->dev,
1432                          "%s: Setting TX power CCK A: %02x, "
1433                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1434                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1435
1436         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1437                 if (cck[i] > RF6052_MAX_TX_PWR)
1438                         cck[i] = RF6052_MAX_TX_PWR;
1439                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1440                         ofdm[i] = RF6052_MAX_TX_PWR;
1441         }
1442
1443         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1444         val32 &= 0xffff00ff;
1445         val32 |= (cck[0] << 8);
1446         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1447
1448         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1449         val32 &= 0xff;
1450         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1451         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1452
1453         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1454         val32 &= 0xffffff00;
1455         val32 |= cck[1];
1456         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1457
1458         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1459         val32 &= 0xff;
1460         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1461         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1462
1463         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1464                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1465         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1466                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1467
1468         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1469                          ofdm_a + power_base->reg_0e00);
1470         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1471                          ofdm_b + power_base->reg_0830);
1472
1473         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1474                          ofdm_a + power_base->reg_0e04);
1475         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1476                          ofdm_b + power_base->reg_0834);
1477
1478         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1479                 mcsbase[0] << 16 | mcsbase[0] << 24;
1480         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1481                 mcsbase[1] << 16 | mcsbase[1] << 24;
1482
1483         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1484                          mcs_a + power_base->reg_0e10);
1485         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1486                          mcs_b + power_base->reg_083c);
1487
1488         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1489                          mcs_a + power_base->reg_0e14);
1490         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1491                          mcs_b + power_base->reg_0848);
1492
1493         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1494                          mcs_a + power_base->reg_0e18);
1495         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1496                          mcs_b + power_base->reg_084c);
1497
1498         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1499                          mcs_a + power_base->reg_0e1c);
1500         for (i = 0; i < 3; i++) {
1501                 if (i != 2)
1502                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1503                 else
1504                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1505                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1506         }
1507         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1508                          mcs_b + power_base->reg_0868);
1509         for (i = 0; i < 3; i++) {
1510                 if (i != 2)
1511                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1512                 else
1513                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1514                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1515         }
1516 }
1517
1518 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1519                                   enum nl80211_iftype linktype)
1520 {
1521         u8 val8;
1522
1523         val8 = rtl8xxxu_read8(priv, REG_MSR);
1524         val8 &= ~MSR_LINKTYPE_MASK;
1525
1526         switch (linktype) {
1527         case NL80211_IFTYPE_UNSPECIFIED:
1528                 val8 |= MSR_LINKTYPE_NONE;
1529                 break;
1530         case NL80211_IFTYPE_ADHOC:
1531                 val8 |= MSR_LINKTYPE_ADHOC;
1532                 break;
1533         case NL80211_IFTYPE_STATION:
1534                 val8 |= MSR_LINKTYPE_STATION;
1535                 break;
1536         case NL80211_IFTYPE_AP:
1537                 val8 |= MSR_LINKTYPE_AP;
1538                 break;
1539         default:
1540                 goto out;
1541         }
1542
1543         rtl8xxxu_write8(priv, REG_MSR, val8);
1544 out:
1545         return;
1546 }
1547
1548 static void
1549 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1550 {
1551         u16 val16;
1552
1553         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1554                  RETRY_LIMIT_SHORT_MASK) |
1555                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1556                  RETRY_LIMIT_LONG_MASK);
1557
1558         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1559 }
1560
1561 static void
1562 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1563 {
1564         u16 val16;
1565
1566         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1567                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1568
1569         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1570 }
1571
1572 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1573 {
1574         struct device *dev = &priv->udev->dev;
1575         char *cut;
1576
1577         switch (priv->chip_cut) {
1578         case 0:
1579                 cut = "A";
1580                 break;
1581         case 1:
1582                 cut = "B";
1583                 break;
1584         case 2:
1585                 cut = "C";
1586                 break;
1587         case 3:
1588                 cut = "D";
1589                 break;
1590         case 4:
1591                 cut = "E";
1592                 break;
1593         default:
1594                 cut = "unknown";
1595         }
1596
1597         dev_info(dev,
1598                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1599                  priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1600                  priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1601                  priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1602
1603         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1604 }
1605
1606 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1607 {
1608         struct device *dev = &priv->udev->dev;
1609         u32 val32, bonding;
1610         u16 val16;
1611
1612         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1613         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1614                 SYS_CFG_CHIP_VERSION_SHIFT;
1615         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1616                 dev_info(dev, "Unsupported test chip\n");
1617                 return -ENOTSUPP;
1618         }
1619
1620         if (val32 & SYS_CFG_BT_FUNC) {
1621                 if (priv->chip_cut >= 3) {
1622                         sprintf(priv->chip_name, "8723BU");
1623                         priv->rtl_chip = RTL8723B;
1624                 } else {
1625                         sprintf(priv->chip_name, "8723AU");
1626                         priv->usb_interrupts = 1;
1627                         priv->rtl_chip = RTL8723A;
1628                 }
1629
1630                 priv->rf_paths = 1;
1631                 priv->rx_paths = 1;
1632                 priv->tx_paths = 1;
1633
1634                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1635                 if (val32 & MULTI_WIFI_FUNC_EN)
1636                         priv->has_wifi = 1;
1637                 if (val32 & MULTI_BT_FUNC_EN)
1638                         priv->has_bluetooth = 1;
1639                 if (val32 & MULTI_GPS_FUNC_EN)
1640                         priv->has_gps = 1;
1641                 priv->is_multi_func = 1;
1642         } else if (val32 & SYS_CFG_TYPE_ID) {
1643                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1644                 bonding &= HPON_FSM_BONDING_MASK;
1645                 if (priv->fops->tx_desc_size ==
1646                     sizeof(struct rtl8xxxu_txdesc40)) {
1647                         if (bonding == HPON_FSM_BONDING_1T2R) {
1648                                 sprintf(priv->chip_name, "8191EU");
1649                                 priv->rf_paths = 2;
1650                                 priv->rx_paths = 2;
1651                                 priv->tx_paths = 1;
1652                                 priv->rtl_chip = RTL8191E;
1653                         } else {
1654                                 sprintf(priv->chip_name, "8192EU");
1655                                 priv->rf_paths = 2;
1656                                 priv->rx_paths = 2;
1657                                 priv->tx_paths = 2;
1658                                 priv->rtl_chip = RTL8192E;
1659                         }
1660                 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1661                         sprintf(priv->chip_name, "8191CU");
1662                         priv->rf_paths = 2;
1663                         priv->rx_paths = 2;
1664                         priv->tx_paths = 1;
1665                         priv->usb_interrupts = 1;
1666                         priv->rtl_chip = RTL8191C;
1667                 } else {
1668                         sprintf(priv->chip_name, "8192CU");
1669                         priv->rf_paths = 2;
1670                         priv->rx_paths = 2;
1671                         priv->tx_paths = 2;
1672                         priv->usb_interrupts = 1;
1673                         priv->rtl_chip = RTL8192C;
1674                 }
1675                 priv->has_wifi = 1;
1676         } else {
1677                 sprintf(priv->chip_name, "8188CU");
1678                 priv->rf_paths = 1;
1679                 priv->rx_paths = 1;
1680                 priv->tx_paths = 1;
1681                 priv->rtl_chip = RTL8188C;
1682                 priv->usb_interrupts = 1;
1683                 priv->has_wifi = 1;
1684         }
1685
1686         switch (priv->rtl_chip) {
1687         case RTL8188E:
1688         case RTL8192E:
1689         case RTL8723B:
1690                 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1691                 case SYS_CFG_VENDOR_ID_TSMC:
1692                         sprintf(priv->chip_vendor, "TSMC");
1693                         break;
1694                 case SYS_CFG_VENDOR_ID_SMIC:
1695                         sprintf(priv->chip_vendor, "SMIC");
1696                         priv->vendor_smic = 1;
1697                         break;
1698                 case SYS_CFG_VENDOR_ID_UMC:
1699                         sprintf(priv->chip_vendor, "UMC");
1700                         priv->vendor_umc = 1;
1701                         break;
1702                 default:
1703                         sprintf(priv->chip_vendor, "unknown");
1704                 }
1705                 break;
1706         default:
1707                 if (val32 & SYS_CFG_VENDOR_ID) {
1708                         sprintf(priv->chip_vendor, "UMC");
1709                         priv->vendor_umc = 1;
1710                 } else {
1711                         sprintf(priv->chip_vendor, "TSMC");
1712                 }
1713         }
1714
1715         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1716         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1717
1718         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1719         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1720                 priv->ep_tx_high_queue = 1;
1721                 priv->ep_tx_count++;
1722         }
1723
1724         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1725                 priv->ep_tx_normal_queue = 1;
1726                 priv->ep_tx_count++;
1727         }
1728
1729         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1730                 priv->ep_tx_low_queue = 1;
1731                 priv->ep_tx_count++;
1732         }
1733
1734         /*
1735          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1736          */
1737         if (!priv->ep_tx_count) {
1738                 switch (priv->nr_out_eps) {
1739                 case 4:
1740                 case 3:
1741                         priv->ep_tx_low_queue = 1;
1742                         priv->ep_tx_count++;
1743                 case 2:
1744                         priv->ep_tx_normal_queue = 1;
1745                         priv->ep_tx_count++;
1746                 case 1:
1747                         priv->ep_tx_high_queue = 1;
1748                         priv->ep_tx_count++;
1749                         break;
1750                 default:
1751                         dev_info(dev, "Unsupported USB TX end-points\n");
1752                         return -ENOTSUPP;
1753                 }
1754         }
1755
1756         return 0;
1757 }
1758
1759 static int
1760 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1761 {
1762         int i;
1763         u8 val8;
1764         u32 val32;
1765
1766         /* Write Address */
1767         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1768         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1769         val8 &= 0xfc;
1770         val8 |= (offset >> 8) & 0x03;
1771         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1772
1773         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1774         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1775
1776         /* Poll for data read */
1777         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1778         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1779                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1780                 if (val32 & BIT(31))
1781                         break;
1782         }
1783
1784         if (i == RTL8XXXU_MAX_REG_POLL)
1785                 return -EIO;
1786
1787         udelay(50);
1788         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1789
1790         *data = val32 & 0xff;
1791         return 0;
1792 }
1793
1794 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1795 {
1796         struct device *dev = &priv->udev->dev;
1797         int i, ret = 0;
1798         u8 val8, word_mask, header, extheader;
1799         u16 val16, efuse_addr, offset;
1800         u32 val32;
1801
1802         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1803         if (val16 & EEPROM_ENABLE)
1804                 priv->has_eeprom = 1;
1805         if (val16 & EEPROM_BOOT)
1806                 priv->boot_eeprom = 1;
1807
1808         if (priv->is_multi_func) {
1809                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1810                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1811                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1812         }
1813
1814         dev_dbg(dev, "Booting from %s\n",
1815                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1816
1817         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1818
1819         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1820         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1821         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1822                 val16 |= SYS_ISO_PWC_EV12V;
1823                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1824         }
1825         /*  Reset: 0x0000[28], default valid */
1826         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1827         if (!(val16 & SYS_FUNC_ELDR)) {
1828                 val16 |= SYS_FUNC_ELDR;
1829                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1830         }
1831
1832         /*
1833          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1834          */
1835         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1836         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1837                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1838                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1839         }
1840
1841         /* Default value is 0xff */
1842         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1843
1844         efuse_addr = 0;
1845         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1846                 u16 map_addr;
1847
1848                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1849                 if (ret || header == 0xff)
1850                         goto exit;
1851
1852                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1853                         offset = (header & 0xe0) >> 5;
1854
1855                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1856                                                    &extheader);
1857                         if (ret)
1858                                 goto exit;
1859                         /* All words disabled */
1860                         if ((extheader & 0x0f) == 0x0f)
1861                                 continue;
1862
1863                         offset |= ((extheader & 0xf0) >> 1);
1864                         word_mask = extheader & 0x0f;
1865                 } else {
1866                         offset = (header >> 4) & 0x0f;
1867                         word_mask = header & 0x0f;
1868                 }
1869
1870                 /* Get word enable value from PG header */
1871
1872                 /* We have 8 bits to indicate validity */
1873                 map_addr = offset * 8;
1874                 if (map_addr >= EFUSE_MAP_LEN) {
1875                         dev_warn(dev, "%s: Illegal map_addr (%04x), "
1876                                  "efuse corrupt!\n",
1877                                  __func__, map_addr);
1878                         ret = -EINVAL;
1879                         goto exit;
1880                 }
1881                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1882                         /* Check word enable condition in the section */
1883                         if (word_mask & BIT(i)) {
1884                                 map_addr += 2;
1885                                 continue;
1886                         }
1887
1888                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1889                         if (ret)
1890                                 goto exit;
1891                         priv->efuse_wifi.raw[map_addr++] = val8;
1892
1893                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1894                         if (ret)
1895                                 goto exit;
1896                         priv->efuse_wifi.raw[map_addr++] = val8;
1897                 }
1898         }
1899
1900 exit:
1901         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1902
1903         return ret;
1904 }
1905
1906 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1907 {
1908         u8 val8;
1909         u16 sys_func;
1910
1911         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1912         val8 &= ~BIT(0);
1913         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1914
1915         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1916         sys_func &= ~SYS_FUNC_CPU_ENABLE;
1917         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1918
1919         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1920         val8 |= BIT(0);
1921         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1922
1923         sys_func |= SYS_FUNC_CPU_ENABLE;
1924         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1925 }
1926
1927 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1928 {
1929         struct device *dev = &priv->udev->dev;
1930         int ret = 0, i;
1931         u32 val32;
1932
1933         /* Poll checksum report */
1934         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1935                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1936                 if (val32 & MCU_FW_DL_CSUM_REPORT)
1937                         break;
1938         }
1939
1940         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1941                 dev_warn(dev, "Firmware checksum poll timed out\n");
1942                 ret = -EAGAIN;
1943                 goto exit;
1944         }
1945
1946         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1947         val32 |= MCU_FW_DL_READY;
1948         val32 &= ~MCU_WINT_INIT_READY;
1949         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1950
1951         /*
1952          * Reset the 8051 in order for the firmware to start running,
1953          * otherwise it won't come up on the 8192eu
1954          */
1955         priv->fops->reset_8051(priv);
1956
1957         /* Wait for firmware to become ready */
1958         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1959                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1960                 if (val32 & MCU_WINT_INIT_READY)
1961                         break;
1962
1963                 udelay(100);
1964         }
1965
1966         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1967                 dev_warn(dev, "Firmware failed to start\n");
1968                 ret = -EAGAIN;
1969                 goto exit;
1970         }
1971
1972         /*
1973          * Init H2C command
1974          */
1975         if (priv->rtl_chip == RTL8723B)
1976                 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1977 exit:
1978         return ret;
1979 }
1980
1981 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1982 {
1983         int pages, remainder, i, ret;
1984         u8 val8;
1985         u16 val16;
1986         u32 val32;
1987         u8 *fwptr;
1988
1989         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1990         val8 |= 4;
1991         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
1992
1993         /* 8051 enable */
1994         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1995         val16 |= SYS_FUNC_CPU_ENABLE;
1996         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1997
1998         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
1999         if (val8 & MCU_FW_RAM_SEL) {
2000                 pr_info("do the RAM reset\n");
2001                 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2002                 priv->fops->reset_8051(priv);
2003         }
2004
2005         /* MCU firmware download enable */
2006         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2007         val8 |= MCU_FW_DL_ENABLE;
2008         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2009
2010         /* 8051 reset */
2011         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2012         val32 &= ~BIT(19);
2013         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2014
2015         /* Reset firmware download checksum */
2016         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2017         val8 |= MCU_FW_DL_CSUM_REPORT;
2018         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2019
2020         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2021         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2022
2023         fwptr = priv->fw_data->data;
2024
2025         for (i = 0; i < pages; i++) {
2026                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2027                 val8 |= i;
2028                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2029
2030                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2031                                       fwptr, RTL_FW_PAGE_SIZE);
2032                 if (ret != RTL_FW_PAGE_SIZE) {
2033                         ret = -EAGAIN;
2034                         goto fw_abort;
2035                 }
2036
2037                 fwptr += RTL_FW_PAGE_SIZE;
2038         }
2039
2040         if (remainder) {
2041                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2042                 val8 |= i;
2043                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2044                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2045                                       fwptr, remainder);
2046                 if (ret != remainder) {
2047                         ret = -EAGAIN;
2048                         goto fw_abort;
2049                 }
2050         }
2051
2052         ret = 0;
2053 fw_abort:
2054         /* MCU firmware download disable */
2055         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2056         val16 &= ~MCU_FW_DL_ENABLE;
2057         rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2058
2059         return ret;
2060 }
2061
2062 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2063 {
2064         struct device *dev = &priv->udev->dev;
2065         const struct firmware *fw;
2066         int ret = 0;
2067         u16 signature;
2068
2069         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2070         if (reject_firmware(&fw, fw_name, &priv->udev->dev)) {
2071                 dev_warn(dev, "reject_firmware(%s) failed\n", fw_name);
2072                 ret = -EAGAIN;
2073                 goto exit;
2074         }
2075         if (!fw) {
2076                 dev_warn(dev, "Firmware data not available\n");
2077                 ret = -EINVAL;
2078                 goto exit;
2079         }
2080
2081         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2082         if (!priv->fw_data) {
2083                 ret = -ENOMEM;
2084                 goto exit;
2085         }
2086         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2087
2088         signature = le16_to_cpu(priv->fw_data->signature);
2089         switch (signature & 0xfff0) {
2090         case 0x92e0:
2091         case 0x92c0:
2092         case 0x88c0:
2093         case 0x5300:
2094         case 0x2300:
2095                 break;
2096         default:
2097                 ret = -EINVAL;
2098                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2099                          __func__, signature);
2100         }
2101
2102         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2103                  le16_to_cpu(priv->fw_data->major_version),
2104                  priv->fw_data->minor_version, signature);
2105
2106 exit:
2107         release_firmware(fw);
2108         return ret;
2109 }
2110
2111 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2112 {
2113         u16 val16;
2114         int i = 100;
2115
2116         /* Inform 8051 to perform reset */
2117         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2118
2119         for (i = 100; i > 0; i--) {
2120                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2121
2122                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2123                         dev_dbg(&priv->udev->dev,
2124                                 "%s: Firmware self reset success!\n", __func__);
2125                         break;
2126                 }
2127                 udelay(50);
2128         }
2129
2130         if (!i) {
2131                 /* Force firmware reset */
2132                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2133                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2134                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2135         }
2136 }
2137
2138 static int
2139 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2140 {
2141         struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2142         int i, ret;
2143         u16 reg;
2144         u8 val;
2145
2146         for (i = 0; ; i++) {
2147                 reg = array[i].reg;
2148                 val = array[i].val;
2149
2150                 if (reg == 0xffff && val == 0xff)
2151                         break;
2152
2153                 ret = rtl8xxxu_write8(priv, reg, val);
2154                 if (ret != 1) {
2155                         dev_warn(&priv->udev->dev,
2156                                  "Failed to initialize MAC "
2157                                  "(reg: %04x, val %02x)\n", reg, val);
2158                         return -EAGAIN;
2159                 }
2160         }
2161
2162         if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
2163                 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2164
2165         return 0;
2166 }
2167
2168 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2169                            struct rtl8xxxu_reg32val *array)
2170 {
2171         int i, ret;
2172         u16 reg;
2173         u32 val;
2174
2175         for (i = 0; ; i++) {
2176                 reg = array[i].reg;
2177                 val = array[i].val;
2178
2179                 if (reg == 0xffff && val == 0xffffffff)
2180                         break;
2181
2182                 ret = rtl8xxxu_write32(priv, reg, val);
2183                 if (ret != sizeof(val)) {
2184                         dev_warn(&priv->udev->dev,
2185                                  "Failed to initialize PHY\n");
2186                         return -EAGAIN;
2187                 }
2188                 udelay(1);
2189         }
2190
2191         return 0;
2192 }
2193
2194 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2195 {
2196         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2197         u16 val16;
2198         u32 val32;
2199
2200         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2201         udelay(2);
2202         val8 |= AFE_PLL_320_ENABLE;
2203         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2204         udelay(2);
2205
2206         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2207         udelay(2);
2208
2209         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2210         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2211         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2212
2213         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2214         val32 &= ~AFE_XTAL_RF_GATE;
2215         if (priv->has_bluetooth)
2216                 val32 &= ~AFE_XTAL_BT_GATE;
2217         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2218
2219         /* 6. 0x1f[7:0] = 0x07 */
2220         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2221         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2222
2223         if (priv->hi_pa)
2224                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2225         else if (priv->tx_paths == 2)
2226                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2227         else
2228                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2229
2230         if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2231             priv->vendor_umc && priv->chip_cut == 1)
2232                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2233
2234         if (priv->hi_pa)
2235                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2236         else
2237                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2238
2239         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2240         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2241         ldohci12 = 0x57;
2242         lpldo = 1;
2243         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2244         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2245 }
2246
2247 /*
2248  * Most of this is black magic retrieved from the old rtl8723au driver
2249  */
2250 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2251 {
2252         u8 val8;
2253         u32 val32;
2254
2255         priv->fops->init_phy_bb(priv);
2256
2257         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2258                 /*
2259                  * For 1T2R boards, patch the registers.
2260                  *
2261                  * It looks like 8191/2 1T2R boards use path B for TX
2262                  */
2263                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2264                 val32 &= ~(BIT(0) | BIT(1));
2265                 val32 |= BIT(1);
2266                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2267
2268                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2269                 val32 &= ~0x300033;
2270                 val32 |= 0x200022;
2271                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2272
2273                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2274                 val32 &= ~CCK0_AFE_RX_MASK;
2275                 val32 &= 0x00ffffff;
2276                 val32 |= 0x40000000;
2277                 val32 |= CCK0_AFE_RX_ANT_B;
2278                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2279
2280                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2281                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2282                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2283                           OFDM_RF_PATH_TX_B);
2284                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2285
2286                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2287                 val32 &= ~(BIT(4) | BIT(5));
2288                 val32 |= BIT(4);
2289                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2290
2291                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2292                 val32 &= ~(BIT(27) | BIT(26));
2293                 val32 |= BIT(27);
2294                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2295
2296                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2297                 val32 &= ~(BIT(27) | BIT(26));
2298                 val32 |= BIT(27);
2299                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2300
2301                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2302                 val32 &= ~(BIT(27) | BIT(26));
2303                 val32 |= BIT(27);
2304                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2305
2306                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2307                 val32 &= ~(BIT(27) | BIT(26));
2308                 val32 |= BIT(27);
2309                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2310
2311                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2312                 val32 &= ~(BIT(27) | BIT(26));
2313                 val32 |= BIT(27);
2314                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2315         }
2316
2317         if (priv->has_xtalk) {
2318                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2319
2320                 val8 = priv->xtalk;
2321                 val32 &= 0xff000fff;
2322                 val32 |= ((val8 | (val8 << 6)) << 12);
2323
2324                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2325         }
2326
2327         if (priv->rtl_chip == RTL8192E)
2328                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2329
2330         return 0;
2331 }
2332
2333 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2334                                  struct rtl8xxxu_rfregval *array,
2335                                  enum rtl8xxxu_rfpath path)
2336 {
2337         int i, ret;
2338         u8 reg;
2339         u32 val;
2340
2341         for (i = 0; ; i++) {
2342                 reg = array[i].reg;
2343                 val = array[i].val;
2344
2345                 if (reg == 0xff && val == 0xffffffff)
2346                         break;
2347
2348                 switch (reg) {
2349                 case 0xfe:
2350                         msleep(50);
2351                         continue;
2352                 case 0xfd:
2353                         mdelay(5);
2354                         continue;
2355                 case 0xfc:
2356                         mdelay(1);
2357                         continue;
2358                 case 0xfb:
2359                         udelay(50);
2360                         continue;
2361                 case 0xfa:
2362                         udelay(5);
2363                         continue;
2364                 case 0xf9:
2365                         udelay(1);
2366                         continue;
2367                 }
2368
2369                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2370                 if (ret) {
2371                         dev_warn(&priv->udev->dev,
2372                                  "Failed to initialize RF\n");
2373                         return -EAGAIN;
2374                 }
2375                 udelay(1);
2376         }
2377
2378         return 0;
2379 }
2380
2381 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2382                          struct rtl8xxxu_rfregval *table,
2383                          enum rtl8xxxu_rfpath path)
2384 {
2385         u32 val32;
2386         u16 val16, rfsi_rfenv;
2387         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2388
2389         switch (path) {
2390         case RF_A:
2391                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2392                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2393                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2394                 break;
2395         case RF_B:
2396                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2397                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2398                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2399                 break;
2400         default:
2401                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2402                         __func__, path + 'A');
2403                 return -EINVAL;
2404         }
2405         /* For path B, use XB */
2406         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2407         rfsi_rfenv &= FPGA0_RF_RFENV;
2408
2409         /*
2410          * These two we might be able to optimize into one
2411          */
2412         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2413         val32 |= BIT(20);       /* 0x10 << 16 */
2414         rtl8xxxu_write32(priv, reg_int_oe, val32);
2415         udelay(1);
2416
2417         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2418         val32 |= BIT(4);
2419         rtl8xxxu_write32(priv, reg_int_oe, val32);
2420         udelay(1);
2421
2422         /*
2423          * These two we might be able to optimize into one
2424          */
2425         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2426         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2427         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2428         udelay(1);
2429
2430         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2431         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2432         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2433         udelay(1);
2434
2435         rtl8xxxu_init_rf_regs(priv, table, path);
2436
2437         /* For path B, use XB */
2438         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2439         val16 &= ~FPGA0_RF_RFENV;
2440         val16 |= rfsi_rfenv;
2441         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2442
2443         return 0;
2444 }
2445
2446 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2447 {
2448         int ret = -EBUSY;
2449         int count = 0;
2450         u32 value;
2451
2452         value = LLT_OP_WRITE | address << 8 | data;
2453
2454         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2455
2456         do {
2457                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2458                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2459                         ret = 0;
2460                         break;
2461                 }
2462         } while (count++ < 20);
2463
2464         return ret;
2465 }
2466
2467 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2468 {
2469         int ret;
2470         int i;
2471         u8 last_tx_page;
2472
2473         last_tx_page = priv->fops->total_page_num;
2474
2475         for (i = 0; i < last_tx_page; i++) {
2476                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2477                 if (ret)
2478                         goto exit;
2479         }
2480
2481         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2482         if (ret)
2483                 goto exit;
2484
2485         /* Mark remaining pages as a ring buffer */
2486         for (i = last_tx_page + 1; i < 0xff; i++) {
2487                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2488                 if (ret)
2489                         goto exit;
2490         }
2491
2492         /*  Let last entry point to the start entry of ring buffer */
2493         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2494         if (ret)
2495                 goto exit;
2496
2497 exit:
2498         return ret;
2499 }
2500
2501 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2502 {
2503         u32 val32;
2504         int ret = 0;
2505         int i;
2506
2507         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2508         val32 |= AUTO_LLT_INIT_LLT;
2509         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2510
2511         for (i = 500; i; i--) {
2512                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2513                 if (!(val32 & AUTO_LLT_INIT_LLT))
2514                         break;
2515                 usleep_range(2, 4);
2516         }
2517
2518         if (!i) {
2519                 ret = -EBUSY;
2520                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2521         }
2522
2523         return ret;
2524 }
2525
2526 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2527 {
2528         u16 val16, hi, lo;
2529         u16 hiq, mgq, bkq, beq, viq, voq;
2530         int hip, mgp, bkp, bep, vip, vop;
2531         int ret = 0;
2532
2533         switch (priv->ep_tx_count) {
2534         case 1:
2535                 if (priv->ep_tx_high_queue) {
2536                         hi = TRXDMA_QUEUE_HIGH;
2537                 } else if (priv->ep_tx_low_queue) {
2538                         hi = TRXDMA_QUEUE_LOW;
2539                 } else if (priv->ep_tx_normal_queue) {
2540                         hi = TRXDMA_QUEUE_NORMAL;
2541                 } else {
2542                         hi = 0;
2543                         ret = -EINVAL;
2544                 }
2545
2546                 hiq = hi;
2547                 mgq = hi;
2548                 bkq = hi;
2549                 beq = hi;
2550                 viq = hi;
2551                 voq = hi;
2552
2553                 hip = 0;
2554                 mgp = 0;
2555                 bkp = 0;
2556                 bep = 0;
2557                 vip = 0;
2558                 vop = 0;
2559                 break;
2560         case 2:
2561                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2562                         hi = TRXDMA_QUEUE_HIGH;
2563                         lo = TRXDMA_QUEUE_LOW;
2564                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2565                         hi = TRXDMA_QUEUE_NORMAL;
2566                         lo = TRXDMA_QUEUE_LOW;
2567                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2568                         hi = TRXDMA_QUEUE_HIGH;
2569                         lo = TRXDMA_QUEUE_NORMAL;
2570                 } else {
2571                         ret = -EINVAL;
2572                         hi = 0;
2573                         lo = 0;
2574                 }
2575
2576                 hiq = hi;
2577                 mgq = hi;
2578                 bkq = lo;
2579                 beq = lo;
2580                 viq = hi;
2581                 voq = hi;
2582
2583                 hip = 0;
2584                 mgp = 0;
2585                 bkp = 1;
2586                 bep = 1;
2587                 vip = 0;
2588                 vop = 0;
2589                 break;
2590         case 3:
2591                 beq = TRXDMA_QUEUE_LOW;
2592                 bkq = TRXDMA_QUEUE_LOW;
2593                 viq = TRXDMA_QUEUE_NORMAL;
2594                 voq = TRXDMA_QUEUE_HIGH;
2595                 mgq = TRXDMA_QUEUE_HIGH;
2596                 hiq = TRXDMA_QUEUE_HIGH;
2597
2598                 hip = hiq ^ 3;
2599                 mgp = mgq ^ 3;
2600                 bkp = bkq ^ 3;
2601                 bep = beq ^ 3;
2602                 vip = viq ^ 3;
2603                 vop = viq ^ 3;
2604                 break;
2605         default:
2606                 ret = -EINVAL;
2607         }
2608
2609         /*
2610          * None of the vendor drivers are configuring the beacon
2611          * queue here .... why?
2612          */
2613         if (!ret) {
2614                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2615                 val16 &= 0x7;
2616                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2617                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2618                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2619                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2620                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2621                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2622                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2623
2624                 priv->pipe_out[TXDESC_QUEUE_VO] =
2625                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2626                 priv->pipe_out[TXDESC_QUEUE_VI] =
2627                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2628                 priv->pipe_out[TXDESC_QUEUE_BE] =
2629                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2630                 priv->pipe_out[TXDESC_QUEUE_BK] =
2631                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2632                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2633                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2634                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2635                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2636                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2637                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2638                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2639                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2640         }
2641
2642         return ret;
2643 }
2644
2645 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2646                                 int result[][8], int candidate, bool tx_only)
2647 {
2648         u32 oldval, x, tx0_a, reg;
2649         int y, tx0_c;
2650         u32 val32;
2651
2652         if (!iqk_ok)
2653                 return;
2654
2655         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2656         oldval = val32 >> 22;
2657
2658         x = result[candidate][0];
2659         if ((x & 0x00000200) != 0)
2660                 x = x | 0xfffffc00;
2661         tx0_a = (x * oldval) >> 8;
2662
2663         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2664         val32 &= ~0x3ff;
2665         val32 |= tx0_a;
2666         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2667
2668         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2669         val32 &= ~BIT(31);
2670         if ((x * oldval >> 7) & 0x1)
2671                 val32 |= BIT(31);
2672         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2673
2674         y = result[candidate][1];
2675         if ((y & 0x00000200) != 0)
2676                 y = y | 0xfffffc00;
2677         tx0_c = (y * oldval) >> 8;
2678
2679         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2680         val32 &= ~0xf0000000;
2681         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2682         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2683
2684         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2685         val32 &= ~0x003f0000;
2686         val32 |= ((tx0_c & 0x3f) << 16);
2687         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2688
2689         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2690         val32 &= ~BIT(29);
2691         if ((y * oldval >> 7) & 0x1)
2692                 val32 |= BIT(29);
2693         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2694
2695         if (tx_only) {
2696                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2697                 return;
2698         }
2699
2700         reg = result[candidate][2];
2701
2702         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2703         val32 &= ~0x3ff;
2704         val32 |= (reg & 0x3ff);
2705         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2706
2707         reg = result[candidate][3] & 0x3F;
2708
2709         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2710         val32 &= ~0xfc00;
2711         val32 |= ((reg << 10) & 0xfc00);
2712         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2713
2714         reg = (result[candidate][3] >> 6) & 0xF;
2715
2716         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2717         val32 &= ~0xf0000000;
2718         val32 |= (reg << 28);
2719         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2720 }
2721
2722 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2723                                 int result[][8], int candidate, bool tx_only)
2724 {
2725         u32 oldval, x, tx1_a, reg;
2726         int y, tx1_c;
2727         u32 val32;
2728
2729         if (!iqk_ok)
2730                 return;
2731
2732         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2733         oldval = val32 >> 22;
2734
2735         x = result[candidate][4];
2736         if ((x & 0x00000200) != 0)
2737                 x = x | 0xfffffc00;
2738         tx1_a = (x * oldval) >> 8;
2739
2740         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2741         val32 &= ~0x3ff;
2742         val32 |= tx1_a;
2743         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2744
2745         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2746         val32 &= ~BIT(27);
2747         if ((x * oldval >> 7) & 0x1)
2748                 val32 |= BIT(27);
2749         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2750
2751         y = result[candidate][5];
2752         if ((y & 0x00000200) != 0)
2753                 y = y | 0xfffffc00;
2754         tx1_c = (y * oldval) >> 8;
2755
2756         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2757         val32 &= ~0xf0000000;
2758         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2759         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2760
2761         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2762         val32 &= ~0x003f0000;
2763         val32 |= ((tx1_c & 0x3f) << 16);
2764         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2765
2766         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2767         val32 &= ~BIT(25);
2768         if ((y * oldval >> 7) & 0x1)
2769                 val32 |= BIT(25);
2770         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2771
2772         if (tx_only) {
2773                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2774                 return;
2775         }
2776
2777         reg = result[candidate][6];
2778
2779         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2780         val32 &= ~0x3ff;
2781         val32 |= (reg & 0x3ff);
2782         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2783
2784         reg = result[candidate][7] & 0x3f;
2785
2786         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2787         val32 &= ~0xfc00;
2788         val32 |= ((reg << 10) & 0xfc00);
2789         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2790
2791         reg = (result[candidate][7] >> 6) & 0xf;
2792
2793         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2794         val32 &= ~0x0000f000;
2795         val32 |= (reg << 12);
2796         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2797 }
2798
2799 #define MAX_TOLERANCE           5
2800
2801 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2802                                         int result[][8], int c1, int c2)
2803 {
2804         u32 i, j, diff, simubitmap, bound = 0;
2805         int candidate[2] = {-1, -1};    /* for path A and path B */
2806         bool retval = true;
2807
2808         if (priv->tx_paths > 1)
2809                 bound = 8;
2810         else
2811                 bound = 4;
2812
2813         simubitmap = 0;
2814
2815         for (i = 0; i < bound; i++) {
2816                 diff = (result[c1][i] > result[c2][i]) ?
2817                         (result[c1][i] - result[c2][i]) :
2818                         (result[c2][i] - result[c1][i]);
2819                 if (diff > MAX_TOLERANCE) {
2820                         if ((i == 2 || i == 6) && !simubitmap) {
2821                                 if (result[c1][i] + result[c1][i + 1] == 0)
2822                                         candidate[(i / 4)] = c2;
2823                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2824                                         candidate[(i / 4)] = c1;
2825                                 else
2826                                         simubitmap = simubitmap | (1 << i);
2827                         } else {
2828                                 simubitmap = simubitmap | (1 << i);
2829                         }
2830                 }
2831         }
2832
2833         if (simubitmap == 0) {
2834                 for (i = 0; i < (bound / 4); i++) {
2835                         if (candidate[i] >= 0) {
2836                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2837                                         result[3][j] = result[candidate[i]][j];
2838                                 retval = false;
2839                         }
2840                 }
2841                 return retval;
2842         } else if (!(simubitmap & 0x0f)) {
2843                 /* path A OK */
2844                 for (i = 0; i < 4; i++)
2845                         result[3][i] = result[c1][i];
2846         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2847                 /* path B OK */
2848                 for (i = 4; i < 8; i++)
2849                         result[3][i] = result[c1][i];
2850         }
2851
2852         return false;
2853 }
2854
2855 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2856                                       int result[][8], int c1, int c2)
2857 {
2858         u32 i, j, diff, simubitmap, bound = 0;
2859         int candidate[2] = {-1, -1};    /* for path A and path B */
2860         int tmp1, tmp2;
2861         bool retval = true;
2862
2863         if (priv->tx_paths > 1)
2864                 bound = 8;
2865         else
2866                 bound = 4;
2867
2868         simubitmap = 0;
2869
2870         for (i = 0; i < bound; i++) {
2871                 if (i & 1) {
2872                         if ((result[c1][i] & 0x00000200))
2873                                 tmp1 = result[c1][i] | 0xfffffc00;
2874                         else
2875                                 tmp1 = result[c1][i];
2876
2877                         if ((result[c2][i]& 0x00000200))
2878                                 tmp2 = result[c2][i] | 0xfffffc00;
2879                         else
2880                                 tmp2 = result[c2][i];
2881                 } else {
2882                         tmp1 = result[c1][i];
2883                         tmp2 = result[c2][i];
2884                 }
2885
2886                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2887
2888                 if (diff > MAX_TOLERANCE) {
2889                         if ((i == 2 || i == 6) && !simubitmap) {
2890                                 if (result[c1][i] + result[c1][i + 1] == 0)
2891                                         candidate[(i / 4)] = c2;
2892                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2893                                         candidate[(i / 4)] = c1;
2894                                 else
2895                                         simubitmap = simubitmap | (1 << i);
2896                         } else {
2897                                 simubitmap = simubitmap | (1 << i);
2898                         }
2899                 }
2900         }
2901
2902         if (simubitmap == 0) {
2903                 for (i = 0; i < (bound / 4); i++) {
2904                         if (candidate[i] >= 0) {
2905                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2906                                         result[3][j] = result[candidate[i]][j];
2907                                 retval = false;
2908                         }
2909                 }
2910                 return retval;
2911         } else {
2912                 if (!(simubitmap & 0x03)) {
2913                         /* path A TX OK */
2914                         for (i = 0; i < 2; i++)
2915                                 result[3][i] = result[c1][i];
2916                 }
2917
2918                 if (!(simubitmap & 0x0c)) {
2919                         /* path A RX OK */
2920                         for (i = 2; i < 4; i++)
2921                                 result[3][i] = result[c1][i];
2922                 }
2923
2924                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2925                         /* path B RX OK */
2926                         for (i = 4; i < 6; i++)
2927                                 result[3][i] = result[c1][i];
2928                 }
2929
2930                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2931                         /* path B RX OK */
2932                         for (i = 6; i < 8; i++)
2933                                 result[3][i] = result[c1][i];
2934                 }
2935         }
2936
2937         return false;
2938 }
2939
2940 void
2941 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2942 {
2943         int i;
2944
2945         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2946                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2947
2948         backup[i] = rtl8xxxu_read32(priv, reg[i]);
2949 }
2950
2951 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2952                                const u32 *reg, u32 *backup)
2953 {
2954         int i;
2955
2956         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2957                 rtl8xxxu_write8(priv, reg[i], backup[i]);
2958
2959         rtl8xxxu_write32(priv, reg[i], backup[i]);
2960 }
2961
2962 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2963                         u32 *backup, int count)
2964 {
2965         int i;
2966
2967         for (i = 0; i < count; i++)
2968                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2969 }
2970
2971 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2972                            u32 *backup, int count)
2973 {
2974         int i;
2975
2976         for (i = 0; i < count; i++)
2977                 rtl8xxxu_write32(priv, regs[i], backup[i]);
2978 }
2979
2980
2981 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2982                            bool path_a_on)
2983 {
2984         u32 path_on;
2985         int i;
2986
2987         if (priv->tx_paths == 1) {
2988                 path_on = priv->fops->adda_1t_path_on;
2989                 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
2990         } else {
2991                 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
2992                         priv->fops->adda_2t_path_on_b;
2993
2994                 rtl8xxxu_write32(priv, regs[0], path_on);
2995         }
2996
2997         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
2998                 rtl8xxxu_write32(priv, regs[i], path_on);
2999 }
3000
3001 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3002                               const u32 *regs, u32 *backup)
3003 {
3004         int i = 0;
3005
3006         rtl8xxxu_write8(priv, regs[i], 0x3f);
3007
3008         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3009                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3010
3011         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3012 }
3013
3014 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3015 {
3016         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3017         int result = 0;
3018
3019         /* path-A IQK setting */
3020         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3021         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3022         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3023
3024         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3025                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3026                 0x28160502;
3027         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3028
3029         /* path-B IQK setting */
3030         if (priv->rf_paths > 1) {
3031                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3032                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3033                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3034                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3035         }
3036
3037         /* LO calibration setting */
3038         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3039
3040         /* One shot, path A LOK & IQK */
3041         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3042         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3043
3044         mdelay(1);
3045
3046         /* Check failed */
3047         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3048         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3049         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3050         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3051
3052         if (!(reg_eac & BIT(28)) &&
3053             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3054             ((reg_e9c & 0x03ff0000) != 0x00420000))
3055                 result |= 0x01;
3056         else    /* If TX not OK, ignore RX */
3057                 goto out;
3058
3059         /* If TX is OK, check whether RX is OK */
3060         if (!(reg_eac & BIT(27)) &&
3061             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3062             ((reg_eac & 0x03ff0000) != 0x00360000))
3063                 result |= 0x02;
3064         else
3065                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3066                          __func__);
3067 out:
3068         return result;
3069 }
3070
3071 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3072 {
3073         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3074         int result = 0;
3075
3076         /* One shot, path B LOK & IQK */
3077         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3078         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3079
3080         mdelay(1);
3081
3082         /* Check failed */
3083         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3084         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3085         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3086         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3087         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3088
3089         if (!(reg_eac & BIT(31)) &&
3090             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3091             ((reg_ebc & 0x03ff0000) != 0x00420000))
3092                 result |= 0x01;
3093         else
3094                 goto out;
3095
3096         if (!(reg_eac & BIT(30)) &&
3097             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3098             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3099                 result |= 0x02;
3100         else
3101                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3102                          __func__);
3103 out:
3104         return result;
3105 }
3106
3107 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3108                                      int result[][8], int t)
3109 {
3110         struct device *dev = &priv->udev->dev;
3111         u32 i, val32;
3112         int path_a_ok, path_b_ok;
3113         int retry = 2;
3114         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3115                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3116                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3117                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3118                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3119                 REG_TX_TO_TX, REG_RX_CCK,
3120                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3121                 REG_RX_TO_RX, REG_STANDBY,
3122                 REG_SLEEP, REG_PMPD_ANAEN
3123         };
3124         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3125                 REG_TXPAUSE, REG_BEACON_CTRL,
3126                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3127         };
3128         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3129                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3130                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3131                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3132                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3133         };
3134
3135         /*
3136          * Note: IQ calibration must be performed after loading
3137          *       PHY_REG.txt , and radio_a, radio_b.txt
3138          */
3139
3140         if (t == 0) {
3141                 /* Save ADDA parameters, turn Path A ADDA on */
3142                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3143                                    RTL8XXXU_ADDA_REGS);
3144                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3145                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3146                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3147         }
3148
3149         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3150
3151         if (t == 0) {
3152                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3153                 if (val32 & FPGA0_HSSI_PARM1_PI)
3154                         priv->pi_enabled = 1;
3155         }
3156
3157         if (!priv->pi_enabled) {
3158                 /* Switch BB to PI mode to do IQ Calibration. */
3159                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3160                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3161         }
3162
3163         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3164         val32 &= ~FPGA_RF_MODE_CCK;
3165         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3166
3167         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3168         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3169         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3170
3171         if (!priv->no_pape) {
3172                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3173                 val32 |= (FPGA0_RF_PAPE |
3174                           (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3175                 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3176         }
3177
3178         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3179         val32 &= ~BIT(10);
3180         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3181         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3182         val32 &= ~BIT(10);
3183         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3184
3185         if (priv->tx_paths > 1) {
3186                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3187                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3188         }
3189
3190         /* MAC settings */
3191         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3192
3193         /* Page B init */
3194         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3195
3196         if (priv->tx_paths > 1)
3197                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3198
3199         /* IQ calibration setting */
3200         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3201         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3202         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3203
3204         for (i = 0; i < retry; i++) {
3205                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3206                 if (path_a_ok == 0x03) {
3207                         val32 = rtl8xxxu_read32(priv,
3208                                                 REG_TX_POWER_BEFORE_IQK_A);
3209                         result[t][0] = (val32 >> 16) & 0x3ff;
3210                         val32 = rtl8xxxu_read32(priv,
3211                                                 REG_TX_POWER_AFTER_IQK_A);
3212                         result[t][1] = (val32 >> 16) & 0x3ff;
3213                         val32 = rtl8xxxu_read32(priv,
3214                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3215                         result[t][2] = (val32 >> 16) & 0x3ff;
3216                         val32 = rtl8xxxu_read32(priv,
3217                                                 REG_RX_POWER_AFTER_IQK_A_2);
3218                         result[t][3] = (val32 >> 16) & 0x3ff;
3219                         break;
3220                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3221                         /* TX IQK OK */
3222                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3223                                 __func__);
3224
3225                         val32 = rtl8xxxu_read32(priv,
3226                                                 REG_TX_POWER_BEFORE_IQK_A);
3227                         result[t][0] = (val32 >> 16) & 0x3ff;
3228                         val32 = rtl8xxxu_read32(priv,
3229                                                 REG_TX_POWER_AFTER_IQK_A);
3230                         result[t][1] = (val32 >> 16) & 0x3ff;
3231                 }
3232         }
3233
3234         if (!path_a_ok)
3235                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3236
3237         if (priv->tx_paths > 1) {
3238                 /*
3239                  * Path A into standby
3240                  */
3241                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3242                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3243                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3244
3245                 /* Turn Path B ADDA on */
3246                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3247
3248                 for (i = 0; i < retry; i++) {
3249                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3250                         if (path_b_ok == 0x03) {
3251                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3252                                 result[t][4] = (val32 >> 16) & 0x3ff;
3253                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3254                                 result[t][5] = (val32 >> 16) & 0x3ff;
3255                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3256                                 result[t][6] = (val32 >> 16) & 0x3ff;
3257                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3258                                 result[t][7] = (val32 >> 16) & 0x3ff;
3259                                 break;
3260                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3261                                 /* TX IQK OK */
3262                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3263                                 result[t][4] = (val32 >> 16) & 0x3ff;
3264                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3265                                 result[t][5] = (val32 >> 16) & 0x3ff;
3266                         }
3267                 }
3268
3269                 if (!path_b_ok)
3270                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3271         }
3272
3273         /* Back to BB mode, load original value */
3274         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3275
3276         if (t) {
3277                 if (!priv->pi_enabled) {
3278                         /*
3279                          * Switch back BB to SI mode after finishing
3280                          * IQ Calibration
3281                          */
3282                         val32 = 0x01000000;
3283                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3284                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3285                 }
3286
3287                 /* Reload ADDA power saving parameters */
3288                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3289                                       RTL8XXXU_ADDA_REGS);
3290
3291                 /* Reload MAC parameters */
3292                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3293
3294                 /* Reload BB parameters */
3295                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3296                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3297
3298                 /* Restore RX initial gain */
3299                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3300
3301                 if (priv->tx_paths > 1) {
3302                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3303                                          0x00032ed3);
3304                 }
3305
3306                 /* Load 0xe30 IQC default value */
3307                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3308                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3309         }
3310 }
3311
3312 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3313 {
3314         struct h2c_cmd h2c;
3315
3316         memset(&h2c, 0, sizeof(struct h2c_cmd));
3317         h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3318         h2c.bt_wlan_calibration.data = start;
3319
3320         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3321 }
3322
3323 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3324 {
3325         struct device *dev = &priv->udev->dev;
3326         int result[4][8];       /* last is final result */
3327         int i, candidate;
3328         bool path_a_ok, path_b_ok;
3329         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3330         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3331         s32 reg_tmp = 0;
3332         bool simu;
3333
3334         memset(result, 0, sizeof(result));
3335         candidate = -1;
3336
3337         path_a_ok = false;
3338         path_b_ok = false;
3339
3340         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3341
3342         for (i = 0; i < 3; i++) {
3343                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3344
3345                 if (i == 1) {
3346                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3347                         if (simu) {
3348                                 candidate = 0;
3349                                 break;
3350                         }
3351                 }
3352
3353                 if (i == 2) {
3354                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3355                         if (simu) {
3356                                 candidate = 0;
3357                                 break;
3358                         }
3359
3360                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3361                         if (simu) {
3362                                 candidate = 1;
3363                         } else {
3364                                 for (i = 0; i < 8; i++)
3365                                         reg_tmp += result[3][i];
3366
3367                                 if (reg_tmp)
3368                                         candidate = 3;
3369                                 else
3370                                         candidate = -1;
3371                         }
3372                 }
3373         }
3374
3375         for (i = 0; i < 4; i++) {
3376                 reg_e94 = result[i][0];
3377                 reg_e9c = result[i][1];
3378                 reg_ea4 = result[i][2];
3379                 reg_eac = result[i][3];
3380                 reg_eb4 = result[i][4];
3381                 reg_ebc = result[i][5];
3382                 reg_ec4 = result[i][6];
3383                 reg_ecc = result[i][7];
3384         }
3385
3386         if (candidate >= 0) {
3387                 reg_e94 = result[candidate][0];
3388                 priv->rege94 =  reg_e94;
3389                 reg_e9c = result[candidate][1];
3390                 priv->rege9c = reg_e9c;
3391                 reg_ea4 = result[candidate][2];
3392                 reg_eac = result[candidate][3];
3393                 reg_eb4 = result[candidate][4];
3394                 priv->regeb4 = reg_eb4;
3395                 reg_ebc = result[candidate][5];
3396                 priv->regebc = reg_ebc;
3397                 reg_ec4 = result[candidate][6];
3398                 reg_ecc = result[candidate][7];
3399                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3400                 dev_dbg(dev,
3401                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3402                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3403                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3404                 path_a_ok = true;
3405                 path_b_ok = true;
3406         } else {
3407                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3408                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3409         }
3410
3411         if (reg_e94 && candidate >= 0)
3412                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3413                                            candidate, (reg_ea4 == 0));
3414
3415         if (priv->tx_paths > 1 && reg_eb4)
3416                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3417                                            candidate, (reg_ec4 == 0));
3418
3419         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3420                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3421 }
3422
3423 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3424 {
3425         u32 val32;
3426         u32 rf_amode, rf_bmode = 0, lstf;
3427
3428         /* Check continuous TX and Packet TX */
3429         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3430
3431         if (lstf & OFDM_LSTF_MASK) {
3432                 /* Disable all continuous TX */
3433                 val32 = lstf & ~OFDM_LSTF_MASK;
3434                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3435
3436                 /* Read original RF mode Path A */
3437                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3438
3439                 /* Set RF mode to standby Path A */
3440                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3441                                      (rf_amode & 0x8ffff) | 0x10000);
3442
3443                 /* Path-B */
3444                 if (priv->tx_paths > 1) {
3445                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3446                                                        RF6052_REG_AC);
3447
3448                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3449                                              (rf_bmode & 0x8ffff) | 0x10000);
3450                 }
3451         } else {
3452                 /*  Deal with Packet TX case */
3453                 /*  block all queues */
3454                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3455         }
3456
3457         /* Start LC calibration */
3458         if (priv->fops->has_s0s1)
3459                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3460         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3461         val32 |= 0x08000;
3462         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3463
3464         msleep(100);
3465
3466         if (priv->fops->has_s0s1)
3467                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3468
3469         /* Restore original parameters */
3470         if (lstf & OFDM_LSTF_MASK) {
3471                 /* Path-A */
3472                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3473                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3474
3475                 /* Path-B */
3476                 if (priv->tx_paths > 1)
3477                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3478                                              rf_bmode);
3479         } else /*  Deal with Packet TX case */
3480                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3481 }
3482
3483 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3484 {
3485         int i;
3486         u16 reg;
3487
3488         reg = REG_MACID;
3489
3490         for (i = 0; i < ETH_ALEN; i++)
3491                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3492
3493         return 0;
3494 }
3495
3496 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3497 {
3498         int i;
3499         u16 reg;
3500
3501         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3502
3503         reg = REG_BSSID;
3504
3505         for (i = 0; i < ETH_ALEN; i++)
3506                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3507
3508         return 0;
3509 }
3510
3511 static void
3512 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3513 {
3514         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3515         u8 max_agg = 0xf;
3516         int i;
3517
3518         ampdu_factor = 1 << (ampdu_factor + 2);
3519         if (ampdu_factor > max_agg)
3520                 ampdu_factor = max_agg;
3521
3522         for (i = 0; i < 4; i++) {
3523                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3524                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3525
3526                 if ((vals[i] & 0x0f) > ampdu_factor)
3527                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3528
3529                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3530         }
3531 }
3532
3533 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3534 {
3535         u8 val8;
3536
3537         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3538         val8 &= 0xf8;
3539         val8 |= density;
3540         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3541 }
3542
3543 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3544 {
3545         u8 val8;
3546         int count, ret = 0;
3547
3548         /* Start of rtl8723AU_card_enable_flow */
3549         /* Act to Cardemu sequence*/
3550         /* Turn off RF */
3551         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3552
3553         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3554         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3555         val8 &= ~LEDCFG2_DPDT_SELECT;
3556         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3557
3558         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3559         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3560         val8 |= BIT(1);
3561         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3562
3563         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3564                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3565                 if ((val8 & BIT(1)) == 0)
3566                         break;
3567                 udelay(10);
3568         }
3569
3570         if (!count) {
3571                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3572                          __func__);
3573                 ret = -EBUSY;
3574                 goto exit;
3575         }
3576
3577         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3578         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3579         val8 |= SYS_ISO_ANALOG_IPS;
3580         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3581
3582         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3583         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3584         val8 &= ~LDOA15_ENABLE;
3585         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3586
3587 exit:
3588         return ret;
3589 }
3590
3591 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3592 {
3593         u8 val8;
3594         u8 val32;
3595         int count, ret = 0;
3596
3597         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3598
3599         /*
3600          * Poll - wait for RX packet to complete
3601          */
3602         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3603                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3604                 if (!val32)
3605                         break;
3606                 udelay(10);
3607         }
3608
3609         if (!count) {
3610                 dev_warn(&priv->udev->dev,
3611                          "%s: RX poll timed out (0x05f8)\n", __func__);
3612                 ret = -EBUSY;
3613                 goto exit;
3614         }
3615
3616         /* Disable CCK and OFDM, clock gated */
3617         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3618         val8 &= ~SYS_FUNC_BBRSTB;
3619         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3620
3621         udelay(2);
3622
3623         /* Reset baseband */
3624         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3625         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3626         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3627
3628         /* Reset MAC TRX */
3629         val8 = rtl8xxxu_read8(priv, REG_CR);
3630         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3631         rtl8xxxu_write8(priv, REG_CR, val8);
3632
3633         /* Reset MAC TRX */
3634         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3635         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3636         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3637
3638         /* Respond TX OK to scheduler */
3639         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3640         val8 |= DUAL_TSF_TX_OK;
3641         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3642
3643 exit:
3644         return ret;
3645 }
3646
3647 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3648 {
3649         u8 val8;
3650
3651         /* Clear suspend enable and power down enable*/
3652         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3653         val8 &= ~(BIT(3) | BIT(7));
3654         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3655
3656         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3657         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3658         val8 &= ~BIT(0);
3659         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3660
3661         /* 0x04[12:11] = 11 enable WL suspend*/
3662         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3663         val8 &= ~(BIT(3) | BIT(4));
3664         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3665 }
3666
3667 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3668 {
3669         u8 val8;
3670
3671         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3672         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3673
3674         /* 0x04[12:11] = 01 enable WL suspend */
3675         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3676         val8 &= ~BIT(4);
3677         val8 |= BIT(3);
3678         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3679
3680         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3681         val8 |= BIT(7);
3682         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3683
3684         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3685         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3686         val8 |= BIT(0);
3687         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3688
3689         return 0;
3690 }
3691
3692 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3693 {
3694         struct device *dev = &priv->udev->dev;
3695         u32 val32;
3696         int retry, retval;
3697
3698         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3699
3700         val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3701         val32 |= RXPKT_NUM_RW_RELEASE_EN;
3702         rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3703
3704         retry = 100;
3705         retval = -EBUSY;
3706
3707         do {
3708                 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3709                 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3710                         retval = 0;
3711                         break;
3712                 }
3713         } while (retry--);
3714
3715         rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3716         rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3717         mdelay(2);
3718
3719         if (!retry)
3720                 dev_warn(dev, "Failed to flush FIFO\n");
3721
3722         return retval;
3723 }
3724
3725 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3726 {
3727         /* Fix USB interface interference issue */
3728         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3729         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3730         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3731         /*
3732          * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3733          * 8 and 5, for which I have found no documentation.
3734          */
3735         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3736
3737         /*
3738          * Solve too many protocol error on USB bus.
3739          * Can't do this for 8188/8192 UMC A cut parts
3740          */
3741         if (!(!priv->chip_cut && priv->vendor_umc)) {
3742                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3743                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3744                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3745
3746                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3747                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3748                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3749
3750                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3751                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3752                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3753
3754                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3755                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3756                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3757         }
3758 }
3759
3760 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3761 {
3762         u32 val32;
3763
3764         val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3765         val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3766         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3767 }
3768
3769 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3770 {
3771         u8 val8;
3772         u16 val16;
3773         u32 val32;
3774
3775         /*
3776          * Workaround for 8188RU LNA power leakage problem.
3777          */
3778         if (priv->rtl_chip == RTL8188R) {
3779                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3780                 val32 |= BIT(1);
3781                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3782         }
3783
3784         rtl8xxxu_flush_fifo(priv);
3785
3786         rtl8xxxu_active_to_lps(priv);
3787
3788         /* Turn off RF */
3789         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3790
3791         /* Reset Firmware if running in RAM */
3792         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3793                 rtl8xxxu_firmware_self_reset(priv);
3794
3795         /* Reset MCU */
3796         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3797         val16 &= ~SYS_FUNC_CPU_ENABLE;
3798         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3799
3800         /* Reset MCU ready status */
3801         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3802
3803         rtl8xxxu_active_to_emu(priv);
3804         rtl8xxxu_emu_to_disabled(priv);
3805
3806         /* Reset MCU IO Wrapper */
3807         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3808         val8 &= ~BIT(0);
3809         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3810
3811         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3812         val8 |= BIT(0);
3813         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3814
3815         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3816         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3817 }
3818
3819 #ifdef NEED_PS_TDMA
3820 static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3821                                   u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3822 {
3823         struct h2c_cmd h2c;
3824
3825         memset(&h2c, 0, sizeof(struct h2c_cmd));
3826         h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3827         h2c.b_type_dma.data1 = arg1;
3828         h2c.b_type_dma.data2 = arg2;
3829         h2c.b_type_dma.data3 = arg3;
3830         h2c.b_type_dma.data4 = arg4;
3831         h2c.b_type_dma.data5 = arg5;
3832         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3833 }
3834 #endif
3835
3836 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3837 {
3838         u32 val32;
3839
3840         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3841         val32 &= ~(BIT(22) | BIT(23));
3842         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3843 }
3844
3845 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3846 {
3847         struct rtl8xxxu_fileops *fops = priv->fops;
3848         u32 hq, lq, nq, eq, pubq;
3849         u32 val32;
3850
3851         hq = 0;
3852         lq = 0;
3853         nq = 0;
3854         eq = 0;
3855         pubq = 0;
3856
3857         if (priv->ep_tx_high_queue)
3858                 hq = fops->page_num_hi;
3859         if (priv->ep_tx_low_queue)
3860                 lq = fops->page_num_lo;
3861         if (priv->ep_tx_normal_queue)
3862                 nq = fops->page_num_norm;
3863
3864         val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3865         rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3866
3867         pubq = fops->total_page_num - hq - lq - nq - 1;
3868
3869         val32 = RQPN_LOAD;
3870         val32 |= (hq << RQPN_HI_PQ_SHIFT);
3871         val32 |= (lq << RQPN_LO_PQ_SHIFT);
3872         val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3873
3874         rtl8xxxu_write32(priv, REG_RQPN, val32);
3875 }
3876
3877 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3878 {
3879         struct rtl8xxxu_priv *priv = hw->priv;
3880         struct device *dev = &priv->udev->dev;
3881         struct rtl8xxxu_fileops *fops = priv->fops;
3882         bool macpower;
3883         int ret;
3884         u8 val8;
3885         u16 val16;
3886         u32 val32;
3887
3888         /* Check if MAC is already powered on */
3889         val8 = rtl8xxxu_read8(priv, REG_CR);
3890
3891         /*
3892          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3893          * initialized. First MAC returns 0xea, second MAC returns 0x00
3894          */
3895         if (val8 == 0xea)
3896                 macpower = false;
3897         else
3898                 macpower = true;
3899
3900         if (fops->needs_full_init)
3901                 macpower = false;
3902
3903         ret = fops->power_on(priv);
3904         if (ret < 0) {
3905                 dev_warn(dev, "%s: Failed power on\n", __func__);
3906                 goto exit;
3907         }
3908
3909         if (!macpower)
3910                 rtl8xxxu_init_queue_reserved_page(priv);
3911
3912         ret = rtl8xxxu_init_queue_priority(priv);
3913         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3914         if (ret)
3915                 goto exit;
3916
3917         /*
3918          * Set RX page boundary
3919          */
3920         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
3921
3922         ret = rtl8xxxu_download_firmware(priv);
3923         dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
3924         if (ret)
3925                 goto exit;
3926         ret = rtl8xxxu_start_firmware(priv);
3927         dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
3928         if (ret)
3929                 goto exit;
3930
3931         if (fops->phy_init_antenna_selection)
3932                 fops->phy_init_antenna_selection(priv);
3933
3934         ret = rtl8xxxu_init_mac(priv);
3935
3936         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3937         if (ret)
3938                 goto exit;
3939
3940         ret = rtl8xxxu_init_phy_bb(priv);
3941         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3942         if (ret)
3943                 goto exit;
3944
3945         ret = fops->init_phy_rf(priv);
3946         if (ret)
3947                 goto exit;
3948
3949         /* RFSW Control - clear bit 14 ?? */
3950         if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
3951                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
3952
3953         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
3954                 FPGA0_RF_ANTSWB |
3955                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3956         if (!priv->no_pape) {
3957                 val32 |= (FPGA0_RF_PAPE |
3958                           (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3959         }
3960         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3961
3962         /* 0x860[6:5]= 00 - why? - this sets antenna B */
3963         if (priv->rtl_chip != RTL8192E)
3964                 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3965
3966         if (!macpower) {
3967                 /*
3968                  * Set TX buffer boundary
3969                  */
3970                 val8 = fops->total_page_num + 1;
3971
3972                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3973                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3974                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3975                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3976                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3977         }
3978
3979         /*
3980          * The vendor drivers set PBP for all devices, except 8192e.
3981          * There is no explanation for this in any of the sources.
3982          */
3983         val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3984                 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
3985         if (priv->rtl_chip != RTL8192E)
3986                 rtl8xxxu_write8(priv, REG_PBP, val8);
3987
3988         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3989         if (!macpower) {
3990                 ret = fops->llt_init(priv);
3991                 if (ret) {
3992                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
3993                         goto exit;
3994                 }
3995
3996                 /*
3997                  * Chip specific quirks
3998                  */
3999                 fops->usb_quirks(priv);
4000
4001                 /*
4002                  * Enable TX report and TX report timer for 8723bu/8188eu/...
4003                  */
4004                 if (fops->has_tx_report) {
4005                         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4006                         val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4007                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4008                         /* Set MAX RPT MACID */
4009                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4010                         /* TX report Timer. Unit: 32us */
4011                         rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4012
4013                         /* tmp ps ? */
4014                         val8 = rtl8xxxu_read8(priv, 0xa3);
4015                         val8 &= 0xf8;
4016                         rtl8xxxu_write8(priv, 0xa3, val8);
4017                 }
4018         }
4019
4020         /*
4021          * Unit in 8 bytes, not obvious what it is used for
4022          */
4023         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4024
4025         if (priv->rtl_chip == RTL8192E) {
4026                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4027                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4028         } else {
4029                 /*
4030                  * Enable all interrupts - not obvious USB needs to do this
4031                  */
4032                 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4033                 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4034         }
4035
4036         rtl8xxxu_set_mac(priv);
4037         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4038
4039         /*
4040          * Configure initial WMAC settings
4041          */
4042         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4043                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4044                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4045         rtl8xxxu_write32(priv, REG_RCR, val32);
4046
4047         /*
4048          * Accept all multicast
4049          */
4050         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4051         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4052
4053         /*
4054          * Init adaptive controls
4055          */
4056         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4057         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4058         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4059         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4060
4061         /* CCK = 0x0a, OFDM = 0x10 */
4062         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4063         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4064         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4065
4066         /*
4067          * Init EDCA
4068          */
4069         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4070
4071         /* Set CCK SIFS */
4072         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4073
4074         /* Set OFDM SIFS */
4075         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4076
4077         /* TXOP */
4078         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4079         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4080         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4081         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4082
4083         /* Set data auto rate fallback retry count */
4084         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4085         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4086         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4087         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4088
4089         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4090         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4091         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4092
4093         /*  Set ACK timeout */
4094         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4095
4096         /*
4097          * Initialize beacon parameters
4098          */
4099         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4100         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4101         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4102         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4103         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4104         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4105
4106         /*
4107          * Initialize burst parameters
4108          */
4109         if (priv->rtl_chip == RTL8723B) {
4110                 /*
4111                  * For USB high speed set 512B packets
4112                  */
4113                 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4114                 val8 &= ~(BIT(4) | BIT(5));
4115                 val8 |= BIT(4);
4116                 val8 |= BIT(1) | BIT(2) | BIT(3);
4117                 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4118
4119                 /*
4120                  * For USB high speed set 512B packets
4121                  */
4122                 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4123                 val8 |= BIT(7);
4124                 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4125
4126                 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4127                 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4128                 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4129                 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4130                 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4131                 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4132                 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4133
4134                 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4135                 val8 |= BIT(5) | BIT(6);
4136                 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4137         }
4138
4139         if (fops->init_aggregation)
4140                 fops->init_aggregation(priv);
4141
4142         /*
4143          * Enable CCK and OFDM block
4144          */
4145         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4146         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4147         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4148
4149         /*
4150          * Invalidate all CAM entries - bit 30 is undocumented
4151          */
4152         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4153
4154         /*
4155          * Start out with default power levels for channel 6, 20MHz
4156          */
4157         fops->set_tx_power(priv, 1, false);
4158
4159         /* Let the 8051 take control of antenna setting */
4160         if (priv->rtl_chip != RTL8192E) {
4161                 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4162                 val8 |= LEDCFG2_DPDT_SELECT;
4163                 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4164         }
4165
4166         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4167
4168         /* Disable BAR - not sure if this has any effect on USB */
4169         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4170
4171         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4172
4173         if (fops->init_statistics)
4174                 fops->init_statistics(priv);
4175
4176         if (priv->rtl_chip == RTL8192E) {
4177                 /*
4178                  * 0x4c6[3] 1: RTS BW = Data BW
4179                  * 0: RTS BW depends on CCA / secondary CCA result.
4180                  */
4181                 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4182                 val8 &= ~BIT(3);
4183                 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4184                 /*
4185                  * Reset USB mode switch setting
4186                  */
4187                 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4188         }
4189
4190         rtl8723a_phy_lc_calibrate(priv);
4191
4192         fops->phy_iq_calibrate(priv);
4193
4194         /*
4195          * This should enable thermal meter
4196          */
4197         if (fops->gen2_thermal_meter)
4198                 rtl8xxxu_write_rfreg(priv,
4199                                      RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4200         else
4201                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4202
4203         /* Set NAV_UPPER to 30000us */
4204         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4205         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4206
4207         if (priv->rtl_chip == RTL8723A) {
4208                 /*
4209                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4210                  * but we need to find root cause.
4211                  * This is 8723au only.
4212                  */
4213                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4214                 if ((val32 & 0xff000000) != 0x83000000) {
4215                         val32 |= FPGA_RF_MODE_CCK;
4216                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4217                 }
4218         } else if (priv->rtl_chip == RTL8192E) {
4219                 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4220         }
4221
4222         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4223         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4224         /* ack for xmit mgmt frames. */
4225         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4226
4227         if (priv->rtl_chip == RTL8192E) {
4228                 /*
4229                  * Fix LDPC rx hang issue.
4230                  */
4231                 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4232                 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4233                 val32 &= 0xfff00fff;
4234                 val32 |= 0x0007e000;
4235                 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4236         }
4237 exit:
4238         return ret;
4239 }
4240
4241 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4242                                struct ieee80211_key_conf *key, const u8 *mac)
4243 {
4244         u32 cmd, val32, addr, ctrl;
4245         int j, i, tmp_debug;
4246
4247         tmp_debug = rtl8xxxu_debug;
4248         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4249                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4250
4251         /*
4252          * This is a bit of a hack - the lower bits of the cipher
4253          * suite selector happens to match the cipher index in the CAM
4254          */
4255         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4256         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4257
4258         for (j = 5; j >= 0; j--) {
4259                 switch (j) {
4260                 case 0:
4261                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4262                         break;
4263                 case 1:
4264                         val32 = mac[2] | (mac[3] << 8) |
4265                                 (mac[4] << 16) | (mac[5] << 24);
4266                         break;
4267                 default:
4268                         i = (j - 2) << 2;
4269                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4270                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4271                         break;
4272                 }
4273
4274                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4275                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4276                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4277                 udelay(100);
4278         }
4279
4280         rtl8xxxu_debug = tmp_debug;
4281 }
4282
4283 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4284                                    struct ieee80211_vif *vif, const u8 *mac)
4285 {
4286         struct rtl8xxxu_priv *priv = hw->priv;
4287         u8 val8;
4288
4289         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4290         val8 |= BEACON_DISABLE_TSF_UPDATE;
4291         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4292 }
4293
4294 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4295                                       struct ieee80211_vif *vif)
4296 {
4297         struct rtl8xxxu_priv *priv = hw->priv;
4298         u8 val8;
4299
4300         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4301         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4302         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4303 }
4304
4305 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi)
4306 {
4307         struct h2c_cmd h2c;
4308
4309         memset(&h2c, 0, sizeof(struct h2c_cmd));
4310
4311         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4312         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4313         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4314
4315         h2c.ramask.arg = 0x80;
4316         if (sgi)
4317                 h2c.ramask.arg |= 0x20;
4318
4319         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4320                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4321         rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4322 }
4323
4324 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4325                                     u32 ramask, int sgi)
4326 {
4327         struct h2c_cmd h2c;
4328         u8 bw = 0;
4329
4330         memset(&h2c, 0, sizeof(struct h2c_cmd));
4331
4332         h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4333         h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4334         h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4335         h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4336         h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4337
4338         h2c.ramask.arg = 0x80;
4339         h2c.b_macid_cfg.data1 = 0;
4340         if (sgi)
4341                 h2c.b_macid_cfg.data1 |= BIT(7);
4342
4343         h2c.b_macid_cfg.data2 = bw;
4344
4345         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4346                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
4347         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4348 }
4349
4350 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4351                                   u8 macid, bool connect)
4352 {
4353         struct h2c_cmd h2c;
4354
4355         memset(&h2c, 0, sizeof(struct h2c_cmd));
4356
4357         h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4358
4359         if (connect)
4360                 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4361         else
4362                 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4363
4364         rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4365 }
4366
4367 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4368                                   u8 macid, bool connect)
4369 {
4370 #ifdef RTL8XXXU_GEN2_REPORT_CONNECT
4371         /*
4372          * Barry Day reports this causes issues with 8192eu and 8723bu
4373          * devices reconnecting. The reason for this is unclear, but
4374          * until it is better understood, leave the code in place but
4375          * disabled, so it is not lost.
4376          */
4377         struct h2c_cmd h2c;
4378
4379         memset(&h2c, 0, sizeof(struct h2c_cmd));
4380
4381         h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4382         if (connect)
4383                 h2c.media_status_rpt.parm |= BIT(0);
4384         else
4385                 h2c.media_status_rpt.parm &= ~BIT(0);
4386
4387         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4388 #endif
4389 }
4390
4391 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4392 {
4393         u8 agg_ctrl, usb_spec, page_thresh, timeout;
4394
4395         usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4396         usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4397         rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4398
4399         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4400         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4401
4402         if (!rtl8xxxu_dma_aggregation) {
4403                 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4404                 return;
4405         }
4406
4407         agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4408         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4409
4410         /*
4411          * The number of packets we can take looks to be buffer size / 512
4412          * which matches the 512 byte rounding we have to do when de-muxing
4413          * the packets.
4414          *
4415          * Sample numbers from the vendor driver:
4416          * USB High-Speed mode values:
4417          *   RxAggBlockCount = 8 : 512 byte unit
4418          *   RxAggBlockTimeout = 6
4419          *   RxAggPageCount = 48 : 128 byte unit
4420          *   RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4421          */
4422
4423         page_thresh = (priv->fops->rx_agg_buf_size / 512);
4424         if (rtl8xxxu_dma_agg_pages >= 0) {
4425                 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4426                         timeout = page_thresh;
4427                 else if (rtl8xxxu_dma_agg_pages <= 6)
4428                         dev_err(&priv->udev->dev,
4429                                 "%s: dma_agg_pages=%i too small, minium is 6\n",
4430                                 __func__, rtl8xxxu_dma_agg_pages);
4431                 else
4432                         dev_err(&priv->udev->dev,
4433                                 "%s: dma_agg_pages=%i larger than limit %i\n",
4434                                 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4435         }
4436         rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4437         /*
4438          * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4439          * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4440          * don't set it, so better set both.
4441          */
4442         timeout = 4;
4443
4444         if (rtl8xxxu_dma_agg_timeout >= 0) {
4445                 if (rtl8xxxu_dma_agg_timeout <= 127)
4446                         timeout = rtl8xxxu_dma_agg_timeout;
4447                 else
4448                         dev_err(&priv->udev->dev,
4449                                 "%s: Invalid dma_agg_timeout: %i\n",
4450                                 __func__, rtl8xxxu_dma_agg_timeout);
4451         }
4452
4453         rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4454         rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4455         priv->rx_buf_aggregation = 1;
4456 }
4457
4458 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4459 {
4460         u32 val32;
4461         u8 rate_idx = 0;
4462
4463         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4464
4465         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4466         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4467         val32 |= rate_cfg;
4468         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4469
4470         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4471
4472         while (rate_cfg) {
4473                 rate_cfg = (rate_cfg >> 1);
4474                 rate_idx++;
4475         }
4476         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4477 }
4478
4479 static void
4480 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4481                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4482 {
4483         struct rtl8xxxu_priv *priv = hw->priv;
4484         struct device *dev = &priv->udev->dev;
4485         struct ieee80211_sta *sta;
4486         u32 val32;
4487         u8 val8;
4488
4489         if (changed & BSS_CHANGED_ASSOC) {
4490                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4491
4492                 rtl8xxxu_set_linktype(priv, vif->type);
4493
4494                 if (bss_conf->assoc) {
4495                         u32 ramask;
4496                         int sgi = 0;
4497
4498                         rcu_read_lock();
4499                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4500                         if (!sta) {
4501                                 dev_info(dev, "%s: ASSOC no sta found\n",
4502                                          __func__);
4503                                 rcu_read_unlock();
4504                                 goto error;
4505                         }
4506
4507                         if (sta->ht_cap.ht_supported)
4508                                 dev_info(dev, "%s: HT supported\n", __func__);
4509                         if (sta->vht_cap.vht_supported)
4510                                 dev_info(dev, "%s: VHT supported\n", __func__);
4511
4512                         /* TODO: Set bits 28-31 for rate adaptive id */
4513                         ramask = (sta->supp_rates[0] & 0xfff) |
4514                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4515                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4516                         if (sta->ht_cap.cap &
4517                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4518                                 sgi = 1;
4519                         rcu_read_unlock();
4520
4521                         priv->fops->update_rate_mask(priv, ramask, sgi);
4522
4523                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4524
4525                         rtl8xxxu_stop_tx_beacon(priv);
4526
4527                         /* joinbss sequence */
4528                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4529                                          0xc000 | bss_conf->aid);
4530
4531                         priv->fops->report_connect(priv, 0, true);
4532                 } else {
4533                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4534                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4535                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4536
4537                         priv->fops->report_connect(priv, 0, false);
4538                 }
4539         }
4540
4541         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4542                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4543                         bss_conf->use_short_preamble);
4544                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4545                 if (bss_conf->use_short_preamble)
4546                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4547                 else
4548                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4549                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4550         }
4551
4552         if (changed & BSS_CHANGED_ERP_SLOT) {
4553                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4554                         bss_conf->use_short_slot);
4555
4556                 if (bss_conf->use_short_slot)
4557                         val8 = 9;
4558                 else
4559                         val8 = 20;
4560                 rtl8xxxu_write8(priv, REG_SLOT, val8);
4561         }
4562
4563         if (changed & BSS_CHANGED_BSSID) {
4564                 dev_dbg(dev, "Changed BSSID!\n");
4565                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4566         }
4567
4568         if (changed & BSS_CHANGED_BASIC_RATES) {
4569                 dev_dbg(dev, "Changed BASIC_RATES!\n");
4570                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4571         }
4572 error:
4573         return;
4574 }
4575
4576 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4577 {
4578         u32 rtlqueue;
4579
4580         switch (queue) {
4581         case IEEE80211_AC_VO:
4582                 rtlqueue = TXDESC_QUEUE_VO;
4583                 break;
4584         case IEEE80211_AC_VI:
4585                 rtlqueue = TXDESC_QUEUE_VI;
4586                 break;
4587         case IEEE80211_AC_BE:
4588                 rtlqueue = TXDESC_QUEUE_BE;
4589                 break;
4590         case IEEE80211_AC_BK:
4591                 rtlqueue = TXDESC_QUEUE_BK;
4592                 break;
4593         default:
4594                 rtlqueue = TXDESC_QUEUE_BE;
4595         }
4596
4597         return rtlqueue;
4598 }
4599
4600 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4601 {
4602         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4603         u32 queue;
4604
4605         if (ieee80211_is_mgmt(hdr->frame_control))
4606                 queue = TXDESC_QUEUE_MGNT;
4607         else
4608                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4609
4610         return queue;
4611 }
4612
4613 /*
4614  * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
4615  * format. The descriptor checksum is still only calculated over the
4616  * initial 32 bytes of the descriptor!
4617  */
4618 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
4619 {
4620         __le16 *ptr = (__le16 *)tx_desc;
4621         u16 csum = 0;
4622         int i;
4623
4624         /*
4625          * Clear csum field before calculation, as the csum field is
4626          * in the middle of the struct.
4627          */
4628         tx_desc->csum = cpu_to_le16(0);
4629
4630         for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
4631                 csum = csum ^ le16_to_cpu(ptr[i]);
4632
4633         tx_desc->csum |= cpu_to_le16(csum);
4634 }
4635
4636 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4637 {
4638         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4639         unsigned long flags;
4640
4641         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4642         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4643                 list_del(&tx_urb->list);
4644                 priv->tx_urb_free_count--;
4645                 usb_free_urb(&tx_urb->urb);
4646         }
4647         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4648 }
4649
4650 static struct rtl8xxxu_tx_urb *
4651 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4652 {
4653         struct rtl8xxxu_tx_urb *tx_urb;
4654         unsigned long flags;
4655
4656         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4657         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4658                                           struct rtl8xxxu_tx_urb, list);
4659         if (tx_urb) {
4660                 list_del(&tx_urb->list);
4661                 priv->tx_urb_free_count--;
4662                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4663                     !priv->tx_stopped) {
4664                         priv->tx_stopped = true;
4665                         ieee80211_stop_queues(priv->hw);
4666                 }
4667         }
4668
4669         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4670
4671         return tx_urb;
4672 }
4673
4674 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4675                                  struct rtl8xxxu_tx_urb *tx_urb)
4676 {
4677         unsigned long flags;
4678
4679         INIT_LIST_HEAD(&tx_urb->list);
4680
4681         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4682
4683         list_add(&tx_urb->list, &priv->tx_urb_free_list);
4684         priv->tx_urb_free_count++;
4685         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4686             priv->tx_stopped) {
4687                 priv->tx_stopped = false;
4688                 ieee80211_wake_queues(priv->hw);
4689         }
4690
4691         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4692 }
4693
4694 static void rtl8xxxu_tx_complete(struct urb *urb)
4695 {
4696         struct sk_buff *skb = (struct sk_buff *)urb->context;
4697         struct ieee80211_tx_info *tx_info;
4698         struct ieee80211_hw *hw;
4699         struct rtl8xxxu_priv *priv;
4700         struct rtl8xxxu_tx_urb *tx_urb =
4701                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4702
4703         tx_info = IEEE80211_SKB_CB(skb);
4704         hw = tx_info->rate_driver_data[0];
4705         priv = hw->priv;
4706
4707         skb_pull(skb, priv->fops->tx_desc_size);
4708
4709         ieee80211_tx_info_clear_status(tx_info);
4710         tx_info->status.rates[0].idx = -1;
4711         tx_info->status.rates[0].count = 0;
4712
4713         if (!urb->status)
4714                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4715
4716         ieee80211_tx_status_irqsafe(hw, skb);
4717
4718         rtl8xxxu_free_tx_urb(priv, tx_urb);
4719 }
4720
4721 static void rtl8xxxu_dump_action(struct device *dev,
4722                                  struct ieee80211_hdr *hdr)
4723 {
4724         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4725         u16 cap, timeout;
4726
4727         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4728                 return;
4729
4730         switch (mgmt->u.action.u.addba_resp.action_code) {
4731         case WLAN_ACTION_ADDBA_RESP:
4732                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4733                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4734                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4735                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4736                          "status %02x\n",
4737                          timeout,
4738                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4739                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4740                          (cap >> 1) & 0x1,
4741                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4742                 break;
4743         case WLAN_ACTION_ADDBA_REQ:
4744                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4745                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4746                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4747                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4748                          timeout,
4749                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4750                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4751                          (cap >> 1) & 0x1);
4752                 break;
4753         default:
4754                 dev_info(dev, "action frame %02x\n",
4755                          mgmt->u.action.u.addba_resp.action_code);
4756                 break;
4757         }
4758 }
4759
4760 /*
4761  * Fill in v1 (gen1) specific TX descriptor bits.
4762  * This format is used on 8188cu/8192cu/8723au
4763  */
4764 void
4765 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4766                         struct ieee80211_tx_info *tx_info,
4767                         struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
4768                         bool short_preamble, bool ampdu_enable, u32 rts_rate)
4769 {
4770         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4771         struct rtl8xxxu_priv *priv = hw->priv;
4772         struct device *dev = &priv->udev->dev;
4773         u32 rate;
4774         u16 rate_flags = tx_info->control.rates[0].flags;
4775         u16 seq_number;
4776
4777         if (rate_flags & IEEE80211_TX_RC_MCS &&
4778             !ieee80211_is_mgmt(hdr->frame_control))
4779                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4780         else
4781                 rate = tx_rate->hw_value;
4782
4783         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4784                 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4785                          __func__, rate, cpu_to_le16(tx_desc->pkt_size));
4786
4787         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4788
4789         tx_desc->txdw5 = cpu_to_le32(rate);
4790
4791         if (ieee80211_is_data(hdr->frame_control))
4792                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4793
4794         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4795
4796         if (ampdu_enable)
4797                 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4798         else
4799                 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4800
4801         if (ieee80211_is_mgmt(hdr->frame_control)) {
4802                 tx_desc->txdw5 = cpu_to_le32(rate);
4803                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4804                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4805                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4806         }
4807
4808         if (ieee80211_is_data_qos(hdr->frame_control))
4809                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4810
4811         if (short_preamble)
4812                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4813
4814         if (sgi)
4815                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4816
4817         /*
4818          * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
4819          */
4820         tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
4821         if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4822                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4823                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4824         } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4825                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
4826                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4827         }
4828 }
4829
4830 /*
4831  * Fill in v2 (gen2) specific TX descriptor bits.
4832  * This format is used on 8192eu/8723bu
4833  */
4834 void
4835 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4836                         struct ieee80211_tx_info *tx_info,
4837                         struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
4838                         bool short_preamble, bool ampdu_enable, u32 rts_rate)
4839 {
4840         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4841         struct rtl8xxxu_priv *priv = hw->priv;
4842         struct device *dev = &priv->udev->dev;
4843         struct rtl8xxxu_txdesc40 *tx_desc40;
4844         u32 rate;
4845         u16 rate_flags = tx_info->control.rates[0].flags;
4846         u16 seq_number;
4847
4848         tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4849
4850         if (rate_flags & IEEE80211_TX_RC_MCS &&
4851             !ieee80211_is_mgmt(hdr->frame_control))
4852                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4853         else
4854                 rate = tx_rate->hw_value;
4855
4856         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4857                 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4858                          __func__, rate, cpu_to_le16(tx_desc40->pkt_size));
4859
4860         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4861
4862         tx_desc40->txdw4 = cpu_to_le32(rate);
4863         if (ieee80211_is_data(hdr->frame_control)) {
4864                 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4865                                                 TXDESC40_DATA_RATE_FB_SHIFT);
4866         }
4867
4868         tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4869
4870         if (ampdu_enable)
4871                 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4872         else
4873                 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4874
4875         if (ieee80211_is_mgmt(hdr->frame_control)) {
4876                 tx_desc40->txdw4 = cpu_to_le32(rate);
4877                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4878                 tx_desc40->txdw4 |=
4879                         cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4880                 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4881         }
4882
4883         if (short_preamble)
4884                 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4885
4886         tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
4887         /*
4888          * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
4889          */
4890         if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4891                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
4892                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4893         } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4894                 /*
4895                  * For some reason the vendor driver doesn't set
4896                  * TXDESC40_HW_RTS_ENABLE for CTS to SELF
4897                  */
4898                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
4899         }
4900 }
4901
4902 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4903                         struct ieee80211_tx_control *control,
4904                         struct sk_buff *skb)
4905 {
4906         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4907         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4908         struct rtl8xxxu_priv *priv = hw->priv;
4909         struct rtl8xxxu_txdesc32 *tx_desc;
4910         struct rtl8xxxu_tx_urb *tx_urb;
4911         struct ieee80211_sta *sta = NULL;
4912         struct ieee80211_vif *vif = tx_info->control.vif;
4913         struct device *dev = &priv->udev->dev;
4914         u32 queue, rts_rate;
4915         u16 pktlen = skb->len;
4916         u16 seq_number;
4917         u16 rate_flag = tx_info->control.rates[0].flags;
4918         int tx_desc_size = priv->fops->tx_desc_size;
4919         int ret;
4920         bool usedesc40, ampdu_enable, sgi = false, short_preamble = false;
4921
4922         if (skb_headroom(skb) < tx_desc_size) {
4923                 dev_warn(dev,
4924                          "%s: Not enough headroom (%i) for tx descriptor\n",
4925                          __func__, skb_headroom(skb));
4926                 goto error;
4927         }
4928
4929         if (unlikely(skb->len > (65535 - tx_desc_size))) {
4930                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4931                          __func__, skb->len);
4932                 goto error;
4933         }
4934
4935         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4936         if (!tx_urb) {
4937                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4938                 goto error;
4939         }
4940
4941         if (ieee80211_is_action(hdr->frame_control))
4942                 rtl8xxxu_dump_action(dev, hdr);
4943
4944         usedesc40 = (tx_desc_size == 40);
4945         tx_info->rate_driver_data[0] = hw;
4946
4947         if (control && control->sta)
4948                 sta = control->sta;
4949
4950         tx_desc = skb_push(skb, tx_desc_size);
4951
4952         memset(tx_desc, 0, tx_desc_size);
4953         tx_desc->pkt_size = cpu_to_le16(pktlen);
4954         tx_desc->pkt_offset = tx_desc_size;
4955
4956         tx_desc->txdw0 =
4957                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4958         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4959             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4960                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4961
4962         queue = rtl8xxxu_queue_select(hw, skb);
4963         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4964
4965         if (tx_info->control.hw_key) {
4966                 switch (tx_info->control.hw_key->cipher) {
4967                 case WLAN_CIPHER_SUITE_WEP40:
4968                 case WLAN_CIPHER_SUITE_WEP104:
4969                 case WLAN_CIPHER_SUITE_TKIP:
4970                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4971                         break;
4972                 case WLAN_CIPHER_SUITE_CCMP:
4973                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4974                         break;
4975                 default:
4976                         break;
4977                 }
4978         }
4979
4980         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4981         ampdu_enable = false;
4982         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4983                 if (sta->ht_cap.ht_supported) {
4984                         u32 ampdu, val32;
4985
4986                         ampdu = (u32)sta->ht_cap.ampdu_density;
4987                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4988                         tx_desc->txdw2 |= cpu_to_le32(val32);
4989
4990                         ampdu_enable = true;
4991                 }
4992         }
4993
4994         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4995             (ieee80211_is_data_qos(hdr->frame_control) &&
4996              sta && sta->ht_cap.cap &
4997              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
4998                 sgi = true;
4999
5000         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5001             (sta && vif && vif->bss_conf.use_short_preamble))
5002                 short_preamble = true;
5003
5004         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS)
5005                 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5006         else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT)
5007                 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5008         else
5009                 rts_rate = 0;
5010
5011         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5012
5013         priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5014                                 ampdu_enable, rts_rate);
5015
5016         rtl8xxxu_calc_tx_desc_csum(tx_desc);
5017
5018         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5019                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5020
5021         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5022         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5023         if (ret) {
5024                 usb_unanchor_urb(&tx_urb->urb);
5025                 rtl8xxxu_free_tx_urb(priv, tx_urb);
5026                 goto error;
5027         }
5028         return;
5029 error:
5030         dev_kfree_skb(skb);
5031 }
5032
5033 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5034                                        struct ieee80211_rx_status *rx_status,
5035                                        struct rtl8723au_phy_stats *phy_stats,
5036                                        u32 rxmcs)
5037 {
5038         if (phy_stats->sgi_en)
5039                 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5040
5041         if (rxmcs < DESC_RATE_6M) {
5042                 /*
5043                  * Handle PHY stats for CCK rates
5044                  */
5045                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5046
5047                 switch (cck_agc_rpt & 0xc0) {
5048                 case 0xc0:
5049                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5050                         break;
5051                 case 0x80:
5052                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5053                         break;
5054                 case 0x40:
5055                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5056                         break;
5057                 case 0x00:
5058                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5059                         break;
5060                 }
5061         } else {
5062                 rx_status->signal =
5063                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5064         }
5065 }
5066
5067 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5068 {
5069         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5070         unsigned long flags;
5071
5072         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5073
5074         list_for_each_entry_safe(rx_urb, tmp,
5075                                  &priv->rx_urb_pending_list, list) {
5076                 list_del(&rx_urb->list);
5077                 priv->rx_urb_pending_count--;
5078                 usb_free_urb(&rx_urb->urb);
5079         }
5080
5081         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5082 }
5083
5084 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5085                                   struct rtl8xxxu_rx_urb *rx_urb)
5086 {
5087         struct sk_buff *skb;
5088         unsigned long flags;
5089         int pending = 0;
5090
5091         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5092
5093         if (!priv->shutdown) {
5094                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5095                 priv->rx_urb_pending_count++;
5096                 pending = priv->rx_urb_pending_count;
5097         } else {
5098                 skb = (struct sk_buff *)rx_urb->urb.context;
5099                 dev_kfree_skb(skb);
5100                 usb_free_urb(&rx_urb->urb);
5101         }
5102
5103         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5104
5105         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5106                 schedule_work(&priv->rx_urb_wq);
5107 }
5108
5109 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5110 {
5111         struct rtl8xxxu_priv *priv;
5112         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5113         struct list_head local;
5114         struct sk_buff *skb;
5115         unsigned long flags;
5116         int ret;
5117
5118         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5119         INIT_LIST_HEAD(&local);
5120
5121         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5122
5123         list_splice_init(&priv->rx_urb_pending_list, &local);
5124         priv->rx_urb_pending_count = 0;
5125
5126         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5127
5128         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5129                 list_del_init(&rx_urb->list);
5130                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5131                 /*
5132                  * If out of memory or temporary error, put it back on the
5133                  * queue and try again. Otherwise the device is dead/gone
5134                  * and we should drop it.
5135                  */
5136                 switch (ret) {
5137                 case 0:
5138                         break;
5139                 case -ENOMEM:
5140                 case -EAGAIN:
5141                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5142                         break;
5143                 default:
5144                         pr_info("failed to requeue urb %i\n", ret);
5145                         skb = (struct sk_buff *)rx_urb->urb.context;
5146                         dev_kfree_skb(skb);
5147                         usb_free_urb(&rx_urb->urb);
5148                 }
5149         }
5150 }
5151
5152 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5153                                  struct sk_buff *skb)
5154 {
5155         struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5156         struct device *dev = &priv->udev->dev;
5157         int len;
5158
5159         len = skb->len - 2;
5160
5161         dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5162                 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5163
5164         switch(c2h->id) {
5165         case C2H_8723B_BT_INFO:
5166                 if (c2h->bt_info.response_source >
5167                     BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5168                         dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5169                 else
5170                         dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5171
5172                 if (c2h->bt_info.bt_has_reset)
5173                         dev_dbg(dev, "BT has been reset\n");
5174                 if (c2h->bt_info.tx_rx_mask)
5175                         dev_dbg(dev, "BT TRx mask\n");
5176
5177                 break;
5178         case C2H_8723B_BT_MP_INFO:
5179                 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5180                         c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5181                 break;
5182         case C2H_8723B_RA_REPORT:
5183                 dev_dbg(dev,
5184                         "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5185                         c2h->ra_report.rate, c2h->ra_report.dummy0_0,
5186                         c2h->ra_report.macid, c2h->ra_report.noisy_state);
5187                 break;
5188         default:
5189                 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5190                          c2h->id, c2h->seq);
5191                 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5192                                16, 1, c2h->raw.payload, len, false);
5193                 break;
5194         }
5195 }
5196
5197 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5198 {
5199         struct ieee80211_hw *hw = priv->hw;
5200         struct ieee80211_rx_status *rx_status;
5201         struct rtl8xxxu_rxdesc16 *rx_desc;
5202         struct rtl8723au_phy_stats *phy_stats;
5203         struct sk_buff *next_skb = NULL;
5204         __le32 *_rx_desc_le;
5205         u32 *_rx_desc;
5206         int drvinfo_sz, desc_shift;
5207         int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
5208
5209         urb_len = skb->len;
5210         pkt_cnt = 0;
5211
5212         do {
5213                 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5214                 _rx_desc_le = (__le32 *)skb->data;
5215                 _rx_desc = (u32 *)skb->data;
5216
5217                 for (i = 0;
5218                      i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5219                         _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5220
5221                 /*
5222                  * Only read pkt_cnt from the header if we're parsing the
5223                  * first packet
5224                  */
5225                 if (!pkt_cnt)
5226                         pkt_cnt = rx_desc->pkt_cnt;
5227                 pkt_len = rx_desc->pktlen;
5228
5229                 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5230                 desc_shift = rx_desc->shift;
5231                 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5232                                      sizeof(struct rtl8xxxu_rxdesc16), 128);
5233
5234                 /*
5235                  * Only clone the skb if there's enough data at the end to
5236                  * at least cover the rx descriptor
5237                  */
5238                 if (pkt_cnt > 1 &&
5239                     urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
5240                         next_skb = skb_clone(skb, GFP_ATOMIC);
5241
5242                 rx_status = IEEE80211_SKB_RXCB(skb);
5243                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5244
5245                 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
5246
5247                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5248
5249                 skb_pull(skb, drvinfo_sz + desc_shift);
5250
5251                 skb_trim(skb, pkt_len);
5252
5253                 if (rx_desc->phy_stats)
5254                         rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5255                                                    rx_desc->rxmcs);
5256
5257                 rx_status->mactime = rx_desc->tsfl;
5258                 rx_status->flag |= RX_FLAG_MACTIME_START;
5259
5260                 if (!rx_desc->swdec)
5261                         rx_status->flag |= RX_FLAG_DECRYPTED;
5262                 if (rx_desc->crc32)
5263                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5264                 if (rx_desc->bw)
5265                         rx_status->bw = RATE_INFO_BW_40;
5266
5267                 if (rx_desc->rxht) {
5268                         rx_status->encoding = RX_ENC_HT;
5269                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5270                 } else {
5271                         rx_status->rate_idx = rx_desc->rxmcs;
5272                 }
5273
5274                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5275                 rx_status->band = hw->conf.chandef.chan->band;
5276
5277                 ieee80211_rx_irqsafe(hw, skb);
5278
5279                 skb = next_skb;
5280                 if (skb)
5281                         skb_pull(next_skb, pkt_offset);
5282
5283                 pkt_cnt--;
5284                 urb_len -= pkt_offset;
5285         } while (skb && urb_len > 0 && pkt_cnt > 0);
5286
5287         return RX_TYPE_DATA_PKT;
5288 }
5289
5290 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5291 {
5292         struct ieee80211_hw *hw = priv->hw;
5293         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5294         struct rtl8xxxu_rxdesc24 *rx_desc =
5295                 (struct rtl8xxxu_rxdesc24 *)skb->data;
5296         struct rtl8723au_phy_stats *phy_stats;
5297         __le32 *_rx_desc_le = (__le32 *)skb->data;
5298         u32 *_rx_desc = (u32 *)skb->data;
5299         int drvinfo_sz, desc_shift;
5300         int i;
5301
5302         for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
5303                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5304
5305         memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5306
5307         skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
5308
5309         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5310
5311         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5312         desc_shift = rx_desc->shift;
5313         skb_pull(skb, drvinfo_sz + desc_shift);
5314
5315         if (rx_desc->rpt_sel) {
5316                 struct device *dev = &priv->udev->dev;
5317                 dev_dbg(dev, "%s: C2H packet\n", __func__);
5318                 rtl8723bu_handle_c2h(priv, skb);
5319                 dev_kfree_skb(skb);
5320                 return RX_TYPE_C2H;
5321         }
5322
5323         if (rx_desc->phy_stats)
5324                 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5325                                            rx_desc->rxmcs);
5326
5327         rx_status->mactime = rx_desc->tsfl;
5328         rx_status->flag |= RX_FLAG_MACTIME_START;
5329
5330         if (!rx_desc->swdec)
5331                 rx_status->flag |= RX_FLAG_DECRYPTED;
5332         if (rx_desc->crc32)
5333                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5334         if (rx_desc->bw)
5335                 rx_status->bw = RATE_INFO_BW_40;
5336
5337         if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5338                 rx_status->encoding = RX_ENC_HT;
5339                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5340         } else {
5341                 rx_status->rate_idx = rx_desc->rxmcs;
5342         }
5343
5344         rx_status->freq = hw->conf.chandef.chan->center_freq;
5345         rx_status->band = hw->conf.chandef.chan->band;
5346
5347         ieee80211_rx_irqsafe(hw, skb);
5348         return RX_TYPE_DATA_PKT;
5349 }
5350
5351 static void rtl8xxxu_rx_complete(struct urb *urb)
5352 {
5353         struct rtl8xxxu_rx_urb *rx_urb =
5354                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5355         struct ieee80211_hw *hw = rx_urb->hw;
5356         struct rtl8xxxu_priv *priv = hw->priv;
5357         struct sk_buff *skb = (struct sk_buff *)urb->context;
5358         struct device *dev = &priv->udev->dev;
5359
5360         skb_put(skb, urb->actual_length);
5361
5362         if (urb->status == 0) {
5363                 priv->fops->parse_rx_desc(priv, skb);
5364
5365                 skb = NULL;
5366                 rx_urb->urb.context = NULL;
5367                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5368         } else {
5369                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5370                 goto cleanup;
5371         }
5372         return;
5373
5374 cleanup:
5375         usb_free_urb(urb);
5376         dev_kfree_skb(skb);
5377         return;
5378 }
5379
5380 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5381                                   struct rtl8xxxu_rx_urb *rx_urb)
5382 {
5383         struct rtl8xxxu_fileops *fops = priv->fops;
5384         struct sk_buff *skb;
5385         int skb_size;
5386         int ret, rx_desc_sz;
5387
5388         rx_desc_sz = fops->rx_desc_size;
5389
5390         if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
5391                 skb_size = fops->rx_agg_buf_size;
5392                 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5393         } else {
5394                 skb_size = IEEE80211_MAX_FRAME_LEN;
5395         }
5396
5397         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5398         if (!skb)
5399                 return -ENOMEM;
5400
5401         memset(skb->data, 0, rx_desc_sz);
5402         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5403                           skb_size, rtl8xxxu_rx_complete, skb);
5404         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5405         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5406         if (ret)
5407                 usb_unanchor_urb(&rx_urb->urb);
5408         return ret;
5409 }
5410
5411 static void rtl8xxxu_int_complete(struct urb *urb)
5412 {
5413         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5414         struct device *dev = &priv->udev->dev;
5415         int ret;
5416
5417         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
5418                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5419         if (urb->status == 0) {
5420                 usb_anchor_urb(urb, &priv->int_anchor);
5421                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5422                 if (ret)
5423                         usb_unanchor_urb(urb);
5424         } else {
5425                 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
5426         }
5427 }
5428
5429
5430 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5431 {
5432         struct rtl8xxxu_priv *priv = hw->priv;
5433         struct urb *urb;
5434         u32 val32;
5435         int ret;
5436
5437         urb = usb_alloc_urb(0, GFP_KERNEL);
5438         if (!urb)
5439                 return -ENOMEM;
5440
5441         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5442                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5443                          rtl8xxxu_int_complete, priv, 1);
5444         usb_anchor_urb(urb, &priv->int_anchor);
5445         ret = usb_submit_urb(urb, GFP_KERNEL);
5446         if (ret) {
5447                 usb_unanchor_urb(urb);
5448                 goto error;
5449         }
5450
5451         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5452         val32 |= USB_HIMR_CPWM;
5453         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5454
5455 error:
5456         usb_free_urb(urb);
5457         return ret;
5458 }
5459
5460 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5461                                   struct ieee80211_vif *vif)
5462 {
5463         struct rtl8xxxu_priv *priv = hw->priv;
5464         int ret;
5465         u8 val8;
5466
5467         switch (vif->type) {
5468         case NL80211_IFTYPE_STATION:
5469                 rtl8xxxu_stop_tx_beacon(priv);
5470
5471                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5472                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5473                         BEACON_DISABLE_TSF_UPDATE;
5474                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5475                 ret = 0;
5476                 break;
5477         default:
5478                 ret = -EOPNOTSUPP;
5479         }
5480
5481         rtl8xxxu_set_linktype(priv, vif->type);
5482
5483         return ret;
5484 }
5485
5486 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5487                                       struct ieee80211_vif *vif)
5488 {
5489         struct rtl8xxxu_priv *priv = hw->priv;
5490
5491         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5492 }
5493
5494 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5495 {
5496         struct rtl8xxxu_priv *priv = hw->priv;
5497         struct device *dev = &priv->udev->dev;
5498         u16 val16;
5499         int ret = 0, channel;
5500         bool ht40;
5501
5502         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5503                 dev_info(dev,
5504                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5505                          __func__, hw->conf.chandef.chan->hw_value,
5506                          changed, hw->conf.chandef.width);
5507
5508         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5509                 val16 = ((hw->conf.long_frame_max_tx_count <<
5510                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5511                         ((hw->conf.short_frame_max_tx_count <<
5512                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5513                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5514         }
5515
5516         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5517                 switch (hw->conf.chandef.width) {
5518                 case NL80211_CHAN_WIDTH_20_NOHT:
5519                 case NL80211_CHAN_WIDTH_20:
5520                         ht40 = false;
5521                         break;
5522                 case NL80211_CHAN_WIDTH_40:
5523                         ht40 = true;
5524                         break;
5525                 default:
5526                         ret = -ENOTSUPP;
5527                         goto exit;
5528                 }
5529
5530                 channel = hw->conf.chandef.chan->hw_value;
5531
5532                 priv->fops->set_tx_power(priv, channel, ht40);
5533
5534                 priv->fops->config_channel(hw);
5535         }
5536
5537 exit:
5538         return ret;
5539 }
5540
5541 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5542                             struct ieee80211_vif *vif, u16 queue,
5543                             const struct ieee80211_tx_queue_params *param)
5544 {
5545         struct rtl8xxxu_priv *priv = hw->priv;
5546         struct device *dev = &priv->udev->dev;
5547         u32 val32;
5548         u8 aifs, acm_ctrl, acm_bit;
5549
5550         aifs = param->aifs;
5551
5552         val32 = aifs |
5553                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5554                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5555                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5556
5557         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5558         dev_dbg(dev,
5559                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5560                 __func__, queue, val32, param->acm, acm_ctrl);
5561
5562         switch (queue) {
5563         case IEEE80211_AC_VO:
5564                 acm_bit = ACM_HW_CTRL_VO;
5565                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5566                 break;
5567         case IEEE80211_AC_VI:
5568                 acm_bit = ACM_HW_CTRL_VI;
5569                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5570                 break;
5571         case IEEE80211_AC_BE:
5572                 acm_bit = ACM_HW_CTRL_BE;
5573                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5574                 break;
5575         case IEEE80211_AC_BK:
5576                 acm_bit = ACM_HW_CTRL_BK;
5577                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5578                 break;
5579         default:
5580                 acm_bit = 0;
5581                 break;
5582         }
5583
5584         if (param->acm)
5585                 acm_ctrl |= acm_bit;
5586         else
5587                 acm_ctrl &= ~acm_bit;
5588         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5589
5590         return 0;
5591 }
5592
5593 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5594                                       unsigned int changed_flags,
5595                                       unsigned int *total_flags, u64 multicast)
5596 {
5597         struct rtl8xxxu_priv *priv = hw->priv;
5598         u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5599
5600         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5601                 __func__, changed_flags, *total_flags);
5602
5603         /*
5604          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5605          */
5606
5607         if (*total_flags & FIF_FCSFAIL)
5608                 rcr |= RCR_ACCEPT_CRC32;
5609         else
5610                 rcr &= ~RCR_ACCEPT_CRC32;
5611
5612         /*
5613          * FIF_PLCPFAIL not supported?
5614          */
5615
5616         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5617                 rcr &= ~RCR_CHECK_BSSID_BEACON;
5618         else
5619                 rcr |= RCR_CHECK_BSSID_BEACON;
5620
5621         if (*total_flags & FIF_CONTROL)
5622                 rcr |= RCR_ACCEPT_CTRL_FRAME;
5623         else
5624                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5625
5626         if (*total_flags & FIF_OTHER_BSS) {
5627                 rcr |= RCR_ACCEPT_AP;
5628                 rcr &= ~RCR_CHECK_BSSID_MATCH;
5629         } else {
5630                 rcr &= ~RCR_ACCEPT_AP;
5631                 rcr |= RCR_CHECK_BSSID_MATCH;
5632         }
5633
5634         if (*total_flags & FIF_PSPOLL)
5635                 rcr |= RCR_ACCEPT_PM;
5636         else
5637                 rcr &= ~RCR_ACCEPT_PM;
5638
5639         /*
5640          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5641          */
5642
5643         rtl8xxxu_write32(priv, REG_RCR, rcr);
5644
5645         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5646                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5647                          FIF_PROBE_REQ);
5648 }
5649
5650 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5651 {
5652         if (rts > 2347)
5653                 return -EINVAL;
5654
5655         return 0;
5656 }
5657
5658 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5659                             struct ieee80211_vif *vif,
5660                             struct ieee80211_sta *sta,
5661                             struct ieee80211_key_conf *key)
5662 {
5663         struct rtl8xxxu_priv *priv = hw->priv;
5664         struct device *dev = &priv->udev->dev;
5665         u8 mac_addr[ETH_ALEN];
5666         u8 val8;
5667         u16 val16;
5668         u32 val32;
5669         int retval = -EOPNOTSUPP;
5670
5671         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5672                 __func__, cmd, key->cipher, key->keyidx);
5673
5674         if (vif->type != NL80211_IFTYPE_STATION)
5675                 return -EOPNOTSUPP;
5676
5677         if (key->keyidx > 3)
5678                 return -EOPNOTSUPP;
5679
5680         switch (key->cipher) {
5681         case WLAN_CIPHER_SUITE_WEP40:
5682         case WLAN_CIPHER_SUITE_WEP104:
5683
5684                 break;
5685         case WLAN_CIPHER_SUITE_CCMP:
5686                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5687                 break;
5688         case WLAN_CIPHER_SUITE_TKIP:
5689                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5690                 break;
5691         default:
5692                 return -EOPNOTSUPP;
5693         }
5694
5695         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5696                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5697                 ether_addr_copy(mac_addr, sta->addr);
5698         } else {
5699                 dev_dbg(dev, "%s: group key\n", __func__);
5700                 eth_broadcast_addr(mac_addr);
5701         }
5702
5703         val16 = rtl8xxxu_read16(priv, REG_CR);
5704         val16 |= CR_SECURITY_ENABLE;
5705         rtl8xxxu_write16(priv, REG_CR, val16);
5706
5707         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5708                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5709         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5710         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5711
5712         switch (cmd) {
5713         case SET_KEY:
5714                 key->hw_key_idx = key->keyidx;
5715                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5716                 rtl8xxxu_cam_write(priv, key, mac_addr);
5717                 retval = 0;
5718                 break;
5719         case DISABLE_KEY:
5720                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5721                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5722                         key->keyidx << CAM_CMD_KEY_SHIFT;
5723                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5724                 retval = 0;
5725                 break;
5726         default:
5727                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5728         }
5729
5730         return retval;
5731 }
5732
5733 static int
5734 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5735                       struct ieee80211_ampdu_params *params)
5736 {
5737         struct rtl8xxxu_priv *priv = hw->priv;
5738         struct device *dev = &priv->udev->dev;
5739         u8 ampdu_factor, ampdu_density;
5740         struct ieee80211_sta *sta = params->sta;
5741         enum ieee80211_ampdu_mlme_action action = params->action;
5742
5743         switch (action) {
5744         case IEEE80211_AMPDU_TX_START:
5745                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5746                 ampdu_factor = sta->ht_cap.ampdu_factor;
5747                 ampdu_density = sta->ht_cap.ampdu_density;
5748                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5749                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5750                 dev_dbg(dev,
5751                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5752                         ampdu_factor, ampdu_density);
5753                 break;
5754         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5755                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5756                 rtl8xxxu_set_ampdu_factor(priv, 0);
5757                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5758                 break;
5759         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5760                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5761                          __func__);
5762                 rtl8xxxu_set_ampdu_factor(priv, 0);
5763                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5764                 break;
5765         case IEEE80211_AMPDU_RX_START:
5766                 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5767                 break;
5768         case IEEE80211_AMPDU_RX_STOP:
5769                 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5770                 break;
5771         default:
5772                 break;
5773         }
5774         return 0;
5775 }
5776
5777 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5778 {
5779         struct rtl8xxxu_priv *priv = hw->priv;
5780         struct rtl8xxxu_rx_urb *rx_urb;
5781         struct rtl8xxxu_tx_urb *tx_urb;
5782         struct sk_buff *skb;
5783         unsigned long flags;
5784         int ret, i;
5785
5786         ret = 0;
5787
5788         init_usb_anchor(&priv->rx_anchor);
5789         init_usb_anchor(&priv->tx_anchor);
5790         init_usb_anchor(&priv->int_anchor);
5791
5792         priv->fops->enable_rf(priv);
5793         if (priv->usb_interrupts) {
5794                 ret = rtl8xxxu_submit_int_urb(hw);
5795                 if (ret)
5796                         goto exit;
5797         }
5798
5799         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5800                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5801                 if (!tx_urb) {
5802                         if (!i)
5803                                 ret = -ENOMEM;
5804
5805                         goto error_out;
5806                 }
5807                 usb_init_urb(&tx_urb->urb);
5808                 INIT_LIST_HEAD(&tx_urb->list);
5809                 tx_urb->hw = hw;
5810                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5811                 priv->tx_urb_free_count++;
5812         }
5813
5814         priv->tx_stopped = false;
5815
5816         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5817         priv->shutdown = false;
5818         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5819
5820         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5821                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5822                 if (!rx_urb) {
5823                         if (!i)
5824                                 ret = -ENOMEM;
5825
5826                         goto error_out;
5827                 }
5828                 usb_init_urb(&rx_urb->urb);
5829                 INIT_LIST_HEAD(&rx_urb->list);
5830                 rx_urb->hw = hw;
5831
5832                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5833                 if (ret) {
5834                         if (ret != -ENOMEM) {
5835                                 skb = (struct sk_buff *)rx_urb->urb.context;
5836                                 dev_kfree_skb(skb);
5837                         }
5838                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5839                 }
5840         }
5841 exit:
5842         /*
5843          * Accept all data and mgmt frames
5844          */
5845         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5846         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5847
5848         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5849
5850         return ret;
5851
5852 error_out:
5853         rtl8xxxu_free_tx_resources(priv);
5854         /*
5855          * Disable all data and mgmt frames
5856          */
5857         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5858         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5859
5860         return ret;
5861 }
5862
5863 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5864 {
5865         struct rtl8xxxu_priv *priv = hw->priv;
5866         unsigned long flags;
5867
5868         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5869
5870         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5871         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5872
5873         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5874         priv->shutdown = true;
5875         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5876
5877         usb_kill_anchored_urbs(&priv->rx_anchor);
5878         usb_kill_anchored_urbs(&priv->tx_anchor);
5879         if (priv->usb_interrupts)
5880                 usb_kill_anchored_urbs(&priv->int_anchor);
5881
5882         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5883
5884         priv->fops->disable_rf(priv);
5885
5886         /*
5887          * Disable interrupts
5888          */
5889         if (priv->usb_interrupts)
5890                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5891
5892         rtl8xxxu_free_rx_resources(priv);
5893         rtl8xxxu_free_tx_resources(priv);
5894 }
5895
5896 static const struct ieee80211_ops rtl8xxxu_ops = {
5897         .tx = rtl8xxxu_tx,
5898         .add_interface = rtl8xxxu_add_interface,
5899         .remove_interface = rtl8xxxu_remove_interface,
5900         .config = rtl8xxxu_config,
5901         .conf_tx = rtl8xxxu_conf_tx,
5902         .bss_info_changed = rtl8xxxu_bss_info_changed,
5903         .configure_filter = rtl8xxxu_configure_filter,
5904         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5905         .start = rtl8xxxu_start,
5906         .stop = rtl8xxxu_stop,
5907         .sw_scan_start = rtl8xxxu_sw_scan_start,
5908         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5909         .set_key = rtl8xxxu_set_key,
5910         .ampdu_action = rtl8xxxu_ampdu_action,
5911 };
5912
5913 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5914                               struct usb_interface *interface)
5915 {
5916         struct usb_interface_descriptor *interface_desc;
5917         struct usb_host_interface *host_interface;
5918         struct usb_endpoint_descriptor *endpoint;
5919         struct device *dev = &priv->udev->dev;
5920         int i, j = 0, endpoints;
5921         u8 dir, xtype, num;
5922         int ret = 0;
5923
5924         host_interface = interface->cur_altsetting;
5925         interface_desc = &host_interface->desc;
5926         endpoints = interface_desc->bNumEndpoints;
5927
5928         for (i = 0; i < endpoints; i++) {
5929                 endpoint = &host_interface->endpoint[i].desc;
5930
5931                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5932                 num = usb_endpoint_num(endpoint);
5933                 xtype = usb_endpoint_type(endpoint);
5934                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5935                         dev_dbg(dev,
5936                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5937                                 __func__, dir, num, xtype);
5938                 if (usb_endpoint_dir_in(endpoint) &&
5939                     usb_endpoint_xfer_bulk(endpoint)) {
5940                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5941                                 dev_dbg(dev, "%s: in endpoint num %i\n",
5942                                         __func__, num);
5943
5944                         if (priv->pipe_in) {
5945                                 dev_warn(dev,
5946                                          "%s: Too many IN pipes\n", __func__);
5947                                 ret = -EINVAL;
5948                                 goto exit;
5949                         }
5950
5951                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5952                 }
5953
5954                 if (usb_endpoint_dir_in(endpoint) &&
5955                     usb_endpoint_xfer_int(endpoint)) {
5956                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5957                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5958                                         __func__, num);
5959
5960                         if (priv->pipe_interrupt) {
5961                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5962                                          __func__);
5963                                 ret = -EINVAL;
5964                                 goto exit;
5965                         }
5966
5967                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5968                 }
5969
5970                 if (usb_endpoint_dir_out(endpoint) &&
5971                     usb_endpoint_xfer_bulk(endpoint)) {
5972                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5973                                 dev_dbg(dev, "%s: out endpoint num %i\n",
5974                                         __func__, num);
5975                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5976                                 dev_warn(dev,
5977                                          "%s: Too many OUT pipes\n", __func__);
5978                                 ret = -EINVAL;
5979                                 goto exit;
5980                         }
5981                         priv->out_ep[j++] = num;
5982                 }
5983         }
5984 exit:
5985         priv->nr_out_eps = j;
5986         return ret;
5987 }
5988
5989 static int rtl8xxxu_probe(struct usb_interface *interface,
5990                           const struct usb_device_id *id)
5991 {
5992         struct rtl8xxxu_priv *priv;
5993         struct ieee80211_hw *hw;
5994         struct usb_device *udev;
5995         struct ieee80211_supported_band *sband;
5996         int ret;
5997         int untested = 1;
5998
5999         udev = usb_get_dev(interface_to_usbdev(interface));
6000
6001         switch (id->idVendor) {
6002         case USB_VENDOR_ID_REALTEK:
6003                 switch(id->idProduct) {
6004                 case 0x1724:
6005                 case 0x8176:
6006                 case 0x8178:
6007                 case 0x817f:
6008                 case 0x818b:
6009                         untested = 0;
6010                         break;
6011                 }
6012                 break;
6013         case 0x7392:
6014                 if (id->idProduct == 0x7811)
6015                         untested = 0;
6016                 break;
6017         case 0x050d:
6018                 if (id->idProduct == 0x1004)
6019                         untested = 0;
6020                 break;
6021         case 0x20f4:
6022                 if (id->idProduct == 0x648b)
6023                         untested = 0;
6024                 break;
6025         case 0x2001:
6026                 if (id->idProduct == 0x3308)
6027                         untested = 0;
6028                 break;
6029         case 0x2357:
6030                 if (id->idProduct == 0x0109)
6031                         untested = 0;
6032                 break;
6033         default:
6034                 break;
6035         }
6036
6037         if (untested) {
6038                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
6039                 dev_info(&udev->dev,
6040                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6041                          id->idVendor, id->idProduct);
6042                 dev_info(&udev->dev,
6043                          "Please report results to Jes.Sorensen@gmail.com\n");
6044         }
6045
6046         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6047         if (!hw) {
6048                 ret = -ENOMEM;
6049                 priv = NULL;
6050                 goto exit;
6051         }
6052
6053         priv = hw->priv;
6054         priv->hw = hw;
6055         priv->udev = udev;
6056         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6057         mutex_init(&priv->usb_buf_mutex);
6058         mutex_init(&priv->h2c_mutex);
6059         INIT_LIST_HEAD(&priv->tx_urb_free_list);
6060         spin_lock_init(&priv->tx_urb_lock);
6061         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6062         spin_lock_init(&priv->rx_urb_lock);
6063         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6064
6065         usb_set_intfdata(interface, hw);
6066
6067         ret = rtl8xxxu_parse_usb(priv, interface);
6068         if (ret)
6069                 goto exit;
6070
6071         ret = rtl8xxxu_identify_chip(priv);
6072         if (ret) {
6073                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6074                 goto exit;
6075         }
6076
6077         ret = rtl8xxxu_read_efuse(priv);
6078         if (ret) {
6079                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6080                 goto exit;
6081         }
6082
6083         ret = priv->fops->parse_efuse(priv);
6084         if (ret) {
6085                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6086                 goto exit;
6087         }
6088
6089         rtl8xxxu_print_chipinfo(priv);
6090
6091         ret = priv->fops->load_firmware(priv);
6092         if (ret) {
6093                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6094                 goto exit;
6095         }
6096
6097         ret = rtl8xxxu_init_device(hw);
6098         if (ret)
6099                 goto exit;
6100
6101         hw->wiphy->max_scan_ssids = 1;
6102         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6103         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6104         hw->queues = 4;
6105
6106         sband = &rtl8xxxu_supported_band;
6107         sband->ht_cap.ht_supported = true;
6108         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6109         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6110         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6111         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6112         sband->ht_cap.mcs.rx_mask[0] = 0xff;
6113         sband->ht_cap.mcs.rx_mask[4] = 0x01;
6114         if (priv->rf_paths > 1) {
6115                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6116                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6117         }
6118         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6119         /*
6120          * Some APs will negotiate HT20_40 in a noisy environment leading
6121          * to miserable performance. Rather than defaulting to this, only
6122          * enable it if explicitly requested at module load time.
6123          */
6124         if (rtl8xxxu_ht40_2g) {
6125                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6126                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6127         }
6128         hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6129
6130         hw->wiphy->rts_threshold = 2347;
6131
6132         SET_IEEE80211_DEV(priv->hw, &interface->dev);
6133         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6134
6135         hw->extra_tx_headroom = priv->fops->tx_desc_size;
6136         ieee80211_hw_set(hw, SIGNAL_DBM);
6137         /*
6138          * The firmware handles rate control
6139          */
6140         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6141         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6142
6143         wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
6144
6145         ret = ieee80211_register_hw(priv->hw);
6146         if (ret) {
6147                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6148                         __func__, ret);
6149                 goto exit;
6150         }
6151
6152         return 0;
6153
6154 exit:
6155         usb_set_intfdata(interface, NULL);
6156
6157         if (priv) {
6158                 kfree(priv->fw_data);
6159                 mutex_destroy(&priv->usb_buf_mutex);
6160                 mutex_destroy(&priv->h2c_mutex);
6161         }
6162         usb_put_dev(udev);
6163
6164         ieee80211_free_hw(hw);
6165
6166         return ret;
6167 }
6168
6169 static void rtl8xxxu_disconnect(struct usb_interface *interface)
6170 {
6171         struct rtl8xxxu_priv *priv;
6172         struct ieee80211_hw *hw;
6173
6174         hw = usb_get_intfdata(interface);
6175         priv = hw->priv;
6176
6177         ieee80211_unregister_hw(hw);
6178
6179         priv->fops->power_off(priv);
6180
6181         usb_set_intfdata(interface, NULL);
6182
6183         dev_info(&priv->udev->dev, "disconnecting\n");
6184
6185         kfree(priv->fw_data);
6186         mutex_destroy(&priv->usb_buf_mutex);
6187         mutex_destroy(&priv->h2c_mutex);
6188
6189         if (priv->udev->state != USB_STATE_NOTATTACHED) {
6190                 dev_info(&priv->udev->dev,
6191                          "Device still attached, trying to reset\n");
6192                 usb_reset_device(priv->udev);
6193         }
6194         usb_put_dev(priv->udev);
6195         ieee80211_free_hw(hw);
6196 }
6197
6198 static const struct usb_device_id dev_table[] = {
6199 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6200         .driver_info = (unsigned long)&rtl8723au_fops},
6201 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6202         .driver_info = (unsigned long)&rtl8723au_fops},
6203 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6204         .driver_info = (unsigned long)&rtl8723au_fops},
6205 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6206         .driver_info = (unsigned long)&rtl8192eu_fops},
6207 /* TP-Link TL-WN822N v4 */
6208 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
6209         .driver_info = (unsigned long)&rtl8192eu_fops},
6210 /* D-Link DWA-131 rev E1, tested by David Patiño */
6211 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
6212         .driver_info = (unsigned long)&rtl8192eu_fops},
6213 /* Tested by Myckel Habets */
6214 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6215         .driver_info = (unsigned long)&rtl8192eu_fops},
6216 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6217         .driver_info = (unsigned long)&rtl8723bu_fops},
6218 #ifdef CONFIG_RTL8XXXU_UNTESTED
6219 /* Still supported by rtlwifi */
6220 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6221         .driver_info = (unsigned long)&rtl8192cu_fops},
6222 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6223         .driver_info = (unsigned long)&rtl8192cu_fops},
6224 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6225         .driver_info = (unsigned long)&rtl8192cu_fops},
6226 /* Tested by Larry Finger */
6227 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6228         .driver_info = (unsigned long)&rtl8192cu_fops},
6229 /* Tested by Andrea Merello */
6230 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6231         .driver_info = (unsigned long)&rtl8192cu_fops},
6232 /* Tested by Jocelyn Mayer */
6233 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6234         .driver_info = (unsigned long)&rtl8192cu_fops},
6235 /* Tested by Stefano Bravi */
6236 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6237         .driver_info = (unsigned long)&rtl8192cu_fops},
6238 /* Currently untested 8188 series devices */
6239 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6240         .driver_info = (unsigned long)&rtl8192cu_fops},
6241 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6242         .driver_info = (unsigned long)&rtl8192cu_fops},
6243 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6244         .driver_info = (unsigned long)&rtl8192cu_fops},
6245 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6246         .driver_info = (unsigned long)&rtl8192cu_fops},
6247 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6248         .driver_info = (unsigned long)&rtl8192cu_fops},
6249 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6250         .driver_info = (unsigned long)&rtl8192cu_fops},
6251 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6252         .driver_info = (unsigned long)&rtl8192cu_fops},
6253 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6254         .driver_info = (unsigned long)&rtl8192cu_fops},
6255 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6256         .driver_info = (unsigned long)&rtl8192cu_fops},
6257 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6258         .driver_info = (unsigned long)&rtl8192cu_fops},
6259 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6260         .driver_info = (unsigned long)&rtl8192cu_fops},
6261 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6262         .driver_info = (unsigned long)&rtl8192cu_fops},
6263 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6264         .driver_info = (unsigned long)&rtl8192cu_fops},
6265 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6266         .driver_info = (unsigned long)&rtl8192cu_fops},
6267 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6268         .driver_info = (unsigned long)&rtl8192cu_fops},
6269 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6270         .driver_info = (unsigned long)&rtl8192cu_fops},
6271 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6272         .driver_info = (unsigned long)&rtl8192cu_fops},
6273 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6274         .driver_info = (unsigned long)&rtl8192cu_fops},
6275 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6276         .driver_info = (unsigned long)&rtl8192cu_fops},
6277 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6278         .driver_info = (unsigned long)&rtl8192cu_fops},
6279 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6280         .driver_info = (unsigned long)&rtl8192cu_fops},
6281 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6282         .driver_info = (unsigned long)&rtl8192cu_fops},
6283 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6284         .driver_info = (unsigned long)&rtl8192cu_fops},
6285 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6286         .driver_info = (unsigned long)&rtl8192cu_fops},
6287 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6288         .driver_info = (unsigned long)&rtl8192cu_fops},
6289 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6290         .driver_info = (unsigned long)&rtl8192cu_fops},
6291 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6292         .driver_info = (unsigned long)&rtl8192cu_fops},
6293 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6294         .driver_info = (unsigned long)&rtl8192cu_fops},
6295 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6296         .driver_info = (unsigned long)&rtl8192cu_fops},
6297 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6298         .driver_info = (unsigned long)&rtl8192cu_fops},
6299 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6300         .driver_info = (unsigned long)&rtl8192cu_fops},
6301 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6302         .driver_info = (unsigned long)&rtl8192cu_fops},
6303 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6304         .driver_info = (unsigned long)&rtl8192cu_fops},
6305 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6306         .driver_info = (unsigned long)&rtl8192cu_fops},
6307 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6308         .driver_info = (unsigned long)&rtl8192cu_fops},
6309 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6310         .driver_info = (unsigned long)&rtl8192cu_fops},
6311 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6312         .driver_info = (unsigned long)&rtl8192cu_fops},
6313 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6314         .driver_info = (unsigned long)&rtl8192cu_fops},
6315 /* Currently untested 8192 series devices */
6316 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6317         .driver_info = (unsigned long)&rtl8192cu_fops},
6318 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6319         .driver_info = (unsigned long)&rtl8192cu_fops},
6320 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6321         .driver_info = (unsigned long)&rtl8192cu_fops},
6322 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6323         .driver_info = (unsigned long)&rtl8192cu_fops},
6324 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6325         .driver_info = (unsigned long)&rtl8192cu_fops},
6326 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6327         .driver_info = (unsigned long)&rtl8192cu_fops},
6328 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6329         .driver_info = (unsigned long)&rtl8192cu_fops},
6330 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6331         .driver_info = (unsigned long)&rtl8192cu_fops},
6332 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6333         .driver_info = (unsigned long)&rtl8192cu_fops},
6334 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6335         .driver_info = (unsigned long)&rtl8192cu_fops},
6336 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6337         .driver_info = (unsigned long)&rtl8192cu_fops},
6338 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6339         .driver_info = (unsigned long)&rtl8192cu_fops},
6340 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6341         .driver_info = (unsigned long)&rtl8192cu_fops},
6342 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6343         .driver_info = (unsigned long)&rtl8192cu_fops},
6344 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6345         .driver_info = (unsigned long)&rtl8192cu_fops},
6346 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6347         .driver_info = (unsigned long)&rtl8192cu_fops},
6348 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6349         .driver_info = (unsigned long)&rtl8192cu_fops},
6350 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6351         .driver_info = (unsigned long)&rtl8192cu_fops},
6352 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6353         .driver_info = (unsigned long)&rtl8192cu_fops},
6354 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6355         .driver_info = (unsigned long)&rtl8192cu_fops},
6356 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6357         .driver_info = (unsigned long)&rtl8192cu_fops},
6358 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6359         .driver_info = (unsigned long)&rtl8192cu_fops},
6360 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6361         .driver_info = (unsigned long)&rtl8192cu_fops},
6362 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6363         .driver_info = (unsigned long)&rtl8192cu_fops},
6364 /* found in rtl8192eu vendor driver */
6365 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
6366         .driver_info = (unsigned long)&rtl8192eu_fops},
6367 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
6368         .driver_info = (unsigned long)&rtl8192eu_fops},
6369 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
6370         .driver_info = (unsigned long)&rtl8192eu_fops},
6371 #endif
6372 { }
6373 };
6374
6375 static struct usb_driver rtl8xxxu_driver = {
6376         .name = DRIVER_NAME,
6377         .probe = rtl8xxxu_probe,
6378         .disconnect = rtl8xxxu_disconnect,
6379         .id_table = dev_table,
6380         .no_dynamic_id = 1,
6381         .disable_hub_initiated_lpm = 1,
6382 };
6383
6384 static int __init rtl8xxxu_module_init(void)
6385 {
6386         int res;
6387
6388         res = usb_register(&rtl8xxxu_driver);
6389         if (res < 0)
6390                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6391
6392         return res;
6393 }
6394
6395 static void __exit rtl8xxxu_module_exit(void)
6396 {
6397         usb_deregister(&rtl8xxxu_driver);
6398 }
6399
6400
6401 MODULE_DEVICE_TABLE(usb, dev_table);
6402
6403 module_init(rtl8xxxu_module_init);
6404 module_exit(rtl8xxxu_module_exit);