drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver
   4  *
   5  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   6  *
   7  * Portions, notably calibration code:
   8  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   9  *
  10  * This driver was written as a replacement for the vendor provided
  11  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  12  * their programming interface, I have started adding support for
  13  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/list.h>
  24 #include <linux/usb.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/wireless.h>
  29 #include <linux/firmware.h>
  30 #include <linux/moduleparam.h>
  31 #include <net/mac80211.h>
  32 #include "rtl8xxxu.h"
  33 #include "rtl8xxxu_regs.h"
  34
  35 #define DRIVER_NAME "rtl8xxxu"
  36
  37 int rtl8xxxu_debug;
  38 static bool rtl8xxxu_ht40_2g;
  39 static bool rtl8xxxu_dma_aggregation;
  40 static int rtl8xxxu_dma_agg_timeout = -1;
  41 static int rtl8xxxu_dma_agg_pages = -1;
  42
  43 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
  44 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  45 MODULE_LICENSE("GPL");
  46 /*(DEBLOBBED)*/
  47
  48 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  49 MODULE_PARM_DESC(debug, "Set debug mask");
  50 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  51 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  52 module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
  53 MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
  54 module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
  55 MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
  56 module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
  57 MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
  58
  59 #define USB_VENDOR_ID_REALTEK           0x0bda
  60 #define RTL8XXXU_RX_URBS                32
  61 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  62 #define RTL8XXXU_TX_URBS                64
  63 #define RTL8XXXU_TX_URB_LOW_WATER       25
  64 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  65
  66 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  67                                   struct rtl8xxxu_rx_urb *rx_urb);
  68
  69 static struct ieee80211_rate rtl8xxxu_rates[] = {
  70         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  71         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  72         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  73         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  74         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  75         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  76         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  77         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  78         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  79         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  80         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  81         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  82 };
  83
  84 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  85         { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
  86           .hw_value = 1, .max_power = 30 },
  87         { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
  88           .hw_value = 2, .max_power = 30 },
  89         { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
  90           .hw_value = 3, .max_power = 30 },
  91         { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
  92           .hw_value = 4, .max_power = 30 },
  93         { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
  94           .hw_value = 5, .max_power = 30 },
  95         { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
  96           .hw_value = 6, .max_power = 30 },
  97         { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
  98           .hw_value = 7, .max_power = 30 },
  99         { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
 100           .hw_value = 8, .max_power = 30 },
 101         { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
 102           .hw_value = 9, .max_power = 30 },
 103         { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
 104           .hw_value = 10, .max_power = 30 },
 105         { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
 106           .hw_value = 11, .max_power = 30 },
 107         { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
 108           .hw_value = 12, .max_power = 30 },
 109         { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
 110           .hw_value = 13, .max_power = 30 },
 111         { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
 112           .hw_value = 14, .max_power = 30 }
 113 };
 114
 115 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 116         .channels = rtl8xxxu_channels_2g,
 117         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 118         .bitrates = rtl8xxxu_rates,
 119         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 120 };
 121
 122 const struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
 123         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 124         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 125         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 126         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 127         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 128         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 129         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 130         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 131         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 132         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 133         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 134         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 135         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 136         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 137         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 138         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 139         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 140         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 141         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 142         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 143         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 144         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 145 };
 146
 147 static const struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 148         {0x800, 0x80040000}, {0x804, 0x00000003},
 149         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 150         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 151         {0x818, 0x02200385}, {0x81c, 0x00000000},
 152         {0x820, 0x01000100}, {0x824, 0x00390004},
 153         {0x828, 0x00000000}, {0x82c, 0x00000000},
 154         {0x830, 0x00000000}, {0x834, 0x00000000},
 155         {0x838, 0x00000000}, {0x83c, 0x00000000},
 156         {0x840, 0x00010000}, {0x844, 0x00000000},
 157         {0x848, 0x00000000}, {0x84c, 0x00000000},
 158         {0x850, 0x00000000}, {0x854, 0x00000000},
 159         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 160         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 161         {0x868, 0x00000000}, {0x86c, 0x32323200},
 162         {0x870, 0x07000760}, {0x874, 0x22004000},
 163         {0x878, 0x00000808}, {0x87c, 0x00000000},
 164         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 165         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 166         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 167         {0x898, 0x40302010}, {0x89c, 0x00706050},
 168         {0x900, 0x00000000}, {0x904, 0x00000023},
 169         {0x908, 0x00000000}, {0x90c, 0x81121111},
 170         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 171         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 172         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 173         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 174         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 175         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 176         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 177         {0xa78, 0x00000900},
 178         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 179         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 180         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 181         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 182         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 183         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 184         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 185         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 186         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 187         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 188         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 189         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 190         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 191         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 192         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 193         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 194         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 195         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 196         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 197         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 198         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 199         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 200         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 201         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 202         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 203         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 204         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 205         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 206         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 207         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 208         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 209         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 210         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 211         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 212         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 213         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 214         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 215         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 216         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 217         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 218         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 219         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 220         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 221         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 222         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 223         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 224         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 225         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 226         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 227         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 228         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 229         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 230         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 231         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 232         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 233         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 234         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 235         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 236         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 237         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 238         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 239         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 240         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 241         {0xf00, 0x00000300},
 242         {0xffff, 0xffffffff},
 243 };
 244
 245 static const struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 246         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 247         {0x800, 0x80040002}, {0x804, 0x00000003},
 248         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 249         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 250         {0x818, 0x02200385}, {0x81c, 0x00000000},
 251         {0x820, 0x01000100}, {0x824, 0x00390004},
 252         {0x828, 0x01000100}, {0x82c, 0x00390004},
 253         {0x830, 0x27272727}, {0x834, 0x27272727},
 254         {0x838, 0x27272727}, {0x83c, 0x27272727},
 255         {0x840, 0x00010000}, {0x844, 0x00010000},
 256         {0x848, 0x27272727}, {0x84c, 0x27272727},
 257         {0x850, 0x00000000}, {0x854, 0x00000000},
 258         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 259         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 260         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 261         {0x870, 0x07000700}, {0x874, 0x22184000},
 262         {0x878, 0x08080808}, {0x87c, 0x00000000},
 263         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 264         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 265         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 266         {0x898, 0x40302010}, {0x89c, 0x00706050},
 267         {0x900, 0x00000000}, {0x904, 0x00000023},
 268         {0x908, 0x00000000}, {0x90c, 0x81121313},
 269         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 270         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 271         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 272         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 273         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 274         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 275         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 276         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 277         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 278         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 279         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 280         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 281         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 282         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 283         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 284         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 285         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 286         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 287         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 288         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 289         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 290         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 291         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 292         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 293         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 294         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 295         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 296         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 297         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 298         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 299         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 300         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 301         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 302         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 303         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 304         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 305         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 306         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 307         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 308         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 309         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 310         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 311         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 312         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 313         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 314         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 315         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 316         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 317         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 318         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 319         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 320         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 321         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 322         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 323         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 324         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 325         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 326         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 327         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 328         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 329         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 330         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 331         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 332         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 333         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 334         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 335         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 336         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 337         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 338         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 339         {0xf00, 0x00000300},
 340         {0xffff, 0xffffffff},
 341 };
 342
 343 static const struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 344         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 345         {0x040, 0x000c0004}, {0x800, 0x80040000},
 346         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 347         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 348         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 349         {0x81c, 0x00000000}, {0x820, 0x01000100},
 350         {0x824, 0x00390204}, {0x828, 0x00000000},
 351         {0x82c, 0x00000000}, {0x830, 0x00000000},
 352         {0x834, 0x00000000}, {0x838, 0x00000000},
 353         {0x83c, 0x00000000}, {0x840, 0x00010000},
 354         {0x844, 0x00000000}, {0x848, 0x00000000},
 355         {0x84c, 0x00000000}, {0x850, 0x00000000},
 356         {0x854, 0x00000000}, {0x858, 0x569a569a},
 357         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 358         {0x864, 0x061f0130}, {0x868, 0x00000000},
 359         {0x86c, 0x20202000}, {0x870, 0x03000300},
 360         {0x874, 0x22004000}, {0x878, 0x00000808},
 361         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 362         {0x884, 0x000004d5}, {0x888, 0x00000000},
 363         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 364         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 365         {0x89c, 0x00706050}, {0x900, 0x00000000},
 366         {0x904, 0x00000023}, {0x908, 0x00000000},
 367         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 368         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 369         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 370         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 371         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 372         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 373         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 374         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 375         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 376         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 377         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 378         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 379         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 380         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 381         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 382         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 383         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 384         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 385         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 386         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 387         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 388         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 389         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 390         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 391         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 392         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 393         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 394         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 395         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 396         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 397         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 398         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 399         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 400         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 401         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 402         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 403         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 404         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 405         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 406         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 407         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 408         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 409         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 410         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 411         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 412         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 413         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 414         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 415         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 416         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 417         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 418         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 419         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 420         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 421         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 422         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 423         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 424         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 425         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 426         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 427         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 428         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 429         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 430         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 431         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 432         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 433         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 434         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 435         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 436         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 437         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 438         {0xf00, 0x00000300},
 439         {0xffff, 0xffffffff},
 440 };
 441
 442 static const struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 443         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 444         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 445         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 446         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 447         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 448         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 449         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 450         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 451         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 452         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 453         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 454         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 455         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 456         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 457         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 458         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 459         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 460         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 461         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 462         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 463         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 464         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 465         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 466         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 467         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 468         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 469         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 470         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 471         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 472         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 473         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 474         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 475         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 476         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 477         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 478         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 479         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 480         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 481         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 482         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 483         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 484         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 485         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 486         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 487         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 488         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 489         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 490         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 491         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 492         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 493         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 494         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 495         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 496         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 497         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 498         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 499         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 500         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 501         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 502         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 503         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 504         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 505         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 506         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 507         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 508         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 509         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 510         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 511         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 512         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 513         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 514         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 515         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 516         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 517         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 518         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 519         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 520         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 521         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 522         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 523         {0xffff, 0xffffffff}
 524 };
 525
 526 static const struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 527         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 528         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 529         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 530         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 531         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 532         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 533         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 534         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 535         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 536         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 537         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 538         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 539         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 540         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 541         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 542         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 543         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 544         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 545         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 546         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 547         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 548         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 549         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 550         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 551         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 552         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 553         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 554         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 555         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 556         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 557         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 558         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 559         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 560         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 561         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 562         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 563         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 564         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 565         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 566         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 567         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 568         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 569         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 570         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 571         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 572         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 573         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 574         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 575         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 576         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 577         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 578         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 579         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 580         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 581         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 582         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 583         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 584         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 585         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 586         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 587         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 588         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 589         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 590         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 591         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 592         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 593         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 594         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 595         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 596         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 597         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 598         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 599         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 600         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 601         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 602         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 603         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 604         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 605         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 606         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 607         {0xffff, 0xffffffff}
 608 };
 609
 610 static const struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 611         {       /* RF_A */
 612                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 613                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 614                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 615                 .hspiread = REG_HSPI_XA_READBACK,
 616                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 617                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 618         },
 619         {       /* RF_B */
 620                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 621                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 622                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 623                 .hspiread = REG_HSPI_XB_READBACK,
 624                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 625                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 626         },
 627 };
 628
 629 const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 630         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 631         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 632         REG_OFDM0_ENERGY_CCA_THRES,
 633         REG_OFDM0_AGC_RSSI_TABLE,
 634         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 635         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 636         REG_OFDM0_XC_TX_AFE,
 637         REG_OFDM0_XD_TX_AFE,
 638         REG_OFDM0_RX_IQ_EXT_ANTA
 639 };
 640
 641 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 642 {
 643         struct usb_device *udev = priv->udev;
 644         int len;
 645         u8 data;
 646
 647         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 648                 addr |= 0x8000;
 649
 650         mutex_lock(&priv->usb_buf_mutex);
 651         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 652                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 653                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 654                               RTW_USB_CONTROL_MSG_TIMEOUT);
 655         data = priv->usb_buf.val8;
 656         mutex_unlock(&priv->usb_buf_mutex);
 657
 658         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 659                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 660                          __func__, addr, data, len);
 661         return data;
 662 }
 663
 664 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 665 {
 666         struct usb_device *udev = priv->udev;
 667         int len;
 668         u16 data;
 669
 670         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 671                 addr |= 0x8000;
 672
 673         mutex_lock(&priv->usb_buf_mutex);
 674         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 675                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 676                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
 677                               RTW_USB_CONTROL_MSG_TIMEOUT);
 678         data = le16_to_cpu(priv->usb_buf.val16);
 679         mutex_unlock(&priv->usb_buf_mutex);
 680
 681         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 682                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
 683                          __func__, addr, data, len);
 684         return data;
 685 }
 686
 687 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
 688 {
 689         struct usb_device *udev = priv->udev;
 690         int len;
 691         u32 data;
 692
 693         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 694                 addr |= 0x8000;
 695
 696         mutex_lock(&priv->usb_buf_mutex);
 697         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 698                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 699                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
 700                               RTW_USB_CONTROL_MSG_TIMEOUT);
 701         data = le32_to_cpu(priv->usb_buf.val32);
 702         mutex_unlock(&priv->usb_buf_mutex);
 703
 704         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 705                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
 706                          __func__, addr, data, len);
 707         return data;
 708 }
 709
 710 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
 711 {
 712         struct usb_device *udev = priv->udev;
 713         int ret;
 714
 715         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 716                 addr |= 0x8000;
 717
 718         mutex_lock(&priv->usb_buf_mutex);
 719         priv->usb_buf.val8 = val;
 720         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 721                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 722                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 723                               RTW_USB_CONTROL_MSG_TIMEOUT);
 724
 725         mutex_unlock(&priv->usb_buf_mutex);
 726
 727         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 728                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
 729                          __func__, addr, val);
 730         return ret;
 731 }
 732
 733 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
 734 {
 735         struct usb_device *udev = priv->udev;
 736         int ret;
 737
 738         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 739                 addr |= 0x8000;
 740
 741         mutex_lock(&priv->usb_buf_mutex);
 742         priv->usb_buf.val16 = cpu_to_le16(val);
 743         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 744                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 745                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
 746                               RTW_USB_CONTROL_MSG_TIMEOUT);
 747         mutex_unlock(&priv->usb_buf_mutex);
 748
 749         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 750                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
 751                          __func__, addr, val);
 752         return ret;
 753 }
 754
 755 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
 756 {
 757         struct usb_device *udev = priv->udev;
 758         int ret;
 759
 760         if (priv->rtl_chip == RTL8710B && addr <= 0xff)
 761                 addr |= 0x8000;
 762
 763         mutex_lock(&priv->usb_buf_mutex);
 764         priv->usb_buf.val32 = cpu_to_le32(val);
 765         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 766                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 767                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
 768                               RTW_USB_CONTROL_MSG_TIMEOUT);
 769         mutex_unlock(&priv->usb_buf_mutex);
 770
 771         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 772                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
 773                          __func__, addr, val);
 774         return ret;
 775 }
 776
 777 int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
 778 {
 779         u8 val8;
 780
 781         val8 = rtl8xxxu_read8(priv, addr);
 782         val8 |= bits;
 783         return rtl8xxxu_write8(priv, addr, val8);
 784 }
 785
 786 int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits)
 787 {
 788         u8 val8;
 789
 790         val8 = rtl8xxxu_read8(priv, addr);
 791         val8 &= ~bits;
 792         return rtl8xxxu_write8(priv, addr, val8);
 793 }
 794
 795 int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
 796 {
 797         u16 val16;
 798
 799         val16 = rtl8xxxu_read16(priv, addr);
 800         val16 |= bits;
 801         return rtl8xxxu_write16(priv, addr, val16);
 802 }
 803
 804 int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits)
 805 {
 806         u16 val16;
 807
 808         val16 = rtl8xxxu_read16(priv, addr);
 809         val16 &= ~bits;
 810         return rtl8xxxu_write16(priv, addr, val16);
 811 }
 812
 813 int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
 814 {
 815         u32 val32;
 816
 817         val32 = rtl8xxxu_read32(priv, addr);
 818         val32 |= bits;
 819         return rtl8xxxu_write32(priv, addr, val32);
 820 }
 821
 822 int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits)
 823 {
 824         u32 val32;
 825
 826         val32 = rtl8xxxu_read32(priv, addr);
 827         val32 &= ~bits;
 828         return rtl8xxxu_write32(priv, addr, val32);
 829 }
 830
 831 int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr,
 832                           u32 mask, u32 val)
 833 {
 834         u32 orig, new, shift;
 835
 836         shift = __ffs(mask);
 837
 838         orig = rtl8xxxu_read32(priv, addr);
 839         new = (orig & ~mask) | ((val << shift) & mask);
 840         return rtl8xxxu_write32(priv, addr, new);
 841 }
 842
 843 int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv,
 844                               enum rtl8xxxu_rfpath path, u8 reg,
 845                               u32 mask, u32 val)
 846 {
 847         u32 orig, new, shift;
 848
 849         shift = __ffs(mask);
 850
 851         orig = rtl8xxxu_read_rfreg(priv, path, reg);
 852         new = (orig & ~mask) | ((val << shift) & mask);
 853         return rtl8xxxu_write_rfreg(priv, path, reg, new);
 854 }
 855
 856 static int
 857 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
 858 {
 859         struct usb_device *udev = priv->udev;
 860         int blocksize = priv->fops->writeN_block_size;
 861         int ret, i, count, remainder;
 862
 863         count = len / blocksize;
 864         remainder = len % blocksize;
 865
 866         for (i = 0; i < count; i++) {
 867                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 868                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 869                                       addr, 0, buf, blocksize,
 870                                       RTW_USB_CONTROL_MSG_TIMEOUT);
 871                 if (ret != blocksize)
 872                         goto write_error;
 873
 874                 addr += blocksize;
 875                 buf += blocksize;
 876         }
 877
 878         if (remainder) {
 879                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
 880                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
 881                                       addr, 0, buf, remainder,
 882                                       RTW_USB_CONTROL_MSG_TIMEOUT);
 883                 if (ret != remainder)
 884                         goto write_error;
 885         }
 886
 887         return len;
 888
 889 write_error:
 890         dev_info(&udev->dev,
 891                  "%s: Failed to write block at addr: %04x size: %04x\n",
 892                  __func__, addr, blocksize);
 893         return -EAGAIN;
 894 }
 895
 896 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
 897                         enum rtl8xxxu_rfpath path, u8 reg)
 898 {
 899         u32 hssia, val32, retval;
 900
 901         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
 902         if (path != RF_A)
 903                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
 904         else
 905                 val32 = hssia;
 906
 907         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
 908         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
 909         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
 910         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
 911         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
 912
 913         udelay(10);
 914
 915         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
 916         udelay(100);
 917
 918         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
 919         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
 920         udelay(10);
 921
 922         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
 923         if (val32 & FPGA0_HSSI_PARM1_PI)
 924                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
 925         else
 926                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
 927
 928         retval &= 0xfffff;
 929
 930         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
 931                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
 932                          __func__, reg, retval);
 933         return retval;
 934 }
 935
 936 /*
 937  * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can
 938  * have write issues in high temperature conditions. We may have to
 939  * retry writing them.
 940  */
 941 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
 942                          enum rtl8xxxu_rfpath path, u8 reg, u32 data)
 943 {
 944         int ret, retval;
 945         u32 dataaddr, val32;
 946
 947         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
 948                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
 949                          __func__, reg, data);
 950
 951         data &= FPGA0_LSSI_PARM_DATA_MASK;
 952         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
 953
 954         if (priv->rtl_chip == RTL8192E) {
 955                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
 956                 val32 &= ~0x20000;
 957                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
 958         }
 959
 960         /* Use XB for path B */
 961         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
 962         if (ret != sizeof(dataaddr))
 963                 retval = -EIO;
 964         else
 965                 retval = 0;
 966
 967         udelay(1);
 968
 969         if (priv->rtl_chip == RTL8192E) {
 970                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
 971                 val32 |= 0x20000;
 972                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
 973         }
 974
 975         return retval;
 976 }
 977
 978 static int
 979 rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
 980 {
 981         struct device *dev = &priv->udev->dev;
 982         int mbox_nr, retry, retval = 0;
 983         int mbox_reg, mbox_ext_reg;
 984         u8 val8;
 985
 986         mutex_lock(&priv->h2c_mutex);
 987
 988         mbox_nr = priv->next_mbox;
 989         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
 990         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
 991
 992         /*
 993          * MBOX ready?
 994          */
 995         retry = 100;
 996         do {
 997                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
 998                 if (!(val8 & BIT(mbox_nr)))
 999                         break;
1000         } while (retry--);
1001
1002         if (!retry) {
1003                 dev_info(dev, "%s: Mailbox busy\n", __func__);
1004                 retval = -EBUSY;
1005                 goto error;
1006         }
1007
1008         /*
1009          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1010          */
1011         if (len > sizeof(u32)) {
1012                 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
1013                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1014                         dev_info(dev, "H2C_EXT %04x\n",
1015                                  le16_to_cpu(h2c->raw.ext));
1016         }
1017         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1018         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1019                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1020
1021         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1022
1023 error:
1024         mutex_unlock(&priv->h2c_mutex);
1025         return retval;
1026 }
1027
1028 int
1029 rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
1030 {
1031         struct device *dev = &priv->udev->dev;
1032         int mbox_nr, retry, retval = 0;
1033         int mbox_reg, mbox_ext_reg;
1034         u8 val8;
1035
1036         mutex_lock(&priv->h2c_mutex);
1037
1038         mbox_nr = priv->next_mbox;
1039         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1040         mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
1041
1042         /*
1043          * MBOX ready?
1044          */
1045         retry = 100;
1046         do {
1047                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1048                 if (!(val8 & BIT(mbox_nr)))
1049                         break;
1050         } while (retry--);
1051
1052         if (!retry) {
1053                 dev_info(dev, "%s: Mailbox busy\n", __func__);
1054                 retval = -EBUSY;
1055                 goto error;
1056         }
1057
1058         /*
1059          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1060          */
1061         if (len > sizeof(u32)) {
1062                 rtl8xxxu_write32(priv, mbox_ext_reg,
1063                                  le32_to_cpu(h2c->raw_wide.ext));
1064                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1065                         dev_info(dev, "H2C_EXT %08x\n",
1066                                  le32_to_cpu(h2c->raw_wide.ext));
1067         }
1068         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1069         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1070                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1071
1072         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1073
1074 error:
1075         mutex_unlock(&priv->h2c_mutex);
1076         return retval;
1077 }
1078
1079 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
1080 {
1081         u8 val8;
1082         u32 val32;
1083
1084         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1085         val8 |= BIT(0) | BIT(3);
1086         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1087
1088         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1089         val32 &= ~(BIT(4) | BIT(5));
1090         val32 |= BIT(3);
1091         if (priv->rf_paths == 2) {
1092                 val32 &= ~(BIT(20) | BIT(21));
1093                 val32 |= BIT(19);
1094         }
1095         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1096
1097         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1098         val32 &= ~OFDM_RF_PATH_TX_MASK;
1099         if (priv->tx_paths == 2)
1100                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1101         else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1102                 val32 |= OFDM_RF_PATH_TX_B;
1103         else
1104                 val32 |= OFDM_RF_PATH_TX_A;
1105         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1106
1107         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1108         val32 &= ~FPGA_RF_MODE_JAPAN;
1109         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1110
1111         if (priv->rf_paths == 2)
1112                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1113         else
1114                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1115
1116         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1117         if (priv->rf_paths == 2)
1118                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1119
1120         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1121 }
1122
1123 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1124 {
1125         u8 sps0;
1126         u32 val32;
1127
1128         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1129
1130         /* RF RX code for preamble power saving */
1131         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1132         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1133         if (priv->rf_paths == 2)
1134                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1135         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1136
1137         /* Disable TX for four paths */
1138         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1139         val32 &= ~OFDM_RF_PATH_TX_MASK;
1140         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1141
1142         /* Enable power saving */
1143         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1144         val32 |= FPGA_RF_MODE_JAPAN;
1145         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1146
1147         /* AFE control register to power down bits [30:22] */
1148         if (priv->rf_paths == 2)
1149                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1150         else
1151                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1152
1153         /* Power down RF module */
1154         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1155         if (priv->rf_paths == 2)
1156                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1157
1158         sps0 &= ~(BIT(0) | BIT(3));
1159         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1160 }
1161
1162 static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1163 {
1164         u8 val8;
1165
1166         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1167         val8 &= ~BIT(6);
1168         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1169
1170         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1171         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1172         val8 &= ~BIT(0);
1173         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1174 }
1175
1176 static void rtl8xxxu_start_tx_beacon(struct rtl8xxxu_priv *priv)
1177 {
1178         u8 val8;
1179
1180         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1181         val8 |= EN_BCNQ_DL >> 16;
1182         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1183
1184         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x80);
1185         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1186         val8 &= 0xF0;
1187         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1188 }
1189
1190
1191 /*
1192  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1193  * supports the 2.4GHz band, so channels 1 - 14:
1194  *  group 0: channels 1 - 3
1195  *  group 1: channels 4 - 9
1196  *  group 2: channels 10 - 14
1197  *
1198  * Note: We index from 0 in the code
1199  */
1200 static int rtl8xxxu_gen1_channel_to_group(int channel)
1201 {
1202         int group;
1203
1204         if (channel < 4)
1205                 group = 0;
1206         else if (channel < 10)
1207                 group = 1;
1208         else
1209                 group = 2;
1210
1211         return group;
1212 }
1213
1214 /*
1215  * Valid for rtl8723bu and rtl8192eu
1216  */
1217 int rtl8xxxu_gen2_channel_to_group(int channel)
1218 {
1219         int group;
1220
1221         if (channel < 3)
1222                 group = 0;
1223         else if (channel < 6)
1224                 group = 1;
1225         else if (channel < 9)
1226                 group = 2;
1227         else if (channel < 12)
1228                 group = 3;
1229         else
1230                 group = 4;
1231
1232         return group;
1233 }
1234
1235 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1236 {
1237         struct rtl8xxxu_priv *priv = hw->priv;
1238         u32 val32, rsr;
1239         u8 val8, opmode;
1240         bool ht = true;
1241         int sec_ch_above, channel;
1242         int i;
1243
1244         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1245         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1246         channel = hw->conf.chandef.chan->hw_value;
1247
1248         switch (hw->conf.chandef.width) {
1249         case NL80211_CHAN_WIDTH_20_NOHT:
1250                 ht = false;
1251                 fallthrough;
1252         case NL80211_CHAN_WIDTH_20:
1253                 opmode |= BW_OPMODE_20MHZ;
1254                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1255
1256                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1257                 val32 &= ~FPGA_RF_MODE;
1258                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1259
1260                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1261                 val32 &= ~FPGA_RF_MODE;
1262                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1263
1264                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1265                 val32 |= FPGA0_ANALOG2_20MHZ;
1266                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1267                 break;
1268         case NL80211_CHAN_WIDTH_40:
1269                 if (hw->conf.chandef.center_freq1 >
1270                     hw->conf.chandef.chan->center_freq) {
1271                         sec_ch_above = 1;
1272                         channel += 2;
1273                 } else {
1274                         sec_ch_above = 0;
1275                         channel -= 2;
1276                 }
1277
1278                 opmode &= ~BW_OPMODE_20MHZ;
1279                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1280                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1281                 if (sec_ch_above)
1282                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1283                 else
1284                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1285                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1286
1287                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1288                 val32 |= FPGA_RF_MODE;
1289                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1290
1291                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1292                 val32 |= FPGA_RF_MODE;
1293                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1294
1295                 /*
1296                  * Set Control channel to upper or lower. These settings
1297                  * are required only for 40MHz
1298                  */
1299                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1300                 val32 &= ~CCK0_SIDEBAND;
1301                 if (!sec_ch_above)
1302                         val32 |= CCK0_SIDEBAND;
1303                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1304
1305                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1306                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1307                 if (sec_ch_above)
1308                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1309                 else
1310                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1311                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1312
1313                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1314                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1315                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1316
1317                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1318                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1319                 if (sec_ch_above)
1320                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1321                 else
1322                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1323                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1324                 break;
1325
1326         default:
1327                 break;
1328         }
1329
1330         for (i = RF_A; i < priv->rf_paths; i++) {
1331                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1332                 val32 &= ~MODE_AG_CHANNEL_MASK;
1333                 val32 |= channel;
1334                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1335         }
1336
1337         if (ht)
1338                 val8 = 0x0e;
1339         else
1340                 val8 = 0x0a;
1341
1342         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1343         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1344
1345         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1346         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1347
1348         for (i = RF_A; i < priv->rf_paths; i++) {
1349                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1350                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1351                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1352                 else
1353                         val32 |= MODE_AG_CHANNEL_20MHZ;
1354                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1355         }
1356 }
1357
1358 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1359 {
1360         struct rtl8xxxu_priv *priv = hw->priv;
1361         u32 val32;
1362         u8 val8, subchannel;
1363         u16 rf_mode_bw;
1364         bool ht = true;
1365         int sec_ch_above, channel;
1366         int i;
1367
1368         rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1369         rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1370         channel = hw->conf.chandef.chan->hw_value;
1371
1372 /* Hack */
1373         subchannel = 0;
1374
1375         switch (hw->conf.chandef.width) {
1376         case NL80211_CHAN_WIDTH_20_NOHT:
1377                 ht = false;
1378                 fallthrough;
1379         case NL80211_CHAN_WIDTH_20:
1380                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1381                 subchannel = 0;
1382
1383                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1384                 val32 &= ~FPGA_RF_MODE;
1385                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1386
1387                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1388                 val32 &= ~FPGA_RF_MODE;
1389                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1390
1391                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1392                 val32 &= ~(BIT(30) | BIT(31));
1393                 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1394
1395                 break;
1396         case NL80211_CHAN_WIDTH_40:
1397                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1398
1399                 if (hw->conf.chandef.center_freq1 >
1400                     hw->conf.chandef.chan->center_freq) {
1401                         sec_ch_above = 1;
1402                         channel += 2;
1403                 } else {
1404                         sec_ch_above = 0;
1405                         channel -= 2;
1406                 }
1407
1408                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1409                 val32 |= FPGA_RF_MODE;
1410                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1411
1412                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1413                 val32 |= FPGA_RF_MODE;
1414                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1415
1416                 /*
1417                  * Set Control channel to upper or lower. These settings
1418                  * are required only for 40MHz
1419                  */
1420                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1421                 val32 &= ~CCK0_SIDEBAND;
1422                 if (!sec_ch_above)
1423                         val32 |= CCK0_SIDEBAND;
1424                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1425
1426                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1427                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1428                 if (sec_ch_above)
1429                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1430                 else
1431                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1432                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1433
1434                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1435                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1436                 if (sec_ch_above)
1437                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1438                 else
1439                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1440                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1441                 break;
1442         case NL80211_CHAN_WIDTH_80:
1443                 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1444                 break;
1445         default:
1446                 break;
1447         }
1448
1449         for (i = RF_A; i < priv->rf_paths; i++) {
1450                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1451                 val32 &= ~MODE_AG_CHANNEL_MASK;
1452                 val32 |= channel;
1453                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1454         }
1455
1456         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1457         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1458
1459         if (ht)
1460                 val8 = 0x0e;
1461         else
1462                 val8 = 0x0a;
1463
1464         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1465         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1466
1467         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1468         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1469
1470         for (i = RF_A; i < priv->rf_paths; i++) {
1471                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1472                 val32 &= ~MODE_AG_BW_MASK;
1473                 switch(hw->conf.chandef.width) {
1474                 case NL80211_CHAN_WIDTH_80:
1475                         val32 |= MODE_AG_BW_80MHZ_8723B;
1476                         break;
1477                 case NL80211_CHAN_WIDTH_40:
1478                         val32 |= MODE_AG_BW_40MHZ_8723B;
1479                         break;
1480                 default:
1481                         val32 |= MODE_AG_BW_20MHZ_8723B;
1482                         break;
1483                 }
1484                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1485         }
1486 }
1487
1488 void
1489 rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1490 {
1491         struct rtl8xxxu_power_base *power_base = priv->power_base;
1492         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1493         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1494         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1495         u8 val8;
1496         int group, i;
1497
1498         group = rtl8xxxu_gen1_channel_to_group(channel);
1499
1500         cck[0] = priv->cck_tx_power_index_A[group] - 1;
1501         cck[1] = priv->cck_tx_power_index_B[group] - 1;
1502
1503         if (priv->hi_pa) {
1504                 if (cck[0] > 0x20)
1505                         cck[0] = 0x20;
1506                 if (cck[1] > 0x20)
1507                         cck[1] = 0x20;
1508         }
1509
1510         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1511         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1512         if (ofdm[0])
1513                 ofdm[0] -= 1;
1514         if (ofdm[1])
1515                 ofdm[1] -= 1;
1516
1517         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1518         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1519
1520         mcsbase[0] = ofdm[0];
1521         mcsbase[1] = ofdm[1];
1522         if (!ht40) {
1523                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1524                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1525         }
1526
1527         if (priv->tx_paths > 1) {
1528                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1529                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1530                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1531                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1532         }
1533
1534         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1535                 dev_info(&priv->udev->dev,
1536                          "%s: Setting TX power CCK A: %02x, "
1537                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1538                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1539
1540         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1541                 if (cck[i] > RF6052_MAX_TX_PWR)
1542                         cck[i] = RF6052_MAX_TX_PWR;
1543                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1544                         ofdm[i] = RF6052_MAX_TX_PWR;
1545         }
1546
1547         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1548         val32 &= 0xffff00ff;
1549         val32 |= (cck[0] << 8);
1550         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1551
1552         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1553         val32 &= 0xff;
1554         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1555         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1556
1557         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1558         val32 &= 0xffffff00;
1559         val32 |= cck[1];
1560         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1561
1562         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1563         val32 &= 0xff;
1564         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1565         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1566
1567         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1568                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1569         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1570                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1571
1572         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1573                          ofdm_a + power_base->reg_0e00);
1574         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1575                          ofdm_b + power_base->reg_0830);
1576
1577         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1578                          ofdm_a + power_base->reg_0e04);
1579         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1580                          ofdm_b + power_base->reg_0834);
1581
1582         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1583                 mcsbase[0] << 16 | mcsbase[0] << 24;
1584         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1585                 mcsbase[1] << 16 | mcsbase[1] << 24;
1586
1587         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1588                          mcs_a + power_base->reg_0e10);
1589         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1590                          mcs_b + power_base->reg_083c);
1591
1592         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1593                          mcs_a + power_base->reg_0e14);
1594         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1595                          mcs_b + power_base->reg_0848);
1596
1597         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1598                          mcs_a + power_base->reg_0e18);
1599         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1600                          mcs_b + power_base->reg_084c);
1601
1602         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1603                          mcs_a + power_base->reg_0e1c);
1604         for (i = 0; i < 3; i++) {
1605                 if (i != 2)
1606                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1607                 else
1608                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1609                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1610         }
1611         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1612                          mcs_b + power_base->reg_0868);
1613         for (i = 0; i < 3; i++) {
1614                 if (i != 2)
1615                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1616                 else
1617                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1618                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1619         }
1620 }
1621
1622 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1623                                   enum nl80211_iftype linktype)
1624 {
1625         u8 val8;
1626
1627         val8 = rtl8xxxu_read8(priv, REG_MSR);
1628         val8 &= ~MSR_LINKTYPE_MASK;
1629
1630         switch (linktype) {
1631         case NL80211_IFTYPE_UNSPECIFIED:
1632                 val8 |= MSR_LINKTYPE_NONE;
1633                 break;
1634         case NL80211_IFTYPE_ADHOC:
1635                 val8 |= MSR_LINKTYPE_ADHOC;
1636                 break;
1637         case NL80211_IFTYPE_STATION:
1638                 val8 |= MSR_LINKTYPE_STATION;
1639                 break;
1640         case NL80211_IFTYPE_AP:
1641                 val8 |= MSR_LINKTYPE_AP;
1642                 break;
1643         default:
1644                 goto out;
1645         }
1646
1647         rtl8xxxu_write8(priv, REG_MSR, val8);
1648 out:
1649         return;
1650 }
1651
1652 static void
1653 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1654 {
1655         u16 val16;
1656
1657         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1658                  RETRY_LIMIT_SHORT_MASK) |
1659                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1660                  RETRY_LIMIT_LONG_MASK);
1661
1662         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1663 }
1664
1665 static void
1666 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1667 {
1668         u16 val16;
1669
1670         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1671                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1672
1673         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1674 }
1675
1676 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1677 {
1678         struct device *dev = &priv->udev->dev;
1679         char cut = 'A' + priv->chip_cut;
1680
1681         dev_info(dev,
1682                  "RTL%s rev %c (%s) romver %d, %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1683                  priv->chip_name, cut, priv->chip_vendor, priv->rom_rev,
1684                  priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1685                  priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1686                  priv->hi_pa);
1687
1688         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1689 }
1690
1691 void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor)
1692 {
1693         if (vendor) {
1694                 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1695                 priv->vendor_umc = 1;
1696         } else {
1697                 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1698         }
1699 }
1700
1701 void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor)
1702 {
1703         switch (vendor) {
1704         case SYS_CFG_VENDOR_ID_TSMC:
1705                 strscpy(priv->chip_vendor, "TSMC", sizeof(priv->chip_vendor));
1706                 break;
1707         case SYS_CFG_VENDOR_ID_SMIC:
1708                 strscpy(priv->chip_vendor, "SMIC", sizeof(priv->chip_vendor));
1709                 priv->vendor_smic = 1;
1710                 break;
1711         case SYS_CFG_VENDOR_ID_UMC:
1712                 strscpy(priv->chip_vendor, "UMC", sizeof(priv->chip_vendor));
1713                 priv->vendor_umc = 1;
1714                 break;
1715         default:
1716                 strscpy(priv->chip_vendor, "unknown", sizeof(priv->chip_vendor));
1717         }
1718 }
1719
1720 void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv)
1721 {
1722         u16 val16;
1723
1724         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1725
1726         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1727                 priv->ep_tx_high_queue = 1;
1728                 priv->ep_tx_count++;
1729         }
1730
1731         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1732                 priv->ep_tx_normal_queue = 1;
1733                 priv->ep_tx_count++;
1734         }
1735
1736         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1737                 priv->ep_tx_low_queue = 1;
1738                 priv->ep_tx_count++;
1739         }
1740 }
1741
1742 int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv)
1743 {
1744         struct device *dev = &priv->udev->dev;
1745
1746         switch (priv->nr_out_eps) {
1747         case 6:
1748         case 5:
1749         case 4:
1750         case 3:
1751                 priv->ep_tx_low_queue = 1;
1752                 priv->ep_tx_count++;
1753                 fallthrough;
1754         case 2:
1755                 priv->ep_tx_normal_queue = 1;
1756                 priv->ep_tx_count++;
1757                 fallthrough;
1758         case 1:
1759                 priv->ep_tx_high_queue = 1;
1760                 priv->ep_tx_count++;
1761                 break;
1762         default:
1763                 dev_info(dev, "Unsupported USB TX end-points\n");
1764                 return -ENOTSUPP;
1765         }
1766
1767         return 0;
1768 }
1769
1770 int
1771 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1772 {
1773         int i;
1774         u8 val8;
1775         u32 val32;
1776
1777         /* Write Address */
1778         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1779         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1780         val8 &= 0xfc;
1781         val8 |= (offset >> 8) & 0x03;
1782         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1783
1784         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1785         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1786
1787         /* Poll for data read */
1788         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1789         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1790                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1791                 if (val32 & BIT(31))
1792                         break;
1793         }
1794
1795         if (i == RTL8XXXU_MAX_REG_POLL)
1796                 return -EIO;
1797
1798         udelay(50);
1799         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1800
1801         *data = val32 & 0xff;
1802         return 0;
1803 }
1804
1805 int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1806 {
1807         struct device *dev = &priv->udev->dev;
1808         int i, ret = 0;
1809         u8 val8, word_mask, header, extheader;
1810         u16 val16, efuse_addr, offset;
1811         u32 val32;
1812
1813         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1814         if (val16 & EEPROM_ENABLE)
1815                 priv->has_eeprom = 1;
1816         if (val16 & EEPROM_BOOT)
1817                 priv->boot_eeprom = 1;
1818
1819         if (priv->is_multi_func) {
1820                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1821                 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1822                 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1823         }
1824
1825         dev_dbg(dev, "Booting from %s\n",
1826                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1827
1828         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1829
1830         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1831         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1832         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1833                 val16 |= SYS_ISO_PWC_EV12V;
1834                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1835         }
1836         /*  Reset: 0x0000[28], default valid */
1837         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1838         if (!(val16 & SYS_FUNC_ELDR)) {
1839                 val16 |= SYS_FUNC_ELDR;
1840                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1841         }
1842
1843         /*
1844          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1845          */
1846         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1847         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1848                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1849                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1850         }
1851
1852         /* Default value is 0xff */
1853         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1854
1855         efuse_addr = 0;
1856         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1857                 u16 map_addr;
1858
1859                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1860                 if (ret || header == 0xff)
1861                         goto exit;
1862
1863                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1864                         offset = (header & 0xe0) >> 5;
1865
1866                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1867                                                    &extheader);
1868                         if (ret)
1869                                 goto exit;
1870                         /* All words disabled */
1871                         if ((extheader & 0x0f) == 0x0f)
1872                                 continue;
1873
1874                         offset |= ((extheader & 0xf0) >> 1);
1875                         word_mask = extheader & 0x0f;
1876                 } else {
1877                         offset = (header >> 4) & 0x0f;
1878                         word_mask = header & 0x0f;
1879                 }
1880
1881                 /* Get word enable value from PG header */
1882
1883                 /* We have 8 bits to indicate validity */
1884                 map_addr = offset * 8;
1885                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1886                         /* Check word enable condition in the section */
1887                         if (word_mask & BIT(i)) {
1888                                 map_addr += 2;
1889                                 continue;
1890                         }
1891
1892                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1893                         if (ret)
1894                                 goto exit;
1895                         if (map_addr >= EFUSE_MAP_LEN - 1) {
1896                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1897                                          "efuse corrupt!\n",
1898                                          __func__, map_addr);
1899                                 ret = -EINVAL;
1900                                 goto exit;
1901                         }
1902                         priv->efuse_wifi.raw[map_addr++] = val8;
1903
1904                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1905                         if (ret)
1906                                 goto exit;
1907                         priv->efuse_wifi.raw[map_addr++] = val8;
1908                 }
1909         }
1910
1911 exit:
1912         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1913
1914         return ret;
1915 }
1916
1917 static void rtl8xxxu_dump_efuse(struct rtl8xxxu_priv *priv)
1918 {
1919         dev_info(&priv->udev->dev,
1920                  "Dumping efuse for RTL%s (0x%02x bytes):\n",
1921                  priv->chip_name, EFUSE_MAP_LEN);
1922
1923         print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
1924                        priv->efuse_wifi.raw, EFUSE_MAP_LEN, true);
1925 }
1926
1927 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1928 {
1929         u8 val8;
1930         u16 sys_func;
1931
1932         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1933         val8 &= ~BIT(0);
1934         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1935
1936         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1937         sys_func &= ~SYS_FUNC_CPU_ENABLE;
1938         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1939
1940         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1941         val8 |= BIT(0);
1942         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1943
1944         sys_func |= SYS_FUNC_CPU_ENABLE;
1945         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1946 }
1947
1948 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1949 {
1950         struct device *dev = &priv->udev->dev;
1951         u16 reg_mcu_fw_dl;
1952         int ret = 0, i;
1953         u32 val32;
1954
1955         if (priv->rtl_chip == RTL8710B)
1956                 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
1957         else
1958                 reg_mcu_fw_dl = REG_MCU_FW_DL;
1959
1960         /* Poll checksum report */
1961         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1962                 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1963                 if (val32 & MCU_FW_DL_CSUM_REPORT)
1964                         break;
1965         }
1966
1967         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1968                 dev_warn(dev, "Firmware checksum poll timed out\n");
1969                 ret = -EAGAIN;
1970                 goto exit;
1971         }
1972
1973         val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1974         val32 |= MCU_FW_DL_READY;
1975         val32 &= ~MCU_WINT_INIT_READY;
1976         rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
1977
1978         /*
1979          * Reset the 8051 in order for the firmware to start running,
1980          * otherwise it won't come up on the 8192eu
1981          */
1982         priv->fops->reset_8051(priv);
1983
1984         /* Wait for firmware to become ready */
1985         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1986                 val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
1987                 if (val32 & MCU_WINT_INIT_READY)
1988                         break;
1989
1990                 udelay(100);
1991         }
1992
1993         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1994                 dev_warn(dev, "Firmware failed to start\n");
1995                 ret = -EAGAIN;
1996                 goto exit;
1997         }
1998
1999         /*
2000          * Init H2C command
2001          */
2002         if (priv->fops->init_reg_hmtfr)
2003                 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
2004 exit:
2005         return ret;
2006 }
2007
2008 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2009 {
2010         int pages, remainder, i, ret;
2011         u16 reg_fw_start_address;
2012         u16 reg_mcu_fw_dl;
2013         u8 val8;
2014         u16 val16;
2015         u32 val32;
2016         u8 *fwptr;
2017
2018         if (priv->rtl_chip == RTL8192F)
2019                 reg_fw_start_address = REG_FW_START_ADDRESS_8192F;
2020         else
2021                 reg_fw_start_address = REG_FW_START_ADDRESS;
2022
2023         if (priv->rtl_chip == RTL8710B) {
2024                 reg_mcu_fw_dl = REG_8051FW_CTRL_V1_8710B;
2025         } else {
2026                 reg_mcu_fw_dl = REG_MCU_FW_DL;
2027
2028                 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2029                 val8 |= 4;
2030                 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2031
2032                 /* 8051 enable */
2033                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2034                 val16 |= SYS_FUNC_CPU_ENABLE;
2035                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2036         }
2037
2038         val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2039         if (val8 & MCU_FW_RAM_SEL) {
2040                 dev_info(&priv->udev->dev,
2041                          "Firmware is already running, resetting the MCU.\n");
2042                 rtl8xxxu_write8(priv, reg_mcu_fw_dl, 0x00);
2043                 priv->fops->reset_8051(priv);
2044         }
2045
2046         /* MCU firmware download enable */
2047         val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2048         val8 |= MCU_FW_DL_ENABLE;
2049         rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2050
2051         /* 8051 reset */
2052         val32 = rtl8xxxu_read32(priv, reg_mcu_fw_dl);
2053         val32 &= ~BIT(19);
2054         rtl8xxxu_write32(priv, reg_mcu_fw_dl, val32);
2055
2056         if (priv->rtl_chip == RTL8710B) {
2057                 /* We must set 0x8090[8]=1 before download FW. */
2058                 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 1);
2059                 val8 |= BIT(0);
2060                 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 1, val8);
2061         }
2062
2063         /* Reset firmware download checksum */
2064         val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl);
2065         val8 |= MCU_FW_DL_CSUM_REPORT;
2066         rtl8xxxu_write8(priv, reg_mcu_fw_dl, val8);
2067
2068         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2069         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2070
2071         fwptr = priv->fw_data->data;
2072
2073         for (i = 0; i < pages; i++) {
2074                 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2075                 val8 |= i;
2076                 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2077
2078                 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2079                                       fwptr, RTL_FW_PAGE_SIZE);
2080                 if (ret != RTL_FW_PAGE_SIZE) {
2081                         ret = -EAGAIN;
2082                         goto fw_abort;
2083                 }
2084
2085                 fwptr += RTL_FW_PAGE_SIZE;
2086         }
2087
2088         if (remainder) {
2089                 val8 = rtl8xxxu_read8(priv, reg_mcu_fw_dl + 2) & 0xF8;
2090                 val8 |= i;
2091                 rtl8xxxu_write8(priv, reg_mcu_fw_dl + 2, val8);
2092                 ret = rtl8xxxu_writeN(priv, reg_fw_start_address,
2093                                       fwptr, remainder);
2094                 if (ret != remainder) {
2095                         ret = -EAGAIN;
2096                         goto fw_abort;
2097                 }
2098         }
2099
2100         ret = 0;
2101 fw_abort:
2102         /* MCU firmware download disable */
2103         val16 = rtl8xxxu_read16(priv, reg_mcu_fw_dl);
2104         val16 &= ~MCU_FW_DL_ENABLE;
2105         rtl8xxxu_write16(priv, reg_mcu_fw_dl, val16);
2106
2107         return ret;
2108 }
2109
2110 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name)
2111 {
2112         struct device *dev = &priv->udev->dev;
2113         const struct firmware *fw;
2114         int ret = 0;
2115         u16 signature;
2116
2117         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2118         if (reject_firmware(&fw, fw_name, &priv->udev->dev)) {
2119                 dev_warn(dev, "reject_firmware(%s) failed\n", fw_name);
2120                 ret = -EAGAIN;
2121                 goto exit;
2122         }
2123         if (!fw) {
2124                 dev_warn(dev, "Firmware data not available\n");
2125                 ret = -EINVAL;
2126                 goto exit;
2127         }
2128
2129         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2130         if (!priv->fw_data) {
2131                 ret = -ENOMEM;
2132                 goto exit;
2133         }
2134         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2135
2136         signature = le16_to_cpu(priv->fw_data->signature);
2137         switch (signature & 0xfff0) {
2138         case 0x92e0:
2139         case 0x92c0:
2140         case 0x88e0:
2141         case 0x88c0:
2142         case 0x5300:
2143         case 0x2300:
2144         case 0x88f0:
2145         case 0x10b0:
2146         case 0x92f0:
2147                 break;
2148         default:
2149                 ret = -EINVAL;
2150                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2151                          __func__, signature);
2152         }
2153
2154         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2155                  le16_to_cpu(priv->fw_data->major_version),
2156                  priv->fw_data->minor_version, signature);
2157
2158 exit:
2159         release_firmware(fw);
2160         return ret;
2161 }
2162
2163 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2164 {
2165         u16 val16;
2166         int i = 100;
2167
2168         /* Inform 8051 to perform reset */
2169         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2170
2171         for (i = 100; i > 0; i--) {
2172                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2173
2174                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2175                         dev_dbg(&priv->udev->dev,
2176                                 "%s: Firmware self reset success!\n", __func__);
2177                         break;
2178                 }
2179                 udelay(50);
2180         }
2181
2182         if (!i) {
2183                 /* Force firmware reset */
2184                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2185                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2186                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2187         }
2188 }
2189
2190 static int
2191 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2192 {
2193         const struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2194         int i, ret;
2195         u16 reg;
2196         u8 val;
2197
2198         for (i = 0; ; i++) {
2199                 reg = array[i].reg;
2200                 val = array[i].val;
2201
2202                 if (reg == 0xffff && val == 0xff)
2203                         break;
2204
2205                 ret = rtl8xxxu_write8(priv, reg, val);
2206                 if (ret != 1) {
2207                         dev_warn(&priv->udev->dev,
2208                                  "Failed to initialize MAC "
2209                                  "(reg: %04x, val %02x)\n", reg, val);
2210                         return -EAGAIN;
2211                 }
2212         }
2213
2214         switch (priv->rtl_chip) {
2215         case RTL8188C:
2216         case RTL8188R:
2217         case RTL8191C:
2218         case RTL8192C:
2219         case RTL8723A:
2220                 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2221                 break;
2222         case RTL8188E:
2223                 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0707);
2224                 break;
2225         default:
2226                 break;
2227         }
2228
2229         return 0;
2230 }
2231
2232 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2233                            const struct rtl8xxxu_reg32val *array)
2234 {
2235         int i, ret;
2236         u16 reg;
2237         u32 val;
2238
2239         for (i = 0; ; i++) {
2240                 reg = array[i].reg;
2241                 val = array[i].val;
2242
2243                 if (reg == 0xffff && val == 0xffffffff)
2244                         break;
2245
2246                 ret = rtl8xxxu_write32(priv, reg, val);
2247                 if (ret != sizeof(val)) {
2248                         dev_warn(&priv->udev->dev,
2249                                  "Failed to initialize PHY\n");
2250                         return -EAGAIN;
2251                 }
2252                 udelay(1);
2253         }
2254
2255         return 0;
2256 }
2257
2258 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2259 {
2260         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2261         u16 val16;
2262         u32 val32;
2263
2264         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2265         udelay(2);
2266         val8 |= AFE_PLL_320_ENABLE;
2267         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2268         udelay(2);
2269
2270         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2271         udelay(2);
2272
2273         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2274         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2275         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2276
2277         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2278         val32 &= ~AFE_XTAL_RF_GATE;
2279         if (priv->has_bluetooth)
2280                 val32 &= ~AFE_XTAL_BT_GATE;
2281         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2282
2283         /* 6. 0x1f[7:0] = 0x07 */
2284         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2285         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2286
2287         if (priv->hi_pa)
2288                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2289         else if (priv->tx_paths == 2)
2290                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2291         else
2292                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2293
2294         if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2295             priv->vendor_umc && priv->chip_cut == 1)
2296                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2297
2298         if (priv->hi_pa)
2299                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2300         else
2301                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2302
2303         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2304         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2305         ldohci12 = 0x57;
2306         lpldo = 1;
2307         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2308         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2309 }
2310
2311 /*
2312  * Most of this is black magic retrieved from the old rtl8723au driver
2313  */
2314 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2315 {
2316         u32 val32;
2317
2318         priv->fops->init_phy_bb(priv);
2319
2320         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2321                 /*
2322                  * For 1T2R boards, patch the registers.
2323                  *
2324                  * It looks like 8191/2 1T2R boards use path B for TX
2325                  */
2326                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2327                 val32 &= ~(BIT(0) | BIT(1));
2328                 val32 |= BIT(1);
2329                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2330
2331                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2332                 val32 &= ~0x300033;
2333                 val32 |= 0x200022;
2334                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2335
2336                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2337                 val32 &= ~CCK0_AFE_RX_MASK;
2338                 val32 &= 0x00ffffff;
2339                 val32 |= 0x40000000;
2340                 val32 |= CCK0_AFE_RX_ANT_B;
2341                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2342
2343                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2344                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2345                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2346                           OFDM_RF_PATH_TX_B);
2347                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2348
2349                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2350                 val32 &= ~(BIT(4) | BIT(5));
2351                 val32 |= BIT(4);
2352                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2353
2354                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2355                 val32 &= ~(BIT(27) | BIT(26));
2356                 val32 |= BIT(27);
2357                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2358
2359                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2360                 val32 &= ~(BIT(27) | BIT(26));
2361                 val32 |= BIT(27);
2362                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2363
2364                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2365                 val32 &= ~(BIT(27) | BIT(26));
2366                 val32 |= BIT(27);
2367                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2368
2369                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2370                 val32 &= ~(BIT(27) | BIT(26));
2371                 val32 |= BIT(27);
2372                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2373
2374                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2375                 val32 &= ~(BIT(27) | BIT(26));
2376                 val32 |= BIT(27);
2377                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2378         }
2379
2380         if (priv->fops->set_crystal_cap)
2381                 priv->fops->set_crystal_cap(priv, priv->default_crystal_cap);
2382
2383         if (priv->rtl_chip == RTL8192E)
2384                 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2385
2386         return 0;
2387 }
2388
2389 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2390                                  const struct rtl8xxxu_rfregval *array,
2391                                  enum rtl8xxxu_rfpath path)
2392 {
2393         int i, ret;
2394         u8 reg;
2395         u32 val;
2396
2397         for (i = 0; ; i++) {
2398                 reg = array[i].reg;
2399                 val = array[i].val;
2400
2401                 if (reg == 0xff && val == 0xffffffff)
2402                         break;
2403
2404                 switch (reg) {
2405                 case 0xfe:
2406                         msleep(50);
2407                         continue;
2408                 case 0xfd:
2409                         mdelay(5);
2410                         continue;
2411                 case 0xfc:
2412                         mdelay(1);
2413                         continue;
2414                 case 0xfb:
2415                         udelay(50);
2416                         continue;
2417                 case 0xfa:
2418                         udelay(5);
2419                         continue;
2420                 case 0xf9:
2421                         udelay(1);
2422                         continue;
2423                 }
2424
2425                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2426                 if (ret) {
2427                         dev_warn(&priv->udev->dev,
2428                                  "Failed to initialize RF\n");
2429                         return -EAGAIN;
2430                 }
2431                 udelay(1);
2432         }
2433
2434         return 0;
2435 }
2436
2437 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2438                          const struct rtl8xxxu_rfregval *table,
2439                          enum rtl8xxxu_rfpath path)
2440 {
2441         u32 val32;
2442         u16 val16, rfsi_rfenv;
2443         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2444
2445         switch (path) {
2446         case RF_A:
2447                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2448                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2449                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2450                 break;
2451         case RF_B:
2452                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2453                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2454                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2455                 break;
2456         default:
2457                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2458                         __func__, path + 'A');
2459                 return -EINVAL;
2460         }
2461         /* For path B, use XB */
2462         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2463         rfsi_rfenv &= FPGA0_RF_RFENV;
2464
2465         /*
2466          * These two we might be able to optimize into one
2467          */
2468         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2469         val32 |= BIT(20);       /* 0x10 << 16 */
2470         rtl8xxxu_write32(priv, reg_int_oe, val32);
2471         udelay(1);
2472
2473         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2474         val32 |= BIT(4);
2475         rtl8xxxu_write32(priv, reg_int_oe, val32);
2476         udelay(1);
2477
2478         /*
2479          * These two we might be able to optimize into one
2480          */
2481         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2482         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2483         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2484         udelay(1);
2485
2486         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2487         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2488         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2489         udelay(1);
2490
2491         rtl8xxxu_init_rf_regs(priv, table, path);
2492
2493         /* For path B, use XB */
2494         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2495         val16 &= ~FPGA0_RF_RFENV;
2496         val16 |= rfsi_rfenv;
2497         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2498
2499         return 0;
2500 }
2501
2502 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2503 {
2504         int ret = -EBUSY;
2505         int count = 0;
2506         u32 value;
2507
2508         value = LLT_OP_WRITE | address << 8 | data;
2509
2510         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2511
2512         do {
2513                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2514                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2515                         ret = 0;
2516                         break;
2517                 }
2518         } while (count++ < 20);
2519
2520         return ret;
2521 }
2522
2523 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2524 {
2525         int ret;
2526         int i, last_entry;
2527         u8 last_tx_page;
2528
2529         last_tx_page = priv->fops->total_page_num;
2530
2531         if (priv->fops->last_llt_entry)
2532                 last_entry = priv->fops->last_llt_entry;
2533         else
2534                 last_entry = 255;
2535
2536         for (i = 0; i < last_tx_page; i++) {
2537                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2538                 if (ret)
2539                         goto exit;
2540         }
2541
2542         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2543         if (ret)
2544                 goto exit;
2545
2546         /* Mark remaining pages as a ring buffer */
2547         for (i = last_tx_page + 1; i < last_entry; i++) {
2548                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2549                 if (ret)
2550                         goto exit;
2551         }
2552
2553         /*  Let last entry point to the start entry of ring buffer */
2554         ret = rtl8xxxu_llt_write(priv, last_entry, last_tx_page + 1);
2555         if (ret)
2556                 goto exit;
2557
2558 exit:
2559         return ret;
2560 }
2561
2562 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2563 {
2564         u32 val32;
2565         int ret = 0;
2566         int i;
2567
2568         val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2569         val32 |= AUTO_LLT_INIT_LLT;
2570         rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2571
2572         for (i = 500; i; i--) {
2573                 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2574                 if (!(val32 & AUTO_LLT_INIT_LLT))
2575                         break;
2576                 usleep_range(2, 4);
2577         }
2578
2579         if (!i) {
2580                 ret = -EBUSY;
2581                 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2582         }
2583
2584         return ret;
2585 }
2586
2587 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2588 {
2589         u16 val16, hi, lo;
2590         u16 hiq, mgq, bkq, beq, viq, voq;
2591         int hip, mgp, bkp, bep, vip, vop;
2592         int ret = 0;
2593         u32 val32;
2594
2595         switch (priv->ep_tx_count) {
2596         case 1:
2597                 if (priv->ep_tx_high_queue) {
2598                         hi = TRXDMA_QUEUE_HIGH;
2599                 } else if (priv->ep_tx_low_queue) {
2600                         hi = TRXDMA_QUEUE_LOW;
2601                 } else if (priv->ep_tx_normal_queue) {
2602                         hi = TRXDMA_QUEUE_NORMAL;
2603                 } else {
2604                         hi = 0;
2605                         ret = -EINVAL;
2606                 }
2607
2608                 hiq = hi;
2609                 mgq = hi;
2610                 bkq = hi;
2611                 beq = hi;
2612                 viq = hi;
2613                 voq = hi;
2614
2615                 hip = 0;
2616                 mgp = 0;
2617                 bkp = 0;
2618                 bep = 0;
2619                 vip = 0;
2620                 vop = 0;
2621                 break;
2622         case 2:
2623                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2624                         hi = TRXDMA_QUEUE_HIGH;
2625                         lo = TRXDMA_QUEUE_LOW;
2626                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2627                         hi = TRXDMA_QUEUE_NORMAL;
2628                         lo = TRXDMA_QUEUE_LOW;
2629                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2630                         hi = TRXDMA_QUEUE_HIGH;
2631                         lo = TRXDMA_QUEUE_NORMAL;
2632                 } else {
2633                         ret = -EINVAL;
2634                         hi = 0;
2635                         lo = 0;
2636                 }
2637
2638                 hiq = hi;
2639                 mgq = hi;
2640                 bkq = lo;
2641                 beq = lo;
2642                 viq = hi;
2643                 voq = hi;
2644
2645                 hip = 0;
2646                 mgp = 0;
2647                 bkp = 1;
2648                 bep = 1;
2649                 vip = 0;
2650                 vop = 0;
2651                 break;
2652         case 3:
2653                 beq = TRXDMA_QUEUE_LOW;
2654                 bkq = TRXDMA_QUEUE_LOW;
2655                 viq = TRXDMA_QUEUE_NORMAL;
2656                 voq = TRXDMA_QUEUE_HIGH;
2657                 mgq = TRXDMA_QUEUE_HIGH;
2658                 hiq = TRXDMA_QUEUE_HIGH;
2659
2660                 hip = hiq ^ 3;
2661                 mgp = mgq ^ 3;
2662                 bkp = bkq ^ 3;
2663                 bep = beq ^ 3;
2664                 vip = viq ^ 3;
2665                 vop = viq ^ 3;
2666                 break;
2667         default:
2668                 ret = -EINVAL;
2669         }
2670
2671         /*
2672          * None of the vendor drivers are configuring the beacon
2673          * queue here .... why?
2674          */
2675         if (!ret) {
2676                 /* Only RTL8192F seems to do it like this. */
2677                 if (priv->rtl_chip == RTL8192F) {
2678                         val32 = rtl8xxxu_read32(priv, REG_TRXDMA_CTRL);
2679                         val32 &= 0x7;
2680                         val32 |= (voq << TRXDMA_CTRL_VOQ_SHIFT_8192F) |
2681                                  (viq << TRXDMA_CTRL_VIQ_SHIFT_8192F) |
2682                                  (beq << TRXDMA_CTRL_BEQ_SHIFT_8192F) |
2683                                  (bkq << TRXDMA_CTRL_BKQ_SHIFT_8192F) |
2684                                  (mgq << TRXDMA_CTRL_MGQ_SHIFT_8192F) |
2685                                  (hiq << TRXDMA_CTRL_HIQ_SHIFT_8192F);
2686                         rtl8xxxu_write32(priv, REG_TRXDMA_CTRL, val32);
2687                 } else {
2688                         val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2689                         val16 &= 0x7;
2690                         val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2691                                  (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2692                                  (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2693                                  (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2694                                  (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2695                                  (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2696                         rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2697                 }
2698
2699                 priv->pipe_out[TXDESC_QUEUE_VO] =
2700                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2701                 priv->pipe_out[TXDESC_QUEUE_VI] =
2702                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2703                 priv->pipe_out[TXDESC_QUEUE_BE] =
2704                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2705                 priv->pipe_out[TXDESC_QUEUE_BK] =
2706                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2707                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2708                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2709                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2710                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2711                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2712                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2713                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2714                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2715         }
2716
2717         return ret;
2718 }
2719
2720 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2721                                 int result[][8], int candidate, bool tx_only)
2722 {
2723         u32 oldval, x, tx0_a, reg;
2724         int y, tx0_c;
2725         u32 val32;
2726
2727         if (!iqk_ok)
2728                 return;
2729
2730         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2731         oldval = val32 >> 22;
2732
2733         x = result[candidate][0];
2734         if ((x & 0x00000200) != 0)
2735                 x = x | 0xfffffc00;
2736         tx0_a = (x * oldval) >> 8;
2737
2738         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2739         val32 &= ~0x3ff;
2740         val32 |= tx0_a;
2741         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2742
2743         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2744         val32 &= ~BIT(31);
2745         if ((x * oldval >> 7) & 0x1)
2746                 val32 |= BIT(31);
2747         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2748
2749         y = result[candidate][1];
2750         if ((y & 0x00000200) != 0)
2751                 y = y | 0xfffffc00;
2752         tx0_c = (y * oldval) >> 8;
2753
2754         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2755         val32 &= ~0xf0000000;
2756         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2757         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2758
2759         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2760         val32 &= ~0x003f0000;
2761         val32 |= ((tx0_c & 0x3f) << 16);
2762         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2763
2764         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2765         val32 &= ~BIT(29);
2766         if ((y * oldval >> 7) & 0x1)
2767                 val32 |= BIT(29);
2768         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2769
2770         if (tx_only) {
2771                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2772                 return;
2773         }
2774
2775         reg = result[candidate][2];
2776
2777         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2778         val32 &= ~0x3ff;
2779         val32 |= (reg & 0x3ff);
2780         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2781
2782         reg = result[candidate][3] & 0x3F;
2783
2784         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2785         val32 &= ~0xfc00;
2786         val32 |= ((reg << 10) & 0xfc00);
2787         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2788
2789         reg = (result[candidate][3] >> 6) & 0xF;
2790
2791         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2792         val32 &= ~0xf0000000;
2793         val32 |= (reg << 28);
2794         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2795 }
2796
2797 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2798                                 int result[][8], int candidate, bool tx_only)
2799 {
2800         u32 oldval, x, tx1_a, reg;
2801         int y, tx1_c;
2802         u32 val32;
2803
2804         if (!iqk_ok)
2805                 return;
2806
2807         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2808         oldval = val32 >> 22;
2809
2810         x = result[candidate][4];
2811         if ((x & 0x00000200) != 0)
2812                 x = x | 0xfffffc00;
2813         tx1_a = (x * oldval) >> 8;
2814
2815         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2816         val32 &= ~0x3ff;
2817         val32 |= tx1_a;
2818         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2819
2820         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2821         val32 &= ~BIT(27);
2822         if ((x * oldval >> 7) & 0x1)
2823                 val32 |= BIT(27);
2824         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2825
2826         y = result[candidate][5];
2827         if ((y & 0x00000200) != 0)
2828                 y = y | 0xfffffc00;
2829         tx1_c = (y * oldval) >> 8;
2830
2831         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2832         val32 &= ~0xf0000000;
2833         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2834         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2835
2836         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2837         val32 &= ~0x003f0000;
2838         val32 |= ((tx1_c & 0x3f) << 16);
2839         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2840
2841         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2842         val32 &= ~BIT(25);
2843         if ((y * oldval >> 7) & 0x1)
2844                 val32 |= BIT(25);
2845         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2846
2847         if (tx_only) {
2848                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2849                 return;
2850         }
2851
2852         reg = result[candidate][6];
2853
2854         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2855         val32 &= ~0x3ff;
2856         val32 |= (reg & 0x3ff);
2857         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2858
2859         reg = result[candidate][7] & 0x3f;
2860
2861         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2862         val32 &= ~0xfc00;
2863         val32 |= ((reg << 10) & 0xfc00);
2864         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2865
2866         reg = (result[candidate][7] >> 6) & 0xf;
2867
2868         if (priv->rtl_chip == RTL8192F) {
2869                 rtl8xxxu_write32_mask(priv, REG_RXIQB_EXT, 0x000000f0, reg);
2870         } else {
2871                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_RSSI_TABLE);
2872                 val32 &= ~0x0000f000;
2873                 val32 |= (reg << 12);
2874                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_RSSI_TABLE, val32);
2875         }
2876 }
2877
2878 #define MAX_TOLERANCE           5
2879
2880 bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2881                                  int result[][8], int c1, int c2)
2882 {
2883         u32 i, j, diff, simubitmap, bound = 0;
2884         int candidate[2] = {-1, -1};    /* for path A and path B */
2885         bool retval = true;
2886
2887         if (priv->tx_paths > 1)
2888                 bound = 8;
2889         else
2890                 bound = 4;
2891
2892         simubitmap = 0;
2893
2894         for (i = 0; i < bound; i++) {
2895                 diff = (result[c1][i] > result[c2][i]) ?
2896                         (result[c1][i] - result[c2][i]) :
2897                         (result[c2][i] - result[c1][i]);
2898                 if (diff > MAX_TOLERANCE) {
2899                         if ((i == 2 || i == 6) && !simubitmap) {
2900                                 if (result[c1][i] + result[c1][i + 1] == 0)
2901                                         candidate[(i / 4)] = c2;
2902                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2903                                         candidate[(i / 4)] = c1;
2904                                 else
2905                                         simubitmap = simubitmap | (1 << i);
2906                         } else {
2907                                 simubitmap = simubitmap | (1 << i);
2908                         }
2909                 }
2910         }
2911
2912         if (simubitmap == 0) {
2913                 for (i = 0; i < (bound / 4); i++) {
2914                         if (candidate[i] >= 0) {
2915                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2916                                         result[3][j] = result[candidate[i]][j];
2917                                 retval = false;
2918                         }
2919                 }
2920                 return retval;
2921         } else if (!(simubitmap & 0x0f)) {
2922                 /* path A OK */
2923                 for (i = 0; i < 4; i++)
2924                         result[3][i] = result[c1][i];
2925         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2926                 /* path B OK */
2927                 for (i = 4; i < 8; i++)
2928                         result[3][i] = result[c1][i];
2929         }
2930
2931         return false;
2932 }
2933
2934 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2935                                       int result[][8], int c1, int c2)
2936 {
2937         u32 i, j, diff, simubitmap, bound = 0;
2938         int candidate[2] = {-1, -1};    /* for path A and path B */
2939         int tmp1, tmp2;
2940         bool retval = true;
2941
2942         if (priv->tx_paths > 1)
2943                 bound = 8;
2944         else
2945                 bound = 4;
2946
2947         simubitmap = 0;
2948
2949         for (i = 0; i < bound; i++) {
2950                 if (i & 1) {
2951                         if ((result[c1][i] & 0x00000200))
2952                                 tmp1 = result[c1][i] | 0xfffffc00;
2953                         else
2954                                 tmp1 = result[c1][i];
2955
2956                         if ((result[c2][i]& 0x00000200))
2957                                 tmp2 = result[c2][i] | 0xfffffc00;
2958                         else
2959                                 tmp2 = result[c2][i];
2960                 } else {
2961                         tmp1 = result[c1][i];
2962                         tmp2 = result[c2][i];
2963                 }
2964
2965                 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2966
2967                 if (diff > MAX_TOLERANCE) {
2968                         if ((i == 2 || i == 6) && !simubitmap) {
2969                                 if (result[c1][i] + result[c1][i + 1] == 0)
2970                                         candidate[(i / 4)] = c2;
2971                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2972                                         candidate[(i / 4)] = c1;
2973                                 else
2974                                         simubitmap = simubitmap | (1 << i);
2975                         } else {
2976                                 simubitmap = simubitmap | (1 << i);
2977                         }
2978                 }
2979         }
2980
2981         if (simubitmap == 0) {
2982                 for (i = 0; i < (bound / 4); i++) {
2983                         if (candidate[i] >= 0) {
2984                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2985                                         result[3][j] = result[candidate[i]][j];
2986                                 retval = false;
2987                         }
2988                 }
2989                 return retval;
2990         } else {
2991                 if (!(simubitmap & 0x03)) {
2992                         /* path A TX OK */
2993                         for (i = 0; i < 2; i++)
2994                                 result[3][i] = result[c1][i];
2995                 }
2996
2997                 if (!(simubitmap & 0x0c)) {
2998                         /* path A RX OK */
2999                         for (i = 2; i < 4; i++)
3000                                 result[3][i] = result[c1][i];
3001                 }
3002
3003                 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
3004                         /* path B TX OK */
3005                         for (i = 4; i < 6; i++)
3006                                 result[3][i] = result[c1][i];
3007                 }
3008
3009                 if (!(simubitmap & 0xc0) && priv->tx_paths > 1) {
3010                         /* path B RX OK */
3011                         for (i = 6; i < 8; i++)
3012                                 result[3][i] = result[c1][i];
3013                 }
3014         }
3015
3016         return false;
3017 }
3018
3019 void
3020 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3021 {
3022         int i;
3023
3024         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3025                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3026
3027         backup[i] = rtl8xxxu_read32(priv, reg[i]);
3028 }
3029
3030 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3031                                const u32 *reg, u32 *backup)
3032 {
3033         int i;
3034
3035         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3036                 rtl8xxxu_write8(priv, reg[i], backup[i]);
3037
3038         rtl8xxxu_write32(priv, reg[i], backup[i]);
3039 }
3040
3041 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3042                         u32 *backup, int count)
3043 {
3044         int i;
3045
3046         for (i = 0; i < count; i++)
3047                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3048 }
3049
3050 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3051                            u32 *backup, int count)
3052 {
3053         int i;
3054
3055         for (i = 0; i < count; i++)
3056                 rtl8xxxu_write32(priv, regs[i], backup[i]);
3057 }
3058
3059
3060 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3061                            bool path_a_on)
3062 {
3063         u32 path_on;
3064         int i;
3065
3066         if (priv->tx_paths == 1) {
3067                 path_on = priv->fops->adda_1t_path_on;
3068                 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
3069         } else {
3070                 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3071                         priv->fops->adda_2t_path_on_b;
3072
3073                 rtl8xxxu_write32(priv, regs[0], path_on);
3074         }
3075
3076         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3077                 rtl8xxxu_write32(priv, regs[i], path_on);
3078 }
3079
3080 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3081                               const u32 *regs, u32 *backup)
3082 {
3083         int i = 0;
3084
3085         rtl8xxxu_write8(priv, regs[i], 0x3f);
3086
3087         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3088                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3089
3090         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3091 }
3092
3093 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3094 {
3095         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3096         int result = 0;
3097
3098         /* path-A IQK setting */
3099         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3100         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3101         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3102
3103         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3104                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3105                 0x28160502;
3106         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3107
3108         /* path-B IQK setting */
3109         if (priv->rf_paths > 1) {
3110                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3111                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3112                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3113                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3114         }
3115
3116         /* LO calibration setting */
3117         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3118
3119         /* One shot, path A LOK & IQK */
3120         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3121         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3122
3123         mdelay(1);
3124
3125         /* Check failed */
3126         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3127         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3128         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3129         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3130
3131         if (!(reg_eac & BIT(28)) &&
3132             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3133             ((reg_e9c & 0x03ff0000) != 0x00420000))
3134                 result |= 0x01;
3135         else    /* If TX not OK, ignore RX */
3136                 goto out;
3137
3138         /* If TX is OK, check whether RX is OK */
3139         if (!(reg_eac & BIT(27)) &&
3140             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3141             ((reg_eac & 0x03ff0000) != 0x00360000))
3142                 result |= 0x02;
3143         else
3144                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3145                          __func__);
3146 out:
3147         return result;
3148 }
3149
3150 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3151 {
3152         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3153         int result = 0;
3154
3155         /* One shot, path B LOK & IQK */
3156         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3157         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3158
3159         mdelay(1);
3160
3161         /* Check failed */
3162         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3163         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3164         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3165         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3166         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3167
3168         if (!(reg_eac & BIT(31)) &&
3169             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3170             ((reg_ebc & 0x03ff0000) != 0x00420000))
3171                 result |= 0x01;
3172         else
3173                 goto out;
3174
3175         if (!(reg_eac & BIT(30)) &&
3176             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3177             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3178                 result |= 0x02;
3179         else
3180                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3181                          __func__);
3182 out:
3183         return result;
3184 }
3185
3186 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3187                                      int result[][8], int t)
3188 {
3189         struct device *dev = &priv->udev->dev;
3190         u32 i, val32;
3191         int path_a_ok, path_b_ok;
3192         int retry = 2;
3193         static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3194                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3195                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3196                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3197                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3198                 REG_TX_TO_TX, REG_RX_CCK,
3199                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3200                 REG_RX_TO_RX, REG_STANDBY,
3201                 REG_SLEEP, REG_PMPD_ANAEN
3202         };
3203         static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3204                 REG_TXPAUSE, REG_BEACON_CTRL,
3205                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3206         };
3207         static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3208                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3209                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3210                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3211                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3212         };
3213
3214         /*
3215          * Note: IQ calibration must be performed after loading
3216          *       PHY_REG.txt , and radio_a, radio_b.txt
3217          */
3218
3219         if (t == 0) {
3220                 /* Save ADDA parameters, turn Path A ADDA on */
3221                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3222                                    RTL8XXXU_ADDA_REGS);
3223                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3224                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3225                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3226         }
3227
3228         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3229
3230         if (t == 0) {
3231                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3232                 if (val32 & FPGA0_HSSI_PARM1_PI)
3233                         priv->pi_enabled = 1;
3234         }
3235
3236         if (!priv->pi_enabled) {
3237                 /* Switch BB to PI mode to do IQ Calibration. */
3238                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3239                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3240         }
3241
3242         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3243         val32 &= ~FPGA_RF_MODE_CCK;
3244         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3245
3246         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3247         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3248         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3249
3250         if (!priv->no_pape) {
3251                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3252                 val32 |= (FPGA0_RF_PAPE |
3253                           (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3254                 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3255         }
3256
3257         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3258         val32 &= ~BIT(10);
3259         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3260         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3261         val32 &= ~BIT(10);
3262         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3263
3264         if (priv->tx_paths > 1) {
3265                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3266                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3267         }
3268
3269         /* MAC settings */
3270         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3271
3272         /* Page B init */
3273         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3274
3275         if (priv->tx_paths > 1)
3276                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3277
3278         /* IQ calibration setting */
3279         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3280         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3281         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3282
3283         for (i = 0; i < retry; i++) {
3284                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3285                 if (path_a_ok == 0x03) {
3286                         val32 = rtl8xxxu_read32(priv,
3287                                                 REG_TX_POWER_BEFORE_IQK_A);
3288                         result[t][0] = (val32 >> 16) & 0x3ff;
3289                         val32 = rtl8xxxu_read32(priv,
3290                                                 REG_TX_POWER_AFTER_IQK_A);
3291                         result[t][1] = (val32 >> 16) & 0x3ff;
3292                         val32 = rtl8xxxu_read32(priv,
3293                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3294                         result[t][2] = (val32 >> 16) & 0x3ff;
3295                         val32 = rtl8xxxu_read32(priv,
3296                                                 REG_RX_POWER_AFTER_IQK_A_2);
3297                         result[t][3] = (val32 >> 16) & 0x3ff;
3298                         break;
3299                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3300                         /* TX IQK OK */
3301                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3302                                 __func__);
3303
3304                         val32 = rtl8xxxu_read32(priv,
3305                                                 REG_TX_POWER_BEFORE_IQK_A);
3306                         result[t][0] = (val32 >> 16) & 0x3ff;
3307                         val32 = rtl8xxxu_read32(priv,
3308                                                 REG_TX_POWER_AFTER_IQK_A);
3309                         result[t][1] = (val32 >> 16) & 0x3ff;
3310                 }
3311         }
3312
3313         if (!path_a_ok)
3314                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3315
3316         if (priv->tx_paths > 1) {
3317                 /*
3318                  * Path A into standby
3319                  */
3320                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3321                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3322                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3323
3324                 /* Turn Path B ADDA on */
3325                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3326
3327                 for (i = 0; i < retry; i++) {
3328                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3329                         if (path_b_ok == 0x03) {
3330                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3331                                 result[t][4] = (val32 >> 16) & 0x3ff;
3332                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3333                                 result[t][5] = (val32 >> 16) & 0x3ff;
3334                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3335                                 result[t][6] = (val32 >> 16) & 0x3ff;
3336                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3337                                 result[t][7] = (val32 >> 16) & 0x3ff;
3338                                 break;
3339                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3340                                 /* TX IQK OK */
3341                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3342                                 result[t][4] = (val32 >> 16) & 0x3ff;
3343                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3344                                 result[t][5] = (val32 >> 16) & 0x3ff;
3345                         }
3346                 }
3347
3348                 if (!path_b_ok)
3349                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3350         }
3351
3352         /* Back to BB mode, load original value */
3353         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3354
3355         if (t) {
3356                 if (!priv->pi_enabled) {
3357                         /*
3358                          * Switch back BB to SI mode after finishing
3359                          * IQ Calibration
3360                          */
3361                         val32 = 0x01000000;
3362                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3363                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3364                 }
3365
3366                 /* Reload ADDA power saving parameters */
3367                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3368                                       RTL8XXXU_ADDA_REGS);
3369
3370                 /* Reload MAC parameters */
3371                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3372
3373                 /* Reload BB parameters */
3374                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3375                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3376
3377                 /* Restore RX initial gain */
3378                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3379
3380                 if (priv->tx_paths > 1) {
3381                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3382                                          0x00032ed3);
3383                 }
3384
3385                 /* Load 0xe30 IQC default value */
3386                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3387                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3388         }
3389 }
3390
3391 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3392 {
3393         struct h2c_cmd h2c;
3394
3395         memset(&h2c, 0, sizeof(struct h2c_cmd));
3396         h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3397         h2c.bt_wlan_calibration.data = start;
3398
3399         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3400 }
3401
3402 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3403 {
3404         struct device *dev = &priv->udev->dev;
3405         int result[4][8];       /* last is final result */
3406         int i, candidate;
3407         bool path_a_ok, path_b_ok;
3408         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3409         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3410         s32 reg_tmp = 0;
3411         bool simu;
3412
3413         memset(result, 0, sizeof(result));
3414         candidate = -1;
3415
3416         path_a_ok = false;
3417         path_b_ok = false;
3418
3419         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3420
3421         for (i = 0; i < 3; i++) {
3422                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3423
3424                 if (i == 1) {
3425                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3426                         if (simu) {
3427                                 candidate = 0;
3428                                 break;
3429                         }
3430                 }
3431
3432                 if (i == 2) {
3433                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3434                         if (simu) {
3435                                 candidate = 0;
3436                                 break;
3437                         }
3438
3439                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3440                         if (simu) {
3441                                 candidate = 1;
3442                         } else {
3443                                 for (i = 0; i < 8; i++)
3444                                         reg_tmp += result[3][i];
3445
3446                                 if (reg_tmp)
3447                                         candidate = 3;
3448                                 else
3449                                         candidate = -1;
3450                         }
3451                 }
3452         }
3453
3454         for (i = 0; i < 4; i++) {
3455                 reg_e94 = result[i][0];
3456                 reg_e9c = result[i][1];
3457                 reg_ea4 = result[i][2];
3458                 reg_eac = result[i][3];
3459                 reg_eb4 = result[i][4];
3460                 reg_ebc = result[i][5];
3461                 reg_ec4 = result[i][6];
3462                 reg_ecc = result[i][7];
3463         }
3464
3465         if (candidate >= 0) {
3466                 reg_e94 = result[candidate][0];
3467                 priv->rege94 =  reg_e94;
3468                 reg_e9c = result[candidate][1];
3469                 priv->rege9c = reg_e9c;
3470                 reg_ea4 = result[candidate][2];
3471                 reg_eac = result[candidate][3];
3472                 reg_eb4 = result[candidate][4];
3473                 priv->regeb4 = reg_eb4;
3474                 reg_ebc = result[candidate][5];
3475                 priv->regebc = reg_ebc;
3476                 reg_ec4 = result[candidate][6];
3477                 reg_ecc = result[candidate][7];
3478                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3479                 dev_dbg(dev,
3480                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
3481                         __func__, reg_e94, reg_e9c,
3482                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3483                 path_a_ok = true;
3484                 path_b_ok = true;
3485         } else {
3486                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3487                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3488         }
3489
3490         if (reg_e94 && candidate >= 0)
3491                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3492                                            candidate, (reg_ea4 == 0));
3493
3494         if (priv->tx_paths > 1 && reg_eb4)
3495                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3496                                            candidate, (reg_ec4 == 0));
3497
3498         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3499                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3500 }
3501
3502 void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3503 {
3504         u32 val32;
3505         u32 rf_amode, rf_bmode = 0, lstf;
3506
3507         /* Check continuous TX and Packet TX */
3508         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3509
3510         if (lstf & OFDM_LSTF_MASK) {
3511                 /* Disable all continuous TX */
3512                 val32 = lstf & ~OFDM_LSTF_MASK;
3513                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3514
3515                 /* Read original RF mode Path A */
3516                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3517
3518                 /* Set RF mode to standby Path A */
3519                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3520                                      (rf_amode & 0x8ffff) | 0x10000);
3521
3522                 /* Path-B */
3523                 if (priv->tx_paths > 1) {
3524                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3525                                                        RF6052_REG_AC);
3526
3527                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3528                                              (rf_bmode & 0x8ffff) | 0x10000);
3529                 }
3530         } else {
3531                 /*  Deal with Packet TX case */
3532                 /*  block all queues */
3533                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3534         }
3535
3536         /* Start LC calibration */
3537         if (priv->fops->has_s0s1)
3538                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3539         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3540         val32 |= 0x08000;
3541         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3542
3543         msleep(100);
3544
3545         if (priv->fops->has_s0s1)
3546                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3547
3548         /* Restore original parameters */
3549         if (lstf & OFDM_LSTF_MASK) {
3550                 /* Path-A */
3551                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3552                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3553
3554                 /* Path-B */
3555                 if (priv->tx_paths > 1)
3556                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3557                                              rf_bmode);
3558         } else /*  Deal with Packet TX case */
3559                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3560 }
3561
3562 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3563 {
3564         int i;
3565         u16 reg;
3566
3567         reg = REG_MACID;
3568
3569         for (i = 0; i < ETH_ALEN; i++)
3570                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3571
3572         return 0;
3573 }
3574
3575 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3576 {
3577         int i;
3578         u16 reg;
3579
3580         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3581
3582         reg = REG_BSSID;
3583
3584         for (i = 0; i < ETH_ALEN; i++)
3585                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3586
3587         return 0;
3588 }
3589
3590 static void
3591 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3592 {
3593         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3594         u8 max_agg = 0xf;
3595         int i;
3596
3597         ampdu_factor = 1 << (ampdu_factor + 2);
3598         if (ampdu_factor > max_agg)
3599                 ampdu_factor = max_agg;
3600
3601         for (i = 0; i < 4; i++) {
3602                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3603                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3604
3605                 if ((vals[i] & 0x0f) > ampdu_factor)
3606                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3607
3608                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3609         }
3610 }
3611
3612 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3613 {
3614         u8 val8;
3615
3616         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3617         val8 &= 0xf8;
3618         val8 |= density;
3619         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3620 }
3621
3622 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3623 {
3624         u8 val8;
3625         int count, ret = 0;
3626
3627         /* Start of rtl8723AU_card_enable_flow */
3628         /* Act to Cardemu sequence*/
3629         /* Turn off RF */
3630         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3631
3632         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3633         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3634         val8 &= ~LEDCFG2_DPDT_SELECT;
3635         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3636
3637         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3638         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3639         val8 |= BIT(1);
3640         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3641
3642         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3643                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3644                 if ((val8 & BIT(1)) == 0)
3645                         break;
3646                 udelay(10);
3647         }
3648
3649         if (!count) {
3650                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3651                          __func__);
3652                 ret = -EBUSY;
3653                 goto exit;
3654         }
3655
3656         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3657         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3658         val8 |= SYS_ISO_ANALOG_IPS;
3659         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3660
3661         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3662         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3663         val8 &= ~LDOA15_ENABLE;
3664         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3665
3666 exit:
3667         return ret;
3668 }
3669
3670 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3671 {
3672         u8 val8;
3673         u8 val32;
3674         int count, ret = 0;
3675
3676         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3677
3678         /*
3679          * Poll - wait for RX packet to complete
3680          */
3681         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3682                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3683                 if (!val32)
3684                         break;
3685                 udelay(10);
3686         }
3687
3688         if (!count) {
3689                 dev_warn(&priv->udev->dev,
3690                          "%s: RX poll timed out (0x05f8)\n", __func__);
3691                 ret = -EBUSY;
3692                 goto exit;
3693         }
3694
3695         /* Disable CCK and OFDM, clock gated */
3696         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3697         val8 &= ~SYS_FUNC_BBRSTB;
3698         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3699
3700         udelay(2);
3701
3702         /* Reset baseband */
3703         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3704         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3705         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3706
3707         /* Reset MAC TRX */
3708         val8 = rtl8xxxu_read8(priv, REG_CR);
3709         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3710         rtl8xxxu_write8(priv, REG_CR, val8);
3711
3712         /* Reset MAC TRX */
3713         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3714         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3715         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3716
3717         /* Respond TX OK to scheduler */
3718         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3719         val8 |= DUAL_TSF_TX_OK;
3720         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3721
3722 exit:
3723         return ret;
3724 }
3725
3726 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3727 {
3728         u8 val8;
3729
3730         /* Clear suspend enable and power down enable*/
3731         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3732         val8 &= ~(BIT(3) | BIT(7));
3733         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3734
3735         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3736         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3737         val8 &= ~BIT(0);
3738         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3739
3740         /* 0x04[12:11] = 11 enable WL suspend*/
3741         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3742         val8 &= ~(BIT(3) | BIT(4));
3743         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3744 }
3745
3746 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3747 {
3748         u8 val8;
3749
3750         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3751         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3752
3753         /* 0x04[12:11] = 01 enable WL suspend */
3754         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3755         val8 &= ~BIT(4);
3756         val8 |= BIT(3);
3757         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3758
3759         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3760         val8 |= BIT(7);
3761         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3762
3763         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3764         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3765         val8 |= BIT(0);
3766         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3767
3768         return 0;
3769 }
3770
3771 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3772 {
3773         struct device *dev = &priv->udev->dev;
3774         u32 val32;
3775         int retry, retval;
3776
3777         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3778
3779         val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3780         val32 |= RXPKT_NUM_RW_RELEASE_EN;
3781         rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3782
3783         retry = 100;
3784         retval = -EBUSY;
3785
3786         do {
3787                 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3788                 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3789                         retval = 0;
3790                         break;
3791                 }
3792         } while (retry--);
3793
3794         rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3795         rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3796         mdelay(2);
3797
3798         if (!retry)
3799                 dev_warn(dev, "Failed to flush FIFO\n");
3800
3801         return retval;
3802 }
3803
3804 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3805 {
3806         /* Fix USB interface interference issue */
3807         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3808         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3809         rtl8xxxu_write8(priv, 0xfe42, 0x80);
3810         /*
3811          * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits
3812          * 8 and 5, for which I have found no documentation.
3813          */
3814         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3815
3816         /*
3817          * Solve too many protocol error on USB bus.
3818          * Can't do this for 8188/8192 UMC A cut parts
3819          */
3820         if (!(!priv->chip_cut && priv->vendor_umc)) {
3821                 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3822                 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3823                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3824
3825                 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3826                 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3827                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3828
3829                 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3830                 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3831                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3832
3833                 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3834                 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3835                 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3836         }
3837 }
3838
3839 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3840 {
3841         u32 val32;
3842
3843         val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3844         val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3845         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3846 }
3847
3848 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3849 {
3850         u8 val8;
3851         u16 val16;
3852         u32 val32;
3853
3854         /*
3855          * Workaround for 8188RU LNA power leakage problem.
3856          */
3857         if (priv->rtl_chip == RTL8188R) {
3858                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3859                 val32 |= BIT(1);
3860                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3861         }
3862
3863         rtl8xxxu_flush_fifo(priv);
3864
3865         rtl8xxxu_active_to_lps(priv);
3866
3867         /* Turn off RF */
3868         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3869
3870         /* Reset Firmware if running in RAM */
3871         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3872                 rtl8xxxu_firmware_self_reset(priv);
3873
3874         /* Reset MCU */
3875         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3876         val16 &= ~SYS_FUNC_CPU_ENABLE;
3877         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3878
3879         /* Reset MCU ready status */
3880         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3881
3882         rtl8xxxu_active_to_emu(priv);
3883         rtl8xxxu_emu_to_disabled(priv);
3884
3885         /* Reset MCU IO Wrapper */
3886         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3887         val8 &= ~BIT(0);
3888         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3889
3890         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3891         val8 |= BIT(0);
3892         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3893
3894         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3895         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3896 }
3897
3898 void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3899                            u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3900 {
3901         struct h2c_cmd h2c;
3902
3903         memset(&h2c, 0, sizeof(struct h2c_cmd));
3904         h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3905         h2c.b_type_dma.data1 = arg1;
3906         h2c.b_type_dma.data2 = arg2;
3907         h2c.b_type_dma.data3 = arg3;
3908         h2c.b_type_dma.data4 = arg4;
3909         h2c.b_type_dma.data5 = arg5;
3910         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3911 }
3912
3913 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3914 {
3915         u32 val32;
3916
3917         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3918         val32 &= ~(BIT(22) | BIT(23));
3919         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3920 }
3921
3922 static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3923 {
3924         struct rtl8xxxu_fileops *fops = priv->fops;
3925         u32 hq, lq, nq, eq, pubq;
3926         u32 val32;
3927
3928         hq = 0;
3929         lq = 0;
3930         nq = 0;
3931         eq = 0;
3932         pubq = 0;
3933
3934         if (priv->ep_tx_high_queue)
3935                 hq = fops->page_num_hi;
3936         if (priv->ep_tx_low_queue)
3937                 lq = fops->page_num_lo;
3938         if (priv->ep_tx_normal_queue)
3939                 nq = fops->page_num_norm;
3940
3941         val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3942         rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3943
3944         pubq = fops->total_page_num - hq - lq - nq - 1;
3945
3946         val32 = RQPN_LOAD;
3947         val32 |= (hq << RQPN_HI_PQ_SHIFT);
3948         val32 |= (lq << RQPN_LO_PQ_SHIFT);
3949         val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3950
3951         rtl8xxxu_write32(priv, REG_RQPN, val32);
3952 }
3953
3954 void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv)
3955 {
3956         u8 val8;
3957
3958         /*
3959          * For USB high speed set 512B packets
3960          */
3961         val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
3962         u8p_replace_bits(&val8, 1, RXDMA_PRO_DMA_BURST_SIZE);
3963         u8p_replace_bits(&val8, 3, RXDMA_PRO_DMA_BURST_CNT);
3964         val8 |= RXDMA_PRO_DMA_MODE;
3965         rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
3966
3967         /*
3968          * Enable single packet AMPDU
3969          */
3970         val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
3971         val8 |= HT_SINGLE_AMPDU_ENABLE;
3972         rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
3973
3974         rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, priv->fops->max_aggr_num);
3975         rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B,
3976                         priv->fops->ampdu_max_time);
3977         rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
3978         rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
3979         rtl8xxxu_write8(priv, REG_PIFS, 0x00);
3980         if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B ||
3981             priv->rtl_chip == RTL8192F) {
3982                 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, FWHW_TXQ_CTRL_AMPDU_RETRY);
3983                 rtl8xxxu_write32(priv, REG_FAST_EDCA_CTRL, 0x03086666);
3984         }
3985         rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, priv->fops->ustime_tsf_edca);
3986         rtl8xxxu_write8(priv, REG_USTIME_EDCA, priv->fops->ustime_tsf_edca);
3987
3988         /* to prevent mac is reseted by bus. */
3989         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
3990         val8 |= RSV_CTRL_WLOCK_1C | RSV_CTRL_DIS_PRST;
3991         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
3992 }
3993
3994 static u8 rtl8xxxu_acquire_macid(struct rtl8xxxu_priv *priv)
3995 {
3996         u8 macid;
3997
3998         macid = find_first_zero_bit(priv->mac_id_map, RTL8XXXU_MAX_MAC_ID_NUM);
3999         if (macid < RTL8XXXU_MAX_MAC_ID_NUM)
4000                 set_bit(macid, priv->mac_id_map);
4001
4002         return macid;
4003 }
4004
4005 static void rtl8xxxu_release_macid(struct rtl8xxxu_priv *priv, u8 macid)
4006 {
4007         clear_bit(macid, priv->mac_id_map);
4008 }
4009
4010 static inline u8 rtl8xxxu_get_macid(struct rtl8xxxu_priv *priv,
4011                                     struct ieee80211_sta *sta)
4012 {
4013         struct rtl8xxxu_sta_info *sta_info;
4014
4015         if (!priv->vif || priv->vif->type == NL80211_IFTYPE_STATION || !sta)
4016                 return 0;
4017
4018         sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
4019         return sta_info->macid;
4020 }
4021
4022 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4023 {
4024         struct rtl8xxxu_priv *priv = hw->priv;
4025         struct device *dev = &priv->udev->dev;
4026         struct rtl8xxxu_fileops *fops = priv->fops;
4027         bool macpower;
4028         int ret;
4029         u8 val8;
4030         u16 val16;
4031         u32 val32;
4032
4033         /* Check if MAC is already powered on */
4034         val8 = rtl8xxxu_read8(priv, REG_CR);
4035         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
4036
4037         /*
4038          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4039          * initialized. First MAC returns 0xea, second MAC returns 0x00
4040          */
4041         if (val8 == 0xea || !(val16 & SYS_CLK_MAC_CLK_ENABLE))
4042                 macpower = false;
4043         else
4044                 macpower = true;
4045
4046         if (fops->needs_full_init)
4047                 macpower = false;
4048
4049         ret = fops->power_on(priv);
4050         if (ret < 0) {
4051                 dev_warn(dev, "%s: Failed power on\n", __func__);
4052                 goto exit;
4053         }
4054
4055         if (!macpower)
4056                 rtl8xxxu_init_queue_reserved_page(priv);
4057
4058         ret = rtl8xxxu_init_queue_priority(priv);
4059         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4060         if (ret)
4061                 goto exit;
4062
4063         /*
4064          * Set RX page boundary
4065          */
4066         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
4067
4068         ret = rtl8xxxu_download_firmware(priv);
4069         dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
4070         if (ret)
4071                 goto exit;
4072         ret = rtl8xxxu_start_firmware(priv);
4073         dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
4074         if (ret)
4075                 goto exit;
4076
4077         if (fops->phy_init_antenna_selection)
4078                 fops->phy_init_antenna_selection(priv);
4079
4080         ret = rtl8xxxu_init_mac(priv);
4081
4082         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4083         if (ret)
4084                 goto exit;
4085
4086         ret = rtl8xxxu_init_phy_bb(priv);
4087         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4088         if (ret)
4089                 goto exit;
4090
4091         ret = fops->init_phy_rf(priv);
4092         if (ret)
4093                 goto exit;
4094
4095         /* Mac APLL Setting */
4096         if (priv->rtl_chip == RTL8192F)
4097                 rtl8xxxu_write16_set(priv, REG_AFE_CTRL4, BIT(4) | BIT(15));
4098
4099         /* RFSW Control - clear bit 14 ?? */
4100         if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E &&
4101             priv->rtl_chip != RTL8188E && priv->rtl_chip != RTL8710B &&
4102             priv->rtl_chip != RTL8192F)
4103                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4104
4105         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4106                 FPGA0_RF_ANTSWB |
4107                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
4108         if (!priv->no_pape) {
4109                 val32 |= (FPGA0_RF_PAPE |
4110                           (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
4111         }
4112         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4113
4114         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4115         if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188E &&
4116             priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4117                 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
4118
4119         if (!macpower) {
4120                 /*
4121                  * Set TX buffer boundary
4122                  */
4123                 val8 = fops->total_page_num + 1;
4124
4125                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4126                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4127                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4128                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4129                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4130         }
4131
4132         /*
4133          * The vendor drivers set PBP for all devices, except 8192e.
4134          * There is no explanation for this in any of the sources.
4135          */
4136         val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
4137                 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
4138         if (priv->rtl_chip != RTL8192E)
4139                 rtl8xxxu_write8(priv, REG_PBP, val8);
4140
4141         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4142         if (!macpower) {
4143                 ret = fops->llt_init(priv);
4144                 if (ret) {
4145                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4146                         goto exit;
4147                 }
4148
4149                 /*
4150                  * Chip specific quirks
4151                  */
4152                 fops->usb_quirks(priv);
4153
4154                 /*
4155                  * Enable TX report and TX report timer for 8723bu/8188eu/...
4156                  */
4157                 if (fops->has_tx_report) {
4158                         /*
4159                          * The RTL8188EU has two types of TX reports:
4160                          * rpt_sel=1:
4161                          *   One report for one frame. We can use this for frames
4162                          *   with IEEE80211_TX_CTL_REQ_TX_STATUS.
4163                          * rpt_sel=2:
4164                          *   One report for many frames transmitted over a period
4165                          *   of time. (This is what REG_TX_REPORT_TIME is for.) The
4166                          *   report includes the number of frames transmitted
4167                          *   successfully, and the number of unsuccessful
4168                          *   transmissions. We use this for software rate control.
4169                          *
4170                          * Bit 0 of REG_TX_REPORT_CTRL is required for both types.
4171                          * Bit 1 (TX_REPORT_CTRL_TIMER_ENABLE) is required for
4172                          * type 2.
4173                          */
4174                         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4175                         if (priv->rtl_chip == RTL8188E)
4176                                 val8 |= BIT(0);
4177                         val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4178                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4179                         /* Set MAX RPT MACID */
4180                         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4181                         /* TX report Timer. Unit: 32us */
4182                         rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4183
4184                         /* tmp ps ? */
4185                         val8 = rtl8xxxu_read8(priv, 0xa3);
4186                         val8 &= 0xf8;
4187                         rtl8xxxu_write8(priv, 0xa3, val8);
4188                 }
4189
4190                 if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
4191                         rtl8xxxu_write8(priv, REG_EARLY_MODE_CONTROL_8710B, 0);
4192         }
4193
4194         /*
4195          * Unit in 8 bytes.
4196          * Get Rx PHY status in order to report RSSI and others.
4197          */
4198         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4199
4200         if (priv->rtl_chip == RTL8192E) {
4201                 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4202                 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4203         } else if (priv->rtl_chip == RTL8188F) {
4204                 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4205                 rtl8xxxu_write32(priv, REG_HISR1, 0xffffffff);
4206         } else if (priv->rtl_chip == RTL8188E) {
4207                 rtl8xxxu_write32(priv, REG_HISR0, 0xffffffff);
4208                 val32 = IMR0_PSTIMEOUT | IMR0_TBDER | IMR0_CPWM | IMR0_CPWM2;
4209                 rtl8xxxu_write32(priv, REG_HIMR0, val32);
4210                 val32 = IMR1_TXERR | IMR1_RXERR | IMR1_TXFOVW | IMR1_RXFOVW;
4211                 rtl8xxxu_write32(priv, REG_HIMR1, val32);
4212                 val8 = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4213                 val8 |= USB_SPEC_INT_BULK_SELECT;
4214                 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, val8);
4215         } else if (priv->rtl_chip == RTL8710B) {
4216                 rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0);
4217         } else if (priv->rtl_chip != RTL8192F) {
4218                 /*
4219                  * Enable all interrupts - not obvious USB needs to do this
4220                  */
4221                 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4222                 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4223         }
4224
4225         rtl8xxxu_set_mac(priv);
4226         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4227
4228         /*
4229          * Configure initial WMAC settings
4230          */
4231         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4232                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4233                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4234         rtl8xxxu_write32(priv, REG_RCR, val32);
4235         priv->regrcr = val32;
4236
4237         if (fops->init_reg_rxfltmap) {
4238                 /* Accept all data frames */
4239                 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4240
4241                 /*
4242                  * Since ADF is removed from RCR, ps-poll will not be indicate to driver,
4243                  * RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll.
4244                  */
4245                 rtl8xxxu_write16(priv, REG_RXFLTMAP1, 0x400);
4246
4247                 /* Accept all management frames */
4248                 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
4249         } else {
4250                 /*
4251                  * Accept all multicast
4252                  */
4253                 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4254                 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4255         }
4256
4257         /*
4258          * Init adaptive controls
4259          */
4260         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4261         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4262         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4263         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4264
4265         /* CCK = 0x0a, OFDM = 0x10 */
4266         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4267         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4268         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4269
4270         /*
4271          * Init EDCA
4272          */
4273         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4274
4275         /* Set CCK SIFS */
4276         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4277
4278         /* Set OFDM SIFS */
4279         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4280
4281         /* TXOP */
4282         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4283         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4284         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4285         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4286
4287         /* Set data auto rate fallback retry count */
4288         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4289         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4290         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4291         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4292
4293         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4294         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4295         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4296
4297         /*  Set ACK timeout */
4298         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4299
4300         /*
4301          * Initialize beacon parameters
4302          */
4303         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4304         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4305         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4306         if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8710B &&
4307             priv->rtl_chip != RTL8192F)
4308                 /* Firmware will control REG_DRVERLYINT when power saving is enable, */
4309                 /* so don't set this register on STA mode. */
4310                 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4311         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4312         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4313
4314         /*
4315          * Initialize burst parameters
4316          */
4317         if (priv->fops->init_burst)
4318                 priv->fops->init_burst(priv);
4319
4320         if (fops->init_aggregation)
4321                 fops->init_aggregation(priv);
4322
4323         if (fops->init_reg_pkt_life_time) {
4324                 rtl8xxxu_write16(priv, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4325                 rtl8xxxu_write16(priv, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /* unit: 256us. 256ms */
4326         }
4327
4328         /*
4329          * Enable CCK and OFDM block
4330          */
4331         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4332         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4333         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4334
4335         /*
4336          * Invalidate all CAM entries - bit 30 is undocumented
4337          */
4338         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4339
4340         /*
4341          * Start out with default power levels for channel 6, 20MHz
4342          */
4343         fops->set_tx_power(priv, 1, false);
4344
4345         /* Let the 8051 take control of antenna setting */
4346         if (priv->rtl_chip != RTL8192E && priv->rtl_chip != RTL8188F &&
4347             priv->rtl_chip != RTL8710B) {
4348                 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4349                 val8 |= LEDCFG2_DPDT_SELECT;
4350                 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4351         }
4352
4353         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4354
4355         /* Disable BAR - not sure if this has any effect on USB */
4356         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4357
4358         if (priv->rtl_chip != RTL8188F && priv->rtl_chip != RTL8188E &&
4359             priv->rtl_chip != RTL8710B && priv->rtl_chip != RTL8192F)
4360                 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4361
4362         if (fops->init_statistics)
4363                 fops->init_statistics(priv);
4364
4365         if (priv->rtl_chip == RTL8192E) {
4366                 /*
4367                  * 0x4c6[3] 1: RTS BW = Data BW
4368                  * 0: RTS BW depends on CCA / secondary CCA result.
4369                  */
4370                 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4371                 val8 &= ~BIT(3);
4372                 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4373                 /*
4374                  * Reset USB mode switch setting
4375                  */
4376                 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4377         } else if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8188E ||
4378                    priv->rtl_chip == RTL8192F) {
4379                 /*
4380                  * Init GPIO settings for 8188f, 8188e, 8192f
4381                  */
4382                 val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
4383                 val8 &= ~GPIO_MUXCFG_IO_SEL_ENBT;
4384                 rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
4385         }
4386
4387         if (priv->rtl_chip == RTL8188F)
4388                 /* CCK PD */
4389                 rtl8xxxu_write8(priv, REG_CCK_PD_THRESH, CCK_PD_TYPE1_LV1_TH);
4390
4391         fops->phy_lc_calibrate(priv);
4392
4393         fops->phy_iq_calibrate(priv);
4394
4395         /*
4396          * This should enable thermal meter
4397          */
4398         if (fops->gen2_thermal_meter) {
4399                 if (priv->rtl_chip == RTL8188F || priv->rtl_chip == RTL8710B) {
4400                         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B);
4401                         val32 |= 0x30000;
4402                         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER_8723B, val32);
4403                 } else {
4404                         rtl8xxxu_write_rfreg(priv,
4405                                              RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4406                 }
4407         } else {
4408                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4409         }
4410
4411         /* Set NAV_UPPER to 30000us */
4412         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4413         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4414
4415         if (priv->rtl_chip == RTL8723A) {
4416                 /*
4417                  * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4418                  * but we need to find root cause.
4419                  * This is 8723au only.
4420                  */
4421                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4422                 if ((val32 & 0xff000000) != 0x83000000) {
4423                         val32 |= FPGA_RF_MODE_CCK;
4424                         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4425                 }
4426         } else if (priv->rtl_chip == RTL8192E || priv->rtl_chip == RTL8188E) {
4427                 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4428         }
4429
4430         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4431         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4432         /* ack for xmit mgmt frames. */
4433         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4434
4435         if (priv->rtl_chip == RTL8192E) {
4436                 /*
4437                  * Fix LDPC rx hang issue.
4438                  */
4439                 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4440                 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4441                 val32 &= 0xfff00fff;
4442                 val32 |= 0x0007e000;
4443                 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4444
4445                 /*
4446                  * 0x824[9] = 0x82C[9] = 0xA80[7] those registers setting
4447                  * should be equal or CCK RSSI report may be incorrect
4448                  */
4449                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4450                 priv->cck_agc_report_type =
4451                         u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR);
4452
4453                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_HSSI_PARM2);
4454                 if (priv->cck_agc_report_type !=
4455                     u32_get_bits(val32, FPGA0_HSSI_PARM2_CCK_HIGH_PWR)) {
4456                         if (priv->cck_agc_report_type)
4457                                 val32 |= FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4458                         else
4459                                 val32 &= ~FPGA0_HSSI_PARM2_CCK_HIGH_PWR;
4460                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM2, val32);
4461                 }
4462
4463                 val32 = rtl8xxxu_read32(priv, REG_AGC_RPT);
4464                 if (priv->cck_agc_report_type)
4465                         val32 |= AGC_RPT_CCK;
4466                 else
4467                         val32 &= ~AGC_RPT_CCK;
4468                 rtl8xxxu_write32(priv, REG_AGC_RPT, val32);
4469         }
4470
4471         if (priv->rtl_chip == RTL8710B) {
4472                 /*
4473                  * 0x76D[5:4] is Port0,Port1 Enable Bit.
4474                  * This is only for 8710B, 2b'00 for MP and 2b'11 for Normal Driver
4475                  */
4476                 val8 = rtl8xxxu_read8(priv, REG_PORT_CONTROL_8710B);
4477                 val8 |= BIT(5) | BIT(4);
4478                 rtl8xxxu_write8(priv, REG_PORT_CONTROL_8710B, val8);
4479
4480                 /* Set 0x5c[8] and [2:0] = 1, LDO mode */
4481                 val32 = rtl8xxxu_read32(priv, REG_WL_RF_PSS_8710B);
4482                 val32 |= 0x107;
4483                 rtl8xxxu_write32(priv, REG_WL_RF_PSS_8710B, val32);
4484         }
4485
4486         val32 = rtl8xxxu_read32(priv, 0xa9c);
4487         priv->cck_new_agc = u32_get_bits(val32, BIT(17));
4488
4489         /* Initialise the center frequency offset tracking */
4490         if (priv->fops->set_crystal_cap) {
4491                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
4492                 priv->cfo_tracking.atc_status = val32 & CFO_TRACKING_ATC_STATUS;
4493                 priv->cfo_tracking.adjust = true;
4494                 priv->cfo_tracking.crystal_cap = priv->default_crystal_cap;
4495         }
4496
4497         if (priv->rtl_chip == RTL8188E)
4498                 rtl8188e_ra_info_init_all(&priv->ra_info);
4499
4500         set_bit(RTL8XXXU_BC_MC_MACID, priv->mac_id_map);
4501
4502 exit:
4503         return ret;
4504 }
4505
4506 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4507                                struct ieee80211_key_conf *key, const u8 *mac)
4508 {
4509         u32 cmd, val32, addr, ctrl;
4510         int j, i, tmp_debug;
4511
4512         tmp_debug = rtl8xxxu_debug;
4513         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4514                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4515
4516         /*
4517          * This is a bit of a hack - the lower bits of the cipher
4518          * suite selector happens to match the cipher index in the CAM
4519          */
4520         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4521         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4522
4523         for (j = 5; j >= 0; j--) {
4524                 switch (j) {
4525                 case 0:
4526                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4527                         break;
4528                 case 1:
4529                         val32 = mac[2] | (mac[3] << 8) |
4530                                 (mac[4] << 16) | (mac[5] << 24);
4531                         break;
4532                 default:
4533                         i = (j - 2) << 2;
4534                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4535                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4536                         break;
4537                 }
4538
4539                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4540                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4541                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4542                 udelay(100);
4543         }
4544
4545         rtl8xxxu_debug = tmp_debug;
4546 }
4547
4548 static
4549 int rtl8xxxu_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
4550 {
4551         struct rtl8xxxu_priv *priv = hw->priv;
4552
4553         *tx_ant = BIT(priv->tx_paths) - 1;
4554         *rx_ant = BIT(priv->rx_paths) - 1;
4555
4556         return 0;
4557 }
4558
4559 static int rtl8xxxu_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
4560                             bool set)
4561 {
4562         struct rtl8xxxu_priv *priv = hw->priv;
4563
4564         schedule_work(&priv->update_beacon_work);
4565
4566         return 0;
4567 }
4568
4569 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4570                                    struct ieee80211_vif *vif, const u8 *mac)
4571 {
4572         struct rtl8xxxu_priv *priv = hw->priv;
4573         u8 val8;
4574
4575         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4576         val8 |= BEACON_DISABLE_TSF_UPDATE;
4577         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4578 }
4579
4580 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4581                                       struct ieee80211_vif *vif)
4582 {
4583         struct rtl8xxxu_priv *priv = hw->priv;
4584         u8 val8;
4585
4586         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4587         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4588         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4589 }
4590
4591 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4592                                u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4593                                u8 macid)
4594 {
4595         struct h2c_cmd h2c;
4596
4597         memset(&h2c, 0, sizeof(struct h2c_cmd));
4598
4599         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4600         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4601         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4602
4603         h2c.ramask.arg = 0x80;
4604         if (sgi)
4605                 h2c.ramask.arg |= 0x20;
4606
4607         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4608                 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4609         rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4610 }
4611
4612 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4613                                     u32 ramask, u8 rateid, int sgi, int txbw_40mhz,
4614                                     u8 macid)
4615 {
4616         struct h2c_cmd h2c;
4617         u8 bw;
4618
4619         if (txbw_40mhz)
4620                 bw = RTL8XXXU_CHANNEL_WIDTH_40;
4621         else
4622                 bw = RTL8XXXU_CHANNEL_WIDTH_20;
4623
4624         memset(&h2c, 0, sizeof(struct h2c_cmd));
4625
4626         h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4627         h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4628         h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4629         h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4630         h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4631         h2c.b_macid_cfg.macid = macid;
4632
4633         h2c.b_macid_cfg.data1 = rateid;
4634         if (sgi)
4635                 h2c.b_macid_cfg.data1 |= BIT(7);
4636
4637         h2c.b_macid_cfg.data2 = bw;
4638
4639         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, rateid %02x, sgi %d, size %zi\n",
4640                 __func__, ramask, rateid, sgi, sizeof(h2c.b_macid_cfg));
4641         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4642 }
4643
4644 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4645                                   u8 macid, u8 role, bool connect)
4646 {
4647         struct h2c_cmd h2c;
4648
4649         memset(&h2c, 0, sizeof(struct h2c_cmd));
4650
4651         h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4652
4653         if (connect)
4654                 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4655         else
4656                 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4657
4658         rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4659 }
4660
4661 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4662                                   u8 macid, u8 role, bool connect)
4663 {
4664         /*
4665          * The firmware turns on the rate control when it knows it's
4666          * connected to a network.
4667          */
4668         struct h2c_cmd h2c;
4669
4670         memset(&h2c, 0, sizeof(struct h2c_cmd));
4671
4672         h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4673         if (connect)
4674                 h2c.media_status_rpt.parm |= BIT(0);
4675         else
4676                 h2c.media_status_rpt.parm &= ~BIT(0);
4677
4678         h2c.media_status_rpt.parm |= ((role << 4) & 0xf0);
4679         h2c.media_status_rpt.macid = macid;
4680
4681         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4682 }
4683
4684 void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4685 {
4686         struct h2c_cmd h2c;
4687         const int h2c_size = 4;
4688
4689         memset(&h2c, 0, sizeof(struct h2c_cmd));
4690
4691         h2c.rssi_report.cmd = H2C_SET_RSSI;
4692         h2c.rssi_report.macid = macid;
4693         h2c.rssi_report.rssi = rssi;
4694
4695         rtl8xxxu_gen1_h2c_cmd(priv, &h2c, h2c_size);
4696 }
4697
4698 void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi)
4699 {
4700         struct h2c_cmd h2c;
4701         int h2c_size = sizeof(h2c.rssi_report);
4702
4703         if (priv->rtl_chip == RTL8723B)
4704                 h2c_size = 4;
4705
4706         memset(&h2c, 0, sizeof(struct h2c_cmd));
4707
4708         h2c.rssi_report.cmd = H2C_8723B_RSSI_SETTING;
4709         h2c.rssi_report.macid = macid;
4710         h2c.rssi_report.rssi = rssi;
4711
4712         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, h2c_size);
4713 }
4714
4715 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4716 {
4717         u8 agg_ctrl, usb_spec, page_thresh, timeout;
4718
4719         usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4720         usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4721         rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4722
4723         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4724         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4725
4726         if (!rtl8xxxu_dma_aggregation) {
4727                 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4728                 return;
4729         }
4730
4731         agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4732         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4733
4734         /*
4735          * The number of packets we can take looks to be buffer size / 512
4736          * which matches the 512 byte rounding we have to do when de-muxing
4737          * the packets.
4738          *
4739          * Sample numbers from the vendor driver:
4740          * USB High-Speed mode values:
4741          *   RxAggBlockCount = 8 : 512 byte unit
4742          *   RxAggBlockTimeout = 6
4743          *   RxAggPageCount = 48 : 128 byte unit
4744          *   RxAggPageTimeout = 4 or 6 (absolute time 34ms/(2^6))
4745          */
4746
4747         page_thresh = (priv->fops->rx_agg_buf_size / 512);
4748         if (rtl8xxxu_dma_agg_pages >= 0) {
4749                 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4750                         timeout = page_thresh;
4751                 else if (rtl8xxxu_dma_agg_pages <= 6)
4752                         dev_err(&priv->udev->dev,
4753                                 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4754                                 __func__, rtl8xxxu_dma_agg_pages);
4755                 else
4756                         dev_err(&priv->udev->dev,
4757                                 "%s: dma_agg_pages=%i larger than limit %i\n",
4758                                 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4759         }
4760         rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4761         /*
4762          * REG_RXDMA_AGG_PG_TH + 1 seems to be the timeout register on
4763          * gen2 chips and rtl8188eu. The rtl8723au seems unhappy if we
4764          * don't set it, so better set both.
4765          */
4766         timeout = 4;
4767
4768         if (rtl8xxxu_dma_agg_timeout >= 0) {
4769                 if (rtl8xxxu_dma_agg_timeout <= 127)
4770                         timeout = rtl8xxxu_dma_agg_timeout;
4771                 else
4772                         dev_err(&priv->udev->dev,
4773                                 "%s: Invalid dma_agg_timeout: %i\n",
4774                                 __func__, rtl8xxxu_dma_agg_timeout);
4775         }
4776
4777         rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4778         rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4779         priv->rx_buf_aggregation = 1;
4780 }
4781
4782 static const struct ieee80211_rate rtl8xxxu_legacy_ratetable[] = {
4783         {.bitrate = 10, .hw_value = 0x00,},
4784         {.bitrate = 20, .hw_value = 0x01,},
4785         {.bitrate = 55, .hw_value = 0x02,},
4786         {.bitrate = 110, .hw_value = 0x03,},
4787         {.bitrate = 60, .hw_value = 0x04,},
4788         {.bitrate = 90, .hw_value = 0x05,},
4789         {.bitrate = 120, .hw_value = 0x06,},
4790         {.bitrate = 180, .hw_value = 0x07,},
4791         {.bitrate = 240, .hw_value = 0x08,},
4792         {.bitrate = 360, .hw_value = 0x09,},
4793         {.bitrate = 480, .hw_value = 0x0a,},
4794         {.bitrate = 540, .hw_value = 0x0b,},
4795 };
4796
4797 static void rtl8xxxu_desc_to_mcsrate(u16 rate, u8 *mcs, u8 *nss)
4798 {
4799         if (rate <= DESC_RATE_54M)
4800                 return;
4801
4802         if (rate >= DESC_RATE_MCS0 && rate <= DESC_RATE_MCS15) {
4803                 if (rate < DESC_RATE_MCS8)
4804                         *nss = 1;
4805                 else
4806                         *nss = 2;
4807                 *mcs = rate - DESC_RATE_MCS0;
4808         }
4809 }
4810
4811 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4812 {
4813         struct ieee80211_hw *hw = priv->hw;
4814         u32 val32;
4815         u8 rate_idx = 0;
4816
4817         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4818
4819         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4820         if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ)
4821                 val32 &= RESPONSE_RATE_RRSR_INIT_5G;
4822         else
4823                 val32 &= RESPONSE_RATE_RRSR_INIT_2G;
4824         val32 |= rate_cfg;
4825         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4826
4827         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4828
4829         while (rate_cfg) {
4830                 rate_cfg = (rate_cfg >> 1);
4831                 rate_idx++;
4832         }
4833         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4834 }
4835
4836 static u16
4837 rtl8xxxu_wireless_mode(struct ieee80211_hw *hw, struct ieee80211_sta *sta)
4838 {
4839         u16 network_type = WIRELESS_MODE_UNKNOWN;
4840
4841         if (hw->conf.chandef.chan->band == NL80211_BAND_5GHZ) {
4842                 if (sta->deflink.vht_cap.vht_supported)
4843                         network_type = WIRELESS_MODE_AC;
4844                 else if (sta->deflink.ht_cap.ht_supported)
4845                         network_type = WIRELESS_MODE_N_5G;
4846
4847                 network_type |= WIRELESS_MODE_A;
4848         } else {
4849                 if (sta->deflink.vht_cap.vht_supported)
4850                         network_type = WIRELESS_MODE_AC;
4851                 else if (sta->deflink.ht_cap.ht_supported)
4852                         network_type = WIRELESS_MODE_N_24G;
4853
4854                 if (sta->deflink.supp_rates[0] <= 0xf)
4855                         network_type |= WIRELESS_MODE_B;
4856                 else if (sta->deflink.supp_rates[0] & 0xf)
4857                         network_type |= (WIRELESS_MODE_B | WIRELESS_MODE_G);
4858                 else
4859                         network_type |= WIRELESS_MODE_G;
4860         }
4861
4862         return network_type;
4863 }
4864
4865 static void rtl8xxxu_set_aifs(struct rtl8xxxu_priv *priv, u8 slot_time)
4866 {
4867         u32 reg_edca_param[IEEE80211_NUM_ACS] = {
4868                 [IEEE80211_AC_VO] = REG_EDCA_VO_PARAM,
4869                 [IEEE80211_AC_VI] = REG_EDCA_VI_PARAM,
4870                 [IEEE80211_AC_BE] = REG_EDCA_BE_PARAM,
4871                 [IEEE80211_AC_BK] = REG_EDCA_BK_PARAM,
4872         };
4873         u32 val32;
4874         u16 wireless_mode = 0;
4875         u8 aifs, aifsn, sifs;
4876         int i;
4877
4878         if (priv->vif) {
4879                 struct ieee80211_sta *sta;
4880
4881                 rcu_read_lock();
4882                 sta = ieee80211_find_sta(priv->vif, priv->vif->bss_conf.bssid);
4883                 if (sta)
4884                         wireless_mode = rtl8xxxu_wireless_mode(priv->hw, sta);
4885                 rcu_read_unlock();
4886         }
4887
4888         if (priv->hw->conf.chandef.chan->band == NL80211_BAND_5GHZ ||
4889             (wireless_mode & WIRELESS_MODE_N_24G))
4890                 sifs = 16;
4891         else
4892                 sifs = 10;
4893
4894         for (i = 0; i < IEEE80211_NUM_ACS; i++) {
4895                 val32 = rtl8xxxu_read32(priv, reg_edca_param[i]);
4896
4897                 /* It was set in conf_tx. */
4898                 aifsn = val32 & 0xff;
4899
4900                 /* aifsn not set yet or already fixed */
4901                 if (aifsn < 2 || aifsn > 15)
4902                         continue;
4903
4904                 aifs = aifsn * slot_time + sifs;
4905
4906                 val32 &= ~0xff;
4907                 val32 |= aifs;
4908                 rtl8xxxu_write32(priv, reg_edca_param[i], val32);
4909         }
4910 }
4911
4912 void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt,
4913                                u8 rate, u8 sgi, u8 bw)
4914 {
4915         u8 mcs, nss;
4916
4917         rarpt->txrate.flags = 0;
4918
4919         if (rate <= DESC_RATE_54M) {
4920                 rarpt->txrate.legacy = rtl8xxxu_legacy_ratetable[rate].bitrate;
4921         } else {
4922                 rtl8xxxu_desc_to_mcsrate(rate, &mcs, &nss);
4923                 rarpt->txrate.flags |= RATE_INFO_FLAGS_MCS;
4924
4925                 rarpt->txrate.mcs = mcs;
4926                 rarpt->txrate.nss = nss;
4927
4928                 if (sgi)
4929                         rarpt->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
4930
4931                 rarpt->txrate.bw = bw;
4932         }
4933
4934         rarpt->bit_rate = cfg80211_calculate_bitrate(&rarpt->txrate);
4935         rarpt->desc_rate = rate;
4936 }
4937
4938 static void
4939 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4940                           struct ieee80211_bss_conf *bss_conf, u64 changed)
4941 {
4942         struct rtl8xxxu_priv *priv = hw->priv;
4943         struct device *dev = &priv->udev->dev;
4944         struct ieee80211_sta *sta;
4945         struct rtl8xxxu_ra_report *rarpt;
4946         u32 val32;
4947         u8 val8;
4948
4949         rarpt = &priv->ra_report;
4950
4951         if (changed & BSS_CHANGED_ASSOC) {
4952                 dev_dbg(dev, "Changed ASSOC: %i!\n", vif->cfg.assoc);
4953
4954                 rtl8xxxu_set_linktype(priv, vif->type);
4955
4956                 if (vif->cfg.assoc) {
4957                         u32 ramask;
4958                         int sgi = 0;
4959                         u8 highest_rate;
4960                         u8 bw;
4961
4962                         rcu_read_lock();
4963                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4964                         if (!sta) {
4965                                 dev_info(dev, "%s: ASSOC no sta found\n",
4966                                          __func__);
4967                                 rcu_read_unlock();
4968                                 goto error;
4969                         }
4970
4971                         if (sta->deflink.ht_cap.ht_supported)
4972                                 dev_info(dev, "%s: HT supported\n", __func__);
4973                         if (sta->deflink.vht_cap.vht_supported)
4974                                 dev_info(dev, "%s: VHT supported\n", __func__);
4975
4976                         /* TODO: Set bits 28-31 for rate adaptive id */
4977                         ramask = (sta->deflink.supp_rates[0] & 0xfff) |
4978                                 sta->deflink.ht_cap.mcs.rx_mask[0] << 12 |
4979                                 sta->deflink.ht_cap.mcs.rx_mask[1] << 20;
4980                         if (sta->deflink.ht_cap.cap &
4981                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4982                                 sgi = 1;
4983
4984                         highest_rate = fls(ramask) - 1;
4985                         if (rtl8xxxu_ht40_2g &&
4986                             (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40))
4987                                 bw = RATE_INFO_BW_40;
4988                         else
4989                                 bw = RATE_INFO_BW_20;
4990                         rcu_read_unlock();
4991
4992                         rtl8xxxu_update_ra_report(rarpt, highest_rate, sgi, bw);
4993
4994                         priv->vif = vif;
4995                         priv->rssi_level = RTL8XXXU_RATR_STA_INIT;
4996
4997                         priv->fops->update_rate_mask(priv, ramask, 0, sgi,
4998                                                      bw == RATE_INFO_BW_40, 0);
4999
5000                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
5001
5002                         rtl8xxxu_stop_tx_beacon(priv);
5003
5004                         /* joinbss sequence */
5005                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
5006                                          0xc000 | vif->cfg.aid);
5007
5008                         priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, true);
5009                 } else {
5010                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5011                         val8 |= BEACON_DISABLE_TSF_UPDATE;
5012                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5013
5014                         priv->fops->report_connect(priv, 0, H2C_MACID_ROLE_AP, false);
5015                 }
5016         }
5017
5018         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
5019                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
5020                         bss_conf->use_short_preamble);
5021                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
5022                 if (bss_conf->use_short_preamble)
5023                         val32 |= RSR_ACK_SHORT_PREAMBLE;
5024                 else
5025                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
5026                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
5027         }
5028
5029         if (changed & BSS_CHANGED_ERP_SLOT) {
5030                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
5031                         bss_conf->use_short_slot);
5032
5033                 if (bss_conf->use_short_slot)
5034                         val8 = 9;
5035                 else
5036                         val8 = 20;
5037                 rtl8xxxu_write8(priv, REG_SLOT, val8);
5038
5039                 rtl8xxxu_set_aifs(priv, val8);
5040         }
5041
5042         if (changed & BSS_CHANGED_BSSID) {
5043                 dev_dbg(dev, "Changed BSSID!\n");
5044                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
5045         }
5046
5047         if (changed & BSS_CHANGED_BASIC_RATES) {
5048                 dev_dbg(dev, "Changed BASIC_RATES!\n");
5049                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
5050         }
5051
5052         if (changed & BSS_CHANGED_BEACON_ENABLED) {
5053                 if (bss_conf->enable_beacon)
5054                         rtl8xxxu_start_tx_beacon(priv);
5055                 else
5056                         rtl8xxxu_stop_tx_beacon(priv);
5057         }
5058
5059         if (changed & BSS_CHANGED_BEACON)
5060                 schedule_work(&priv->update_beacon_work);
5061
5062 error:
5063         return;
5064 }
5065
5066 static int rtl8xxxu_start_ap(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5067                              struct ieee80211_bss_conf *link_conf)
5068 {
5069         struct rtl8xxxu_priv *priv = hw->priv;
5070         struct device *dev = &priv->udev->dev;
5071
5072         dev_dbg(dev, "Start AP mode\n");
5073         rtl8xxxu_set_bssid(priv, vif->bss_conf.bssid);
5074         rtl8xxxu_write16(priv, REG_BCN_INTERVAL, vif->bss_conf.beacon_int);
5075         priv->fops->report_connect(priv, RTL8XXXU_BC_MC_MACID, 0, true);
5076
5077         return 0;
5078 }
5079
5080 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
5081 {
5082         u32 rtlqueue;
5083
5084         switch (queue) {
5085         case IEEE80211_AC_VO:
5086                 rtlqueue = TXDESC_QUEUE_VO;
5087                 break;
5088         case IEEE80211_AC_VI:
5089                 rtlqueue = TXDESC_QUEUE_VI;
5090                 break;
5091         case IEEE80211_AC_BE:
5092                 rtlqueue = TXDESC_QUEUE_BE;
5093                 break;
5094         case IEEE80211_AC_BK:
5095                 rtlqueue = TXDESC_QUEUE_BK;
5096                 break;
5097         default:
5098                 rtlqueue = TXDESC_QUEUE_BE;
5099         }
5100
5101         return rtlqueue;
5102 }
5103
5104 static u32 rtl8xxxu_queue_select(struct ieee80211_hdr *hdr, struct sk_buff *skb)
5105 {
5106         u32 queue;
5107
5108         if (unlikely(ieee80211_is_beacon(hdr->frame_control)))
5109                 queue = TXDESC_QUEUE_BEACON;
5110         else if (ieee80211_is_mgmt(hdr->frame_control))
5111                 queue = TXDESC_QUEUE_MGNT;
5112         else
5113                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
5114
5115         return queue;
5116 }
5117
5118 /*
5119  * Despite newer chips 8723b/8812/8821 having a larger TX descriptor
5120  * format. The descriptor checksum is still only calculated over the
5121  * initial 32 bytes of the descriptor!
5122  */
5123 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
5124 {
5125         __le16 *ptr = (__le16 *)tx_desc;
5126         u16 csum = 0;
5127         int i;
5128
5129         /*
5130          * Clear csum field before calculation, as the csum field is
5131          * in the middle of the struct.
5132          */
5133         tx_desc->csum = cpu_to_le16(0);
5134
5135         for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
5136                 csum = csum ^ le16_to_cpu(ptr[i]);
5137
5138         tx_desc->csum |= cpu_to_le16(csum);
5139 }
5140
5141 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
5142 {
5143         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
5144         unsigned long flags;
5145
5146         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5147         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
5148                 list_del(&tx_urb->list);
5149                 priv->tx_urb_free_count--;
5150                 usb_free_urb(&tx_urb->urb);
5151         }
5152         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5153 }
5154
5155 static struct rtl8xxxu_tx_urb *
5156 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
5157 {
5158         struct rtl8xxxu_tx_urb *tx_urb;
5159         unsigned long flags;
5160
5161         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5162         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
5163                                           struct rtl8xxxu_tx_urb, list);
5164         if (tx_urb) {
5165                 list_del(&tx_urb->list);
5166                 priv->tx_urb_free_count--;
5167                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
5168                     !priv->tx_stopped) {
5169                         priv->tx_stopped = true;
5170                         ieee80211_stop_queues(priv->hw);
5171                 }
5172         }
5173
5174         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5175
5176         return tx_urb;
5177 }
5178
5179 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
5180                                  struct rtl8xxxu_tx_urb *tx_urb)
5181 {
5182         unsigned long flags;
5183
5184         INIT_LIST_HEAD(&tx_urb->list);
5185
5186         spin_lock_irqsave(&priv->tx_urb_lock, flags);
5187
5188         list_add(&tx_urb->list, &priv->tx_urb_free_list);
5189         priv->tx_urb_free_count++;
5190         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
5191             priv->tx_stopped) {
5192                 priv->tx_stopped = false;
5193                 ieee80211_wake_queues(priv->hw);
5194         }
5195
5196         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
5197 }
5198
5199 static void rtl8xxxu_tx_complete(struct urb *urb)
5200 {
5201         struct sk_buff *skb = (struct sk_buff *)urb->context;
5202         struct ieee80211_tx_info *tx_info;
5203         struct ieee80211_hw *hw;
5204         struct rtl8xxxu_priv *priv;
5205         struct rtl8xxxu_tx_urb *tx_urb =
5206                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
5207
5208         tx_info = IEEE80211_SKB_CB(skb);
5209         hw = tx_info->rate_driver_data[0];
5210         priv = hw->priv;
5211
5212         skb_pull(skb, priv->fops->tx_desc_size);
5213
5214         ieee80211_tx_info_clear_status(tx_info);
5215         tx_info->status.rates[0].idx = -1;
5216         tx_info->status.rates[0].count = 0;
5217
5218         if (!urb->status)
5219                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
5220
5221         ieee80211_tx_status_irqsafe(hw, skb);
5222
5223         rtl8xxxu_free_tx_urb(priv, tx_urb);
5224 }
5225
5226 static void rtl8xxxu_dump_action(struct device *dev,
5227                                  struct ieee80211_hdr *hdr)
5228 {
5229         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
5230         u16 cap, timeout;
5231
5232         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
5233                 return;
5234
5235         switch (mgmt->u.action.u.addba_resp.action_code) {
5236         case WLAN_ACTION_ADDBA_RESP:
5237                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
5238                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
5239                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
5240                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
5241                          "status %02x\n",
5242                          timeout,
5243                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5244                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5245                          (cap >> 1) & 0x1,
5246                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
5247                 break;
5248         case WLAN_ACTION_ADDBA_REQ:
5249                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
5250                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
5251                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
5252                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
5253                          timeout,
5254                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
5255                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
5256                          (cap >> 1) & 0x1);
5257                 break;
5258         default:
5259                 dev_info(dev, "action frame %02x\n",
5260                          mgmt->u.action.u.addba_resp.action_code);
5261                 break;
5262         }
5263 }
5264
5265 /*
5266  * Fill in v1 (gen1) specific TX descriptor bits.
5267  * This format is used on 8188cu/8192cu/8723au
5268  */
5269 void
5270 rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5271                         struct ieee80211_tx_info *tx_info,
5272                         struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5273                         bool short_preamble, bool ampdu_enable, u32 rts_rate,
5274                         u8 macid)
5275 {
5276         struct rtl8xxxu_priv *priv = hw->priv;
5277         struct device *dev = &priv->udev->dev;
5278         u8 *qc = ieee80211_get_qos_ctl(hdr);
5279         u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5280         u32 rate = 0;
5281         u16 seq_number;
5282
5283         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5284                 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5285                          __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5286
5287         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5288
5289         tx_desc->txdw5 = cpu_to_le32(rate);
5290
5291         if (ieee80211_is_data(hdr->frame_control))
5292                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5293
5294         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5295
5296         if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5297                 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
5298         else
5299                 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
5300
5301         if (ieee80211_is_mgmt(hdr->frame_control)) {
5302                 tx_desc->txdw5 = cpu_to_le32(rate);
5303                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5304                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5305                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5306         }
5307
5308         if (ieee80211_is_data_qos(hdr->frame_control))
5309                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5310
5311         if (short_preamble)
5312                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5313
5314         if (sgi)
5315                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5316
5317         /*
5318          * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5319          */
5320         tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5321         if (ampdu_enable || tx_info->control.use_rts) {
5322                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5323                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5324         } else if (tx_info->control.use_cts_prot) {
5325                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5326                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5327         }
5328 }
5329
5330 /*
5331  * Fill in v2 (gen2) specific TX descriptor bits.
5332  * This format is used on 8192eu/8723bu
5333  */
5334 void
5335 rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5336                         struct ieee80211_tx_info *tx_info,
5337                         struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
5338                         bool short_preamble, bool ampdu_enable, u32 rts_rate,
5339                         u8 macid)
5340 {
5341         struct rtl8xxxu_priv *priv = hw->priv;
5342         struct device *dev = &priv->udev->dev;
5343         struct rtl8xxxu_txdesc40 *tx_desc40;
5344         u8 *qc = ieee80211_get_qos_ctl(hdr);
5345         u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5346         u32 rate = 0;
5347         u16 seq_number;
5348
5349         tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
5350
5351         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5352                 dev_info(dev, "%s: TX rate: %d, pkt size %u\n",
5353                          __func__, rate, le16_to_cpu(tx_desc40->pkt_size));
5354
5355         tx_desc40->txdw1 |= cpu_to_le32(macid << TXDESC40_MACID_SHIFT);
5356
5357         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5358
5359         tx_desc40->txdw4 = cpu_to_le32(rate);
5360         if (ieee80211_is_data(hdr->frame_control)) {
5361                 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
5362                                                 TXDESC40_DATA_RATE_FB_SHIFT);
5363         }
5364
5365         tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
5366
5367         if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5368                 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5369         else
5370                 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5371
5372         if (ieee80211_is_mgmt(hdr->frame_control)) {
5373                 tx_desc40->txdw4 = cpu_to_le32(rate);
5374                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
5375                 tx_desc40->txdw4 |=
5376                         cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
5377                 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
5378         }
5379
5380         if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ)
5381                 tx_desc40->txdw8 |= cpu_to_le32(TXDESC40_HW_SEQ_ENABLE);
5382
5383         if (short_preamble)
5384                 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
5385
5386         tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
5387
5388         /*
5389          * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5390          */
5391         if (ampdu_enable || tx_info->control.use_rts) {
5392                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
5393                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
5394         } else if (tx_info->control.use_cts_prot) {
5395                 /*
5396                  * For some reason the vendor driver doesn't set
5397                  * TXDESC40_HW_RTS_ENABLE for CTS to SELF
5398                  */
5399                 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
5400         }
5401 }
5402
5403 /*
5404  * Fill in v3 (gen1) specific TX descriptor bits.
5405  * This format is a hybrid between the v1 and v2 formats, only seen
5406  * on 8188eu devices so far.
5407  */
5408 void
5409 rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
5410                         struct ieee80211_tx_info *tx_info,
5411                         struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
5412                         bool short_preamble, bool ampdu_enable, u32 rts_rate,
5413                         u8 macid)
5414 {
5415         struct rtl8xxxu_priv *priv = hw->priv;
5416         struct device *dev = &priv->udev->dev;
5417         struct rtl8xxxu_ra_info *ra = &priv->ra_info;
5418         u8 *qc = ieee80211_get_qos_ctl(hdr);
5419         u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5420         u32 rate = 0;
5421         u16 seq_number;
5422
5423         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5424
5425         if (ieee80211_is_data(hdr->frame_control)) {
5426                 rate = ra->decision_rate;
5427                 tx_desc->txdw5 = cpu_to_le32(rate);
5428                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5429                 tx_desc->txdw4 |= le32_encode_bits(ra->pt_stage, TXDESC32_PT_STAGE_MASK);
5430                 /* Data/RTS rate FB limit */
5431                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
5432         }
5433
5434         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
5435                 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
5436                          __func__, rate, le16_to_cpu(tx_desc->pkt_size));
5437
5438         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
5439
5440         if (ampdu_enable && test_bit(tid, priv->tid_tx_operational))
5441                 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
5442         else
5443                 tx_desc->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
5444
5445         if (ieee80211_is_mgmt(hdr->frame_control)) {
5446                 tx_desc->txdw5 = cpu_to_le32(rate);
5447                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
5448                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
5449                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
5450         }
5451
5452         if (ieee80211_is_data_qos(hdr->frame_control)) {
5453                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
5454
5455                 if (conf_is_ht40(&hw->conf)) {
5456                         tx_desc->txdw4 |= cpu_to_le32(TXDESC_DATA_BW);
5457
5458                         if (conf_is_ht40_minus(&hw->conf))
5459                                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_UPPER);
5460                         else
5461                                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_PRIME_CH_OFF_LOWER);
5462                 }
5463         }
5464
5465         if (short_preamble)
5466                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
5467
5468         if (sgi && ra->rate_sgi)
5469                 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
5470
5471         /*
5472          * rts_rate is zero if RTS/CTS or CTS to SELF are not enabled
5473          */
5474         tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
5475         if (ampdu_enable || tx_info->control.use_rts) {
5476                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
5477                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5478         } else if (tx_info->control.use_cts_prot) {
5479                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
5480                 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
5481         }
5482
5483         tx_desc->txdw2 |= cpu_to_le32(TXDESC_ANTENNA_SELECT_A |
5484                                       TXDESC_ANTENNA_SELECT_B);
5485         tx_desc->txdw7 |= cpu_to_le16(TXDESC_ANTENNA_SELECT_C >> 16);
5486 }
5487
5488 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
5489                         struct ieee80211_tx_control *control,
5490                         struct sk_buff *skb)
5491 {
5492         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
5493         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
5494         struct rtl8xxxu_priv *priv = hw->priv;
5495         struct rtl8xxxu_txdesc32 *tx_desc;
5496         struct rtl8xxxu_tx_urb *tx_urb;
5497         struct ieee80211_sta *sta = NULL;
5498         struct ieee80211_vif *vif = tx_info->control.vif;
5499         struct device *dev = &priv->udev->dev;
5500         u32 queue, rts_rate;
5501         u16 pktlen = skb->len;
5502         int tx_desc_size = priv->fops->tx_desc_size;
5503         u8 macid;
5504         int ret;
5505         bool ampdu_enable, sgi = false, short_preamble = false;
5506
5507         if (skb_headroom(skb) < tx_desc_size) {
5508                 dev_warn(dev,
5509                          "%s: Not enough headroom (%i) for tx descriptor\n",
5510                          __func__, skb_headroom(skb));
5511                 goto error;
5512         }
5513
5514         if (unlikely(skb->len > (65535 - tx_desc_size))) {
5515                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
5516                          __func__, skb->len);
5517                 goto error;
5518         }
5519
5520         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
5521         if (!tx_urb) {
5522                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
5523                 goto error;
5524         }
5525
5526         if (ieee80211_is_action(hdr->frame_control))
5527                 rtl8xxxu_dump_action(dev, hdr);
5528
5529         tx_info->rate_driver_data[0] = hw;
5530
5531         if (control && control->sta)
5532                 sta = control->sta;
5533
5534         queue = rtl8xxxu_queue_select(hdr, skb);
5535
5536         tx_desc = skb_push(skb, tx_desc_size);
5537
5538         memset(tx_desc, 0, tx_desc_size);
5539         tx_desc->pkt_size = cpu_to_le16(pktlen);
5540         tx_desc->pkt_offset = tx_desc_size;
5541
5542         /* These bits mean different things to the RTL8192F. */
5543         if (priv->rtl_chip != RTL8192F)
5544                 tx_desc->txdw0 =
5545                         TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
5546         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
5547             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
5548                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
5549
5550         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
5551
5552         if (tx_info->control.hw_key) {
5553                 switch (tx_info->control.hw_key->cipher) {
5554                 case WLAN_CIPHER_SUITE_WEP40:
5555                 case WLAN_CIPHER_SUITE_WEP104:
5556                 case WLAN_CIPHER_SUITE_TKIP:
5557                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
5558                         break;
5559                 case WLAN_CIPHER_SUITE_CCMP:
5560                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
5561                         break;
5562                 default:
5563                         break;
5564                 }
5565         }
5566
5567         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
5568         ampdu_enable = false;
5569         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
5570                 if (sta->deflink.ht_cap.ht_supported) {
5571                         u32 ampdu, val32;
5572                         u8 *qc = ieee80211_get_qos_ctl(hdr);
5573                         u8 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
5574
5575                         ampdu = (u32)sta->deflink.ht_cap.ampdu_density;
5576                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
5577                         tx_desc->txdw2 |= cpu_to_le32(val32);
5578
5579                         ampdu_enable = true;
5580
5581                         if (!test_bit(tid, priv->tx_aggr_started) &&
5582                             !(skb->protocol == cpu_to_be16(ETH_P_PAE)))
5583                                 if (!ieee80211_start_tx_ba_session(sta, tid, 0))
5584                                         set_bit(tid, priv->tx_aggr_started);
5585                 }
5586         }
5587
5588         if (ieee80211_is_data_qos(hdr->frame_control) &&
5589             sta && sta->deflink.ht_cap.cap &
5590             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
5591                 sgi = true;
5592
5593         if (sta && vif && vif->bss_conf.use_short_preamble)
5594                 short_preamble = true;
5595
5596         if (skb->len > hw->wiphy->rts_threshold)
5597                 tx_info->control.use_rts = true;
5598
5599         if (sta && vif && vif->bss_conf.use_cts_prot)
5600                 tx_info->control.use_cts_prot = true;
5601
5602         if (ampdu_enable || tx_info->control.use_rts ||
5603             tx_info->control.use_cts_prot)
5604                 rts_rate = DESC_RATE_24M;
5605         else
5606                 rts_rate = 0;
5607
5608         macid = rtl8xxxu_get_macid(priv, sta);
5609         priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5610                                 ampdu_enable, rts_rate, macid);
5611
5612         rtl8xxxu_calc_tx_desc_csum(tx_desc);
5613
5614         /* avoid zero checksum make tx hang */
5615         if (priv->rtl_chip == RTL8710B || priv->rtl_chip == RTL8192F)
5616                 tx_desc->csum = ~tx_desc->csum;
5617
5618         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5619                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5620
5621         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5622         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5623         if (ret) {
5624                 usb_unanchor_urb(&tx_urb->urb);
5625                 rtl8xxxu_free_tx_urb(priv, tx_urb);
5626                 goto error;
5627         }
5628         return;
5629 error:
5630         dev_kfree_skb(skb);
5631 }
5632
5633 static void rtl8xxxu_send_beacon_frame(struct ieee80211_hw *hw,
5634                                        struct ieee80211_vif *vif)
5635 {
5636         struct rtl8xxxu_priv *priv = hw->priv;
5637         struct sk_buff *skb = ieee80211_beacon_get(hw, vif, 0);
5638         struct device *dev = &priv->udev->dev;
5639         int retry;
5640         u8 val8;
5641
5642         /* BCN_VALID, write 1 to clear, cleared by SW */
5643         val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5644         val8 |= BIT_BCN_VALID >> 16;
5645         rtl8xxxu_write8(priv, REG_TDECTRL + 2, val8);
5646
5647         /* SW_BCN_SEL - Port0 */
5648         val8 = rtl8xxxu_read8(priv, REG_DWBCN1_CTRL_8723B + 2);
5649         val8 &= ~(BIT_SW_BCN_SEL >> 16);
5650         rtl8xxxu_write8(priv, REG_DWBCN1_CTRL_8723B + 2, val8);
5651
5652         if (skb)
5653                 rtl8xxxu_tx(hw, NULL, skb);
5654
5655         retry = 100;
5656         do {
5657                 val8 = rtl8xxxu_read8(priv, REG_TDECTRL + 2);
5658                 if (val8 & (BIT_BCN_VALID >> 16))
5659                         break;
5660                 usleep_range(10, 20);
5661         } while (--retry);
5662
5663         if (!retry)
5664                 dev_err(dev, "%s: Failed to read beacon valid bit\n", __func__);
5665 }
5666
5667 static void rtl8xxxu_update_beacon_work_callback(struct work_struct *work)
5668 {
5669         struct rtl8xxxu_priv *priv =
5670                 container_of(work, struct rtl8xxxu_priv, update_beacon_work);
5671         struct ieee80211_hw *hw = priv->hw;
5672         struct ieee80211_vif *vif = priv->vif;
5673
5674         if (!vif) {
5675                 WARN_ONCE(true, "no vif to update beacon\n");
5676                 return;
5677         }
5678
5679         rtl8xxxu_send_beacon_frame(hw, vif);
5680 }
5681
5682 void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5683                                  struct ieee80211_rx_status *rx_status,
5684                                  struct rtl8723au_phy_stats *phy_stats,
5685                                  u32 rxmcs, struct ieee80211_hdr *hdr,
5686                                  bool crc_icv_err)
5687 {
5688         if (phy_stats->sgi_en)
5689                 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5690
5691         if (rxmcs < DESC_RATE_6M) {
5692                 /*
5693                  * Handle PHY stats for CCK rates
5694                  */
5695                 rx_status->signal = priv->fops->cck_rssi(priv, phy_stats);
5696         } else {
5697                 bool parse_cfo = priv->fops->set_crystal_cap &&
5698                                  priv->vif &&
5699                                  priv->vif->type == NL80211_IFTYPE_STATION &&
5700                                  priv->vif->cfg.assoc &&
5701                                  !crc_icv_err &&
5702                                  !ieee80211_is_ctl(hdr->frame_control) &&
5703                                  ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5704
5705                 if (parse_cfo) {
5706                         priv->cfo_tracking.cfo_tail[0] = phy_stats->path_cfotail[0];
5707                         priv->cfo_tracking.cfo_tail[1] = phy_stats->path_cfotail[1];
5708
5709                         priv->cfo_tracking.packet_count++;
5710                 }
5711
5712                 rx_status->signal =
5713                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5714         }
5715 }
5716
5717 static void jaguar2_rx_parse_phystats_type0(struct rtl8xxxu_priv *priv,
5718                                             struct ieee80211_rx_status *rx_status,
5719                                             struct jaguar2_phy_stats_type0 *phy_stats0,
5720                                             u32 rxmcs, struct ieee80211_hdr *hdr,
5721                                             bool crc_icv_err)
5722 {
5723         s8 rx_power = phy_stats0->pwdb - 110;
5724
5725         if (!priv->cck_new_agc)
5726                 rx_power = priv->fops->cck_rssi(priv, (struct rtl8723au_phy_stats *)phy_stats0);
5727
5728         rx_status->signal = rx_power;
5729 }
5730
5731 static void jaguar2_rx_parse_phystats_type1(struct rtl8xxxu_priv *priv,
5732                                             struct ieee80211_rx_status *rx_status,
5733                                             struct jaguar2_phy_stats_type1 *phy_stats1,
5734                                             u32 rxmcs, struct ieee80211_hdr *hdr,
5735                                             bool crc_icv_err)
5736 {
5737         bool parse_cfo = priv->fops->set_crystal_cap &&
5738                          priv->vif &&
5739                          priv->vif->type == NL80211_IFTYPE_STATION &&
5740                          priv->vif->cfg.assoc &&
5741                          !crc_icv_err &&
5742                          !ieee80211_is_ctl(hdr->frame_control) &&
5743                          ether_addr_equal(priv->vif->bss_conf.bssid, hdr->addr2);
5744         u8 pwdb_max = 0;
5745         int rx_path;
5746
5747         if (parse_cfo) {
5748                 /* Only path-A and path-B have CFO tail and short CFO */
5749                 priv->cfo_tracking.cfo_tail[RF_A] = phy_stats1->cfo_tail[RF_A];
5750                 priv->cfo_tracking.cfo_tail[RF_B] = phy_stats1->cfo_tail[RF_B];
5751
5752                 priv->cfo_tracking.packet_count++;
5753         }
5754
5755         for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5756                 pwdb_max = max(pwdb_max, phy_stats1->pwdb[rx_path]);
5757
5758         rx_status->signal = pwdb_max - 110;
5759 }
5760
5761 static void jaguar2_rx_parse_phystats_type2(struct rtl8xxxu_priv *priv,
5762                                             struct ieee80211_rx_status *rx_status,
5763                                             struct jaguar2_phy_stats_type2 *phy_stats2,
5764                                             u32 rxmcs, struct ieee80211_hdr *hdr,
5765                                             bool crc_icv_err)
5766 {
5767         u8 pwdb_max = 0;
5768         int rx_path;
5769
5770         for (rx_path = 0; rx_path < priv->rx_paths; rx_path++)
5771                 pwdb_max = max(pwdb_max, phy_stats2->pwdb[rx_path]);
5772
5773         rx_status->signal = pwdb_max - 110;
5774 }
5775
5776 void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5777                                struct ieee80211_rx_status *rx_status,
5778                                struct rtl8723au_phy_stats *phy_stats,
5779                                u32 rxmcs, struct ieee80211_hdr *hdr,
5780                                bool crc_icv_err)
5781 {
5782         struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
5783         struct jaguar2_phy_stats_type1 *phy_stats1 = (struct jaguar2_phy_stats_type1 *)phy_stats;
5784         struct jaguar2_phy_stats_type2 *phy_stats2 = (struct jaguar2_phy_stats_type2 *)phy_stats;
5785
5786         switch (phy_stats0->page_num) {
5787         case 0:
5788                 /* CCK */
5789                 jaguar2_rx_parse_phystats_type0(priv, rx_status, phy_stats0,
5790                                                 rxmcs, hdr, crc_icv_err);
5791                 break;
5792         case 1:
5793                 /* OFDM */
5794                 jaguar2_rx_parse_phystats_type1(priv, rx_status, phy_stats1,
5795                                                 rxmcs, hdr, crc_icv_err);
5796                 break;
5797         case 2:
5798                 /* Also OFDM but different (how?) */
5799                 jaguar2_rx_parse_phystats_type2(priv, rx_status, phy_stats2,
5800                                                 rxmcs, hdr, crc_icv_err);
5801                 break;
5802         default:
5803                 return;
5804         }
5805 }
5806
5807 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5808 {
5809         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5810         unsigned long flags;
5811
5812         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5813
5814         list_for_each_entry_safe(rx_urb, tmp,
5815                                  &priv->rx_urb_pending_list, list) {
5816                 list_del(&rx_urb->list);
5817                 priv->rx_urb_pending_count--;
5818                 usb_free_urb(&rx_urb->urb);
5819         }
5820
5821         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5822 }
5823
5824 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5825                                   struct rtl8xxxu_rx_urb *rx_urb)
5826 {
5827         struct sk_buff *skb;
5828         unsigned long flags;
5829         int pending = 0;
5830
5831         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5832
5833         if (!priv->shutdown) {
5834                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5835                 priv->rx_urb_pending_count++;
5836                 pending = priv->rx_urb_pending_count;
5837         } else {
5838                 skb = (struct sk_buff *)rx_urb->urb.context;
5839                 dev_kfree_skb_irq(skb);
5840                 usb_free_urb(&rx_urb->urb);
5841         }
5842
5843         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5844
5845         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5846                 schedule_work(&priv->rx_urb_wq);
5847 }
5848
5849 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5850 {
5851         struct rtl8xxxu_priv *priv;
5852         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5853         struct list_head local;
5854         struct sk_buff *skb;
5855         unsigned long flags;
5856         int ret;
5857
5858         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5859         INIT_LIST_HEAD(&local);
5860
5861         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5862
5863         list_splice_init(&priv->rx_urb_pending_list, &local);
5864         priv->rx_urb_pending_count = 0;
5865
5866         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5867
5868         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5869                 list_del_init(&rx_urb->list);
5870                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5871                 /*
5872                  * If out of memory or temporary error, put it back on the
5873                  * queue and try again. Otherwise the device is dead/gone
5874                  * and we should drop it.
5875                  */
5876                 switch (ret) {
5877                 case 0:
5878                         break;
5879                 case -ENOMEM:
5880                 case -EAGAIN:
5881                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5882                         break;
5883                 default:
5884                         dev_warn(&priv->udev->dev,
5885                                  "failed to requeue urb with error %i\n", ret);
5886                         skb = (struct sk_buff *)rx_urb->urb.context;
5887                         dev_kfree_skb(skb);
5888                         usb_free_urb(&rx_urb->urb);
5889                 }
5890         }
5891 }
5892
5893 /*
5894  * The RTL8723BU/RTL8192EU vendor driver use coexistence table type
5895  * 0-7 to represent writing different combinations of register values
5896  * to REG_BT_COEX_TABLEs. It's for different kinds of coexistence use
5897  * cases which Realtek doesn't provide detail for these settings. Keep
5898  * this aligned with vendor driver for easier maintenance.
5899  */
5900 static
5901 void rtl8723bu_set_coex_with_type(struct rtl8xxxu_priv *priv, u8 type)
5902 {
5903         switch (type) {
5904         case 0:
5905                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5906                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
5907                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5908                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5909                 break;
5910         case 1:
5911         case 3:
5912                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5913                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5914                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5915                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5916                 break;
5917         case 2:
5918                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5919                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x5a5a5a5a);
5920                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5921                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5922                 break;
5923         case 4:
5924                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5925                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaa5a5a);
5926                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5927                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5928                 break;
5929         case 5:
5930                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x5a5a5a5a);
5931                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaa5a5a5a);
5932                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5933                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5934                 break;
5935         case 6:
5936                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
5937                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5938                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5939                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5940                 break;
5941         case 7:
5942                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0xaaaaaaaa);
5943                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0xaaaaaaaa);
5944                 rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
5945                 rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
5946                 break;
5947         default:
5948                 break;
5949         }
5950 }
5951
5952 static
5953 void rtl8723bu_update_bt_link_info(struct rtl8xxxu_priv *priv, u8 bt_info)
5954 {
5955         struct rtl8xxxu_btcoex *btcoex = &priv->bt_coex;
5956
5957         if (bt_info & BT_INFO_8723B_1ANT_B_INQ_PAGE)
5958                 btcoex->c2h_bt_inquiry = true;
5959         else
5960                 btcoex->c2h_bt_inquiry = false;
5961
5962         if (!(bt_info & BT_INFO_8723B_1ANT_B_CONNECTION)) {
5963                 btcoex->bt_status = BT_8723B_1ANT_STATUS_NON_CONNECTED_IDLE;
5964                 btcoex->has_sco = false;
5965                 btcoex->has_hid = false;
5966                 btcoex->has_pan = false;
5967                 btcoex->has_a2dp = false;
5968         } else {
5969                 if ((bt_info & 0x1f) == BT_INFO_8723B_1ANT_B_CONNECTION)
5970                         btcoex->bt_status = BT_8723B_1ANT_STATUS_CONNECTED_IDLE;
5971                 else if ((bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO) ||
5972                          (bt_info & BT_INFO_8723B_1ANT_B_SCO_BUSY))
5973                         btcoex->bt_status = BT_8723B_1ANT_STATUS_SCO_BUSY;
5974                 else if (bt_info & BT_INFO_8723B_1ANT_B_ACL_BUSY)
5975                         btcoex->bt_status = BT_8723B_1ANT_STATUS_ACL_BUSY;
5976                 else
5977                         btcoex->bt_status = BT_8723B_1ANT_STATUS_MAX;
5978
5979                 if (bt_info & BT_INFO_8723B_1ANT_B_FTP)
5980                         btcoex->has_pan = true;
5981                 else
5982                         btcoex->has_pan = false;
5983
5984                 if (bt_info & BT_INFO_8723B_1ANT_B_A2DP)
5985                         btcoex->has_a2dp = true;
5986                 else
5987                         btcoex->has_a2dp = false;
5988
5989                 if (bt_info & BT_INFO_8723B_1ANT_B_HID)
5990                         btcoex->has_hid = true;
5991                 else
5992                         btcoex->has_hid = false;
5993
5994                 if (bt_info & BT_INFO_8723B_1ANT_B_SCO_ESCO)
5995                         btcoex->has_sco = true;
5996                 else
5997                         btcoex->has_sco = false;
5998         }
5999
6000         if (!btcoex->has_a2dp && !btcoex->has_sco &&
6001             !btcoex->has_pan && btcoex->has_hid)
6002                 btcoex->hid_only = true;
6003         else
6004                 btcoex->hid_only = false;
6005
6006         if (!btcoex->has_sco && !btcoex->has_pan &&
6007             !btcoex->has_hid && btcoex->has_a2dp)
6008                 btcoex->has_a2dp = true;
6009         else
6010                 btcoex->has_a2dp = false;
6011
6012         if (btcoex->bt_status == BT_8723B_1ANT_STATUS_SCO_BUSY ||
6013             btcoex->bt_status == BT_8723B_1ANT_STATUS_ACL_BUSY)
6014                 btcoex->bt_busy = true;
6015         else
6016                 btcoex->bt_busy = false;
6017 }
6018
6019 static
6020 void rtl8723bu_handle_bt_inquiry(struct rtl8xxxu_priv *priv)
6021 {
6022         struct ieee80211_vif *vif;
6023         struct rtl8xxxu_btcoex *btcoex;
6024         bool wifi_connected;
6025
6026         vif = priv->vif;
6027         btcoex = &priv->bt_coex;
6028         wifi_connected = (vif && vif->cfg.assoc);
6029
6030         if (!wifi_connected) {
6031                 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6032                 rtl8723bu_set_coex_with_type(priv, 0);
6033         } else if (btcoex->has_sco || btcoex->has_hid || btcoex->has_a2dp) {
6034                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35, 0x3, 0x11, 0x11);
6035                 rtl8723bu_set_coex_with_type(priv, 4);
6036         } else if (btcoex->has_pan) {
6037                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x3f, 0x3, 0x11, 0x11);
6038                 rtl8723bu_set_coex_with_type(priv, 4);
6039         } else {
6040                 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6041                 rtl8723bu_set_coex_with_type(priv, 7);
6042         }
6043 }
6044
6045 static
6046 void rtl8723bu_handle_bt_info(struct rtl8xxxu_priv *priv)
6047 {
6048         struct ieee80211_vif *vif;
6049         struct rtl8xxxu_btcoex *btcoex;
6050         bool wifi_connected;
6051
6052         vif = priv->vif;
6053         btcoex = &priv->bt_coex;
6054         wifi_connected = (vif && vif->cfg.assoc);
6055
6056         if (wifi_connected) {
6057                 u32 val32 = 0;
6058                 u32 high_prio_tx = 0, high_prio_rx = 0;
6059
6060                 val32 = rtl8xxxu_read32(priv, 0x770);
6061                 high_prio_tx = val32 & 0x0000ffff;
6062                 high_prio_rx = (val32  & 0xffff0000) >> 16;
6063
6064                 if (btcoex->bt_busy) {
6065                         if (btcoex->hid_only) {
6066                                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x20,
6067                                                       0x3, 0x11, 0x11);
6068                                 rtl8723bu_set_coex_with_type(priv, 5);
6069                         } else if (btcoex->a2dp_only) {
6070                                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6071                                                       0x3, 0x11, 0x11);
6072                                 rtl8723bu_set_coex_with_type(priv, 4);
6073                         } else if ((btcoex->has_a2dp && btcoex->has_pan) ||
6074                                    (btcoex->has_hid && btcoex->has_a2dp &&
6075                                     btcoex->has_pan)) {
6076                                 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6077                                                       0x3, 0x10, 0x10);
6078                                 rtl8723bu_set_coex_with_type(priv, 4);
6079                         } else if (btcoex->has_hid && btcoex->has_a2dp) {
6080                                 rtl8723bu_set_ps_tdma(priv, 0x51, 0x21,
6081                                                       0x3, 0x10, 0x10);
6082                                 rtl8723bu_set_coex_with_type(priv, 3);
6083                         } else {
6084                                 rtl8723bu_set_ps_tdma(priv, 0x61, 0x35,
6085                                                       0x3, 0x11, 0x11);
6086                                 rtl8723bu_set_coex_with_type(priv, 4);
6087                         }
6088                 } else {
6089                         rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6090                         if (high_prio_tx + high_prio_rx <= 60)
6091                                 rtl8723bu_set_coex_with_type(priv, 2);
6092                         else
6093                                 rtl8723bu_set_coex_with_type(priv, 7);
6094                 }
6095         } else {
6096                 rtl8723bu_set_ps_tdma(priv, 0x8, 0x0, 0x0, 0x0, 0x0);
6097                 rtl8723bu_set_coex_with_type(priv, 0);
6098         }
6099 }
6100
6101 static void rtl8xxxu_c2hcmd_callback(struct work_struct *work)
6102 {
6103         struct rtl8xxxu_priv *priv;
6104         struct rtl8723bu_c2h *c2h;
6105         struct sk_buff *skb = NULL;
6106         u8 bt_info = 0;
6107         struct rtl8xxxu_btcoex *btcoex;
6108         struct rtl8xxxu_ra_report *rarpt;
6109         u8 bw;
6110
6111         priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6112         btcoex = &priv->bt_coex;
6113         rarpt = &priv->ra_report;
6114
6115         while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6116                 skb = skb_dequeue(&priv->c2hcmd_queue);
6117
6118                 c2h = (struct rtl8723bu_c2h *)skb->data;
6119
6120                 switch (c2h->id) {
6121                 case C2H_8723B_BT_INFO:
6122                         bt_info = c2h->bt_info.bt_info;
6123
6124                         rtl8723bu_update_bt_link_info(priv, bt_info);
6125                         if (btcoex->c2h_bt_inquiry) {
6126                                 rtl8723bu_handle_bt_inquiry(priv);
6127                                 break;
6128                         }
6129                         rtl8723bu_handle_bt_info(priv);
6130                         break;
6131                 case C2H_8723B_RA_REPORT:
6132                         bw = rarpt->txrate.bw;
6133
6134                         if (skb->len >= offsetofend(typeof(*c2h), ra_report.bw)) {
6135                                 if (c2h->ra_report.bw == RTL8XXXU_CHANNEL_WIDTH_40)
6136                                         bw = RATE_INFO_BW_40;
6137                                 else
6138                                         bw = RATE_INFO_BW_20;
6139                         }
6140
6141                         rtl8xxxu_update_ra_report(rarpt, c2h->ra_report.rate,
6142                                                   c2h->ra_report.sgi, bw);
6143                         break;
6144                 default:
6145                         break;
6146                 }
6147
6148                 dev_kfree_skb(skb);
6149         }
6150 }
6151
6152 static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
6153                                  struct sk_buff *skb)
6154 {
6155         struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
6156         struct device *dev = &priv->udev->dev;
6157         int len;
6158
6159         len = skb->len - 2;
6160
6161         dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
6162                 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
6163
6164         switch(c2h->id) {
6165         case C2H_8723B_BT_INFO:
6166                 if (c2h->bt_info.response_source >
6167                     BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
6168                         dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
6169                 else
6170                         dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
6171
6172                 if (c2h->bt_info.bt_has_reset)
6173                         dev_dbg(dev, "BT has been reset\n");
6174                 if (c2h->bt_info.tx_rx_mask)
6175                         dev_dbg(dev, "BT TRx mask\n");
6176
6177                 break;
6178         case C2H_8723B_BT_MP_INFO:
6179                 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
6180                         c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
6181                 break;
6182         case C2H_8723B_RA_REPORT:
6183                 dev_dbg(dev,
6184                         "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
6185                         c2h->ra_report.rate, c2h->ra_report.sgi,
6186                         c2h->ra_report.macid, c2h->ra_report.noisy_state);
6187                 break;
6188         default:
6189                 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
6190                          c2h->id, c2h->seq);
6191                 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
6192                                16, 1, c2h->raw.payload, len, false);
6193                 break;
6194         }
6195
6196         skb_queue_tail(&priv->c2hcmd_queue, skb);
6197
6198         schedule_work(&priv->c2hcmd_work);
6199 }
6200
6201 static void rtl8188e_c2hcmd_callback(struct work_struct *work)
6202 {
6203         struct rtl8xxxu_priv *priv = container_of(work, struct rtl8xxxu_priv, c2hcmd_work);
6204         struct device *dev = &priv->udev->dev;
6205         struct sk_buff *skb = NULL;
6206         struct rtl8xxxu_rxdesc16 *rx_desc;
6207
6208         while (!skb_queue_empty(&priv->c2hcmd_queue)) {
6209                 skb = skb_dequeue(&priv->c2hcmd_queue);
6210
6211                 rx_desc = (struct rtl8xxxu_rxdesc16 *)(skb->data - sizeof(struct rtl8xxxu_rxdesc16));
6212
6213                 switch (rx_desc->rpt_sel) {
6214                 case 1:
6215                         dev_dbg(dev, "C2H TX report type 1\n");
6216
6217                         break;
6218                 case 2:
6219                         dev_dbg(dev, "C2H TX report type 2\n");
6220
6221                         rtl8188e_handle_ra_tx_report2(priv, skb);
6222
6223                         break;
6224                 case 3:
6225                         dev_dbg(dev, "C2H USB interrupt report\n");
6226
6227                         break;
6228                 default:
6229                         dev_warn(dev, "%s: rpt_sel should not be %d\n",
6230                                  __func__, rx_desc->rpt_sel);
6231
6232                         break;
6233                 }
6234
6235                 dev_kfree_skb(skb);
6236         }
6237 }
6238
6239 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6240 {
6241         struct ieee80211_hw *hw = priv->hw;
6242         struct ieee80211_rx_status *rx_status;
6243         struct rtl8xxxu_rxdesc16 *rx_desc;
6244         struct rtl8723au_phy_stats *phy_stats;
6245         struct sk_buff *next_skb = NULL;
6246         __le32 *_rx_desc_le;
6247         u32 *_rx_desc;
6248         int drvinfo_sz, desc_shift;
6249         int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
6250
6251         urb_len = skb->len;
6252         pkt_cnt = 0;
6253
6254         if (urb_len < sizeof(struct rtl8xxxu_rxdesc16)) {
6255                 kfree_skb(skb);
6256                 return RX_TYPE_ERROR;
6257         }
6258
6259         do {
6260                 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
6261                 _rx_desc_le = (__le32 *)skb->data;
6262                 _rx_desc = (u32 *)skb->data;
6263
6264                 for (i = 0;
6265                      i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
6266                         _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6267
6268                 /*
6269                  * Only read pkt_cnt from the header if we're parsing the
6270                  * first packet
6271                  */
6272                 if (!pkt_cnt)
6273                         pkt_cnt = rx_desc->pkt_cnt;
6274                 pkt_len = rx_desc->pktlen;
6275
6276                 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6277                 desc_shift = rx_desc->shift;
6278                 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6279                                      sizeof(struct rtl8xxxu_rxdesc16), 128);
6280
6281                 /*
6282                  * Only clone the skb if there's enough data at the end to
6283                  * at least cover the rx descriptor
6284                  */
6285                 if (pkt_cnt > 1 &&
6286                     urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
6287                         next_skb = skb_clone(skb, GFP_ATOMIC);
6288
6289                 rx_status = IEEE80211_SKB_RXCB(skb);
6290                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6291
6292                 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
6293
6294                 if (rx_desc->rpt_sel) {
6295                         skb_queue_tail(&priv->c2hcmd_queue, skb);
6296                         schedule_work(&priv->c2hcmd_work);
6297                 } else {
6298                         phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6299
6300                         skb_pull(skb, drvinfo_sz + desc_shift);
6301
6302                         skb_trim(skb, pkt_len);
6303
6304                         if (rx_desc->phy_stats)
6305                                 priv->fops->parse_phystats(
6306                                         priv, rx_status, phy_stats,
6307                                         rx_desc->rxmcs,
6308                                         (struct ieee80211_hdr *)skb->data,
6309                                         rx_desc->crc32 || rx_desc->icverr);
6310
6311                         rx_status->mactime = rx_desc->tsfl;
6312                         rx_status->flag |= RX_FLAG_MACTIME_START;
6313
6314                         if (!rx_desc->swdec)
6315                                 rx_status->flag |= RX_FLAG_DECRYPTED;
6316                         if (rx_desc->crc32)
6317                                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6318                         if (rx_desc->bw)
6319                                 rx_status->bw = RATE_INFO_BW_40;
6320
6321                         if (rx_desc->rxht) {
6322                                 rx_status->encoding = RX_ENC_HT;
6323                                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6324                         } else {
6325                                 rx_status->rate_idx = rx_desc->rxmcs;
6326                         }
6327
6328                         rx_status->freq = hw->conf.chandef.chan->center_freq;
6329                         rx_status->band = hw->conf.chandef.chan->band;
6330
6331                         ieee80211_rx_irqsafe(hw, skb);
6332                 }
6333
6334                 skb = next_skb;
6335                 if (skb)
6336                         skb_pull(next_skb, pkt_offset);
6337
6338                 pkt_cnt--;
6339                 urb_len -= pkt_offset;
6340                 next_skb = NULL;
6341         } while (skb && pkt_cnt > 0 &&
6342                  urb_len >= sizeof(struct rtl8xxxu_rxdesc16));
6343
6344         return RX_TYPE_DATA_PKT;
6345 }
6346
6347 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
6348 {
6349         struct ieee80211_hw *hw = priv->hw;
6350         struct ieee80211_rx_status *rx_status;
6351         struct rtl8xxxu_rxdesc24 *rx_desc;
6352         struct rtl8723au_phy_stats *phy_stats;
6353         struct sk_buff *next_skb = NULL;
6354         __le32 *_rx_desc_le;
6355         u32 *_rx_desc;
6356         int drvinfo_sz, desc_shift;
6357         int i, pkt_len, urb_len, pkt_offset;
6358
6359         urb_len = skb->len;
6360
6361         if (urb_len < sizeof(struct rtl8xxxu_rxdesc24)) {
6362                 kfree_skb(skb);
6363                 return RX_TYPE_ERROR;
6364         }
6365
6366         do {
6367                 rx_desc = (struct rtl8xxxu_rxdesc24 *)skb->data;
6368                 _rx_desc_le = (__le32 *)skb->data;
6369                 _rx_desc = (u32 *)skb->data;
6370
6371                 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
6372                         _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
6373
6374                 pkt_len = rx_desc->pktlen;
6375
6376                 drvinfo_sz = rx_desc->drvinfo_sz * 8;
6377                 desc_shift = rx_desc->shift;
6378                 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
6379                                      sizeof(struct rtl8xxxu_rxdesc24), 8);
6380
6381                 /*
6382                  * Only clone the skb if there's enough data at the end to
6383                  * at least cover the rx descriptor
6384                  */
6385                 if (urb_len >= (pkt_offset + sizeof(struct rtl8xxxu_rxdesc24)))
6386                         next_skb = skb_clone(skb, GFP_ATOMIC);
6387
6388                 rx_status = IEEE80211_SKB_RXCB(skb);
6389                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
6390
6391                 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
6392
6393                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
6394
6395                 skb_pull(skb, drvinfo_sz + desc_shift);
6396
6397                 skb_trim(skb, pkt_len);
6398
6399                 if (rx_desc->rpt_sel) {
6400                         struct device *dev = &priv->udev->dev;
6401                         dev_dbg(dev, "%s: C2H packet\n", __func__);
6402                         rtl8723bu_handle_c2h(priv, skb);
6403                 } else {
6404                         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
6405
6406                         if (rx_desc->phy_stats)
6407                                 priv->fops->parse_phystats(priv, rx_status, phy_stats,
6408                                                            rx_desc->rxmcs, hdr,
6409                                                            rx_desc->crc32 || rx_desc->icverr);
6410
6411                         rx_status->mactime = rx_desc->tsfl;
6412                         rx_status->flag |= RX_FLAG_MACTIME_START;
6413
6414                         if (!rx_desc->swdec)
6415                                 rx_status->flag |= RX_FLAG_DECRYPTED;
6416                         if (rx_desc->crc32)
6417                                 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
6418                         if (rx_desc->bw)
6419                                 rx_status->bw = RATE_INFO_BW_40;
6420
6421                         if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
6422                                 rx_status->encoding = RX_ENC_HT;
6423                                 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
6424                         } else {
6425                                 rx_status->rate_idx = rx_desc->rxmcs;
6426                         }
6427
6428                         rx_status->freq = hw->conf.chandef.chan->center_freq;
6429                         rx_status->band = hw->conf.chandef.chan->band;
6430
6431                         ieee80211_rx_irqsafe(hw, skb);
6432                 }
6433
6434                 skb = next_skb;
6435                 if (skb)
6436                         skb_pull(next_skb, pkt_offset);
6437
6438                 urb_len -= pkt_offset;
6439                 next_skb = NULL;
6440         } while (skb && urb_len >= sizeof(struct rtl8xxxu_rxdesc24));
6441
6442         return RX_TYPE_DATA_PKT;
6443 }
6444
6445 static void rtl8xxxu_rx_complete(struct urb *urb)
6446 {
6447         struct rtl8xxxu_rx_urb *rx_urb =
6448                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
6449         struct ieee80211_hw *hw = rx_urb->hw;
6450         struct rtl8xxxu_priv *priv = hw->priv;
6451         struct sk_buff *skb = (struct sk_buff *)urb->context;
6452         struct device *dev = &priv->udev->dev;
6453
6454         skb_put(skb, urb->actual_length);
6455
6456         if (urb->status == 0) {
6457                 priv->fops->parse_rx_desc(priv, skb);
6458
6459                 skb = NULL;
6460                 rx_urb->urb.context = NULL;
6461                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
6462         } else {
6463                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6464                 goto cleanup;
6465         }
6466         return;
6467
6468 cleanup:
6469         usb_free_urb(urb);
6470         dev_kfree_skb(skb);
6471 }
6472
6473 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
6474                                   struct rtl8xxxu_rx_urb *rx_urb)
6475 {
6476         struct rtl8xxxu_fileops *fops = priv->fops;
6477         struct sk_buff *skb;
6478         int skb_size;
6479         int ret, rx_desc_sz;
6480
6481         rx_desc_sz = fops->rx_desc_size;
6482
6483         if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
6484                 skb_size = fops->rx_agg_buf_size;
6485                 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
6486         } else {
6487                 skb_size = IEEE80211_MAX_FRAME_LEN;
6488         }
6489
6490         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
6491         if (!skb)
6492                 return -ENOMEM;
6493
6494         memset(skb->data, 0, rx_desc_sz);
6495         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
6496                           skb_size, rtl8xxxu_rx_complete, skb);
6497         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
6498         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
6499         if (ret)
6500                 usb_unanchor_urb(&rx_urb->urb);
6501         return ret;
6502 }
6503
6504 static void rtl8xxxu_int_complete(struct urb *urb)
6505 {
6506         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
6507         struct device *dev = &priv->udev->dev;
6508         int ret;
6509
6510         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
6511                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
6512         if (urb->status == 0) {
6513                 usb_anchor_urb(urb, &priv->int_anchor);
6514                 ret = usb_submit_urb(urb, GFP_ATOMIC);
6515                 if (ret)
6516                         usb_unanchor_urb(urb);
6517         } else {
6518                 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
6519         }
6520 }
6521
6522
6523 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
6524 {
6525         struct rtl8xxxu_priv *priv = hw->priv;
6526         struct urb *urb;
6527         u32 val32;
6528         int ret;
6529
6530         urb = usb_alloc_urb(0, GFP_KERNEL);
6531         if (!urb)
6532                 return -ENOMEM;
6533
6534         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
6535                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
6536                          rtl8xxxu_int_complete, priv, 1);
6537         usb_anchor_urb(urb, &priv->int_anchor);
6538         ret = usb_submit_urb(urb, GFP_KERNEL);
6539         if (ret) {
6540                 usb_unanchor_urb(urb);
6541                 goto error;
6542         }
6543
6544         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
6545         val32 |= USB_HIMR_CPWM;
6546         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
6547
6548 error:
6549         usb_free_urb(urb);
6550         return ret;
6551 }
6552
6553 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
6554                                   struct ieee80211_vif *vif)
6555 {
6556         struct rtl8xxxu_priv *priv = hw->priv;
6557         int ret;
6558         u8 val8;
6559
6560         if (!priv->vif)
6561                 priv->vif = vif;
6562         else
6563                 return -EOPNOTSUPP;
6564
6565         switch (vif->type) {
6566         case NL80211_IFTYPE_STATION:
6567                 rtl8xxxu_stop_tx_beacon(priv);
6568
6569                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
6570                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
6571                         BEACON_DISABLE_TSF_UPDATE;
6572                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
6573                 ret = 0;
6574                 break;
6575         case NL80211_IFTYPE_AP:
6576                 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6577                                 BEACON_DISABLE_TSF_UPDATE | BEACON_CTRL_MBSSID);
6578                 rtl8xxxu_write8(priv, REG_ATIMWND, 0x0c); /* 12ms */
6579                 rtl8xxxu_write16(priv, REG_TSFTR_SYN_OFFSET, 0x7fff); /* ~32ms */
6580                 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, DUAL_TSF_RESET_TSF0);
6581
6582                 /* enable BCN0 function */
6583                 rtl8xxxu_write8(priv, REG_BEACON_CTRL,
6584                                 BEACON_DISABLE_TSF_UPDATE |
6585                                 BEACON_FUNCTION_ENABLE | BEACON_CTRL_MBSSID |
6586                                 BEACON_CTRL_TX_BEACON_RPT);
6587
6588                 /* select BCN on port 0 */
6589                 val8 = rtl8xxxu_read8(priv, REG_CCK_CHECK);
6590                 val8 &= ~BIT_BCN_PORT_SEL;
6591                 rtl8xxxu_write8(priv, REG_CCK_CHECK, val8);
6592
6593                 ret = 0;
6594                 break;
6595         default:
6596                 ret = -EOPNOTSUPP;
6597         }
6598
6599         rtl8xxxu_set_linktype(priv, vif->type);
6600         ether_addr_copy(priv->mac_addr, vif->addr);
6601         rtl8xxxu_set_mac(priv);
6602
6603         return ret;
6604 }
6605
6606 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
6607                                       struct ieee80211_vif *vif)
6608 {
6609         struct rtl8xxxu_priv *priv = hw->priv;
6610
6611         dev_dbg(&priv->udev->dev, "%s\n", __func__);
6612
6613         if (priv->vif)
6614                 priv->vif = NULL;
6615 }
6616
6617 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
6618 {
6619         struct rtl8xxxu_priv *priv = hw->priv;
6620         struct device *dev = &priv->udev->dev;
6621         int ret = 0, channel;
6622         bool ht40;
6623
6624         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
6625                 dev_info(dev,
6626                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
6627                          __func__, hw->conf.chandef.chan->hw_value,
6628                          changed, hw->conf.chandef.width);
6629
6630         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
6631                 switch (hw->conf.chandef.width) {
6632                 case NL80211_CHAN_WIDTH_20_NOHT:
6633                 case NL80211_CHAN_WIDTH_20:
6634                         ht40 = false;
6635                         break;
6636                 case NL80211_CHAN_WIDTH_40:
6637                         ht40 = true;
6638                         break;
6639                 default:
6640                         ret = -ENOTSUPP;
6641                         goto exit;
6642                 }
6643
6644                 channel = hw->conf.chandef.chan->hw_value;
6645
6646                 priv->fops->set_tx_power(priv, channel, ht40);
6647
6648                 priv->fops->config_channel(hw);
6649         }
6650
6651 exit:
6652         return ret;
6653 }
6654
6655 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
6656                             struct ieee80211_vif *vif,
6657                             unsigned int link_id, u16 queue,
6658                             const struct ieee80211_tx_queue_params *param)
6659 {
6660         struct rtl8xxxu_priv *priv = hw->priv;
6661         struct device *dev = &priv->udev->dev;
6662         u32 val32;
6663         u8 aifs, acm_ctrl, acm_bit;
6664
6665         aifs = param->aifs;
6666
6667         val32 = aifs |
6668                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
6669                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
6670                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
6671
6672         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
6673         dev_dbg(dev,
6674                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
6675                 __func__, queue, val32, param->acm, acm_ctrl);
6676
6677         switch (queue) {
6678         case IEEE80211_AC_VO:
6679                 acm_bit = ACM_HW_CTRL_VO;
6680                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
6681                 break;
6682         case IEEE80211_AC_VI:
6683                 acm_bit = ACM_HW_CTRL_VI;
6684                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
6685                 break;
6686         case IEEE80211_AC_BE:
6687                 acm_bit = ACM_HW_CTRL_BE;
6688                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
6689                 break;
6690         case IEEE80211_AC_BK:
6691                 acm_bit = ACM_HW_CTRL_BK;
6692                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
6693                 break;
6694         default:
6695                 acm_bit = 0;
6696                 break;
6697         }
6698
6699         if (param->acm)
6700                 acm_ctrl |= acm_bit;
6701         else
6702                 acm_ctrl &= ~acm_bit;
6703         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
6704
6705         return 0;
6706 }
6707
6708 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
6709                                       unsigned int changed_flags,
6710                                       unsigned int *total_flags, u64 multicast)
6711 {
6712         struct rtl8xxxu_priv *priv = hw->priv;
6713         u32 rcr = priv->regrcr;
6714
6715         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
6716                 __func__, changed_flags, *total_flags);
6717
6718         /*
6719          * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
6720          */
6721
6722         if (*total_flags & FIF_FCSFAIL)
6723                 rcr |= RCR_ACCEPT_CRC32;
6724         else
6725                 rcr &= ~RCR_ACCEPT_CRC32;
6726
6727         /*
6728          * FIF_PLCPFAIL not supported?
6729          */
6730
6731         if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
6732                 rcr &= ~(RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH);
6733         else
6734                 rcr |= RCR_CHECK_BSSID_BEACON | RCR_CHECK_BSSID_MATCH;
6735
6736         if (priv->vif && priv->vif->type == NL80211_IFTYPE_AP)
6737                 rcr &= ~RCR_CHECK_BSSID_MATCH;
6738
6739         if (*total_flags & FIF_CONTROL)
6740                 rcr |= RCR_ACCEPT_CTRL_FRAME;
6741         else
6742                 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
6743
6744         if (*total_flags & FIF_OTHER_BSS)
6745                 rcr |= RCR_ACCEPT_AP;
6746         else
6747                 rcr &= ~RCR_ACCEPT_AP;
6748
6749         if (*total_flags & FIF_PSPOLL)
6750                 rcr |= RCR_ACCEPT_PM;
6751         else
6752                 rcr &= ~RCR_ACCEPT_PM;
6753
6754         /*
6755          * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
6756          */
6757
6758         rtl8xxxu_write32(priv, REG_RCR, rcr);
6759         priv->regrcr = rcr;
6760
6761         *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
6762                          FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
6763                          FIF_PROBE_REQ);
6764 }
6765
6766 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
6767 {
6768         if (rts > 2347 && rts != (u32)-1)
6769                 return -EINVAL;
6770
6771         return 0;
6772 }
6773
6774 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
6775                             struct ieee80211_vif *vif,
6776                             struct ieee80211_sta *sta,
6777                             struct ieee80211_key_conf *key)
6778 {
6779         struct rtl8xxxu_priv *priv = hw->priv;
6780         struct device *dev = &priv->udev->dev;
6781         u8 mac_addr[ETH_ALEN];
6782         u8 val8;
6783         u16 val16;
6784         u32 val32;
6785         int retval = -EOPNOTSUPP;
6786
6787         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
6788                 __func__, cmd, key->cipher, key->keyidx);
6789
6790         if (vif->type != NL80211_IFTYPE_STATION)
6791                 return -EOPNOTSUPP;
6792
6793         if (key->keyidx > 3)
6794                 return -EOPNOTSUPP;
6795
6796         switch (key->cipher) {
6797         case WLAN_CIPHER_SUITE_WEP40:
6798         case WLAN_CIPHER_SUITE_WEP104:
6799
6800                 break;
6801         case WLAN_CIPHER_SUITE_CCMP:
6802                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
6803                 break;
6804         case WLAN_CIPHER_SUITE_TKIP:
6805                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
6806                 break;
6807         default:
6808                 return -EOPNOTSUPP;
6809         }
6810
6811         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
6812                 dev_dbg(dev, "%s: pairwise key\n", __func__);
6813                 ether_addr_copy(mac_addr, sta->addr);
6814         } else {
6815                 dev_dbg(dev, "%s: group key\n", __func__);
6816                 eth_broadcast_addr(mac_addr);
6817         }
6818
6819         val16 = rtl8xxxu_read16(priv, REG_CR);
6820         val16 |= CR_SECURITY_ENABLE;
6821         rtl8xxxu_write16(priv, REG_CR, val16);
6822
6823         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
6824                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
6825         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
6826         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
6827
6828         switch (cmd) {
6829         case SET_KEY:
6830                 key->hw_key_idx = key->keyidx;
6831                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
6832                 rtl8xxxu_cam_write(priv, key, mac_addr);
6833                 retval = 0;
6834                 break;
6835         case DISABLE_KEY:
6836                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
6837                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
6838                         key->keyidx << CAM_CMD_KEY_SHIFT;
6839                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
6840                 retval = 0;
6841                 break;
6842         default:
6843                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
6844         }
6845
6846         return retval;
6847 }
6848
6849 static int
6850 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6851                       struct ieee80211_ampdu_params *params)
6852 {
6853         struct rtl8xxxu_priv *priv = hw->priv;
6854         struct device *dev = &priv->udev->dev;
6855         u8 ampdu_factor, ampdu_density;
6856         struct ieee80211_sta *sta = params->sta;
6857         u16 tid = params->tid;
6858         enum ieee80211_ampdu_mlme_action action = params->action;
6859
6860         switch (action) {
6861         case IEEE80211_AMPDU_TX_START:
6862                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
6863                 ampdu_factor = sta->deflink.ht_cap.ampdu_factor;
6864                 ampdu_density = sta->deflink.ht_cap.ampdu_density;
6865                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
6866                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
6867                 dev_dbg(dev,
6868                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
6869                         ampdu_factor, ampdu_density);
6870                 return IEEE80211_AMPDU_TX_START_IMMEDIATE;
6871         case IEEE80211_AMPDU_TX_STOP_CONT:
6872         case IEEE80211_AMPDU_TX_STOP_FLUSH:
6873         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
6874                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP\n", __func__);
6875                 rtl8xxxu_set_ampdu_factor(priv, 0);
6876                 rtl8xxxu_set_ampdu_min_space(priv, 0);
6877                 clear_bit(tid, priv->tx_aggr_started);
6878                 clear_bit(tid, priv->tid_tx_operational);
6879                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
6880                 break;
6881         case IEEE80211_AMPDU_TX_OPERATIONAL:
6882                 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_OPERATIONAL\n", __func__);
6883                 set_bit(tid, priv->tid_tx_operational);
6884                 break;
6885         case IEEE80211_AMPDU_RX_START:
6886                 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
6887                 break;
6888         case IEEE80211_AMPDU_RX_STOP:
6889                 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
6890                 break;
6891         default:
6892                 break;
6893         }
6894         return 0;
6895 }
6896
6897 static void
6898 rtl8xxxu_sta_statistics(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
6899                         struct ieee80211_sta *sta, struct station_info *sinfo)
6900 {
6901         struct rtl8xxxu_priv *priv = hw->priv;
6902
6903         sinfo->txrate = priv->ra_report.txrate;
6904         sinfo->filled |= BIT_ULL(NL80211_STA_INFO_TX_BITRATE);
6905 }
6906
6907 static u8 rtl8xxxu_signal_to_snr(int signal)
6908 {
6909         if (signal < RTL8XXXU_NOISE_FLOOR_MIN)
6910                 signal = RTL8XXXU_NOISE_FLOOR_MIN;
6911         else if (signal > 0)
6912                 signal = 0;
6913         return (u8)(signal - RTL8XXXU_NOISE_FLOOR_MIN);
6914 }
6915
6916 static void rtl8xxxu_refresh_rate_mask(struct rtl8xxxu_priv *priv,
6917                                        int signal, struct ieee80211_sta *sta,
6918                                        bool force)
6919 {
6920         struct ieee80211_hw *hw = priv->hw;
6921         u16 wireless_mode;
6922         u8 rssi_level, ratr_idx;
6923         u8 txbw_40mhz;
6924         u8 snr, snr_thresh_high, snr_thresh_low;
6925         u8 go_up_gap = 5;
6926         u8 macid = rtl8xxxu_get_macid(priv, sta);
6927
6928         rssi_level = priv->rssi_level;
6929         snr = rtl8xxxu_signal_to_snr(signal);
6930         snr_thresh_high = RTL8XXXU_SNR_THRESH_HIGH;
6931         snr_thresh_low = RTL8XXXU_SNR_THRESH_LOW;
6932         txbw_40mhz = (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) ? 1 : 0;
6933
6934         switch (rssi_level) {
6935         case RTL8XXXU_RATR_STA_MID:
6936                 snr_thresh_high += go_up_gap;
6937                 break;
6938         case RTL8XXXU_RATR_STA_LOW:
6939                 snr_thresh_high += go_up_gap;
6940                 snr_thresh_low += go_up_gap;
6941                 break;
6942         default:
6943                 break;
6944         }
6945
6946         if (snr > snr_thresh_high)
6947                 rssi_level = RTL8XXXU_RATR_STA_HIGH;
6948         else if (snr > snr_thresh_low)
6949                 rssi_level = RTL8XXXU_RATR_STA_MID;
6950         else
6951                 rssi_level = RTL8XXXU_RATR_STA_LOW;
6952
6953         if (rssi_level != priv->rssi_level || force) {
6954                 int sgi = 0;
6955                 u32 rate_bitmap = 0;
6956
6957                 rcu_read_lock();
6958                 rate_bitmap = (sta->deflink.supp_rates[0] & 0xfff) |
6959                                 (sta->deflink.ht_cap.mcs.rx_mask[0] << 12) |
6960                                 (sta->deflink.ht_cap.mcs.rx_mask[1] << 20);
6961                 if (sta->deflink.ht_cap.cap &
6962                     (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
6963                         sgi = 1;
6964                 rcu_read_unlock();
6965
6966                 wireless_mode = rtl8xxxu_wireless_mode(hw, sta);
6967                 switch (wireless_mode) {
6968                 case WIRELESS_MODE_B:
6969                         ratr_idx = RATEID_IDX_B;
6970                         if (rate_bitmap & 0x0000000c)
6971                                 rate_bitmap &= 0x0000000d;
6972                         else
6973                                 rate_bitmap &= 0x0000000f;
6974                         break;
6975                 case WIRELESS_MODE_A:
6976                 case WIRELESS_MODE_G:
6977                         ratr_idx = RATEID_IDX_G;
6978                         if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6979                                 rate_bitmap &= 0x00000f00;
6980                         else
6981                                 rate_bitmap &= 0x00000ff0;
6982                         break;
6983                 case (WIRELESS_MODE_B | WIRELESS_MODE_G):
6984                         ratr_idx = RATEID_IDX_BG;
6985                         if (rssi_level == RTL8XXXU_RATR_STA_HIGH)
6986                                 rate_bitmap &= 0x00000f00;
6987                         else if (rssi_level == RTL8XXXU_RATR_STA_MID)
6988                                 rate_bitmap &= 0x00000ff0;
6989                         else
6990                                 rate_bitmap &= 0x00000ff5;
6991                         break;
6992                 case WIRELESS_MODE_N_24G:
6993                 case WIRELESS_MODE_N_5G:
6994                 case (WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
6995                 case (WIRELESS_MODE_A | WIRELESS_MODE_N_5G):
6996                         if (priv->tx_paths == 2 && priv->rx_paths == 2)
6997                                 ratr_idx = RATEID_IDX_GN_N2SS;
6998                         else
6999                                 ratr_idx = RATEID_IDX_GN_N1SS;
7000                         break;
7001                 case (WIRELESS_MODE_B | WIRELESS_MODE_G | WIRELESS_MODE_N_24G):
7002                 case (WIRELESS_MODE_B | WIRELESS_MODE_N_24G):
7003                         if (txbw_40mhz) {
7004                                 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7005                                         ratr_idx = RATEID_IDX_BGN_40M_2SS;
7006                                 else
7007                                         ratr_idx = RATEID_IDX_BGN_40M_1SS;
7008                         } else {
7009                                 if (priv->tx_paths == 2 && priv->rx_paths == 2)
7010                                         ratr_idx = RATEID_IDX_BGN_20M_2SS_BN;
7011                                 else
7012                                         ratr_idx = RATEID_IDX_BGN_20M_1SS_BN;
7013                         }
7014
7015                         if (priv->tx_paths == 2 && priv->rx_paths == 2) {
7016                                 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7017                                         rate_bitmap &= 0x0f8f0000;
7018                                 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7019                                         rate_bitmap &= 0x0f8ff000;
7020                                 } else {
7021                                         if (txbw_40mhz)
7022                                                 rate_bitmap &= 0x0f8ff015;
7023                                         else
7024                                                 rate_bitmap &= 0x0f8ff005;
7025                                 }
7026                         } else {
7027                                 if (rssi_level == RTL8XXXU_RATR_STA_HIGH) {
7028                                         rate_bitmap &= 0x000f0000;
7029                                 } else if (rssi_level == RTL8XXXU_RATR_STA_MID) {
7030                                         rate_bitmap &= 0x000ff000;
7031                                 } else {
7032                                         if (txbw_40mhz)
7033                                                 rate_bitmap &= 0x000ff015;
7034                                         else
7035                                                 rate_bitmap &= 0x000ff005;
7036                                 }
7037                         }
7038                         break;
7039                 default:
7040                         ratr_idx = RATEID_IDX_BGN_40M_2SS;
7041                         rate_bitmap &= 0x0fffffff;
7042                         break;
7043                 }
7044
7045                 priv->rssi_level = rssi_level;
7046                 priv->fops->update_rate_mask(priv, rate_bitmap, ratr_idx, sgi, txbw_40mhz, macid);
7047         }
7048 }
7049
7050 static void rtl8xxxu_set_atc_status(struct rtl8xxxu_priv *priv, bool atc_status)
7051 {
7052         struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7053         u32 val32;
7054
7055         if (atc_status == cfo->atc_status)
7056                 return;
7057
7058         cfo->atc_status = atc_status;
7059
7060         val32 = rtl8xxxu_read32(priv, REG_OFDM1_CFO_TRACKING);
7061         if (atc_status)
7062                 val32 |= CFO_TRACKING_ATC_STATUS;
7063         else
7064                 val32 &= ~CFO_TRACKING_ATC_STATUS;
7065         rtl8xxxu_write32(priv, REG_OFDM1_CFO_TRACKING, val32);
7066 }
7067
7068 /* Central frequency offset correction */
7069 static void rtl8xxxu_track_cfo(struct rtl8xxxu_priv *priv)
7070 {
7071         struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
7072         int cfo_khz_a, cfo_khz_b, cfo_average;
7073         int crystal_cap;
7074
7075         if (!priv->vif || !priv->vif->cfg.assoc) {
7076                 /* Reset */
7077                 cfo->adjust = true;
7078
7079                 if (cfo->crystal_cap > priv->default_crystal_cap)
7080                         priv->fops->set_crystal_cap(priv, cfo->crystal_cap - 1);
7081                 else if (cfo->crystal_cap < priv->default_crystal_cap)
7082                         priv->fops->set_crystal_cap(priv, cfo->crystal_cap + 1);
7083
7084                 rtl8xxxu_set_atc_status(priv, true);
7085
7086                 return;
7087         }
7088
7089         if (cfo->packet_count == cfo->packet_count_pre)
7090                 /* No new information. */
7091                 return;
7092
7093         cfo->packet_count_pre = cfo->packet_count;
7094
7095         /* CFO_tail[1:0] is S(8,7), (num_subcarrier>>7) x 312.5K = CFO value(K Hz) */
7096         cfo_khz_a = (int)((cfo->cfo_tail[0] * 3125) / 10) >> 7;
7097         cfo_khz_b = (int)((cfo->cfo_tail[1] * 3125) / 10) >> 7;
7098
7099         if (priv->tx_paths == 1)
7100                 cfo_average = cfo_khz_a;
7101         else
7102                 cfo_average = (cfo_khz_a + cfo_khz_b) / 2;
7103
7104         dev_dbg(&priv->udev->dev, "cfo_average: %d\n", cfo_average);
7105
7106         if (cfo->adjust) {
7107                 if (abs(cfo_average) < CFO_TH_XTAL_LOW)
7108                         cfo->adjust = false;
7109         } else {
7110                 if (abs(cfo_average) > CFO_TH_XTAL_HIGH)
7111                         cfo->adjust = true;
7112         }
7113
7114         /*
7115          * TODO: We should return here only if bluetooth is enabled.
7116          * See the vendor drivers for how to determine that.
7117          */
7118         if (priv->has_bluetooth)
7119                 return;
7120
7121         if (!cfo->adjust)
7122                 return;
7123
7124         crystal_cap = cfo->crystal_cap;
7125
7126         if (cfo_average > CFO_TH_XTAL_LOW)
7127                 crystal_cap++;
7128         else if (cfo_average < -CFO_TH_XTAL_LOW)
7129                 crystal_cap--;
7130
7131         crystal_cap = clamp(crystal_cap, 0, 0x3f);
7132
7133         priv->fops->set_crystal_cap(priv, crystal_cap);
7134
7135         rtl8xxxu_set_atc_status(priv, abs(cfo_average) >= CFO_TH_ATC);
7136 }
7137
7138 static void rtl8xxxu_watchdog_callback(struct work_struct *work)
7139 {
7140         struct ieee80211_vif *vif;
7141         struct rtl8xxxu_priv *priv;
7142
7143         priv = container_of(work, struct rtl8xxxu_priv, ra_watchdog.work);
7144         vif = priv->vif;
7145
7146         if (vif && vif->type == NL80211_IFTYPE_STATION) {
7147                 int signal;
7148                 struct ieee80211_sta *sta;
7149
7150                 rcu_read_lock();
7151                 sta = ieee80211_find_sta(vif, vif->bss_conf.bssid);
7152                 if (!sta) {
7153                         struct device *dev = &priv->udev->dev;
7154
7155                         dev_dbg(dev, "%s: no sta found\n", __func__);
7156                         rcu_read_unlock();
7157                         goto out;
7158                 }
7159                 rcu_read_unlock();
7160
7161                 signal = ieee80211_ave_rssi(vif);
7162
7163                 priv->fops->report_rssi(priv, 0,
7164                                         rtl8xxxu_signal_to_snr(signal));
7165
7166                 if (priv->fops->set_crystal_cap)
7167                         rtl8xxxu_track_cfo(priv);
7168
7169                 rtl8xxxu_refresh_rate_mask(priv, signal, sta, false);
7170         }
7171
7172 out:
7173         schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7174 }
7175
7176 static int rtl8xxxu_start(struct ieee80211_hw *hw)
7177 {
7178         struct rtl8xxxu_priv *priv = hw->priv;
7179         struct rtl8xxxu_rx_urb *rx_urb;
7180         struct rtl8xxxu_tx_urb *tx_urb;
7181         struct sk_buff *skb;
7182         unsigned long flags;
7183         int ret, i;
7184
7185         ret = 0;
7186
7187         init_usb_anchor(&priv->rx_anchor);
7188         init_usb_anchor(&priv->tx_anchor);
7189         init_usb_anchor(&priv->int_anchor);
7190
7191         priv->fops->enable_rf(priv);
7192         if (priv->usb_interrupts) {
7193                 ret = rtl8xxxu_submit_int_urb(hw);
7194                 if (ret)
7195                         goto exit;
7196         }
7197
7198         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
7199                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
7200                 if (!tx_urb) {
7201                         if (!i)
7202                                 ret = -ENOMEM;
7203
7204                         goto error_out;
7205                 }
7206                 usb_init_urb(&tx_urb->urb);
7207                 INIT_LIST_HEAD(&tx_urb->list);
7208                 tx_urb->hw = hw;
7209                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
7210                 priv->tx_urb_free_count++;
7211         }
7212
7213         priv->tx_stopped = false;
7214
7215         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7216         priv->shutdown = false;
7217         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7218
7219         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
7220                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
7221                 if (!rx_urb) {
7222                         if (!i)
7223                                 ret = -ENOMEM;
7224
7225                         goto error_out;
7226                 }
7227                 usb_init_urb(&rx_urb->urb);
7228                 INIT_LIST_HEAD(&rx_urb->list);
7229                 rx_urb->hw = hw;
7230
7231                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
7232                 if (ret) {
7233                         if (ret != -ENOMEM) {
7234                                 skb = (struct sk_buff *)rx_urb->urb.context;
7235                                 dev_kfree_skb(skb);
7236                         }
7237                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
7238                 }
7239         }
7240
7241         schedule_delayed_work(&priv->ra_watchdog, 2 * HZ);
7242 exit:
7243         /*
7244          * Accept all data and mgmt frames
7245          */
7246         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
7247         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
7248
7249         rtl8xxxu_write32_mask(priv, REG_OFDM0_XA_AGC_CORE1,
7250                               OFDM0_X_AGC_CORE1_IGI_MASK, 0x1e);
7251
7252         return ret;
7253
7254 error_out:
7255         rtl8xxxu_free_tx_resources(priv);
7256         /*
7257          * Disable all data and mgmt frames
7258          */
7259         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7260         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7261
7262         return ret;
7263 }
7264
7265 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
7266 {
7267         struct rtl8xxxu_priv *priv = hw->priv;
7268         unsigned long flags;
7269
7270         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7271
7272         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
7273         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
7274
7275         spin_lock_irqsave(&priv->rx_urb_lock, flags);
7276         priv->shutdown = true;
7277         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
7278
7279         usb_kill_anchored_urbs(&priv->rx_anchor);
7280         usb_kill_anchored_urbs(&priv->tx_anchor);
7281         if (priv->usb_interrupts)
7282                 usb_kill_anchored_urbs(&priv->int_anchor);
7283
7284         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
7285
7286         priv->fops->disable_rf(priv);
7287
7288         /*
7289          * Disable interrupts
7290          */
7291         if (priv->usb_interrupts)
7292                 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
7293
7294         cancel_work_sync(&priv->c2hcmd_work);
7295         cancel_delayed_work_sync(&priv->ra_watchdog);
7296
7297         rtl8xxxu_free_rx_resources(priv);
7298         rtl8xxxu_free_tx_resources(priv);
7299 }
7300
7301 static int rtl8xxxu_sta_add(struct ieee80211_hw *hw,
7302                             struct ieee80211_vif *vif,
7303                             struct ieee80211_sta *sta)
7304 {
7305         struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7306         struct rtl8xxxu_priv *priv = hw->priv;
7307
7308         if (vif->type == NL80211_IFTYPE_AP) {
7309                 sta_info->macid = rtl8xxxu_acquire_macid(priv);
7310                 if (sta_info->macid >= RTL8XXXU_MAX_MAC_ID_NUM)
7311                         return -ENOSPC;
7312
7313                 rtl8xxxu_refresh_rate_mask(priv, 0, sta, true);
7314                 priv->fops->report_connect(priv, sta_info->macid, H2C_MACID_ROLE_STA, true);
7315         }
7316
7317         return 0;
7318 }
7319
7320 static int rtl8xxxu_sta_remove(struct ieee80211_hw *hw,
7321                                struct ieee80211_vif *vif,
7322                                struct ieee80211_sta *sta)
7323 {
7324         struct rtl8xxxu_sta_info *sta_info = (struct rtl8xxxu_sta_info *)sta->drv_priv;
7325         struct rtl8xxxu_priv *priv = hw->priv;
7326
7327         if (vif->type == NL80211_IFTYPE_AP)
7328                 rtl8xxxu_release_macid(priv, sta_info->macid);
7329
7330         return 0;
7331 }
7332
7333 static const struct ieee80211_ops rtl8xxxu_ops = {
7334         .tx = rtl8xxxu_tx,
7335         .wake_tx_queue = ieee80211_handle_wake_tx_queue,
7336         .add_interface = rtl8xxxu_add_interface,
7337         .remove_interface = rtl8xxxu_remove_interface,
7338         .config = rtl8xxxu_config,
7339         .conf_tx = rtl8xxxu_conf_tx,
7340         .bss_info_changed = rtl8xxxu_bss_info_changed,
7341         .start_ap = rtl8xxxu_start_ap,
7342         .configure_filter = rtl8xxxu_configure_filter,
7343         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
7344         .start = rtl8xxxu_start,
7345         .stop = rtl8xxxu_stop,
7346         .sw_scan_start = rtl8xxxu_sw_scan_start,
7347         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
7348         .set_key = rtl8xxxu_set_key,
7349         .ampdu_action = rtl8xxxu_ampdu_action,
7350         .sta_statistics = rtl8xxxu_sta_statistics,
7351         .get_antenna = rtl8xxxu_get_antenna,
7352         .set_tim = rtl8xxxu_set_tim,
7353         .sta_add = rtl8xxxu_sta_add,
7354         .sta_remove = rtl8xxxu_sta_remove,
7355 };
7356
7357 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
7358                               struct usb_interface *interface)
7359 {
7360         struct usb_interface_descriptor *interface_desc;
7361         struct usb_host_interface *host_interface;
7362         struct usb_endpoint_descriptor *endpoint;
7363         struct device *dev = &priv->udev->dev;
7364         int i, j = 0, endpoints;
7365         u8 dir, xtype, num;
7366         int ret = 0;
7367
7368         host_interface = interface->cur_altsetting;
7369         interface_desc = &host_interface->desc;
7370         endpoints = interface_desc->bNumEndpoints;
7371
7372         for (i = 0; i < endpoints; i++) {
7373                 endpoint = &host_interface->endpoint[i].desc;
7374
7375                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
7376                 num = usb_endpoint_num(endpoint);
7377                 xtype = usb_endpoint_type(endpoint);
7378                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7379                         dev_dbg(dev,
7380                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
7381                                 __func__, dir, num, xtype);
7382                 if (usb_endpoint_dir_in(endpoint) &&
7383                     usb_endpoint_xfer_bulk(endpoint)) {
7384                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7385                                 dev_dbg(dev, "%s: in endpoint num %i\n",
7386                                         __func__, num);
7387
7388                         if (priv->pipe_in) {
7389                                 dev_warn(dev,
7390                                          "%s: Too many IN pipes\n", __func__);
7391                                 ret = -EINVAL;
7392                                 goto exit;
7393                         }
7394
7395                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
7396                 }
7397
7398                 if (usb_endpoint_dir_in(endpoint) &&
7399                     usb_endpoint_xfer_int(endpoint)) {
7400                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7401                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
7402                                         __func__, num);
7403
7404                         if (priv->pipe_interrupt) {
7405                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
7406                                          __func__);
7407                                 ret = -EINVAL;
7408                                 goto exit;
7409                         }
7410
7411                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
7412                 }
7413
7414                 if (usb_endpoint_dir_out(endpoint) &&
7415                     usb_endpoint_xfer_bulk(endpoint)) {
7416                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
7417                                 dev_dbg(dev, "%s: out endpoint num %i\n",
7418                                         __func__, num);
7419                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
7420                                 dev_warn(dev,
7421                                          "%s: Too many OUT pipes\n", __func__);
7422                                 ret = -EINVAL;
7423                                 goto exit;
7424                         }
7425                         priv->out_ep[j++] = num;
7426                 }
7427         }
7428 exit:
7429         priv->nr_out_eps = j;
7430         return ret;
7431 }
7432
7433 static void rtl8xxxu_init_led(struct rtl8xxxu_priv *priv)
7434 {
7435         struct led_classdev *led = &priv->led_cdev;
7436
7437         if (!priv->fops->led_classdev_brightness_set)
7438                 return;
7439
7440         led->brightness_set_blocking = priv->fops->led_classdev_brightness_set;
7441
7442         snprintf(priv->led_name, sizeof(priv->led_name),
7443                  "rtl8xxxu-usb%s", dev_name(&priv->udev->dev));
7444         led->name = priv->led_name;
7445         led->max_brightness = RTL8XXXU_HW_LED_CONTROL;
7446
7447         if (led_classdev_register(&priv->udev->dev, led))
7448                 return;
7449
7450         priv->led_registered = true;
7451
7452         led->brightness = led->max_brightness;
7453         priv->fops->led_classdev_brightness_set(led, led->brightness);
7454 }
7455
7456 static void rtl8xxxu_deinit_led(struct rtl8xxxu_priv *priv)
7457 {
7458         struct led_classdev *led = &priv->led_cdev;
7459
7460         if (!priv->led_registered)
7461                 return;
7462
7463         priv->fops->led_classdev_brightness_set(led, LED_OFF);
7464         led_classdev_unregister(led);
7465 }
7466
7467 static int rtl8xxxu_probe(struct usb_interface *interface,
7468                           const struct usb_device_id *id)
7469 {
7470         struct rtl8xxxu_priv *priv;
7471         struct ieee80211_hw *hw;
7472         struct usb_device *udev;
7473         struct ieee80211_supported_band *sband;
7474         int ret;
7475         int untested = 1;
7476
7477         udev = usb_get_dev(interface_to_usbdev(interface));
7478
7479         switch (id->idVendor) {
7480         case USB_VENDOR_ID_REALTEK:
7481                 switch(id->idProduct) {
7482                 case 0x1724:
7483                 case 0x8176:
7484                 case 0x8178:
7485                 case 0x817f:
7486                 case 0x818b:
7487                 case 0xf179:
7488                 case 0x8179:
7489                 case 0xb711:
7490                 case 0xf192:
7491                 case 0x2005:
7492                         untested = 0;
7493                         break;
7494                 }
7495                 break;
7496         case 0x7392:
7497                 if (id->idProduct == 0x7811 || id->idProduct == 0xa611 || id->idProduct == 0xb811)
7498                         untested = 0;
7499                 break;
7500         case 0x050d:
7501                 if (id->idProduct == 0x1004)
7502                         untested = 0;
7503                 break;
7504         case 0x20f4:
7505                 if (id->idProduct == 0x648b)
7506                         untested = 0;
7507                 break;
7508         case 0x2001:
7509                 if (id->idProduct == 0x3308)
7510                         untested = 0;
7511                 break;
7512         case 0x2357:
7513                 if (id->idProduct == 0x0109)
7514                         untested = 0;
7515                 break;
7516         case 0x0b05:
7517                 if (id->idProduct == 0x18f1)
7518                         untested = 0;
7519                 break;
7520         default:
7521                 break;
7522         }
7523
7524         if (untested) {
7525                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
7526                 dev_info(&udev->dev,
7527                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
7528                          id->idVendor, id->idProduct);
7529                 dev_info(&udev->dev,
7530                          "Please report results to Jes.Sorensen@gmail.com\n");
7531         }
7532
7533         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
7534         if (!hw) {
7535                 ret = -ENOMEM;
7536                 goto err_put_dev;
7537         }
7538
7539         priv = hw->priv;
7540         priv->hw = hw;
7541         priv->udev = udev;
7542         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
7543         mutex_init(&priv->usb_buf_mutex);
7544         mutex_init(&priv->syson_indirect_access_mutex);
7545         mutex_init(&priv->h2c_mutex);
7546         INIT_LIST_HEAD(&priv->tx_urb_free_list);
7547         spin_lock_init(&priv->tx_urb_lock);
7548         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
7549         spin_lock_init(&priv->rx_urb_lock);
7550         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
7551         INIT_DELAYED_WORK(&priv->ra_watchdog, rtl8xxxu_watchdog_callback);
7552         INIT_WORK(&priv->update_beacon_work, rtl8xxxu_update_beacon_work_callback);
7553         skb_queue_head_init(&priv->c2hcmd_queue);
7554
7555         usb_set_intfdata(interface, hw);
7556
7557         ret = rtl8xxxu_parse_usb(priv, interface);
7558         if (ret)
7559                 goto err_set_intfdata;
7560
7561         ret = priv->fops->identify_chip(priv);
7562         if (ret) {
7563                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
7564                 goto err_set_intfdata;
7565         }
7566
7567         hw->wiphy->available_antennas_tx = BIT(priv->tx_paths) - 1;
7568         hw->wiphy->available_antennas_rx = BIT(priv->rx_paths) - 1;
7569
7570         if (priv->rtl_chip == RTL8188E)
7571                 INIT_WORK(&priv->c2hcmd_work, rtl8188e_c2hcmd_callback);
7572         else
7573                 INIT_WORK(&priv->c2hcmd_work, rtl8xxxu_c2hcmd_callback);
7574
7575         ret = priv->fops->read_efuse(priv);
7576         if (ret) {
7577                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
7578                 goto err_set_intfdata;
7579         }
7580
7581         ret = priv->fops->parse_efuse(priv);
7582         if (ret) {
7583                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
7584                 goto err_set_intfdata;
7585         }
7586
7587         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE)
7588                 rtl8xxxu_dump_efuse(priv);
7589
7590         rtl8xxxu_print_chipinfo(priv);
7591
7592         ret = priv->fops->load_firmware(priv);
7593         if (ret) {
7594                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
7595                 goto err_set_intfdata;
7596         }
7597
7598         ret = rtl8xxxu_init_device(hw);
7599         if (ret)
7600                 goto err_set_intfdata;
7601
7602         hw->wiphy->max_scan_ssids = 1;
7603         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
7604         if (priv->fops->max_macid_num)
7605                 hw->wiphy->max_ap_assoc_sta = priv->fops->max_macid_num - 1;
7606         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
7607         if (priv->fops->supports_ap)
7608                 hw->wiphy->interface_modes |= BIT(NL80211_IFTYPE_AP);
7609         hw->queues = 4;
7610
7611         sband = &rtl8xxxu_supported_band;
7612         sband->ht_cap.ht_supported = true;
7613         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
7614         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
7615         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
7616         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
7617         sband->ht_cap.mcs.rx_mask[0] = 0xff;
7618         sband->ht_cap.mcs.rx_mask[4] = 0x01;
7619         if (priv->rf_paths > 1) {
7620                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
7621                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
7622         }
7623         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
7624         /*
7625          * Some APs will negotiate HT20_40 in a noisy environment leading
7626          * to miserable performance. Rather than defaulting to this, only
7627          * enable it if explicitly requested at module load time.
7628          */
7629         if (rtl8xxxu_ht40_2g) {
7630                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
7631                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
7632         }
7633         hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
7634
7635         hw->wiphy->rts_threshold = 2347;
7636
7637         SET_IEEE80211_DEV(priv->hw, &interface->dev);
7638         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
7639
7640         hw->extra_tx_headroom = priv->fops->tx_desc_size;
7641         ieee80211_hw_set(hw, SIGNAL_DBM);
7642
7643         /*
7644          * The firmware handles rate control, except for RTL8188EU,
7645          * where we handle the rate control in the driver.
7646          */
7647         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
7648         ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
7649         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
7650
7651         wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
7652
7653         ret = ieee80211_register_hw(priv->hw);
7654         if (ret) {
7655                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
7656                         __func__, ret);
7657                 goto err_set_intfdata;
7658         }
7659
7660         rtl8xxxu_init_led(priv);
7661
7662         return 0;
7663
7664 err_set_intfdata:
7665         usb_set_intfdata(interface, NULL);
7666
7667         kfree(priv->fw_data);
7668         mutex_destroy(&priv->usb_buf_mutex);
7669         mutex_destroy(&priv->syson_indirect_access_mutex);
7670         mutex_destroy(&priv->h2c_mutex);
7671
7672         ieee80211_free_hw(hw);
7673 err_put_dev:
7674         usb_put_dev(udev);
7675
7676         return ret;
7677 }
7678
7679 static void rtl8xxxu_disconnect(struct usb_interface *interface)
7680 {
7681         struct rtl8xxxu_priv *priv;
7682         struct ieee80211_hw *hw;
7683
7684         hw = usb_get_intfdata(interface);
7685         priv = hw->priv;
7686
7687         rtl8xxxu_deinit_led(priv);
7688
7689         ieee80211_unregister_hw(hw);
7690
7691         priv->fops->power_off(priv);
7692
7693         usb_set_intfdata(interface, NULL);
7694
7695         dev_info(&priv->udev->dev, "disconnecting\n");
7696
7697         kfree(priv->fw_data);
7698         mutex_destroy(&priv->usb_buf_mutex);
7699         mutex_destroy(&priv->syson_indirect_access_mutex);
7700         mutex_destroy(&priv->h2c_mutex);
7701
7702         if (priv->udev->state != USB_STATE_NOTATTACHED) {
7703                 dev_info(&priv->udev->dev,
7704                          "Device still attached, trying to reset\n");
7705                 usb_reset_device(priv->udev);
7706         }
7707         usb_put_dev(priv->udev);
7708         ieee80211_free_hw(hw);
7709 }
7710
7711 static const struct usb_device_id dev_table[] = {
7712 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
7713         .driver_info = (unsigned long)&rtl8723au_fops},
7714 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
7715         .driver_info = (unsigned long)&rtl8723au_fops},
7716 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
7717         .driver_info = (unsigned long)&rtl8723au_fops},
7718 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
7719         .driver_info = (unsigned long)&rtl8192eu_fops},
7720 /* TP-Link TL-WN822N v4 */
7721 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
7722         .driver_info = (unsigned long)&rtl8192eu_fops},
7723 /* D-Link DWA-131 rev E1, tested by David Patiño */
7724 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
7725         .driver_info = (unsigned long)&rtl8192eu_fops},
7726 /* Tested by Myckel Habets */
7727 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
7728         .driver_info = (unsigned long)&rtl8192eu_fops},
7729 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
7730         .driver_info = (unsigned long)&rtl8723bu_fops},
7731 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xa611, 0xff, 0xff, 0xff),
7732         .driver_info = (unsigned long)&rtl8723bu_fops},
7733 /* RTL8188FU */
7734 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf179, 0xff, 0xff, 0xff),
7735         .driver_info = (unsigned long)&rtl8188fu_fops},
7736 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8179, 0xff, 0xff, 0xff),
7737         .driver_info = (unsigned long)&rtl8188eu_fops},
7738 /* Tested by Hans de Goede - rtl8188etv */
7739 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0179, 0xff, 0xff, 0xff),
7740         .driver_info = (unsigned long)&rtl8188eu_fops},
7741 /* Sitecom rtl8188eus */
7742 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0076, 0xff, 0xff, 0xff),
7743         .driver_info = (unsigned long)&rtl8188eu_fops},
7744 /* D-Link USB-GO-N150 */
7745 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3311, 0xff, 0xff, 0xff),
7746         .driver_info = (unsigned long)&rtl8188eu_fops},
7747 /* D-Link DWA-125 REV D1 */
7748 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330f, 0xff, 0xff, 0xff),
7749         .driver_info = (unsigned long)&rtl8188eu_fops},
7750 /* D-Link DWA-123 REV D1 */
7751 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3310, 0xff, 0xff, 0xff),
7752         .driver_info = (unsigned long)&rtl8188eu_fops},
7753 /* D-Link DWA-121 rev B1 */
7754 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x331b, 0xff, 0xff, 0xff),
7755         .driver_info = (unsigned long)&rtl8188eu_fops},
7756 /* Abocom - Abocom */
7757 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8179, 0xff, 0xff, 0xff),
7758         .driver_info = (unsigned long)&rtl8188eu_fops},
7759 /* Elecom WDC-150SU2M */
7760 {USB_DEVICE_AND_INTERFACE_INFO(0x056e, 0x4008, 0xff, 0xff, 0xff),
7761         .driver_info = (unsigned long)&rtl8188eu_fops},
7762 /* TP-Link TL-WN722N v2 */
7763 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x010c, 0xff, 0xff, 0xff),
7764         .driver_info = (unsigned long)&rtl8188eu_fops},
7765 /* TP-Link TL-WN727N v5.21 */
7766 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0111, 0xff, 0xff, 0xff),
7767         .driver_info = (unsigned long)&rtl8188eu_fops},
7768 /* MERCUSYS MW150US v2 */
7769 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0102, 0xff, 0xff, 0xff),
7770         .driver_info = (unsigned long)&rtl8188eu_fops},
7771 /* ASUS USB-N10 Nano B1 */
7772 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f0, 0xff, 0xff, 0xff),
7773         .driver_info = (unsigned long)&rtl8188eu_fops},
7774  /* Edimax EW-7811Un V2 */
7775 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb811, 0xff, 0xff, 0xff),
7776         .driver_info = (unsigned long)&rtl8188eu_fops},
7777 /* Rosewill USB-N150 Nano */
7778 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xffef, 0xff, 0xff, 0xff),
7779         .driver_info = (unsigned long)&rtl8188eu_fops},
7780 /* RTL8710BU aka RTL8188GU (not to be confused with RTL8188GTVU) */
7781 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb711, 0xff, 0xff, 0xff),
7782         .driver_info = (unsigned long)&rtl8710bu_fops},
7783 /* TOTOLINK N150UA V5 / N150UA-B */
7784 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2005, 0xff, 0xff, 0xff),
7785         .driver_info = (unsigned long)&rtl8710bu_fops},
7786 /* Comfast CF-826F */
7787 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xf192, 0xff, 0xff, 0xff),
7788         .driver_info = (unsigned long)&rtl8192fu_fops},
7789 /* Asus USB-N13 rev C1 */
7790 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x18f1, 0xff, 0xff, 0xff),
7791         .driver_info = (unsigned long)&rtl8192fu_fops},
7792 /* EDIMAX EW-7722UTn V3 */
7793 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0xb722, 0xff, 0xff, 0xff),
7794         .driver_info = (unsigned long)&rtl8192fu_fops},
7795 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x318b, 0xff, 0xff, 0xff),
7796         .driver_info = (unsigned long)&rtl8192fu_fops},
7797 #ifdef CONFIG_RTL8XXXU_UNTESTED
7798 /* Still supported by rtlwifi */
7799 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
7800         .driver_info = (unsigned long)&rtl8192cu_fops},
7801 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
7802         .driver_info = (unsigned long)&rtl8192cu_fops},
7803 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
7804         .driver_info = (unsigned long)&rtl8192cu_fops},
7805 /* Tested by Larry Finger */
7806 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
7807         .driver_info = (unsigned long)&rtl8192cu_fops},
7808 /* Tested by Andrea Merello */
7809 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
7810         .driver_info = (unsigned long)&rtl8192cu_fops},
7811 /* Tested by Jocelyn Mayer */
7812 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
7813         .driver_info = (unsigned long)&rtl8192cu_fops},
7814 /* Tested by Stefano Bravi */
7815 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
7816         .driver_info = (unsigned long)&rtl8192cu_fops},
7817 /* Currently untested 8188 series devices */
7818 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x018a, 0xff, 0xff, 0xff),
7819         .driver_info = (unsigned long)&rtl8192cu_fops},
7820 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
7821         .driver_info = (unsigned long)&rtl8192cu_fops},
7822 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
7823         .driver_info = (unsigned long)&rtl8192cu_fops},
7824 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
7825         .driver_info = (unsigned long)&rtl8192cu_fops},
7826 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
7827         .driver_info = (unsigned long)&rtl8192cu_fops},
7828 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
7829         .driver_info = (unsigned long)&rtl8192cu_fops},
7830 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
7831         .driver_info = (unsigned long)&rtl8192cu_fops},
7832 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
7833         .driver_info = (unsigned long)&rtl8192cu_fops},
7834 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
7835         .driver_info = (unsigned long)&rtl8192cu_fops},
7836 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
7837         .driver_info = (unsigned long)&rtl8192cu_fops},
7838 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
7839         .driver_info = (unsigned long)&rtl8192cu_fops},
7840 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
7841         .driver_info = (unsigned long)&rtl8192cu_fops},
7842 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
7843         .driver_info = (unsigned long)&rtl8192cu_fops},
7844 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
7845         .driver_info = (unsigned long)&rtl8192cu_fops},
7846 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
7847         .driver_info = (unsigned long)&rtl8192cu_fops},
7848 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
7849         .driver_info = (unsigned long)&rtl8192cu_fops},
7850 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
7851         .driver_info = (unsigned long)&rtl8192cu_fops},
7852 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
7853         .driver_info = (unsigned long)&rtl8192cu_fops},
7854 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
7855         .driver_info = (unsigned long)&rtl8192cu_fops},
7856 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
7857         .driver_info = (unsigned long)&rtl8192cu_fops},
7858 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
7859         .driver_info = (unsigned long)&rtl8192cu_fops},
7860 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
7861         .driver_info = (unsigned long)&rtl8192cu_fops},
7862 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
7863         .driver_info = (unsigned long)&rtl8192cu_fops},
7864 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
7865         .driver_info = (unsigned long)&rtl8192cu_fops},
7866 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
7867         .driver_info = (unsigned long)&rtl8192cu_fops},
7868 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
7869         .driver_info = (unsigned long)&rtl8192cu_fops},
7870 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
7871         .driver_info = (unsigned long)&rtl8192cu_fops},
7872 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
7873         .driver_info = (unsigned long)&rtl8192cu_fops},
7874 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
7875         .driver_info = (unsigned long)&rtl8192cu_fops},
7876 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
7877         .driver_info = (unsigned long)&rtl8192cu_fops},
7878 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
7879         .driver_info = (unsigned long)&rtl8192cu_fops},
7880 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
7881         .driver_info = (unsigned long)&rtl8192cu_fops},
7882 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
7883         .driver_info = (unsigned long)&rtl8192cu_fops},
7884 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
7885         .driver_info = (unsigned long)&rtl8192cu_fops},
7886 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
7887         .driver_info = (unsigned long)&rtl8192cu_fops},
7888 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
7889         .driver_info = (unsigned long)&rtl8192cu_fops},
7890 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
7891         .driver_info = (unsigned long)&rtl8192cu_fops},
7892 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
7893         .driver_info = (unsigned long)&rtl8192cu_fops},
7894 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
7895         .driver_info = (unsigned long)&rtl8192cu_fops},
7896 /* Currently untested 8192 series devices */
7897 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
7898         .driver_info = (unsigned long)&rtl8192cu_fops},
7899 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
7900         .driver_info = (unsigned long)&rtl8192cu_fops},
7901 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
7902         .driver_info = (unsigned long)&rtl8192cu_fops},
7903 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
7904         .driver_info = (unsigned long)&rtl8192cu_fops},
7905 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
7906         .driver_info = (unsigned long)&rtl8192cu_fops},
7907 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
7908         .driver_info = (unsigned long)&rtl8192cu_fops},
7909 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
7910         .driver_info = (unsigned long)&rtl8192cu_fops},
7911 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
7912         .driver_info = (unsigned long)&rtl8192cu_fops},
7913 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
7914         .driver_info = (unsigned long)&rtl8192cu_fops},
7915 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
7916         .driver_info = (unsigned long)&rtl8192cu_fops},
7917 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
7918         .driver_info = (unsigned long)&rtl8192cu_fops},
7919 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
7920         .driver_info = (unsigned long)&rtl8192cu_fops},
7921 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
7922         .driver_info = (unsigned long)&rtl8192cu_fops},
7923 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
7924         .driver_info = (unsigned long)&rtl8192cu_fops},
7925 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
7926         .driver_info = (unsigned long)&rtl8192cu_fops},
7927 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
7928         .driver_info = (unsigned long)&rtl8192cu_fops},
7929 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
7930         .driver_info = (unsigned long)&rtl8192cu_fops},
7931 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
7932         .driver_info = (unsigned long)&rtl8192cu_fops},
7933 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
7934         .driver_info = (unsigned long)&rtl8192cu_fops},
7935 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
7936         .driver_info = (unsigned long)&rtl8192cu_fops},
7937 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
7938         .driver_info = (unsigned long)&rtl8192cu_fops},
7939 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
7940         .driver_info = (unsigned long)&rtl8192cu_fops},
7941 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
7942         .driver_info = (unsigned long)&rtl8192cu_fops},
7943 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
7944         .driver_info = (unsigned long)&rtl8192cu_fops},
7945 /* found in rtl8192eu vendor driver */
7946 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
7947         .driver_info = (unsigned long)&rtl8192eu_fops},
7948 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
7949         .driver_info = (unsigned long)&rtl8192eu_fops},
7950 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
7951         .driver_info = (unsigned long)&rtl8192eu_fops},
7952 /* D-Link DWA-131 rev C1 */
7953 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3312, 0xff, 0xff, 0xff),
7954         .driver_info = (unsigned long)&rtl8192eu_fops},
7955 /* TP-Link TL-WN8200ND V2 */
7956 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0126, 0xff, 0xff, 0xff),
7957         .driver_info = (unsigned long)&rtl8192eu_fops},
7958 /* Mercusys MW300UM */
7959 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0100, 0xff, 0xff, 0xff),
7960         .driver_info = (unsigned long)&rtl8192eu_fops},
7961 /* Mercusys MW300UH */
7962 {USB_DEVICE_AND_INTERFACE_INFO(0x2c4e, 0x0104, 0xff, 0xff, 0xff),
7963         .driver_info = (unsigned long)&rtl8192eu_fops},
7964 #endif
7965 { }
7966 };
7967
7968 static struct usb_driver rtl8xxxu_driver = {
7969         .name = DRIVER_NAME,
7970         .probe = rtl8xxxu_probe,
7971         .disconnect = rtl8xxxu_disconnect,
7972         .id_table = dev_table,
7973         .no_dynamic_id = 1,
7974         .disable_hub_initiated_lpm = 1,
7975 };
7976
7977 MODULE_DEVICE_TABLE(usb, dev_table);
7978
7979 module_usb_driver(rtl8xxxu_driver);