drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723b.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver - 8723b specific subdriver
   4  *
   5  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   6  *
   7  * Portions, notably calibration code:
   8  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   9  *
  10  * This driver was written as a replacement for the vendor provided
  11  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  12  * their programming interface, I have started adding support for
  13  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/list.h>
  24 #include <linux/usb.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/wireless.h>
  29 #include <linux/firmware.h>
  30 #include <linux/moduleparam.h>
  31 #include <net/mac80211.h>
  32 #include "rtl8xxxu.h"
  33 #include "rtl8xxxu_regs.h"
  34
  35 static const struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = {
  36         {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0},
  37         {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10},
  38         {0x430, 0x00}, {0x431, 0x00},
  39         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
  40         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
  41         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
  42         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
  43         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
  44         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
  45         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
  46         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
  47         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
  48         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
  49         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
  50         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
  51         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
  52         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
  53         {0x516, 0x0a}, {0x525, 0x4f},
  54         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50},
  55         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
  56         {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff},
  57         {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff},
  58         {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
  59         {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00},
  60         {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
  61         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
  62         {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04},
  63         {0xffff, 0xff},
  64 };
  65
  66 static const struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = {
  67         {0x800, 0x80040000}, {0x804, 0x00000003},
  68         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
  69         {0x810, 0x10001331}, {0x814, 0x020c3d10},
  70         {0x818, 0x02200385}, {0x81c, 0x00000000},
  71         {0x820, 0x01000100}, {0x824, 0x00190204},
  72         {0x828, 0x00000000}, {0x82c, 0x00000000},
  73         {0x830, 0x00000000}, {0x834, 0x00000000},
  74         {0x838, 0x00000000}, {0x83c, 0x00000000},
  75         {0x840, 0x00010000}, {0x844, 0x00000000},
  76         {0x848, 0x00000000}, {0x84c, 0x00000000},
  77         {0x850, 0x00000000}, {0x854, 0x00000000},
  78         {0x858, 0x569a11a9}, {0x85c, 0x01000014},
  79         {0x860, 0x66f60110}, {0x864, 0x061f0649},
  80         {0x868, 0x00000000}, {0x86c, 0x27272700},
  81         {0x870, 0x07000760}, {0x874, 0x25004000},
  82         {0x878, 0x00000808}, {0x87c, 0x00000000},
  83         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
  84         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
  85         {0x890, 0x00000800}, {0x894, 0xfffffffe},
  86         {0x898, 0x40302010}, {0x89c, 0x00706050},
  87         {0x900, 0x00000000}, {0x904, 0x00000023},
  88         {0x908, 0x00000000}, {0x90c, 0x81121111},
  89         {0x910, 0x00000002}, {0x914, 0x00000201},
  90         {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c},
  91         {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f},
  92         {0xa10, 0x9500bb78}, {0xa14, 0x1114d028},
  93         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
  94         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
  95         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
  96         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
  97         {0xa78, 0x00000900}, {0xa7c, 0x225b0606},
  98         {0xa80, 0x21806490}, {0xb2c, 0x00000000},
  99         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 100         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 101         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 102         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 103         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 104         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 105         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 106         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 107         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 108         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 109         {0xc50, 0x69553420}, {0xc54, 0x43bc0094},
 110         {0xc58, 0x00013149}, {0xc5c, 0x00250492},
 111         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 112         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 113         {0xc70, 0x2c7f000d}, {0xc74, 0x020610db},
 114         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 115         {0xc80, 0x390000e4}, {0xc84, 0x20f60000},
 116         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 117         {0xc90, 0x00020e1a}, {0xc94, 0x00000000},
 118         {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f},
 119         {0xca0, 0x00000000}, {0xca4, 0x000300a0},
 120         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 121         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 122         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 123         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 124         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 125         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 126         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 127         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 128         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 129         {0xd00, 0x00000740}, {0xd04, 0x40020401},
 130         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 131         {0xd10, 0xa0633333}, {0xd14, 0x3333bc53},
 132         {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975},
 133         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 134         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 135         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 136         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 137         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 138         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 139         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 140         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 141         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 142         {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d},
 143         {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d},
 144         {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d},
 145         {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d},
 146         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 147         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 148         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 149         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 150         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 151         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 152         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 153         {0xe68, 0x001b2556}, {0xe6c, 0x00c00096},
 154         {0xe70, 0x00c00096}, {0xe74, 0x01000056},
 155         {0xe78, 0x01000014}, {0xe7c, 0x01000056},
 156         {0xe80, 0x01000014}, {0xe84, 0x00c00096},
 157         {0xe88, 0x01000056}, {0xe8c, 0x00c00096},
 158         {0xed0, 0x00c00096}, {0xed4, 0x00c00096},
 159         {0xed8, 0x00c00096}, {0xedc, 0x000000d6},
 160         {0xee0, 0x000000d6}, {0xeec, 0x01c00016},
 161         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 162         {0xf00, 0x00000300},
 163         {0x820, 0x01000100}, {0x800, 0x83040000},
 164         {0xffff, 0xffffffff},
 165 };
 166
 167 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = {
 168         {0xc78, 0xfd000001}, {0xc78, 0xfc010001},
 169         {0xc78, 0xfb020001}, {0xc78, 0xfa030001},
 170         {0xc78, 0xf9040001}, {0xc78, 0xf8050001},
 171         {0xc78, 0xf7060001}, {0xc78, 0xf6070001},
 172         {0xc78, 0xf5080001}, {0xc78, 0xf4090001},
 173         {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001},
 174         {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001},
 175         {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001},
 176         {0xc78, 0xed100001}, {0xc78, 0xec110001},
 177         {0xc78, 0xeb120001}, {0xc78, 0xea130001},
 178         {0xc78, 0xe9140001}, {0xc78, 0xe8150001},
 179         {0xc78, 0xe7160001}, {0xc78, 0xe6170001},
 180         {0xc78, 0xe5180001}, {0xc78, 0xe4190001},
 181         {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001},
 182         {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001},
 183         {0xc78, 0x671e0001}, {0xc78, 0x661f0001},
 184         {0xc78, 0x65200001}, {0xc78, 0x64210001},
 185         {0xc78, 0x63220001}, {0xc78, 0x4a230001},
 186         {0xc78, 0x49240001}, {0xc78, 0x48250001},
 187         {0xc78, 0x47260001}, {0xc78, 0x46270001},
 188         {0xc78, 0x45280001}, {0xc78, 0x44290001},
 189         {0xc78, 0x432a0001}, {0xc78, 0x422b0001},
 190         {0xc78, 0x292c0001}, {0xc78, 0x282d0001},
 191         {0xc78, 0x272e0001}, {0xc78, 0x262f0001},
 192         {0xc78, 0x0a300001}, {0xc78, 0x09310001},
 193         {0xc78, 0x08320001}, {0xc78, 0x07330001},
 194         {0xc78, 0x06340001}, {0xc78, 0x05350001},
 195         {0xc78, 0x04360001}, {0xc78, 0x03370001},
 196         {0xc78, 0x02380001}, {0xc78, 0x01390001},
 197         {0xc78, 0x013a0001}, {0xc78, 0x013b0001},
 198         {0xc78, 0x013c0001}, {0xc78, 0x013d0001},
 199         {0xc78, 0x013e0001}, {0xc78, 0x013f0001},
 200         {0xc78, 0xfc400001}, {0xc78, 0xfb410001},
 201         {0xc78, 0xfa420001}, {0xc78, 0xf9430001},
 202         {0xc78, 0xf8440001}, {0xc78, 0xf7450001},
 203         {0xc78, 0xf6460001}, {0xc78, 0xf5470001},
 204         {0xc78, 0xf4480001}, {0xc78, 0xf3490001},
 205         {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001},
 206         {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001},
 207         {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001},
 208         {0xc78, 0xec500001}, {0xc78, 0xeb510001},
 209         {0xc78, 0xea520001}, {0xc78, 0xe9530001},
 210         {0xc78, 0xe8540001}, {0xc78, 0xe7550001},
 211         {0xc78, 0xe6560001}, {0xc78, 0xe5570001},
 212         {0xc78, 0xe4580001}, {0xc78, 0xe3590001},
 213         {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001},
 214         {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001},
 215         {0xc78, 0x675e0001}, {0xc78, 0x665f0001},
 216         {0xc78, 0x65600001}, {0xc78, 0x64610001},
 217         {0xc78, 0x63620001}, {0xc78, 0x62630001},
 218         {0xc78, 0x61640001}, {0xc78, 0x48650001},
 219         {0xc78, 0x47660001}, {0xc78, 0x46670001},
 220         {0xc78, 0x45680001}, {0xc78, 0x44690001},
 221         {0xc78, 0x436a0001}, {0xc78, 0x426b0001},
 222         {0xc78, 0x286c0001}, {0xc78, 0x276d0001},
 223         {0xc78, 0x266e0001}, {0xc78, 0x256f0001},
 224         {0xc78, 0x24700001}, {0xc78, 0x09710001},
 225         {0xc78, 0x08720001}, {0xc78, 0x07730001},
 226         {0xc78, 0x06740001}, {0xc78, 0x05750001},
 227         {0xc78, 0x04760001}, {0xc78, 0x03770001},
 228         {0xc78, 0x02780001}, {0xc78, 0x01790001},
 229         {0xc78, 0x017a0001}, {0xc78, 0x017b0001},
 230         {0xc78, 0x017c0001}, {0xc78, 0x017d0001},
 231         {0xc78, 0x017e0001}, {0xc78, 0x017f0001},
 232         {0xc50, 0x69553422},
 233         {0xc50, 0x69553420},
 234         {0x824, 0x00390204},
 235         {0xffff, 0xffffffff}
 236 };
 237
 238 static const struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = {
 239         {0x00, 0x00010000}, {0xb0, 0x000dffe0},
 240         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 241         {0xfe, 0x00000000}, {0xb1, 0x00000018},
 242         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 243         {0xfe, 0x00000000}, {0xb2, 0x00084c00},
 244         {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa},
 245         {0xb7, 0x00000010}, {0xb8, 0x0000907f},
 246         {0x5c, 0x00000002}, {0x7c, 0x00000002},
 247         {0x7e, 0x00000005}, {0x8b, 0x0006fc00},
 248         {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2},
 249         {0x1e, 0x00000000}, {0xdf, 0x00000780},
 250         {0x50, 0x00067435},
 251         /*
 252          * The 8723bu vendor driver indicates that bit 8 should be set in
 253          * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However
 254          * they never actually check the package type - and just default
 255          * to not setting it.
 256          */
 257         {0x51, 0x0006b04e},
 258         {0x52, 0x000007d2}, {0x53, 0x00000000},
 259         {0x54, 0x00050400}, {0x55, 0x0004026e},
 260         {0xdd, 0x0000004c}, {0x70, 0x00067435},
 261         /*
 262          * 0x71 has same package type condition as for register 0x51
 263          */
 264         {0x71, 0x0006b04e},
 265         {0x72, 0x000007d2}, {0x73, 0x00000000},
 266         {0x74, 0x00050400}, {0x75, 0x0004026e},
 267         {0xef, 0x00000100}, {0x34, 0x0000add7},
 268         {0x35, 0x00005c00}, {0x34, 0x00009dd4},
 269         {0x35, 0x00005000}, {0x34, 0x00008dd1},
 270         {0x35, 0x00004400}, {0x34, 0x00007dce},
 271         {0x35, 0x00003800}, {0x34, 0x00006cd1},
 272         {0x35, 0x00004400}, {0x34, 0x00005cce},
 273         {0x35, 0x00003800}, {0x34, 0x000048ce},
 274         {0x35, 0x00004400}, {0x34, 0x000034ce},
 275         {0x35, 0x00003800}, {0x34, 0x00002451},
 276         {0x35, 0x00004400}, {0x34, 0x0000144e},
 277         {0x35, 0x00003800}, {0x34, 0x00000051},
 278         {0x35, 0x00004400}, {0xef, 0x00000000},
 279         {0xef, 0x00000100}, {0xed, 0x00000010},
 280         {0x44, 0x0000add7}, {0x44, 0x00009dd4},
 281         {0x44, 0x00008dd1}, {0x44, 0x00007dce},
 282         {0x44, 0x00006cc1}, {0x44, 0x00005cce},
 283         {0x44, 0x000044d1}, {0x44, 0x000034ce},
 284         {0x44, 0x00002451}, {0x44, 0x0000144e},
 285         {0x44, 0x00000051}, {0xef, 0x00000000},
 286         {0xed, 0x00000000}, {0x7f, 0x00020080},
 287         {0xef, 0x00002000}, {0x3b, 0x000380ef},
 288         {0x3b, 0x000302fe}, {0x3b, 0x00028ce6},
 289         {0x3b, 0x000200bc}, {0x3b, 0x000188a5},
 290         {0x3b, 0x00010fbc}, {0x3b, 0x00008f71},
 291         {0x3b, 0x00000900}, {0xef, 0x00000000},
 292         {0xed, 0x00000001}, {0x40, 0x000380ef},
 293         {0x40, 0x000302fe}, {0x40, 0x00028ce6},
 294         {0x40, 0x000200bc}, {0x40, 0x000188a5},
 295         {0x40, 0x00010fbc}, {0x40, 0x00008f71},
 296         {0x40, 0x00000900}, {0xed, 0x00000000},
 297         {0x82, 0x00080000}, {0x83, 0x00008000},
 298         {0x84, 0x00048d80}, {0x85, 0x00068000},
 299         {0xa2, 0x00080000}, {0xa3, 0x00008000},
 300         {0xa4, 0x00048d80}, {0xa5, 0x00068000},
 301         {0xed, 0x00000002}, {0xef, 0x00000002},
 302         {0x56, 0x00000032}, {0x76, 0x00000032},
 303         {0x01, 0x00000780},
 304         {0xff, 0xffffffff}
 305 };
 306
 307 static int rtl8723bu_identify_chip(struct rtl8xxxu_priv *priv)
 308 {
 309         struct device *dev = &priv->udev->dev;
 310         u32 val32, sys_cfg, vendor;
 311         int ret = 0;
 312
 313         sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
 314         priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
 315         if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
 316                 dev_info(dev, "Unsupported test chip\n");
 317                 ret = -ENOTSUPP;
 318                 goto out;
 319         }
 320
 321         strscpy(priv->chip_name, "8723BU", sizeof(priv->chip_name));
 322         priv->rtl_chip = RTL8723B;
 323         priv->rf_paths = 1;
 324         priv->rx_paths = 1;
 325         priv->tx_paths = 1;
 326
 327         val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
 328         if (val32 & MULTI_WIFI_FUNC_EN)
 329                 priv->has_wifi = 1;
 330         if (val32 & MULTI_BT_FUNC_EN)
 331                 priv->has_bluetooth = 1;
 332         if (val32 & MULTI_GPS_FUNC_EN)
 333                 priv->has_gps = 1;
 334         priv->is_multi_func = 1;
 335
 336         vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;
 337         rtl8xxxu_identify_vendor_2bits(priv, vendor);
 338
 339         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
 340         priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
 341
 342         rtl8xxxu_config_endpoints_sie(priv);
 343
 344         /*
 345          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
 346          */
 347         if (!priv->ep_tx_count)
 348                 ret = rtl8xxxu_config_endpoints_no_sie(priv);
 349
 350 out:
 351         return ret;
 352 }
 353
 354 static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data)
 355 {
 356         struct h2c_cmd h2c;
 357         int reqnum = 0;
 358
 359         memset(&h2c, 0, sizeof(struct h2c_cmd));
 360         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
 361         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
 362         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
 363         h2c.bt_mp_oper.data = data;
 364         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
 365
 366         reqnum++;
 367         memset(&h2c, 0, sizeof(struct h2c_cmd));
 368         h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER;
 369         h2c.bt_mp_oper.operreq = 0 | (reqnum << 4);
 370         h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE;
 371         h2c.bt_mp_oper.addr = reg;
 372         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper));
 373 }
 374
 375 static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv)
 376 {
 377         u8 val8;
 378         u16 sys_func;
 379
 380         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
 381         val8 &= ~BIT(1);
 382         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
 383
 384         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
 385         val8 &= ~BIT(0);
 386         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
 387
 388         sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 389         sys_func &= ~SYS_FUNC_CPU_ENABLE;
 390         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
 391
 392         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
 393         val8 &= ~BIT(1);
 394         rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
 395
 396         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
 397         val8 |= BIT(0);
 398         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
 399
 400         sys_func |= SYS_FUNC_CPU_ENABLE;
 401         rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
 402 }
 403
 404 static void
 405 rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
 406 {
 407         u32 val32, ofdm, mcs;
 408         u8 cck, ofdmbase, mcsbase;
 409         int group, tx_idx;
 410
 411         tx_idx = 0;
 412         group = rtl8xxxu_gen2_channel_to_group(channel);
 413
 414         cck = priv->cck_tx_power_index_B[group];
 415         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
 416         val32 &= 0xffff00ff;
 417         val32 |= (cck << 8);
 418         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
 419
 420         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 421         val32 &= 0xff;
 422         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 423         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 424
 425         ofdmbase = priv->ht40_1s_tx_power_index_B[group];
 426         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
 427         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
 428
 429         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
 430         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
 431
 432         mcsbase = priv->ht40_1s_tx_power_index_B[group];
 433         if (ht40)
 434                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
 435         else
 436                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
 437         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 438
 439         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
 440         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
 441 }
 442
 443 static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv)
 444 {
 445         struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu;
 446         int i;
 447
 448         if (efuse->rtl_id != cpu_to_le16(0x8129))
 449                 return -EINVAL;
 450
 451         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 452
 453         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 454                sizeof(efuse->tx_power_index_A.cck_base));
 455         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
 456                sizeof(efuse->tx_power_index_B.cck_base));
 457
 458         memcpy(priv->ht40_1s_tx_power_index_A,
 459                efuse->tx_power_index_A.ht40_base,
 460                sizeof(efuse->tx_power_index_A.ht40_base));
 461         memcpy(priv->ht40_1s_tx_power_index_B,
 462                efuse->tx_power_index_B.ht40_base,
 463                sizeof(efuse->tx_power_index_B.ht40_base));
 464
 465         priv->ofdm_tx_power_diff[0].a =
 466                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
 467         priv->ofdm_tx_power_diff[0].b =
 468                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.a;
 469
 470         priv->ht20_tx_power_diff[0].a =
 471                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 472         priv->ht20_tx_power_diff[0].b =
 473                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
 474
 475         priv->ht40_tx_power_diff[0].a = 0;
 476         priv->ht40_tx_power_diff[0].b = 0;
 477
 478         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
 479                 priv->ofdm_tx_power_diff[i].a =
 480                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
 481                 priv->ofdm_tx_power_diff[i].b =
 482                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
 483
 484                 priv->ht20_tx_power_diff[i].a =
 485                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
 486                 priv->ht20_tx_power_diff[i].b =
 487                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
 488
 489                 priv->ht40_tx_power_diff[i].a =
 490                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
 491                 priv->ht40_tx_power_diff[i].b =
 492                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
 493         }
 494
 495         priv->default_crystal_cap = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f;
 496
 497         return 0;
 498 }
 499
 500 static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv)
 501 {
 502         const char *fw_name;
 503         int ret;
 504
 505         if (priv->enable_bluetooth)
 506                 fw_name = "/*(DEBLOBBED)*/";
 507         else
 508                 fw_name = "/*(DEBLOBBED)*/";
 509
 510         ret = rtl8xxxu_load_firmware(priv, fw_name);
 511         return ret;
 512 }
 513
 514 static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv)
 515 {
 516         u8 val8;
 517         u16 val16;
 518
 519         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 520         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
 521         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 522
 523         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
 524
 525         /* 6. 0x1f[7:0] = 0x07 */
 526         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 527         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 528
 529         /* Why? */
 530         rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3);
 531         rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80);
 532         rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table);
 533
 534         rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table);
 535 }
 536
 537 static int rtl8723bu_init_phy_rf(struct rtl8xxxu_priv *priv)
 538 {
 539         int ret;
 540
 541         ret = rtl8xxxu_init_phy_rf(priv, rtl8723bu_radioa_1t_init_table, RF_A);
 542         /*
 543          * PHY LCK
 544          */
 545         rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0);
 546         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01);
 547         msleep(200);
 548         rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0);
 549
 550         return ret;
 551 }
 552
 553 void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv)
 554 {
 555         u32 val32;
 556
 557         val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1);
 558         val32 &= ~(BIT(20) | BIT(24));
 559         rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32);
 560
 561         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
 562         val32 &= ~BIT(4);
 563         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
 564
 565         val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG);
 566         val32 |= BIT(3);
 567         rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32);
 568
 569         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
 570         val32 |= BIT(24);
 571         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
 572
 573         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
 574         val32 &= ~BIT(23);
 575         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
 576
 577         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
 578         val32 |= (BIT(0) | BIT(1));
 579         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
 580
 581         val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC);
 582         val32 &= 0xffffff00;
 583         val32 |= 0x77;
 584         rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32);
 585
 586         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
 587         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
 588         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
 589 }
 590
 591 static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv)
 592 {
 593         u32 reg_eac, reg_e94, reg_e9c, path_sel, val32;
 594         int result = 0;
 595
 596         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
 597
 598         /*
 599          * Leave IQK mode
 600          */
 601         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 602         val32 &= 0x000000ff;
 603         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 604
 605         /*
 606          * Enable path A PA in TX IQK mode
 607          */
 608         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 609         val32 |= 0x80000;
 610         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 611         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
 612         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f);
 613         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87);
 614
 615         /*
 616          * Tx IQK setting
 617          */
 618         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 619         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 620
 621         /* path-A IQK setting */
 622         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 623         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 624         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 625         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 626
 627         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea);
 628         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
 629         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 630         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 631
 632         /* LO calibration setting */
 633         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 634
 635         /*
 636          * Enter IQK mode
 637          */
 638         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 639         val32 &= 0x000000ff;
 640         val32 |= 0x80800000;
 641         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 642
 643         /*
 644          * The vendor driver indicates the USB module is always using
 645          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
 646          */
 647         if (priv->rf_paths > 1)
 648                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 649         else
 650                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 651
 652         /*
 653          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
 654          * No trace of this in the 8192eu or 8188eu vendor drivers.
 655          */
 656         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 657
 658         /* One shot, path A LOK & IQK */
 659         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 660         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 661
 662         mdelay(1);
 663
 664         /* Restore Ant Path */
 665         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 666 #ifdef RTL8723BU_BT
 667         /* GNT_BT = 1 */
 668         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 669 #endif
 670
 671         /*
 672          * Leave IQK mode
 673          */
 674         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 675         val32 &= 0x000000ff;
 676         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 677
 678         /* Check failed */
 679         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 680         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 681         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 682
 683         val32 = (reg_e9c >> 16) & 0x3ff;
 684         if (val32 & 0x200)
 685                 val32 = 0x400 - val32;
 686
 687         if (!(reg_eac & BIT(28)) &&
 688             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 689             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
 690             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
 691             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
 692             val32 < 0xf)
 693                 result |= 0x01;
 694         else    /* If TX not OK, ignore RX */
 695                 goto out;
 696
 697 out:
 698         return result;
 699 }
 700
 701 static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
 702 {
 703         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32;
 704         int result = 0;
 705
 706         path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
 707
 708         /*
 709          * Leave IQK mode
 710          */
 711         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 712         val32 &= 0x000000ff;
 713         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 714
 715         /*
 716          * Enable path A PA in TX IQK mode
 717          */
 718         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 719         val32 |= 0x80000;
 720         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 721         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 722         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 723         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
 724
 725         /*
 726          * Tx IQK setting
 727          */
 728         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 729         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 730
 731         /* path-A IQK setting */
 732         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 733         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 734         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 735         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 736
 737         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0);
 738         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000);
 739         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 740         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 741
 742         /* LO calibration setting */
 743         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 744
 745         /*
 746          * Enter IQK mode
 747          */
 748         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 749         val32 &= 0x000000ff;
 750         val32 |= 0x80800000;
 751         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 752
 753         /*
 754          * The vendor driver indicates the USB module is always using
 755          * S0S1 path 1 for the 8723bu. This may be different for 8192eu
 756          */
 757         if (priv->rf_paths > 1)
 758                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 759         else
 760                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 761
 762         /*
 763          * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu.
 764          * No trace of this in the 8192eu or 8188eu vendor drivers.
 765          */
 766         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 767
 768         /* One shot, path A LOK & IQK */
 769         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 770         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 771
 772         mdelay(1);
 773
 774         /* Restore Ant Path */
 775         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 776 #ifdef RTL8723BU_BT
 777         /* GNT_BT = 1 */
 778         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 779 #endif
 780
 781         /*
 782          * Leave IQK mode
 783          */
 784         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 785         val32 &= 0x000000ff;
 786         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 787
 788         /* Check failed */
 789         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 790         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 791         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 792
 793         val32 = (reg_e9c >> 16) & 0x3ff;
 794         if (val32 & 0x200)
 795                 val32 = 0x400 - val32;
 796
 797         if (!(reg_eac & BIT(28)) &&
 798             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 799             ((reg_e9c & 0x03ff0000) != 0x00420000) &&
 800             ((reg_e94 & 0x03ff0000)  < 0x01100000) &&
 801             ((reg_e94 & 0x03ff0000)  > 0x00f00000) &&
 802             val32 < 0xf)
 803                 result |= 0x01;
 804         else    /* If TX not OK, ignore RX */
 805                 goto out;
 806
 807         val32 = 0x80007c00 | (reg_e94 &0x3ff0000) |
 808                 ((reg_e9c & 0x3ff0000) >> 16);
 809         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 810
 811         /*
 812          * Modify RX IQK mode
 813          */
 814         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 815         val32 &= 0x000000ff;
 816         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 817         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 818         val32 |= 0x80000;
 819         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 820         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 821         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 822         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77);
 823
 824         /*
 825          * PA, PAD setting
 826          */
 827         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0xf80);
 828         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f);
 829
 830         /*
 831          * RX IQK setting
 832          */
 833         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 834
 835         /* path-A IQK setting */
 836         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 837         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
 838         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 839         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 840
 841         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000);
 842         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f);
 843         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000);
 844         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000);
 845
 846         /* LO calibration setting */
 847         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1);
 848
 849         /*
 850          * Enter IQK mode
 851          */
 852         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 853         val32 &= 0x000000ff;
 854         val32 |= 0x80800000;
 855         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 856
 857         if (priv->rf_paths > 1)
 858                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000);
 859         else
 860                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280);
 861
 862         /*
 863          * Disable BT
 864          */
 865         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800);
 866
 867         /* One shot, path A LOK & IQK */
 868         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 869         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 870
 871         mdelay(1);
 872
 873         /* Restore Ant Path */
 874         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel);
 875 #ifdef RTL8723BU_BT
 876         /* GNT_BT = 1 */
 877         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800);
 878 #endif
 879
 880         /*
 881          * Leave IQK mode
 882          */
 883         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 884         val32 &= 0x000000ff;
 885         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 886
 887         /* Check failed */
 888         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 889         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
 890
 891         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x780);
 892
 893         val32 = (reg_eac >> 16) & 0x3ff;
 894         if (val32 & 0x200)
 895                 val32 = 0x400 - val32;
 896
 897         if (!(reg_eac & BIT(27)) &&
 898             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
 899             ((reg_eac & 0x03ff0000) != 0x00360000) &&
 900             ((reg_ea4 & 0x03ff0000)  < 0x01100000) &&
 901             ((reg_ea4 & 0x03ff0000)  > 0x00f00000) &&
 902             val32 < 0xf)
 903                 result |= 0x02;
 904         else    /* If TX not OK, ignore RX */
 905                 goto out;
 906 out:
 907         return result;
 908 }
 909
 910 static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
 911                                       int result[][8], int t)
 912 {
 913         struct device *dev = &priv->udev->dev;
 914         u32 i, val32;
 915         int path_a_ok /*, path_b_ok */;
 916         int retry = 2;
 917         static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
 918                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
 919                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
 920                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
 921                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
 922                 REG_TX_TO_TX, REG_RX_CCK,
 923                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
 924                 REG_RX_TO_RX, REG_STANDBY,
 925                 REG_SLEEP, REG_PMPD_ANAEN
 926         };
 927         static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
 928                 REG_TXPAUSE, REG_BEACON_CTRL,
 929                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
 930         };
 931         static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
 932                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
 933                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
 934                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
 935                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
 936         };
 937         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
 938         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
 939
 940         /*
 941          * Note: IQ calibration must be performed after loading
 942          *       PHY_REG.txt , and radio_a, radio_b.txt
 943          */
 944
 945         if (t == 0) {
 946                 /* Save ADDA parameters, turn Path A ADDA on */
 947                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
 948                                    RTL8XXXU_ADDA_REGS);
 949                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
 950                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
 951                                    priv->bb_backup, RTL8XXXU_BB_REGS);
 952         }
 953
 954         rtl8xxxu_path_adda_on(priv, adda_regs, true);
 955
 956         /* MAC settings */
 957         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
 958
 959         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
 960         val32 |= 0x0f000000;
 961         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
 962
 963         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
 964         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
 965         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
 966
 967         /*
 968          * RX IQ calibration setting for 8723B D cut large current issue
 969          * when leaving IPS
 970          */
 971         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 972         val32 &= 0x000000ff;
 973         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 974
 975         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
 976         val32 |= 0x80000;
 977         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
 978
 979         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 980         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
 981         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7);
 982
 983         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
 984         val32 |= 0x20;
 985         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
 986
 987         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd);
 988
 989         for (i = 0; i < retry; i++) {
 990                 path_a_ok = rtl8723bu_iqk_path_a(priv);
 991                 if (path_a_ok == 0x01) {
 992                         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 993                         val32 &= 0x000000ff;
 994                         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 995
 996                         val32 = rtl8xxxu_read32(priv,
 997                                                 REG_TX_POWER_BEFORE_IQK_A);
 998                         result[t][0] = (val32 >> 16) & 0x3ff;
 999                         val32 = rtl8xxxu_read32(priv,
1000                                                 REG_TX_POWER_AFTER_IQK_A);
1001                         result[t][1] = (val32 >> 16) & 0x3ff;
1002
1003                         break;
1004                 }
1005         }
1006
1007         if (!path_a_ok)
1008                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1009
1010         for (i = 0; i < retry; i++) {
1011                 path_a_ok = rtl8723bu_rx_iqk_path_a(priv);
1012                 if (path_a_ok == 0x03) {
1013                         val32 = rtl8xxxu_read32(priv,
1014                                                 REG_RX_POWER_BEFORE_IQK_A_2);
1015                         result[t][2] = (val32 >> 16) & 0x3ff;
1016                         val32 = rtl8xxxu_read32(priv,
1017                                                 REG_RX_POWER_AFTER_IQK_A_2);
1018                         result[t][3] = (val32 >> 16) & 0x3ff;
1019
1020                         break;
1021                 }
1022         }
1023
1024         if (!path_a_ok)
1025                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1026
1027         if (priv->tx_paths > 1) {
1028 #if 1
1029                 dev_warn(dev, "%s: Path B not supported\n", __func__);
1030 #else
1031
1032                 /*
1033                  * Path A into standby
1034                  */
1035                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1036                 val32 &= 0x000000ff;
1037                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1038                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1039
1040                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1041                 val32 &= 0x000000ff;
1042                 val32 |= 0x80800000;
1043                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1044
1045                 /* Turn Path B ADDA on */
1046                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1047
1048                 for (i = 0; i < retry; i++) {
1049                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
1050                         if (path_b_ok == 0x03) {
1051                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1052                                 result[t][4] = (val32 >> 16) & 0x3ff;
1053                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1054                                 result[t][5] = (val32 >> 16) & 0x3ff;
1055                                 break;
1056                         }
1057                 }
1058
1059                 if (!path_b_ok)
1060                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1061
1062                 for (i = 0; i < retry; i++) {
1063                         path_b_ok = rtl8723bu_rx_iqk_path_b(priv);
1064                         if (path_a_ok == 0x03) {
1065                                 val32 = rtl8xxxu_read32(priv,
1066                                                         REG_RX_POWER_BEFORE_IQK_B_2);
1067                                 result[t][6] = (val32 >> 16) & 0x3ff;
1068                                 val32 = rtl8xxxu_read32(priv,
1069                                                         REG_RX_POWER_AFTER_IQK_B_2);
1070                                 result[t][7] = (val32 >> 16) & 0x3ff;
1071                                 break;
1072                         }
1073                 }
1074
1075                 if (!path_b_ok)
1076                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1077 #endif
1078         }
1079
1080         /* Back to BB mode, load original value */
1081         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1082         val32 &= 0x000000ff;
1083         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1084
1085         if (t) {
1086                 /* Reload ADDA power saving parameters */
1087                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1088                                       RTL8XXXU_ADDA_REGS);
1089
1090                 /* Reload MAC parameters */
1091                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1092
1093                 /* Reload BB parameters */
1094                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1095                                       priv->bb_backup, RTL8XXXU_BB_REGS);
1096
1097                 /* Restore RX initial gain */
1098                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1099                 val32 &= 0xffffff00;
1100                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1101                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1102
1103                 if (priv->tx_paths > 1) {
1104                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1105                         val32 &= 0xffffff00;
1106                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1107                                          val32 | 0x50);
1108                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1109                                          val32 | xb_agc);
1110                 }
1111
1112                 /* Load 0xe30 IQC default value */
1113                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1114                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1115         }
1116 }
1117
1118 static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1119 {
1120         struct device *dev = &priv->udev->dev;
1121         int result[4][8];       /* last is final result */
1122         int i, candidate;
1123         bool path_a_ok, path_b_ok;
1124         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1125         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1126         u32 val32, bt_control;
1127         s32 reg_tmp = 0;
1128         bool simu;
1129
1130         rtl8xxxu_gen2_prepare_calibrate(priv, 1);
1131
1132         memset(result, 0, sizeof(result));
1133         candidate = -1;
1134
1135         path_a_ok = false;
1136         path_b_ok = false;
1137
1138         bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU);
1139
1140         for (i = 0; i < 3; i++) {
1141                 rtl8723bu_phy_iqcalibrate(priv, result, i);
1142
1143                 if (i == 1) {
1144                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1145                                                                 result, 0, 1);
1146                         if (simu) {
1147                                 candidate = 0;
1148                                 break;
1149                         }
1150                 }
1151
1152                 if (i == 2) {
1153                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1154                                                                 result, 0, 2);
1155                         if (simu) {
1156                                 candidate = 0;
1157                                 break;
1158                         }
1159
1160                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1161                                                                 result, 1, 2);
1162                         if (simu) {
1163                                 candidate = 1;
1164                         } else {
1165                                 for (i = 0; i < 8; i++)
1166                                         reg_tmp += result[3][i];
1167
1168                                 if (reg_tmp)
1169                                         candidate = 3;
1170                                 else
1171                                         candidate = -1;
1172                         }
1173                 }
1174         }
1175
1176         for (i = 0; i < 4; i++) {
1177                 reg_e94 = result[i][0];
1178                 reg_e9c = result[i][1];
1179                 reg_ea4 = result[i][2];
1180                 reg_eac = result[i][3];
1181                 reg_eb4 = result[i][4];
1182                 reg_ebc = result[i][5];
1183                 reg_ec4 = result[i][6];
1184                 reg_ecc = result[i][7];
1185         }
1186
1187         if (candidate >= 0) {
1188                 reg_e94 = result[candidate][0];
1189                 priv->rege94 =  reg_e94;
1190                 reg_e9c = result[candidate][1];
1191                 priv->rege9c = reg_e9c;
1192                 reg_ea4 = result[candidate][2];
1193                 reg_eac = result[candidate][3];
1194                 reg_eb4 = result[candidate][4];
1195                 priv->regeb4 = reg_eb4;
1196                 reg_ebc = result[candidate][5];
1197                 priv->regebc = reg_ebc;
1198                 reg_ec4 = result[candidate][6];
1199                 reg_ecc = result[candidate][7];
1200                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1201                 dev_dbg(dev,
1202                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1203                         __func__, reg_e94, reg_e9c,
1204                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1205                 path_a_ok = true;
1206                 path_b_ok = true;
1207         } else {
1208                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1209                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1210         }
1211
1212         if (reg_e94 && candidate >= 0)
1213                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1214                                            candidate, (reg_ea4 == 0));
1215
1216         if (priv->tx_paths > 1 && reg_eb4)
1217                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1218                                            candidate, (reg_ec4 == 0));
1219
1220         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1221                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1222
1223         rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control);
1224
1225         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1226         val32 |= 0x80000;
1227         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1228         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000);
1229         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f);
1230         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177);
1231         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED);
1232         val32 |= 0x20;
1233         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32);
1234         rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd);
1235
1236         if (priv->rf_paths > 1)
1237                 dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__);
1238
1239         rtl8xxxu_gen2_prepare_calibrate(priv, 0);
1240 }
1241
1242 static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv)
1243 {
1244         u8 val8;
1245         u16 val16;
1246         u32 val32;
1247         int count, ret = 0;
1248
1249         /* Turn off RF */
1250         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
1251
1252         /* Enable rising edge triggering interrupt */
1253         val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM);
1254         val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ;
1255         rtl8xxxu_write16(priv, REG_GPIO_INTM, val16);
1256
1257         /* Release WLON reset 0x04[16]= 1*/
1258         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1259         val32 |= APS_FSMCO_WLON_RESET;
1260         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1261
1262         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1263         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1264         val8 |= BIT(1);
1265         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1266
1267         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1268                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1269                 if ((val8 & BIT(1)) == 0)
1270                         break;
1271                 udelay(10);
1272         }
1273
1274         if (!count) {
1275                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1276                          __func__);
1277                 ret = -EBUSY;
1278                 goto exit;
1279         }
1280
1281         /* Enable BT control XTAL setting */
1282         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1283         val8 &= ~AFE_MISC_WL_XTAL_CTRL;
1284         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1285
1286         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
1287         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1288         val8 |= SYS_ISO_ANALOG_IPS;
1289         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1290
1291         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
1292         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1293         val8 &= ~LDOA15_ENABLE;
1294         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1295
1296 exit:
1297         return ret;
1298 }
1299
1300 static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv)
1301 {
1302         u8 val8;
1303         u32 val32;
1304         int count, ret = 0;
1305
1306         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */
1307         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
1308         val8 |= LDOA15_ENABLE;
1309         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
1310
1311         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
1312         val8 = rtl8xxxu_read8(priv, 0x0067);
1313         val8 &= ~BIT(4);
1314         rtl8xxxu_write8(priv, 0x0067, val8);
1315
1316         mdelay(1);
1317
1318         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
1319         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1320         val8 &= ~SYS_ISO_ANALOG_IPS;
1321         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1322
1323         /* Disable SW LPS 0x04[10]= 0 */
1324         val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
1325         val32 &= ~APS_FSMCO_SW_LPS;
1326         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1327
1328         /* Wait until 0x04[17] = 1 power ready */
1329         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1330                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1331                 if (val32 & BIT(17))
1332                         break;
1333
1334                 udelay(10);
1335         }
1336
1337         if (!count) {
1338                 ret = -EBUSY;
1339                 goto exit;
1340         }
1341
1342         /* We should be able to optimize the following three entries into one */
1343
1344         /* Release WLON reset 0x04[16]= 1*/
1345         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1346         val32 |= APS_FSMCO_WLON_RESET;
1347         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1348
1349         /* Disable HWPDN 0x04[15]= 0*/
1350         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1351         val32 &= ~APS_FSMCO_HW_POWERDOWN;
1352         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1353
1354         /* Disable WL suspend*/
1355         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1356         val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE);
1357         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1358
1359         /* Set, then poll until 0 */
1360         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1361         val32 |= APS_FSMCO_MAC_ENABLE;
1362         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1363
1364         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1365                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1366                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1367                         ret = 0;
1368                         break;
1369                 }
1370                 udelay(10);
1371         }
1372
1373         if (!count) {
1374                 ret = -EBUSY;
1375                 goto exit;
1376         }
1377
1378         /* Enable WL control XTAL setting */
1379         val8 = rtl8xxxu_read8(priv, REG_AFE_MISC);
1380         val8 |= AFE_MISC_WL_XTAL_CTRL;
1381         rtl8xxxu_write8(priv, REG_AFE_MISC, val8);
1382
1383         /* Enable falling edge triggering interrupt */
1384         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1);
1385         val8 |= BIT(1);
1386         rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8);
1387
1388         /* Enable GPIO9 interrupt mode */
1389         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1);
1390         val8 |= BIT(1);
1391         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8);
1392
1393         /* Enable GPIO9 input mode */
1394         val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2);
1395         val8 &= ~BIT(1);
1396         rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8);
1397
1398         /* Enable HSISR GPIO[C:0] interrupt */
1399         val8 = rtl8xxxu_read8(priv, REG_HSIMR);
1400         val8 |= BIT(0);
1401         rtl8xxxu_write8(priv, REG_HSIMR, val8);
1402
1403         /* Enable HSISR GPIO9 interrupt */
1404         val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2);
1405         val8 |= BIT(1);
1406         rtl8xxxu_write8(priv, REG_HSIMR + 2, val8);
1407
1408         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL);
1409         val8 |= MULTI_WIFI_HW_ROF_EN;
1410         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8);
1411
1412         /* For GPIO9 internal pull high setting BIT(14) */
1413         val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1);
1414         val8 |= BIT(6);
1415         rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8);
1416
1417 exit:
1418         return ret;
1419 }
1420
1421 static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv)
1422 {
1423         u8 val8;
1424         u16 val16;
1425         u32 val32;
1426         int ret;
1427
1428         rtl8xxxu_disabled_to_emu(priv);
1429
1430         ret = rtl8723b_emu_to_active(priv);
1431         if (ret)
1432                 goto exit;
1433
1434         /*
1435          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1436          * Set CR bit10 to enable 32k calibration.
1437          */
1438         val16 = rtl8xxxu_read16(priv, REG_CR);
1439         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1440                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1441                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1442                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1443                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1444         rtl8xxxu_write16(priv, REG_CR, val16);
1445
1446         /*
1447          * BT coexist power on settings. This is identical for 1 and 2
1448          * antenna parts.
1449          */
1450         rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20);
1451
1452         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1453         val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN;
1454         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1455
1456         rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18);
1457         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1458         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00);
1459         /* Antenna inverse */
1460         rtl8xxxu_write8(priv, 0xfe08, 0x01);
1461
1462         val16 = rtl8xxxu_read16(priv, REG_PWR_DATA);
1463         val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1464         rtl8xxxu_write16(priv, REG_PWR_DATA, val16);
1465
1466         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1467         val32 |= LEDCFG0_DPDT_SELECT;
1468         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1469
1470         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1471         val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA;
1472         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1473 exit:
1474         return ret;
1475 }
1476
1477 static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv)
1478 {
1479         u8 val8;
1480         u16 val16;
1481
1482         rtl8xxxu_flush_fifo(priv);
1483
1484         /*
1485          * Disable TX report timer
1486          */
1487         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1488         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1489         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1490
1491         rtl8xxxu_write8(priv, REG_CR, 0x0000);
1492
1493         rtl8xxxu_active_to_lps(priv);
1494
1495         /* Reset Firmware if running in RAM */
1496         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1497                 rtl8xxxu_firmware_self_reset(priv);
1498
1499         /* Reset MCU */
1500         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1501         val16 &= ~SYS_FUNC_CPU_ENABLE;
1502         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1503
1504         /* Reset MCU ready status */
1505         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1506
1507         rtl8723bu_active_to_emu(priv);
1508
1509         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1510         val8 |= BIT(3); /* APS_FSMCO_HW_SUSPEND */
1511         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1512
1513         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
1514         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
1515         val8 |= BIT(0);
1516         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
1517 }
1518
1519 static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv)
1520 {
1521         struct h2c_cmd h2c;
1522         u32 val32;
1523         u8 val8;
1524
1525         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1526         val32 |= (BIT(22) | BIT(23));
1527         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1528
1529         /*
1530          * No indication anywhere as to what 0x0790 does. The 2 antenna
1531          * vendor code preserves bits 6-7 here.
1532          */
1533         rtl8xxxu_write8(priv, 0x0790, 0x05);
1534         /*
1535          * 0x0778 seems to be related to enabling the number of antennas
1536          * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it
1537          * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01
1538          */
1539         rtl8xxxu_write8(priv, 0x0778, 0x01);
1540
1541         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1542         val8 |= BIT(5);
1543         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1544
1545         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780);
1546
1547         rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */
1548
1549         /*
1550          * Set BT grant to low
1551          */
1552         memset(&h2c, 0, sizeof(struct h2c_cmd));
1553         h2c.bt_grant.cmd = H2C_8723B_BT_GRANT;
1554         h2c.bt_grant.data = 0;
1555         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant));
1556
1557         /*
1558          * WLAN action by PTA
1559          */
1560         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x0c);
1561
1562         /*
1563          * BT select S0/S1 controlled by WiFi
1564          */
1565         val8 = rtl8xxxu_read8(priv, 0x0067);
1566         val8 |= BIT(5);
1567         rtl8xxxu_write8(priv, 0x0067, val8);
1568
1569         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1570         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1571         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1572
1573         /*
1574          * Bits 6/7 are marked in/out ... but for what?
1575          */
1576         rtl8xxxu_write8(priv, 0x0974, 0xff);
1577
1578         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1579         val32 |= (BIT(0) | BIT(1));
1580         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1581
1582         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1583
1584         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1585         val32 &= ~BIT(24);
1586         val32 |= BIT(23);
1587         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1588
1589         /*
1590          * Fix external switch Main->S1, Aux->S0
1591          */
1592         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1593         val8 &= ~BIT(0);
1594         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1595
1596         memset(&h2c, 0, sizeof(struct h2c_cmd));
1597         h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV;
1598         h2c.ant_sel_rsv.ant_inverse = 1;
1599         h2c.ant_sel_rsv.int_switch_type = 0;
1600         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv));
1601
1602         /*
1603          * Different settings per different antenna position.
1604          *      Antenna Position:   | Normal   Inverse
1605          * --------------------------------------------------
1606          * Antenna switch to BT:    |  0x280,   0x00
1607          * Antenna switch to WiFi:  |  0x0,     0x280
1608          * Antenna switch to PTA:   |  0x200,   0x80
1609          */
1610         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x80);
1611
1612         /*
1613          * Software control, antenna at WiFi side
1614          */
1615         rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00);
1616
1617         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555);
1618         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555);
1619         rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff);
1620         rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03);
1621
1622         memset(&h2c, 0, sizeof(struct h2c_cmd));
1623         h2c.bt_info.cmd = H2C_8723B_BT_INFO;
1624         h2c.bt_info.data = BIT(0);
1625         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info));
1626
1627         memset(&h2c, 0, sizeof(struct h2c_cmd));
1628         h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT;
1629         h2c.ignore_wlan.data = 0;
1630         rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan));
1631 }
1632
1633 static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv)
1634 {
1635         u32 agg_rx;
1636         u8 agg_ctrl;
1637
1638         /*
1639          * For now simply disable RX aggregation
1640          */
1641         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
1642         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
1643
1644         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
1645         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
1646         agg_rx &= ~0xff0f;
1647
1648         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
1649         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
1650 }
1651
1652 static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv)
1653 {
1654         u32 val32;
1655
1656         /* Time duration for NHM unit: 4us, 0x2710=40ms */
1657         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710);
1658         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
1659         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52);
1660         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
1661         /* TH8 */
1662         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1663         val32 |= 0xff;
1664         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1665         /* Enable CCK */
1666         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
1667         val32 |= BIT(8) | BIT(9) | BIT(10);
1668         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
1669         /* Max power amongst all RX antennas */
1670         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
1671         val32 |= BIT(7);
1672         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
1673 }
1674
1675 static s8 rtl8723b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
1676 {
1677         u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
1678         s8 rx_pwr_all = 0x00;
1679         u8 vga_idx, lna_idx;
1680
1681         lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);
1682         vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);
1683
1684         switch (lna_idx) {
1685         case 6:
1686                 rx_pwr_all = -34 - (2 * vga_idx);
1687                 break;
1688         case 4:
1689                 rx_pwr_all = -14 - (2 * vga_idx);
1690                 break;
1691         case 1:
1692                 rx_pwr_all = 6 - (2 * vga_idx);
1693                 break;
1694         case 0:
1695                 rx_pwr_all = 16 - (2 * vga_idx);
1696                 break;
1697         default:
1698                 break;
1699         }
1700
1701         return rx_pwr_all;
1702 }
1703
1704 struct rtl8xxxu_fileops rtl8723bu_fops = {
1705         .identify_chip = rtl8723bu_identify_chip,
1706         .parse_efuse = rtl8723bu_parse_efuse,
1707         .load_firmware = rtl8723bu_load_firmware,
1708         .power_on = rtl8723bu_power_on,
1709         .power_off = rtl8723bu_power_off,
1710         .read_efuse = rtl8xxxu_read_efuse,
1711         .reset_8051 = rtl8723bu_reset_8051,
1712         .llt_init = rtl8xxxu_auto_llt_table,
1713         .init_phy_bb = rtl8723bu_init_phy_bb,
1714         .init_phy_rf = rtl8723bu_init_phy_rf,
1715         .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection,
1716         .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
1717         .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate,
1718         .config_channel = rtl8xxxu_gen2_config_channel,
1719         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1720         .parse_phystats = rtl8723au_rx_parse_phystats,
1721         .init_aggregation = rtl8723bu_init_aggregation,
1722         .init_statistics = rtl8723bu_init_statistics,
1723         .init_burst = rtl8xxxu_init_burst,
1724         .enable_rf = rtl8723b_enable_rf,
1725         .disable_rf = rtl8xxxu_gen2_disable_rf,
1726         .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1727         .set_tx_power = rtl8723b_set_tx_power,
1728         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1729         .report_connect = rtl8xxxu_gen2_report_connect,
1730         .report_rssi = rtl8xxxu_gen2_report_rssi,
1731         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1732         .set_crystal_cap = rtl8723a_set_crystal_cap,
1733         .cck_rssi = rtl8723b_cck_rssi,
1734         .writeN_block_size = 1024,
1735         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1736         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1737         .has_s0s1 = 1,
1738         .has_tx_report = 1,
1739         .gen2_thermal_meter = 1,
1740         .needs_full_init = 1,
1741         .init_reg_hmtfr = 1,
1742         .ampdu_max_time = 0x5e,
1743         .ustime_tsf_edca = 0x50,
1744         .max_aggr_num = 0x0c14,
1745         .supports_ap = 1,
1746         .max_macid_num = 128,
1747         .adda_1t_init = 0x01c00014,
1748         .adda_1t_path_on = 0x01c00014,
1749         .adda_2t_path_on_a = 0x01c00014,
1750         .adda_2t_path_on_b = 0x01c00014,
1751         .trxff_boundary = 0x3f7f,
1752         .pbp_rx = PBP_PAGE_SIZE_256,
1753         .pbp_tx = PBP_PAGE_SIZE_256,
1754         .mactable = rtl8723b_mac_init_table,
1755         .total_page_num = TX_TOTAL_PAGE_NUM_8723B,
1756         .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,
1757         .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,
1758         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,
1759 };