drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8723a.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver - 8723a specific subdriver
   4  *
   5  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   6  *
   7  * Portions, notably calibration code:
   8  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   9  *
  10  * This driver was written as a replacement for the vendor provided
  11  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  12  * their programming interface, I have started adding support for
  13  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/list.h>
  24 #include <linux/usb.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/wireless.h>
  29 #include <linux/firmware.h>
  30 #include <linux/moduleparam.h>
  31 #include <net/mac80211.h>
  32 #include "rtl8xxxu.h"
  33 #include "rtl8xxxu_regs.h"
  34
  35 static struct rtl8xxxu_power_base rtl8723a_power_base = {
  36         .reg_0e00 = 0x0a0c0c0c,
  37         .reg_0e04 = 0x02040608,
  38         .reg_0e08 = 0x00000000,
  39         .reg_086c = 0x00000000,
  40
  41         .reg_0e10 = 0x0a0c0d0e,
  42         .reg_0e14 = 0x02040608,
  43         .reg_0e18 = 0x0a0c0d0e,
  44         .reg_0e1c = 0x02040608,
  45
  46         .reg_0830 = 0x0a0c0c0c,
  47         .reg_0834 = 0x02040608,
  48         .reg_0838 = 0x00000000,
  49         .reg_086c_2 = 0x00000000,
  50
  51         .reg_083c = 0x0a0c0d0e,
  52         .reg_0848 = 0x02040608,
  53         .reg_084c = 0x0a0c0d0e,
  54         .reg_0868 = 0x02040608,
  55 };
  56
  57 static const struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
  58         {0x00, 0x00030159}, {0x01, 0x00031284},
  59         {0x02, 0x00098000}, {0x03, 0x00039c63},
  60         {0x04, 0x000210e7}, {0x09, 0x0002044f},
  61         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
  62         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
  63         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
  64         {0x19, 0x00000000}, {0x1a, 0x00030355},
  65         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
  66         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
  67         {0x1f, 0x00000000}, {0x20, 0x0000b614},
  68         {0x21, 0x0006c000}, {0x22, 0x00000000},
  69         {0x23, 0x00001558}, {0x24, 0x00000060},
  70         {0x25, 0x00000483}, {0x26, 0x0004f000},
  71         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
  72         {0x29, 0x00004783}, {0x2a, 0x00000001},
  73         {0x2b, 0x00021334}, {0x2a, 0x00000000},
  74         {0x2b, 0x00000054}, {0x2a, 0x00000001},
  75         {0x2b, 0x00000808}, {0x2b, 0x00053333},
  76         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
  77         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
  78         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
  79         {0x2b, 0x00000808}, {0x2b, 0x00063333},
  80         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
  81         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
  82         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
  83         {0x2b, 0x00000808}, {0x2b, 0x00073333},
  84         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
  85         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
  86         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
  87         {0x2b, 0x00000709}, {0x2b, 0x00063333},
  88         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
  89         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
  90         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
  91         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
  92         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
  93         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
  94         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
  95         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
  96         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
  97         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
  98         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
  99         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 100         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 101         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 102         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 103         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 104         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 105         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 106         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 107         {0x10, 0x00000000}, {0x11, 0x00000000},
 108         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 109         {0x10, 0x0009000f}, {0x11, 0x00023100},
 110         {0x12, 0x00032000}, {0x12, 0x00071000},
 111         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 112         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 113         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 114         {0x13, 0x00018493}, {0x13, 0x0001429b},
 115         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 116         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 117         {0x13, 0x00000020}, {0x14, 0x0001944c},
 118         {0x14, 0x00059444}, {0x14, 0x0009944c},
 119         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 120         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 121         {0x15, 0x000cf455}, {0x16, 0x00000339},
 122         {0x16, 0x00040339}, {0x16, 0x00080339},
 123         {0x16, 0x000c0366}, {0x00, 0x00010159},
 124         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 125         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 126         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 127         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 128         {0x00, 0x00030159},
 129         {0xff, 0xffffffff}
 130 };
 131
 132 static int rtl8723au_identify_chip(struct rtl8xxxu_priv *priv)
 133 {
 134         struct device *dev = &priv->udev->dev;
 135         u32 val32, sys_cfg, vendor;
 136         int ret = 0;
 137
 138         sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
 139         priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
 140         if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
 141                 dev_info(dev, "Unsupported test chip\n");
 142                 ret = -ENOTSUPP;
 143                 goto out;
 144         }
 145
 146         strscpy(priv->chip_name, "8723AU", sizeof(priv->chip_name));
 147         priv->usb_interrupts = 1;
 148         priv->rtl_chip = RTL8723A;
 149
 150         priv->rf_paths = 1;
 151         priv->rx_paths = 1;
 152         priv->tx_paths = 1;
 153
 154         val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
 155         if (val32 & MULTI_WIFI_FUNC_EN)
 156                 priv->has_wifi = 1;
 157         if (val32 & MULTI_BT_FUNC_EN)
 158                 priv->has_bluetooth = 1;
 159         if (val32 & MULTI_GPS_FUNC_EN)
 160                 priv->has_gps = 1;
 161         priv->is_multi_func = 1;
 162
 163         vendor = sys_cfg & SYS_CFG_VENDOR_ID;
 164         rtl8xxxu_identify_vendor_1bit(priv, vendor);
 165
 166         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
 167         priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
 168
 169         rtl8xxxu_config_endpoints_sie(priv);
 170
 171         /*
 172          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
 173          */
 174         if (!priv->ep_tx_count)
 175                 ret = rtl8xxxu_config_endpoints_no_sie(priv);
 176
 177 out:
 178         return ret;
 179 }
 180
 181 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
 182 {
 183         struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723;
 184
 185         if (efuse->rtl_id != cpu_to_le16(0x8129))
 186                 return -EINVAL;
 187
 188         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 189
 190         memcpy(priv->cck_tx_power_index_A,
 191                efuse->cck_tx_power_index_A,
 192                sizeof(efuse->cck_tx_power_index_A));
 193         memcpy(priv->cck_tx_power_index_B,
 194                efuse->cck_tx_power_index_B,
 195                sizeof(efuse->cck_tx_power_index_B));
 196
 197         memcpy(priv->ht40_1s_tx_power_index_A,
 198                efuse->ht40_1s_tx_power_index_A,
 199                sizeof(efuse->ht40_1s_tx_power_index_A));
 200         memcpy(priv->ht40_1s_tx_power_index_B,
 201                efuse->ht40_1s_tx_power_index_B,
 202                sizeof(efuse->ht40_1s_tx_power_index_B));
 203
 204         memcpy(priv->ht20_tx_power_index_diff,
 205                efuse->ht20_tx_power_index_diff,
 206                sizeof(efuse->ht20_tx_power_index_diff));
 207         memcpy(priv->ofdm_tx_power_index_diff,
 208                efuse->ofdm_tx_power_index_diff,
 209                sizeof(efuse->ofdm_tx_power_index_diff));
 210
 211         memcpy(priv->ht40_max_power_offset,
 212                efuse->ht40_max_power_offset,
 213                sizeof(efuse->ht40_max_power_offset));
 214         memcpy(priv->ht20_max_power_offset,
 215                efuse->ht20_max_power_offset,
 216                sizeof(efuse->ht20_max_power_offset));
 217
 218         if (priv->efuse_wifi.efuse8723.version >= 0x01)
 219                 priv->default_crystal_cap = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
 220         else
 221                 priv->fops->set_crystal_cap = NULL;
 222
 223         priv->power_base = &rtl8723a_power_base;
 224
 225         return 0;
 226 }
 227
 228 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
 229 {
 230         const char *fw_name;
 231         int ret;
 232
 233         switch (priv->chip_cut) {
 234         case 0:
 235                 fw_name = "/*(DEBLOBBED)*/";
 236                 break;
 237         case 1:
 238                 if (priv->enable_bluetooth)
 239                         fw_name = "/*(DEBLOBBED)*/";
 240                 else
 241                         fw_name = "/*(DEBLOBBED)*/";
 242
 243                 break;
 244         default:
 245                 return -EINVAL;
 246         }
 247
 248         ret = rtl8xxxu_load_firmware(priv, fw_name);
 249         return ret;
 250 }
 251
 252 static int rtl8723au_init_phy_rf(struct rtl8xxxu_priv *priv)
 253 {
 254         int ret;
 255
 256         ret = rtl8xxxu_init_phy_rf(priv, rtl8723au_radioa_1t_init_table, RF_A);
 257
 258         /* Reduce 80M spur */
 259         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
 260         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
 261         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
 262         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
 263
 264         return ret;
 265 }
 266
 267 static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv)
 268 {
 269         u8 val8;
 270         u32 val32;
 271         int count, ret = 0;
 272
 273         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
 274         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
 275         val8 |= LDOA15_ENABLE;
 276         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
 277
 278         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
 279         val8 = rtl8xxxu_read8(priv, 0x0067);
 280         val8 &= ~BIT(4);
 281         rtl8xxxu_write8(priv, 0x0067, val8);
 282
 283         mdelay(1);
 284
 285         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
 286         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
 287         val8 &= ~SYS_ISO_ANALOG_IPS;
 288         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
 289
 290         /* disable SW LPS 0x04[10]= 0 */
 291         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
 292         val8 &= ~BIT(2);
 293         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
 294
 295         /* wait till 0x04[17] = 1 power ready*/
 296         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
 297                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
 298                 if (val32 & BIT(17))
 299                         break;
 300
 301                 udelay(10);
 302         }
 303
 304         if (!count) {
 305                 ret = -EBUSY;
 306                 goto exit;
 307         }
 308
 309         /* We should be able to optimize the following three entries into one */
 310
 311         /* release WLON reset 0x04[16]= 1*/
 312         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
 313         val8 |= BIT(0);
 314         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
 315
 316         /* disable HWPDN 0x04[15]= 0*/
 317         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
 318         val8 &= ~BIT(7);
 319         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
 320
 321         /* disable WL suspend*/
 322         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
 323         val8 &= ~(BIT(3) | BIT(4));
 324         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
 325
 326         /* set, then poll until 0 */
 327         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
 328         val32 |= APS_FSMCO_MAC_ENABLE;
 329         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
 330
 331         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
 332                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
 333                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
 334                         ret = 0;
 335                         break;
 336                 }
 337                 udelay(10);
 338         }
 339
 340         if (!count) {
 341                 ret = -EBUSY;
 342                 goto exit;
 343         }
 344
 345         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
 346         /*
 347          * Note: Vendor driver actually clears this bit, despite the
 348          * documentation claims it's being set!
 349          */
 350         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
 351         val8 |= LEDCFG2_DPDT_SELECT;
 352         val8 &= ~LEDCFG2_DPDT_SELECT;
 353         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
 354
 355 exit:
 356         return ret;
 357 }
 358
 359 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
 360 {
 361         u8 val8;
 362         u16 val16;
 363         u32 val32;
 364         int ret;
 365
 366         /*
 367          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
 368          */
 369         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
 370
 371         rtl8xxxu_disabled_to_emu(priv);
 372
 373         ret = rtl8723a_emu_to_active(priv);
 374         if (ret)
 375                 goto exit;
 376
 377         /*
 378          * 0x0004[19] = 1, reset 8051
 379          */
 380         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
 381         val8 |= BIT(3);
 382         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
 383
 384         /*
 385          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
 386          * Set CR bit10 to enable 32k calibration.
 387          */
 388         val16 = rtl8xxxu_read16(priv, REG_CR);
 389         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
 390                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
 391                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
 392                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
 393                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
 394         rtl8xxxu_write16(priv, REG_CR, val16);
 395
 396         /* For EFuse PG */
 397         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
 398         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
 399         val32 |= (0x06 << 28);
 400         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
 401 exit:
 402         return ret;
 403 }
 404
 405 #define XTAL1   GENMASK(23, 18)
 406 #define XTAL0   GENMASK(17, 12)
 407
 408 void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)
 409 {
 410         struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
 411         u32 val32;
 412
 413         if (crystal_cap == cfo->crystal_cap)
 414                 return;
 415
 416         val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
 417
 418         dev_dbg(&priv->udev->dev,
 419                 "%s: Adjusting crystal cap from 0x%x (actually 0x%lx 0x%lx) to 0x%x\n",
 420                 __func__,
 421                 cfo->crystal_cap,
 422                 FIELD_GET(XTAL1, val32),
 423                 FIELD_GET(XTAL0, val32),
 424                 crystal_cap);
 425
 426         val32 &= ~(XTAL1 | XTAL0);
 427         val32 |= FIELD_PREP(XTAL1, crystal_cap) |
 428                  FIELD_PREP(XTAL0, crystal_cap);
 429         rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
 430
 431         cfo->crystal_cap = crystal_cap;
 432 }
 433
 434 s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
 435 {
 436         u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
 437         s8 rx_pwr_all = 0x00;
 438
 439         switch (cck_agc_rpt & 0xc0) {
 440         case 0xc0:
 441                 rx_pwr_all = -46 - (cck_agc_rpt & 0x3e);
 442                 break;
 443         case 0x80:
 444                 rx_pwr_all = -26 - (cck_agc_rpt & 0x3e);
 445                 break;
 446         case 0x40:
 447                 rx_pwr_all = -12 - (cck_agc_rpt & 0x3e);
 448                 break;
 449         case 0x00:
 450                 rx_pwr_all = 16 - (cck_agc_rpt & 0x3e);
 451                 break;
 452         }
 453
 454         return rx_pwr_all;
 455 }
 456
 457 static int rtl8723au_led_brightness_set(struct led_classdev *led_cdev,
 458                                         enum led_brightness brightness)
 459 {
 460         struct rtl8xxxu_priv *priv = container_of(led_cdev,
 461                                                   struct rtl8xxxu_priv,
 462                                                   led_cdev);
 463         u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG2);
 464
 465         if (brightness == LED_OFF) {
 466                 ledcfg &= ~LEDCFG2_HW_LED_CONTROL;
 467                 ledcfg |= LEDCFG2_SW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE;
 468         } else if (brightness == LED_ON) {
 469                 ledcfg &= ~(LEDCFG2_HW_LED_CONTROL | LEDCFG2_SW_LED_DISABLE);
 470                 ledcfg |= LEDCFG2_SW_LED_CONTROL;
 471         } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {
 472                 ledcfg &= ~LEDCFG2_SW_LED_DISABLE;
 473                 ledcfg |= LEDCFG2_HW_LED_CONTROL | LEDCFG2_HW_LED_ENABLE;
 474         }
 475
 476         rtl8xxxu_write8(priv, REG_LEDCFG2, ledcfg);
 477
 478         return 0;
 479 }
 480
 481 struct rtl8xxxu_fileops rtl8723au_fops = {
 482         .identify_chip = rtl8723au_identify_chip,
 483         .parse_efuse = rtl8723au_parse_efuse,
 484         .load_firmware = rtl8723au_load_firmware,
 485         .power_on = rtl8723au_power_on,
 486         .power_off = rtl8xxxu_power_off,
 487         .read_efuse = rtl8xxxu_read_efuse,
 488         .reset_8051 = rtl8xxxu_reset_8051,
 489         .llt_init = rtl8xxxu_init_llt_table,
 490         .init_phy_bb = rtl8xxxu_gen1_init_phy_bb,
 491         .init_phy_rf = rtl8723au_init_phy_rf,
 492         .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
 493         .phy_iq_calibrate = rtl8xxxu_gen1_phy_iq_calibrate,
 494         .config_channel = rtl8xxxu_gen1_config_channel,
 495         .parse_rx_desc = rtl8xxxu_parse_rxdesc16,
 496         .parse_phystats = rtl8723au_rx_parse_phystats,
 497         .init_aggregation = rtl8xxxu_gen1_init_aggregation,
 498         .enable_rf = rtl8xxxu_gen1_enable_rf,
 499         .disable_rf = rtl8xxxu_gen1_disable_rf,
 500         .usb_quirks = rtl8xxxu_gen1_usb_quirks,
 501         .set_tx_power = rtl8xxxu_gen1_set_tx_power,
 502         .update_rate_mask = rtl8xxxu_update_rate_mask,
 503         .report_connect = rtl8xxxu_gen1_report_connect,
 504         .report_rssi = rtl8xxxu_gen1_report_rssi,
 505         .fill_txdesc = rtl8xxxu_fill_txdesc_v1,
 506         .set_crystal_cap = rtl8723a_set_crystal_cap,
 507         .cck_rssi = rtl8723a_cck_rssi,
 508         .led_classdev_brightness_set = rtl8723au_led_brightness_set,
 509         .writeN_block_size = 1024,
 510         .rx_agg_buf_size = 16000,
 511         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32),
 512         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16),
 513         .adda_1t_init = 0x0b1b25a0,
 514         .adda_1t_path_on = 0x0bdb25a0,
 515         .adda_2t_path_on_a = 0x04db25a4,
 516         .adda_2t_path_on_b = 0x0b1b25a4,
 517         .trxff_boundary = 0x27ff,
 518         .pbp_rx = PBP_PAGE_SIZE_128,
 519         .pbp_tx = PBP_PAGE_SIZE_128,
 520         .mactable = rtl8xxxu_gen1_mac_init_table,
 521         .total_page_num = TX_TOTAL_PAGE_NUM,
 522         .page_num_hi = TX_PAGE_NUM_HI_PQ,
 523         .page_num_lo = TX_PAGE_NUM_LO_PQ,
 524         .page_num_norm = TX_PAGE_NUM_NORM_PQ,
 525 };