drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8710b.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver - 8710bu aka 8188gu specific subdriver
   4  *
   5  * Copyright (c) 2023 Bitterblue Smith <rtl8821cerfe2@gmail.com>
   6  *
   7  * Portions copied from existing rtl8xxxu code:
   8  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   9  *
  10  * Portions, notably calibration code:
  11  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/kernel.h>
  16 #include <linux/sched.h>
  17 #include <linux/errno.h>
  18 #include <linux/slab.h>
  19 #include <linux/module.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/list.h>
  22 #include <linux/usb.h>
  23 #include <linux/netdevice.h>
  24 #include <linux/etherdevice.h>
  25 #include <linux/ethtool.h>
  26 #include <linux/wireless.h>
  27 #include <linux/firmware.h>
  28 #include <linux/moduleparam.h>
  29 #include <net/mac80211.h>
  30 #include "rtl8xxxu.h"
  31 #include "rtl8xxxu_regs.h"
  32
  33 static const struct rtl8xxxu_reg8val rtl8710b_mac_init_table[] = {
  34         {0x421, 0x0F}, {0x428, 0x0A}, {0x429, 0x10}, {0x430, 0x00},
  35         {0x431, 0x00}, {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04},
  36         {0x435, 0x05}, {0x436, 0x07}, {0x437, 0x08}, {0x43C, 0x04},
  37         {0x43D, 0x05}, {0x43E, 0x07}, {0x43F, 0x08}, {0x440, 0x5D},
  38         {0x441, 0x01}, {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00},
  39         {0x446, 0x00}, {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xF0},
  40         {0x44A, 0x0F}, {0x44B, 0x3E}, {0x44C, 0x10}, {0x44D, 0x00},
  41         {0x44E, 0x00}, {0x44F, 0x00}, {0x450, 0x00}, {0x451, 0xF0},
  42         {0x452, 0x0F}, {0x453, 0x00}, {0x456, 0x5E}, {0x460, 0x66},
  43         {0x461, 0x66}, {0x4C8, 0xFF}, {0x4C9, 0x08}, {0x4CC, 0xFF},
  44         {0x4CD, 0xFF}, {0x4CE, 0x01}, {0x500, 0x26}, {0x501, 0xA2},
  45         {0x502, 0x2F}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xA3},
  46         {0x506, 0x5E}, {0x507, 0x00}, {0x508, 0x2B}, {0x509, 0xA4},
  47         {0x50A, 0x5E}, {0x50B, 0x00}, {0x50C, 0x4F}, {0x50D, 0xA4},
  48         {0x50E, 0x00}, {0x50F, 0x00}, {0x512, 0x1C}, {0x514, 0x0A},
  49         {0x516, 0x0A}, {0x525, 0x4F}, {0x550, 0x10}, {0x551, 0x10},
  50         {0x559, 0x02}, {0x55C, 0x28}, {0x55D, 0xFF}, {0x605, 0x30},
  51         {0x608, 0x0E}, {0x609, 0x2A}, {0x620, 0xFF}, {0x621, 0xFF},
  52         {0x622, 0xFF}, {0x623, 0xFF}, {0x624, 0xFF}, {0x625, 0xFF},
  53         {0x626, 0xFF}, {0x627, 0xFF}, {0x638, 0x28}, {0x63C, 0x0A},
  54         {0x63D, 0x0A}, {0x63E, 0x0C}, {0x63F, 0x0C}, {0x640, 0x40},
  55         {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xC8}, {0x66A, 0xB0},
  56         {0x66E, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
  57         {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70A, 0x65},
  58         {0x70B, 0x87},
  59         {0xffff, 0xff},
  60 };
  61
  62 /* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */
  63 static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_u_phy_init_table[] = {
  64         {0x800, 0x80045700}, {0x804, 0x00000001},
  65         {0x808, 0x00FC8000}, {0x80C, 0x0000000A},
  66         {0x810, 0x10001331}, {0x814, 0x020C3D10},
  67         {0x818, 0x00200385}, {0x81C, 0x00000000},
  68         {0x820, 0x01000100}, {0x824, 0x00390204},
  69         {0x828, 0x00000000}, {0x82C, 0x00000000},
  70         {0x830, 0x00000000}, {0x834, 0x00000000},
  71         {0x838, 0x00000000}, {0x83C, 0x00000000},
  72         {0x840, 0x00010000}, {0x844, 0x00000000},
  73         {0x848, 0x00000000}, {0x84C, 0x00000000},
  74         {0x850, 0x00030000}, {0x854, 0x00000000},
  75         {0x858, 0x7E1A569A}, {0x85C, 0x569A569A},
  76         {0x860, 0x00000130}, {0x864, 0x20000000},
  77         {0x868, 0x00000000}, {0x86C, 0x27272700},
  78         {0x870, 0x00050000}, {0x874, 0x25005000},
  79         {0x878, 0x00000808}, {0x87C, 0x004F0201},
  80         {0x880, 0xB0000B1E}, {0x884, 0x00000007},
  81         {0x888, 0x00000000}, {0x88C, 0xCCC400C0},
  82         {0x890, 0x00000800}, {0x894, 0xFFFFFFFE},
  83         {0x898, 0x40302010}, {0x89C, 0x00706050},
  84         {0x900, 0x00000000}, {0x904, 0x00000023},
  85         {0x908, 0x00000000}, {0x90C, 0x81121111},
  86         {0x910, 0x00000402}, {0x914, 0x00000201},
  87         {0x920, 0x18C6318C}, {0x924, 0x0000018C},
  88         {0x948, 0x99000000}, {0x94C, 0x00000010},
  89         {0x950, 0x00003000}, {0x954, 0x5A880000},
  90         {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79},
  91         {0x96C, 0x00000003}, {0x970, 0x00000000},
  92         {0x974, 0x00000000}, {0x978, 0x00000000},
  93         {0x97C, 0x13000000}, {0x980, 0x00000000},
  94         {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C},
  95         {0xA08, 0x84838300}, {0xA0C, 0x2E20100F},
  96         {0xA10, 0x9500BB78}, {0xA14, 0x1114D028},
  97         {0xA18, 0x00881117}, {0xA1C, 0x89140F00},
  98         {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C},
  99         {0xA28, 0x00008810}, {0xA2C, 0x00D30000},
 100         {0xA70, 0x101FBF00}, {0xA74, 0x00000007},
 101         {0xA78, 0x00000900}, {0xA7C, 0x225B0606},
 102         {0xA80, 0x218075B1}, {0xA84, 0x00200000},
 103         {0xA88, 0x040C0000}, {0xA8C, 0x12345678},
 104         {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89},
 105         {0xA98, 0x00000000}, {0xA9C, 0x80020000},
 106         {0xAA0, 0x00000000}, {0xAA4, 0x0000000C},
 107         {0xAA8, 0xCA110058}, {0xAAC, 0x01235667},
 108         {0xAB0, 0x00000000}, {0xAB4, 0x20201402},
 109         {0xB2C, 0x00000000}, {0xC00, 0x48071D40},
 110         {0xC04, 0x03A05611}, {0xC08, 0x000000E4},
 111         {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000},
 112         {0xC14, 0x40000100}, {0xC18, 0x08800000},
 113         {0xC1C, 0x40000100}, {0xC20, 0x00000000},
 114         {0xC24, 0x00000000}, {0xC28, 0x00000000},
 115         {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A},
 116         {0xC34, 0x31000040}, {0xC38, 0x21688080},
 117         {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F},
 118         {0xC44, 0x00010036}, {0xC48, 0xEC020107},
 119         {0xC4C, 0x007F037F}, {0xC50, 0x69553420},
 120         {0xC54, 0x43BC0094}, {0xC58, 0x00013169},
 121         {0xC5C, 0x00250492}, {0xC60, 0x00280A00},
 122         {0xC64, 0x7112848B}, {0xC68, 0x47C074FF},
 123         {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D},
 124         {0xC74, 0x020600DB}, {0xC78, 0x0000001F},
 125         {0xC7C, 0x00B91612}, {0xC80, 0x390000E4},
 126         {0xC84, 0x11F60000}, {0xC88, 0x1051B75F},
 127         {0xC8C, 0x20200109}, {0xC90, 0x00091521},
 128         {0xC94, 0x00000000}, {0xC98, 0x00121820},
 129         {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000},
 130         {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606},
 131         {0xCAC, 0x00000060}, {0xCB0, 0x00000000},
 132         {0xCB4, 0x00000000}, {0xCB8, 0x00000000},
 133         {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F},
 134         {0xCC4, 0x00000109}, {0xCC8, 0x000442D6},
 135         {0xCCC, 0x00000000}, {0xCD0, 0x000001C8},
 136         {0xCD4, 0x001C8000}, {0xCD8, 0x00000100},
 137         {0xCDC, 0x40100000}, {0xCE0, 0x00222220},
 138         {0xCE4, 0x10000000}, {0xCE8, 0x37644302},
 139         {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740},
 140         {0xD04, 0x40020401}, {0xD08, 0x0000907F},
 141         {0xD0C, 0x20010201}, {0xD10, 0xA0633333},
 142         {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F},
 143         {0xD2C, 0xCB979975}, {0xD30, 0x00000000},
 144         {0xD34, 0x40608000}, {0xD38, 0x88000000},
 145         {0xD3C, 0xC0127353}, {0xD40, 0x00000000},
 146         {0xD44, 0x00000000}, {0xD48, 0x00000000},
 147         {0xD4C, 0x00000000}, {0xD50, 0x00006528},
 148         {0xD54, 0x00000000}, {0xD58, 0x00000282},
 149         {0xD5C, 0x30032064}, {0xD60, 0x4653DE68},
 150         {0xD64, 0x04518A3C}, {0xD68, 0x00002101},
 151         {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D},
 152         {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D},
 153         {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D},
 154         {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000},
 155         {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F},
 156         {0xE38, 0x02140102}, {0xE3C, 0x681604C2},
 157         {0xE40, 0x01007C00}, {0xE44, 0x01004800},
 158         {0xE48, 0xFB000000}, {0xE4C, 0x000028D1},
 159         {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F},
 160         {0xE58, 0x02140102}, {0xE5C, 0x28160D05},
 161         {0xE60, 0x0000C008}, {0xE68, 0x001B25A4},
 162         {0xE64, 0x281600A0}, {0xE6C, 0x01C00010},
 163         {0xE70, 0x01C00010}, {0xE74, 0x02000010},
 164         {0xE78, 0x02000010}, {0xE7C, 0x02000010},
 165         {0xE80, 0x02000010}, {0xE84, 0x01C00010},
 166         {0xE88, 0x02000010}, {0xE8C, 0x01C00010},
 167         {0xED0, 0x01C00010}, {0xED4, 0x01C00010},
 168         {0xED8, 0x01C00010}, {0xEDC, 0x00000010},
 169         {0xEE0, 0x00000010}, {0xEEC, 0x03C00010},
 170         {0xF14, 0x00000003}, {0xF00, 0x00100300},
 171         {0xF08, 0x0000800B}, {0xF0C, 0x0000F007},
 172         {0xF10, 0x0000A487}, {0xF1C, 0x80000064},
 173         {0xF38, 0x00030155}, {0xF3C, 0x0000003A},
 174         {0xF4C, 0x13000000}, {0xF50, 0x00000000},
 175         {0xF18, 0x00000000},
 176         {0xffff, 0xffffffff},
 177 };
 178
 179 /* If updating the phy init tables, also update rtl8710b_revise_cck_tx_psf(). */
 180 static const struct rtl8xxxu_reg32val rtl8710bu_qfn48m_s_phy_init_table[] = {
 181         {0x800, 0x80045700}, {0x804, 0x00000001},
 182         {0x808, 0x00FC8000}, {0x80C, 0x0000000A},
 183         {0x810, 0x10001331}, {0x814, 0x020C3D10},
 184         {0x818, 0x00200385}, {0x81C, 0x00000000},
 185         {0x820, 0x01000100}, {0x824, 0x00390204},
 186         {0x828, 0x00000000}, {0x82C, 0x00000000},
 187         {0x830, 0x00000000}, {0x834, 0x00000000},
 188         {0x838, 0x00000000}, {0x83C, 0x00000000},
 189         {0x840, 0x00010000}, {0x844, 0x00000000},
 190         {0x848, 0x00000000}, {0x84C, 0x00000000},
 191         {0x850, 0x00030000}, {0x854, 0x00000000},
 192         {0x858, 0x7E1A569A}, {0x85C, 0x569A569A},
 193         {0x860, 0x00000130}, {0x864, 0x20000000},
 194         {0x868, 0x00000000}, {0x86C, 0x27272700},
 195         {0x870, 0x00050000}, {0x874, 0x25005000},
 196         {0x878, 0x00000808}, {0x87C, 0x004F0201},
 197         {0x880, 0xB0000B1E}, {0x884, 0x00000007},
 198         {0x888, 0x00000000}, {0x88C, 0xCCC400C0},
 199         {0x890, 0x00000800}, {0x894, 0xFFFFFFFE},
 200         {0x898, 0x40302010}, {0x89C, 0x00706050},
 201         {0x900, 0x00000000}, {0x904, 0x00000023},
 202         {0x908, 0x00000000}, {0x90C, 0x81121111},
 203         {0x910, 0x00000402}, {0x914, 0x00000201},
 204         {0x920, 0x18C6318C}, {0x924, 0x0000018C},
 205         {0x948, 0x99000000}, {0x94C, 0x00000010},
 206         {0x950, 0x00003000}, {0x954, 0x5A880000},
 207         {0x958, 0x4BC6D87A}, {0x95C, 0x04EB9B79},
 208         {0x96C, 0x00000003}, {0x970, 0x00000000},
 209         {0x974, 0x00000000}, {0x978, 0x00000000},
 210         {0x97C, 0x13000000}, {0x980, 0x00000000},
 211         {0xA00, 0x00D046C8}, {0xA04, 0x80FF800C},
 212         {0xA08, 0x84838300}, {0xA0C, 0x2A20100F},
 213         {0xA10, 0x9500BB78}, {0xA14, 0x1114D028},
 214         {0xA18, 0x00881117}, {0xA1C, 0x89140F00},
 215         {0xA20, 0xE82C0001}, {0xA24, 0x64B80C1C},
 216         {0xA28, 0x00008810}, {0xA2C, 0x00D30000},
 217         {0xA70, 0x101FBF00}, {0xA74, 0x00000007},
 218         {0xA78, 0x00000900}, {0xA7C, 0x225B0606},
 219         {0xA80, 0x218075B1}, {0xA84, 0x00200000},
 220         {0xA88, 0x040C0000}, {0xA8C, 0x12345678},
 221         {0xA90, 0xABCDEF00}, {0xA94, 0x001B1B89},
 222         {0xA98, 0x00000000}, {0xA9C, 0x80020000},
 223         {0xAA0, 0x00000000}, {0xAA4, 0x0000000C},
 224         {0xAA8, 0xCA110058}, {0xAAC, 0x01235667},
 225         {0xAB0, 0x00000000}, {0xAB4, 0x20201402},
 226         {0xB2C, 0x00000000}, {0xC00, 0x48071D40},
 227         {0xC04, 0x03A05611}, {0xC08, 0x000000E4},
 228         {0xC0C, 0x6C6C6C6C}, {0xC10, 0x18800000},
 229         {0xC14, 0x40000100}, {0xC18, 0x08800000},
 230         {0xC1C, 0x40000100}, {0xC20, 0x00000000},
 231         {0xC24, 0x00000000}, {0xC28, 0x00000000},
 232         {0xC2C, 0x00000000}, {0xC30, 0x69E9AC4A},
 233         {0xC34, 0x31000040}, {0xC38, 0x21688080},
 234         {0xC3C, 0x0000170C}, {0xC40, 0x1F78403F},
 235         {0xC44, 0x00010036}, {0xC48, 0xEC020107},
 236         {0xC4C, 0x007F037F}, {0xC50, 0x69553420},
 237         {0xC54, 0x43BC0094}, {0xC58, 0x00013169},
 238         {0xC5C, 0x00250492}, {0xC60, 0x00280A00},
 239         {0xC64, 0x7112848B}, {0xC68, 0x47C074FF},
 240         {0xC6C, 0x00000036}, {0xC70, 0x2C7F000D},
 241         {0xC74, 0x020600DB}, {0xC78, 0x0000001F},
 242         {0xC7C, 0x00B91612}, {0xC80, 0x390000E4},
 243         {0xC84, 0x11F60000}, {0xC88, 0x1051B75F},
 244         {0xC8C, 0x20200109}, {0xC90, 0x00091521},
 245         {0xC94, 0x00000000}, {0xC98, 0x00121820},
 246         {0xC9C, 0x00007F7F}, {0xCA0, 0x00011000},
 247         {0xCA4, 0x800000A0}, {0xCA8, 0x84E6C606},
 248         {0xCAC, 0x00000060}, {0xCB0, 0x00000000},
 249         {0xCB4, 0x00000000}, {0xCB8, 0x00000000},
 250         {0xCBC, 0x28000000}, {0xCC0, 0x1051B75F},
 251         {0xCC4, 0x00000109}, {0xCC8, 0x000442D6},
 252         {0xCCC, 0x00000000}, {0xCD0, 0x000001C8},
 253         {0xCD4, 0x001C8000}, {0xCD8, 0x00000100},
 254         {0xCDC, 0x40100000}, {0xCE0, 0x00222220},
 255         {0xCE4, 0x10000000}, {0xCE8, 0x37644302},
 256         {0xCEC, 0x2F97D40C}, {0xD00, 0x04030740},
 257         {0xD04, 0x40020401}, {0xD08, 0x0000907F},
 258         {0xD0C, 0x20010201}, {0xD10, 0xA0633333},
 259         {0xD14, 0x3333BC53}, {0xD18, 0x7A8F5B6F},
 260         {0xD2C, 0xCB979975}, {0xD30, 0x00000000},
 261         {0xD34, 0x40608000}, {0xD38, 0x88000000},
 262         {0xD3C, 0xC0127353}, {0xD40, 0x00000000},
 263         {0xD44, 0x00000000}, {0xD48, 0x00000000},
 264         {0xD4C, 0x00000000}, {0xD50, 0x00006528},
 265         {0xD54, 0x00000000}, {0xD58, 0x00000282},
 266         {0xD5C, 0x30032064}, {0xD60, 0x4653DE68},
 267         {0xD64, 0x04518A3C}, {0xD68, 0x00002101},
 268         {0xE00, 0x2D2D2D2D}, {0xE04, 0x2D2D2D2D},
 269         {0xE08, 0x0390272D}, {0xE10, 0x2D2D2D2D},
 270         {0xE14, 0x2D2D2D2D}, {0xE18, 0x2D2D2D2D},
 271         {0xE1C, 0x2D2D2D2D}, {0xE28, 0x00000000},
 272         {0xE30, 0x1000DC1F}, {0xE34, 0x10008C1F},
 273         {0xE38, 0x02140102}, {0xE3C, 0x681604C2},
 274         {0xE40, 0x01007C00}, {0xE44, 0x01004800},
 275         {0xE48, 0xFB000000}, {0xE4C, 0x000028D1},
 276         {0xE50, 0x1000DC1F}, {0xE54, 0x10008C1F},
 277         {0xE58, 0x02140102}, {0xE5C, 0x28160D05},
 278         {0xE60, 0x0000C008}, {0xE68, 0x001B25A4},
 279         {0xE64, 0x281600A0}, {0xE6C, 0x01C00010},
 280         {0xE70, 0x01C00010}, {0xE74, 0x02000010},
 281         {0xE78, 0x02000010}, {0xE7C, 0x02000010},
 282         {0xE80, 0x02000010}, {0xE84, 0x01C00010},
 283         {0xE88, 0x02000010}, {0xE8C, 0x01C00010},
 284         {0xED0, 0x01C00010}, {0xED4, 0x01C00010},
 285         {0xED8, 0x01C00010}, {0xEDC, 0x00000010},
 286         {0xEE0, 0x00000010}, {0xEEC, 0x03C00010},
 287         {0xF14, 0x00000003}, {0xF00, 0x00100300},
 288         {0xF08, 0x0000800B}, {0xF0C, 0x0000F007},
 289         {0xF10, 0x0000A487}, {0xF1C, 0x80000064},
 290         {0xF38, 0x00030155}, {0xF3C, 0x0000003A},
 291         {0xF4C, 0x13000000}, {0xF50, 0x00000000},
 292         {0xF18, 0x00000000},
 293         {0xffff, 0xffffffff},
 294 };
 295
 296 static const struct rtl8xxxu_reg32val rtl8710b_agc_table[] = {
 297         {0xC78, 0xFC000001}, {0xC78, 0xFB010001},
 298         {0xC78, 0xFA020001}, {0xC78, 0xF9030001},
 299         {0xC78, 0xF8040001}, {0xC78, 0xF7050001},
 300         {0xC78, 0xF6060001}, {0xC78, 0xF5070001},
 301         {0xC78, 0xF4080001}, {0xC78, 0xF3090001},
 302         {0xC78, 0xF20A0001}, {0xC78, 0xF10B0001},
 303         {0xC78, 0xF00C0001}, {0xC78, 0xEF0D0001},
 304         {0xC78, 0xEE0E0001}, {0xC78, 0xED0F0001},
 305         {0xC78, 0xEC100001}, {0xC78, 0xEB110001},
 306         {0xC78, 0xEA120001}, {0xC78, 0xE9130001},
 307         {0xC78, 0xE8140001}, {0xC78, 0xE7150001},
 308         {0xC78, 0xE6160001}, {0xC78, 0xE5170001},
 309         {0xC78, 0xE4180001}, {0xC78, 0xE3190001},
 310         {0xC78, 0xE21A0001}, {0xC78, 0xE11B0001},
 311         {0xC78, 0xE01C0001}, {0xC78, 0xC31D0001},
 312         {0xC78, 0xC21E0001}, {0xC78, 0xC11F0001},
 313         {0xC78, 0xC0200001}, {0xC78, 0xA3210001},
 314         {0xC78, 0xA2220001}, {0xC78, 0xA1230001},
 315         {0xC78, 0xA0240001}, {0xC78, 0x86250001},
 316         {0xC78, 0x85260001}, {0xC78, 0x84270001},
 317         {0xC78, 0x83280001}, {0xC78, 0x82290001},
 318         {0xC78, 0x812A0001}, {0xC78, 0x802B0001},
 319         {0xC78, 0x632C0001}, {0xC78, 0x622D0001},
 320         {0xC78, 0x612E0001}, {0xC78, 0x602F0001},
 321         {0xC78, 0x42300001}, {0xC78, 0x41310001},
 322         {0xC78, 0x40320001}, {0xC78, 0x23330001},
 323         {0xC78, 0x22340001}, {0xC78, 0x21350001},
 324         {0xC78, 0x20360001}, {0xC78, 0x02370001},
 325         {0xC78, 0x01380001}, {0xC78, 0x00390001},
 326         {0xC78, 0x003A0001}, {0xC78, 0x003B0001},
 327         {0xC78, 0x003C0001}, {0xC78, 0x003D0001},
 328         {0xC78, 0x003E0001}, {0xC78, 0x003F0001},
 329         {0xC78, 0xF7400001}, {0xC78, 0xF7410001},
 330         {0xC78, 0xF7420001}, {0xC78, 0xF7430001},
 331         {0xC78, 0xF7440001}, {0xC78, 0xF7450001},
 332         {0xC78, 0xF7460001}, {0xC78, 0xF7470001},
 333         {0xC78, 0xF7480001}, {0xC78, 0xF6490001},
 334         {0xC78, 0xF34A0001}, {0xC78, 0xF24B0001},
 335         {0xC78, 0xF14C0001}, {0xC78, 0xF04D0001},
 336         {0xC78, 0xD14E0001}, {0xC78, 0xD04F0001},
 337         {0xC78, 0xB5500001}, {0xC78, 0xB4510001},
 338         {0xC78, 0xB3520001}, {0xC78, 0xB2530001},
 339         {0xC78, 0xB1540001}, {0xC78, 0xB0550001},
 340         {0xC78, 0xAF560001}, {0xC78, 0xAE570001},
 341         {0xC78, 0xAD580001}, {0xC78, 0xAC590001},
 342         {0xC78, 0xAB5A0001}, {0xC78, 0xAA5B0001},
 343         {0xC78, 0xA95C0001}, {0xC78, 0xA85D0001},
 344         {0xC78, 0xA75E0001}, {0xC78, 0xA65F0001},
 345         {0xC78, 0xA5600001}, {0xC78, 0xA4610001},
 346         {0xC78, 0xA3620001}, {0xC78, 0xA2630001},
 347         {0xC78, 0xA1640001}, {0xC78, 0xA0650001},
 348         {0xC78, 0x87660001}, {0xC78, 0x86670001},
 349         {0xC78, 0x85680001}, {0xC78, 0x84690001},
 350         {0xC78, 0x836A0001}, {0xC78, 0x826B0001},
 351         {0xC78, 0x816C0001}, {0xC78, 0x806D0001},
 352         {0xC78, 0x636E0001}, {0xC78, 0x626F0001},
 353         {0xC78, 0x61700001}, {0xC78, 0x60710001},
 354         {0xC78, 0x42720001}, {0xC78, 0x41730001},
 355         {0xC78, 0x40740001}, {0xC78, 0x23750001},
 356         {0xC78, 0x22760001}, {0xC78, 0x21770001},
 357         {0xC78, 0x20780001}, {0xC78, 0x03790001},
 358         {0xC78, 0x027A0001}, {0xC78, 0x017B0001},
 359         {0xC78, 0x007C0001}, {0xC78, 0x007D0001},
 360         {0xC78, 0x007E0001}, {0xC78, 0x007F0001},
 361         {0xC50, 0x69553422}, {0xC50, 0x69553420},
 362         {0xffff, 0xffffffff}
 363 };
 364
 365 static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_u_radioa_init_table[] = {
 366         {0x00, 0x00030000}, {0x08, 0x00008400},
 367         {0x17, 0x00000000}, {0x18, 0x00000C01},
 368         {0x19, 0x000739D2}, {0x1C, 0x00000C4C},
 369         {0x1B, 0x00000C6C}, {0x1E, 0x00080009},
 370         {0x1F, 0x00000880}, {0x2F, 0x0001A060},
 371         {0x3F, 0x00015000}, {0x42, 0x000060C0},
 372         {0x57, 0x000D0000}, {0x58, 0x000C0160},
 373         {0x67, 0x00001552}, {0x83, 0x00000000},
 374         {0xB0, 0x000FF9F0}, {0xB1, 0x00010018},
 375         {0xB2, 0x00054C00}, {0xB4, 0x0004486B},
 376         {0xB5, 0x0000112A}, {0xB6, 0x0000053E},
 377         {0xB7, 0x00014408}, {0xB8, 0x00010200},
 378         {0xB9, 0x00080801}, {0xBA, 0x00040001},
 379         {0xBB, 0x00000400}, {0xBF, 0x000C0000},
 380         {0xC2, 0x00002400}, {0xC3, 0x00000009},
 381         {0xC4, 0x00040C91}, {0xC5, 0x00099999},
 382         {0xC6, 0x000000A3}, {0xC7, 0x00088820},
 383         {0xC8, 0x00076C06}, {0xC9, 0x00000000},
 384         {0xCA, 0x00080000}, {0xDF, 0x00000180},
 385         {0xEF, 0x000001A8}, {0x3D, 0x00000003},
 386         {0x3D, 0x00080003}, {0x51, 0x000F1E69},
 387         {0x52, 0x000FBF6C}, {0x53, 0x0000032F},
 388         {0x54, 0x00055007}, {0x56, 0x000517F0},
 389         {0x35, 0x000000F4}, {0x35, 0x00000179},
 390         {0x35, 0x000002F4}, {0x36, 0x00000BF8},
 391         {0x36, 0x00008BF8}, {0x36, 0x00010BF8},
 392         {0x36, 0x00018BF8}, {0x18, 0x00000C01},
 393         {0x5A, 0x00048000}, {0x5A, 0x00048000},
 394         {0x34, 0x0000ADF5}, {0x34, 0x00009DF2},
 395         {0x34, 0x00008DEF}, {0x34, 0x00007DEC},
 396         {0x34, 0x00006DE9}, {0x34, 0x00005CEC},
 397         {0x34, 0x00004CE9}, {0x34, 0x00003C6C},
 398         {0x34, 0x00002C69}, {0x34, 0x0000106E},
 399         {0x34, 0x0000006B}, {0x84, 0x00048000},
 400         {0x87, 0x00000065}, {0x8E, 0x00065540},
 401         {0xDF, 0x00000110}, {0x86, 0x0000002A},
 402         {0x8F, 0x00088000}, {0x81, 0x0003FD80},
 403         {0xEF, 0x00082000}, {0x3B, 0x000F0F00},
 404         {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00},
 405         {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00},
 406         {0x3B, 0x000A0500}, {0x3B, 0x00090400},
 407         {0x3B, 0x00080000}, {0x3B, 0x00070F00},
 408         {0x3B, 0x00060E00}, {0x3B, 0x00050A00},
 409         {0x3B, 0x00040D00}, {0x3B, 0x00030C00},
 410         {0x3B, 0x00020500}, {0x3B, 0x00010400},
 411         {0x3B, 0x00000000}, {0xEF, 0x00080000},
 412         {0xEF, 0x00088000}, {0x3B, 0x00000170},
 413         {0x3B, 0x000C0030}, {0xEF, 0x00080000},
 414         {0xEF, 0x00080000}, {0x30, 0x00010000},
 415         {0x31, 0x0000000F}, {0x32, 0x00047EFE},
 416         {0xEF, 0x00000000}, {0x00, 0x00010159},
 417         {0x18, 0x0000FC01}, {0xFE, 0x00000000},
 418         {0x00, 0x00033D95},
 419         {0xff, 0xffffffff}
 420 };
 421
 422 static const struct rtl8xxxu_rfregval rtl8710bu_qfn48m_s_radioa_init_table[] = {
 423         {0x00, 0x00030000}, {0x08, 0x00008400},
 424         {0x17, 0x00000000}, {0x18, 0x00000C01},
 425         {0x19, 0x000739D2}, {0x1C, 0x00000C4C},
 426         {0x1B, 0x00000C6C}, {0x1E, 0x00080009},
 427         {0x1F, 0x00000880}, {0x2F, 0x0001A060},
 428         {0x3F, 0x00015000}, {0x42, 0x000060C0},
 429         {0x57, 0x000D0000}, {0x58, 0x000C0160},
 430         {0x67, 0x00001552}, {0x83, 0x00000000},
 431         {0xB0, 0x000FF9F0}, {0xB1, 0x00010018},
 432         {0xB2, 0x00054C00}, {0xB4, 0x0004486B},
 433         {0xB5, 0x0000112A}, {0xB6, 0x0000053E},
 434         {0xB7, 0x00014408}, {0xB8, 0x00010200},
 435         {0xB9, 0x00080801}, {0xBA, 0x00040001},
 436         {0xBB, 0x00000400}, {0xBF, 0x000C0000},
 437         {0xC2, 0x00002400}, {0xC3, 0x00000009},
 438         {0xC4, 0x00040C91}, {0xC5, 0x00099999},
 439         {0xC6, 0x000000A3}, {0xC7, 0x00088820},
 440         {0xC8, 0x00076C06}, {0xC9, 0x00000000},
 441         {0xCA, 0x00080000}, {0xDF, 0x00000180},
 442         {0xEF, 0x000001A8}, {0x3D, 0x00000003},
 443         {0x3D, 0x00080003}, {0x51, 0x000F1E69},
 444         {0x52, 0x000FBF6C}, {0x53, 0x0000032F},
 445         {0x54, 0x00055007}, {0x56, 0x000517F0},
 446         {0x35, 0x000000F4}, {0x35, 0x00000179},
 447         {0x35, 0x000002F4}, {0x36, 0x00000BF8},
 448         {0x36, 0x00008BF8}, {0x36, 0x00010BF8},
 449         {0x36, 0x00018BF8}, {0x18, 0x00000C01},
 450         {0x5A, 0x00048000}, {0x5A, 0x00048000},
 451         {0x34, 0x0000ADF5}, {0x34, 0x00009DF2},
 452         {0x34, 0x00008DEF}, {0x34, 0x00007DEC},
 453         {0x34, 0x00006DE9}, {0x34, 0x00005CEC},
 454         {0x34, 0x00004CE9}, {0x34, 0x00003C6C},
 455         {0x34, 0x00002C69}, {0x34, 0x0000106E},
 456         {0x34, 0x0000006B}, {0x84, 0x00048000},
 457         {0x87, 0x00000065}, {0x8E, 0x00065540},
 458         {0xDF, 0x00000110}, {0x86, 0x0000002A},
 459         {0x8F, 0x00088000}, {0x81, 0x0003FD80},
 460         {0xEF, 0x00082000}, {0x3B, 0x000F0F00},
 461         {0x3B, 0x000E0E00}, {0x3B, 0x000DFE00},
 462         {0x3B, 0x000C0D00}, {0x3B, 0x000B0C00},
 463         {0x3B, 0x000A0500}, {0x3B, 0x00090400},
 464         {0x3B, 0x00080000}, {0x3B, 0x00070F00},
 465         {0x3B, 0x00060E00}, {0x3B, 0x00050A00},
 466         {0x3B, 0x00040D00}, {0x3B, 0x00030C00},
 467         {0x3B, 0x00020500}, {0x3B, 0x00010400},
 468         {0x3B, 0x00000000}, {0xEF, 0x00080000},
 469         {0xEF, 0x00088000}, {0x3B, 0x000000B0},
 470         {0x3B, 0x000C0030}, {0xEF, 0x00080000},
 471         {0xEF, 0x00080000}, {0x30, 0x00010000},
 472         {0x31, 0x0000000F}, {0x32, 0x00047EFE},
 473         {0xEF, 0x00000000}, {0x00, 0x00010159},
 474         {0x18, 0x0000FC01}, {0xFE, 0x00000000},
 475         {0x00, 0x00033D95},
 476         {0xff, 0xffffffff}
 477 };
 478
 479 static u32 rtl8710b_indirect_read32(struct rtl8xxxu_priv *priv, u32 addr)
 480 {
 481         struct device *dev = &priv->udev->dev;
 482         u32 val32, value = 0xffffffff;
 483         u8 polling_count = 0xff;
 484
 485         if (!IS_ALIGNED(addr, 4)) {
 486                 dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n",
 487                          __func__, addr);
 488                 return value;
 489         }
 490
 491         mutex_lock(&priv->syson_indirect_access_mutex);
 492
 493         rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr);
 494         rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_READ_OFFSET);
 495
 496         do
 497                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);
 498         while ((val32 & BIT(31)) && (--polling_count > 0));
 499
 500         if (polling_count == 0)
 501                 dev_warn(dev, "%s: Failed to read from 0x%x, 0x806c = 0x%x\n",
 502                          __func__, addr, val32);
 503         else
 504                 value = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B);
 505
 506         mutex_unlock(&priv->syson_indirect_access_mutex);
 507
 508         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 509                 dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, value);
 510
 511         return value;
 512 }
 513
 514 static void rtl8710b_indirect_write32(struct rtl8xxxu_priv *priv, u32 addr, u32 val)
 515 {
 516         struct device *dev = &priv->udev->dev;
 517         u8 polling_count = 0xff;
 518         u32 val32;
 519
 520         if (!IS_ALIGNED(addr, 4)) {
 521                 dev_warn(dev, "%s: Aborting because 0x%x is not a multiple of 4.\n",
 522                          __func__, addr);
 523                 return;
 524         }
 525
 526         mutex_lock(&priv->syson_indirect_access_mutex);
 527
 528         rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, addr);
 529         rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_DATA_8710B, val);
 530         rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, NORMAL_REG_WRITE_OFFSET);
 531
 532         do
 533                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);
 534         while ((val32 & BIT(31)) && (--polling_count > 0));
 535
 536         if (polling_count == 0)
 537                 dev_warn(dev, "%s: Failed to write 0x%x to 0x%x, 0x806c = 0x%x\n",
 538                          __func__, val, addr, val32);
 539
 540         mutex_unlock(&priv->syson_indirect_access_mutex);
 541
 542         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
 543                 dev_info(dev, "%s(%04x) = 0x%08x\n", __func__, addr, val);
 544 }
 545
 546 static u32 rtl8710b_read_syson_reg(struct rtl8xxxu_priv *priv, u32 addr)
 547 {
 548         return rtl8710b_indirect_read32(priv, addr | SYSON_REG_BASE_ADDR_8710B);
 549 }
 550
 551 static void rtl8710b_write_syson_reg(struct rtl8xxxu_priv *priv, u32 addr, u32 val)
 552 {
 553         rtl8710b_indirect_write32(priv, addr | SYSON_REG_BASE_ADDR_8710B, val);
 554 }
 555
 556 static int rtl8710b_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
 557 {
 558         u32 val32;
 559         int i;
 560
 561         /* Write Address */
 562         rtl8xxxu_write32(priv, REG_USB_HOST_INDIRECT_ADDR_8710B, offset);
 563
 564         rtl8xxxu_write32(priv, REG_EFUSE_INDIRECT_CTRL_8710B, EFUSE_READ_OFFSET);
 565
 566         /* Poll for data read */
 567         val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);
 568         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
 569                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_INDIRECT_CTRL_8710B);
 570                 if (!(val32 & BIT(31)))
 571                         break;
 572         }
 573
 574         if (i == RTL8XXXU_MAX_REG_POLL)
 575                 return -EIO;
 576
 577         val32 = rtl8xxxu_read32(priv, REG_USB_HOST_INDIRECT_DATA_8710B);
 578
 579         *data = val32 & 0xff;
 580         return 0;
 581 }
 582
 583 #define EEPROM_PACKAGE_TYPE_8710B       0xF8
 584 #define PACKAGE_QFN48M_U                0xee
 585 #define PACKAGE_QFN48M_S                0xfe
 586
 587 static int rtl8710bu_identify_chip(struct rtl8xxxu_priv *priv)
 588 {
 589         struct device *dev = &priv->udev->dev;
 590         u32 cfg0, cfg2, vendor;
 591         u8 package_type = 0x7; /* a nonsense value */
 592
 593         sprintf(priv->chip_name, "8710BU");
 594         priv->rtl_chip = RTL8710B;
 595         priv->rf_paths = 1;
 596         priv->rx_paths = 1;
 597         priv->tx_paths = 1;
 598         priv->has_wifi = 1;
 599
 600         cfg0 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG0_8710B);
 601         priv->chip_cut = cfg0 & 0xf;
 602
 603         if (cfg0 & BIT(16)) {
 604                 dev_info(dev, "%s: Unsupported test chip\n", __func__);
 605                 return -EOPNOTSUPP;
 606         }
 607
 608         vendor = u32_get_bits(cfg0, 0xc0);
 609
 610         /* SMIC and TSMC are swapped compared to rtl8xxxu_identify_vendor_2bits */
 611         switch (vendor) {
 612         case 0:
 613                 sprintf(priv->chip_vendor, "SMIC");
 614                 priv->vendor_smic = 1;
 615                 break;
 616         case 1:
 617                 sprintf(priv->chip_vendor, "TSMC");
 618                 break;
 619         case 2:
 620                 sprintf(priv->chip_vendor, "UMC");
 621                 priv->vendor_umc = 1;
 622                 break;
 623         default:
 624                 sprintf(priv->chip_vendor, "unknown");
 625                 break;
 626         }
 627
 628         rtl8710b_read_efuse8(priv, EEPROM_PACKAGE_TYPE_8710B, &package_type);
 629
 630         if (package_type == 0xff) {
 631                 dev_warn(dev, "Package type is undefined. Assuming it based on the vendor.\n");
 632
 633                 if (priv->vendor_umc) {
 634                         package_type = PACKAGE_QFN48M_U;
 635                 } else if (priv->vendor_smic) {
 636                         package_type = PACKAGE_QFN48M_S;
 637                 } else {
 638                         dev_warn(dev, "The vendor is neither UMC nor SMIC. Assuming the package type is QFN48M_U.\n");
 639
 640                         /*
 641                          * In this case the vendor driver doesn't set
 642                          * the package type to anything, which is the
 643                          * same as setting it to PACKAGE_DEFAULT (0).
 644                          */
 645                         package_type = PACKAGE_QFN48M_U;
 646                 }
 647         } else if (package_type != PACKAGE_QFN48M_S &&
 648                    package_type != PACKAGE_QFN48M_U) {
 649                 dev_warn(dev, "Failed to read the package type. Assuming it's the default QFN48M_U.\n");
 650
 651                 /*
 652                  * In this case the vendor driver actually sets it to
 653                  * PACKAGE_DEFAULT, but that selects the same values
 654                  * from the init tables as PACKAGE_QFN48M_U.
 655                  */
 656                 package_type = PACKAGE_QFN48M_U;
 657         }
 658
 659         priv->package_type = package_type;
 660
 661         dev_dbg(dev, "Package type: 0x%x\n", package_type);
 662
 663         cfg2 = rtl8710b_read_syson_reg(priv, REG_SYS_SYSTEM_CFG2_8710B);
 664         priv->rom_rev = cfg2 & 0xf;
 665
 666         return rtl8xxxu_config_endpoints_no_sie(priv);
 667 }
 668
 669 static void rtl8710b_revise_cck_tx_psf(struct rtl8xxxu_priv *priv, u8 channel)
 670 {
 671         if (channel == 13) {
 672                 /* Normal values */
 673                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
 674                 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);
 675                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
 676                 /* Special value for channel 13 */
 677                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xd1d80001);
 678         } else if (channel == 14) {
 679                 /* Special values for channel 14 */
 680                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x0000B81C);
 681                 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00000000);
 682                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x00003667);
 683                 /* Normal value */
 684                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
 685         } else {
 686                 /* Restore normal values from the phy init table */
 687                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER2, 0x64B80C1C);
 688                 rtl8xxxu_write32(priv, REG_CCK0_DEBUG_PORT, 0x00008810);
 689                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER3, 0x01235667);
 690                 rtl8xxxu_write32(priv, REG_CCK0_TX_FILTER1, 0xE82C0001);
 691         }
 692 }
 693
 694 static void rtl8710bu_config_channel(struct ieee80211_hw *hw)
 695 {
 696         struct rtl8xxxu_priv *priv = hw->priv;
 697         bool ht40 = conf_is_ht40(&hw->conf);
 698         u8 channel, subchannel = 0;
 699         bool sec_ch_above = 0;
 700         u32 val32;
 701         u16 val16;
 702
 703         channel = (u8)hw->conf.chandef.chan->hw_value;
 704
 705         if (conf_is_ht40_plus(&hw->conf)) {
 706                 sec_ch_above = 1;
 707                 channel += 2;
 708                 subchannel = 2;
 709         } else if (conf_is_ht40_minus(&hw->conf)) {
 710                 sec_ch_above = 0;
 711                 channel -= 2;
 712                 subchannel = 1;
 713         }
 714
 715         /* Set channel */
 716         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
 717         u32p_replace_bits(&val32, channel, MODE_AG_CHANNEL_MASK);
 718         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
 719
 720         rtl8710b_revise_cck_tx_psf(priv, channel);
 721
 722         /* Set bandwidth mode */
 723         val16 = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
 724         val16 &= ~WMAC_TRXPTCL_CTL_BW_MASK;
 725         if (ht40)
 726                 val16 |= WMAC_TRXPTCL_CTL_BW_40;
 727         rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, val16);
 728
 729         rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
 730
 731         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
 732         u32p_replace_bits(&val32, ht40, FPGA_RF_MODE);
 733         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
 734
 735         val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
 736         u32p_replace_bits(&val32, ht40, FPGA_RF_MODE);
 737         rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
 738
 739         if (ht40) {
 740                 /* Set Control channel to upper or lower. */
 741                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
 742                 u32p_replace_bits(&val32, !sec_ch_above, CCK0_SIDEBAND);
 743                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
 744         }
 745
 746         /* RXADC CLK */
 747         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
 748         val32 |= GENMASK(10, 8);
 749         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
 750
 751         /* TXDAC CLK */
 752         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
 753         val32 |= BIT(14) | BIT(12);
 754         val32 &= ~BIT(13);
 755         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
 756
 757         /* small BW */
 758         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
 759         val32 &= ~GENMASK(31, 30);
 760         rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
 761
 762         /* adc buffer clk */
 763         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
 764         val32 &= ~BIT(29);
 765         val32 |= BIT(28);
 766         rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
 767
 768         /* adc buffer clk */
 769         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_AFE);
 770         val32 &= ~BIT(29);
 771         val32 |= BIT(28);
 772         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_AFE, val32);
 773
 774         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
 775         val32 &= ~BIT(30);
 776         val32 |= BIT(29);
 777         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
 778
 779         if (ht40) {
 780                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 781                 val32 &= ~BIT(19);
 782                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 783
 784                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 785                 val32 &= ~GENMASK(23, 20);
 786                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 787
 788                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 789                 val32 &= ~GENMASK(27, 24);
 790                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 791
 792                 /* RF TRX_BW */
 793                 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
 794                 val32 &= ~MODE_AG_BW_MASK;
 795                 val32 |= MODE_AG_BW_40MHZ_8723B;
 796                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
 797         } else {
 798                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 799                 val32 |= BIT(19);
 800                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 801
 802                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 803                 val32 &= ~GENMASK(23, 20);
 804                 val32 |= BIT(23);
 805                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 806
 807                 val32 = rtl8xxxu_read32(priv, REG_OFDM_RX_DFIR);
 808                 val32 &= ~GENMASK(27, 24);
 809                 val32 |= BIT(27) | BIT(25);
 810                 rtl8xxxu_write32(priv, REG_OFDM_RX_DFIR, val32);
 811
 812                 /* RF TRX_BW */
 813                 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
 814                 val32 &= ~MODE_AG_BW_MASK;
 815                 val32 |= MODE_AG_BW_20MHZ_8723B;
 816                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
 817         }
 818 }
 819
 820 static void rtl8710bu_init_aggregation(struct rtl8xxxu_priv *priv)
 821 {
 822         u32 agg_rx;
 823         u8 agg_ctrl;
 824
 825         /* RX aggregation */
 826         agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
 827         agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
 828
 829         agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH);
 830         agg_rx &= ~RXDMA_USB_AGG_ENABLE;
 831         agg_rx &= ~0xFF0F; /* reset agg size and timeout */
 832
 833         rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
 834         rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx);
 835 }
 836
 837 static void rtl8710bu_init_statistics(struct rtl8xxxu_priv *priv)
 838 {
 839         u32 val32;
 840
 841         /* Time duration for NHM unit: 4us, 0xc350=200ms */
 842         rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0xc350);
 843         rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff);
 844         rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff50);
 845         rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff);
 846
 847         /* TH8 */
 848         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
 849         val32 |= 0xff;
 850         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
 851
 852         /* Enable CCK */
 853         val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B);
 854         val32 &= ~(BIT(8) | BIT(9) | BIT(10));
 855         val32 |= BIT(8);
 856         rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32);
 857
 858         /* Max power amongst all RX antennas */
 859         val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC);
 860         val32 |= BIT(7);
 861         rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32);
 862 }
 863
 864 static int rtl8710b_read_efuse(struct rtl8xxxu_priv *priv)
 865 {
 866         struct device *dev = &priv->udev->dev;
 867         u8 val8, word_mask, header, extheader;
 868         u16 efuse_addr, offset;
 869         int i, ret = 0;
 870         u32 val32;
 871
 872         val32 = rtl8710b_read_syson_reg(priv, REG_SYS_EEPROM_CTRL0_8710B);
 873         priv->boot_eeprom = u32_get_bits(val32, EEPROM_BOOT);
 874         priv->has_eeprom = u32_get_bits(val32, EEPROM_ENABLE);
 875
 876         /* Default value is 0xff */
 877         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
 878
 879         efuse_addr = 0;
 880         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
 881                 u16 map_addr;
 882
 883                 ret = rtl8710b_read_efuse8(priv, efuse_addr++, &header);
 884                 if (ret || header == 0xff)
 885                         goto exit;
 886
 887                 if ((header & 0x1f) == 0x0f) {  /* extended header */
 888                         offset = (header & 0xe0) >> 5;
 889
 890                         ret = rtl8710b_read_efuse8(priv, efuse_addr++, &extheader);
 891                         if (ret)
 892                                 goto exit;
 893
 894                         /* All words disabled */
 895                         if ((extheader & 0x0f) == 0x0f)
 896                                 continue;
 897
 898                         offset |= ((extheader & 0xf0) >> 1);
 899                         word_mask = extheader & 0x0f;
 900                 } else {
 901                         offset = (header >> 4) & 0x0f;
 902                         word_mask = header & 0x0f;
 903                 }
 904
 905                 /* Get word enable value from PG header */
 906
 907                 /* We have 8 bits to indicate validity */
 908                 map_addr = offset * 8;
 909                 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
 910                         /* Check word enable condition in the section */
 911                         if (word_mask & BIT(i)) {
 912                                 map_addr += 2;
 913                                 continue;
 914                         }
 915
 916                         ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8);
 917                         if (ret)
 918                                 goto exit;
 919                         if (map_addr >= EFUSE_MAP_LEN - 1) {
 920                                 dev_warn(dev, "%s: Illegal map_addr (%04x), efuse corrupt!\n",
 921                                          __func__, map_addr);
 922                                 ret = -EINVAL;
 923                                 goto exit;
 924                         }
 925                         priv->efuse_wifi.raw[map_addr++] = val8;
 926
 927                         ret = rtl8710b_read_efuse8(priv, efuse_addr++, &val8);
 928                         if (ret)
 929                                 goto exit;
 930                         priv->efuse_wifi.raw[map_addr++] = val8;
 931                 }
 932         }
 933
 934 exit:
 935
 936         return ret;
 937 }
 938
 939 static int rtl8710bu_parse_efuse(struct rtl8xxxu_priv *priv)
 940 {
 941         struct rtl8710bu_efuse *efuse = &priv->efuse_wifi.efuse8710bu;
 942
 943         if (efuse->rtl_id != cpu_to_le16(0x8195))
 944                 return -EINVAL;
 945
 946         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 947
 948         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 949                sizeof(efuse->tx_power_index_A.cck_base));
 950
 951         memcpy(priv->ht40_1s_tx_power_index_A,
 952                efuse->tx_power_index_A.ht40_base,
 953                sizeof(efuse->tx_power_index_A.ht40_base));
 954
 955         priv->ofdm_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.a;
 956         priv->ht20_tx_power_diff[0].a = efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 957
 958         priv->default_crystal_cap = efuse->xtal_k & 0x3f;
 959
 960         return 0;
 961 }
 962
 963 static int rtl8710bu_load_firmware(struct rtl8xxxu_priv *priv)
 964 {
 965         if (priv->vendor_smic) {
 966                 return rtl8xxxu_load_firmware(priv, "/*(DEBLOBBED)*/");
 967         } else if (priv->vendor_umc) {
 968                 return rtl8xxxu_load_firmware(priv, "/*(DEBLOBBED)*/");
 969         } else {
 970                 dev_err(&priv->udev->dev, "We have no suitable firmware for this chip.\n");
 971                 return -1;
 972         }
 973 }
 974
 975 static void rtl8710bu_init_phy_bb(struct rtl8xxxu_priv *priv)
 976 {
 977         const struct rtl8xxxu_reg32val *phy_init_table;
 978         u32 val32;
 979
 980         /* Enable BB and RF */
 981         val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);
 982         val32 |= GENMASK(17, 16) | GENMASK(26, 24);
 983         rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);
 984
 985         if (priv->package_type == PACKAGE_QFN48M_U)
 986                 phy_init_table = rtl8710bu_qfn48m_u_phy_init_table;
 987         else
 988                 phy_init_table = rtl8710bu_qfn48m_s_phy_init_table;
 989
 990         rtl8xxxu_init_phy_regs(priv, phy_init_table);
 991
 992         rtl8xxxu_init_phy_regs(priv, rtl8710b_agc_table);
 993 }
 994
 995 static int rtl8710bu_init_phy_rf(struct rtl8xxxu_priv *priv)
 996 {
 997         const struct rtl8xxxu_rfregval *radioa_init_table;
 998
 999         if (priv->package_type == PACKAGE_QFN48M_U)
1000                 radioa_init_table = rtl8710bu_qfn48m_u_radioa_init_table;
1001         else
1002                 radioa_init_table = rtl8710bu_qfn48m_s_radioa_init_table;
1003
1004         return rtl8xxxu_init_phy_rf(priv, radioa_init_table, RF_A);
1005 }
1006
1007 static int rtl8710bu_iqk_path_a(struct rtl8xxxu_priv *priv, u32 *lok_result)
1008 {
1009         u32 reg_eac, reg_e94, reg_e9c, val32, path_sel_bb;
1010         int result = 0;
1011
1012         path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1013
1014         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000);
1015
1016         /*
1017          * Leave IQK mode
1018          */
1019         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1020         u32p_replace_bits(&val32, 0, 0xffffff00);
1021         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1022
1023         /*
1024          * Enable path A PA in TX IQK mode
1025          */
1026         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1027         val32 |= 0x80000;
1028         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1029         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
1030         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
1031         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07ff7);
1032
1033         /* PA,PAD gain adjust */
1034         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1035         val32 |= BIT(11);
1036         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1037         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
1038         u32p_replace_bits(&val32, 0x1ed, 0x00fff);
1039         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
1040
1041         /* enter IQK mode */
1042         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1043         u32p_replace_bits(&val32, 0x808000, 0xffffff00);
1044         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1045
1046         /* path-A IQK setting */
1047         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
1048         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1049
1050         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ff);
1051         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c06);
1052
1053         /* LO calibration setting */
1054         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x02002911);
1055
1056         /* One shot, path A LOK & IQK */
1057         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
1058         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1059
1060         mdelay(10);
1061
1062         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);
1063
1064         /*
1065          * Leave IQK mode
1066          */
1067         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1068         u32p_replace_bits(&val32, 0, 0xffffff00);
1069         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1070
1071         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1072         val32 &= ~BIT(11);
1073         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1074
1075         /* save LOK result */
1076         *lok_result = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC);
1077
1078         /* Check failed */
1079         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1080         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
1081         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
1082
1083         if (!(reg_eac & BIT(28)) &&
1084             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
1085             ((reg_e9c & 0x03ff0000) != 0x00420000))
1086                 result |= 0x01;
1087
1088         return result;
1089 }
1090
1091 static int rtl8710bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv, u32 lok_result)
1092 {
1093         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32, path_sel_bb, tmp;
1094         int result = 0;
1095
1096         path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1097
1098         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x99000000);
1099
1100         /*
1101          * Leave IQK mode
1102          */
1103         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1104         u32p_replace_bits(&val32, 0, 0xffffff00);
1105         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1106
1107         /* modify RXIQK mode table */
1108         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1109         val32 |= 0x80000;
1110         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1111         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
1112         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
1113         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
1114
1115         /* PA,PAD gain adjust */
1116         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1117         val32 |= BIT(11);
1118         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1119         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
1120         u32p_replace_bits(&val32, 0xf, 0x003e0);
1121         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
1122
1123         /*
1124          * Enter IQK mode
1125          */
1126         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1127         u32p_replace_bits(&val32, 0x808000, 0xffffff00);
1128         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1129
1130         /* path-A IQK setting */
1131         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
1132         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1133
1134         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216129f);
1135         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c00);
1136
1137         /*
1138          * Tx IQK setting
1139          */
1140         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1141         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1142
1143         /* LO calibration setting */
1144         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
1145
1146         /* One shot, path A LOK & IQK */
1147         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
1148         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1149
1150         mdelay(10);
1151
1152         /* Check failed */
1153         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1154         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
1155         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
1156
1157         if (!(reg_eac & BIT(28)) &&
1158             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
1159             ((reg_e9c & 0x03ff0000) != 0x00420000)) {
1160                 result |= 0x01;
1161         } else { /* If TX not OK, ignore RX */
1162
1163                 /* reload RF path */
1164                 rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);
1165
1166                 /*
1167                  * Leave IQK mode
1168                  */
1169                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1170                 u32p_replace_bits(&val32, 0, 0xffffff00);
1171                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1172
1173                 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1174                 val32 &= ~BIT(11);
1175                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1176
1177                 return result;
1178         }
1179
1180         val32 = 0x80007c00 | (reg_e94 & 0x3ff0000) | ((reg_e9c & 0x3ff0000) >> 16);
1181         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
1182
1183         /*
1184          * Modify RX IQK mode table
1185          */
1186         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1187         u32p_replace_bits(&val32, 0, 0xffffff00);
1188         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1189
1190         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT);
1191         val32 |= 0x80000;
1192         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32);
1193         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
1194         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
1195         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);
1196
1197         /*
1198          * PA, PAD setting
1199          */
1200         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1201         val32 |= BIT(11);
1202         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1203         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_PAD_TXG);
1204         u32p_replace_bits(&val32, 0x2a, 0x00fff);
1205         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, val32);
1206
1207         /*
1208          * Enter IQK mode
1209          */
1210         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1211         u32p_replace_bits(&val32, 0x808000, 0xffffff00);
1212         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1213
1214         /*
1215          * RX IQK setting
1216          */
1217         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1218
1219         /* path-A IQK setting */
1220         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
1221         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
1222
1223         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816169f);
1224
1225         /* LO calibration setting */
1226         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
1227
1228         /* One shot, path A LOK & IQK */
1229         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
1230         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1231
1232         mdelay(10);
1233
1234         /* reload RF path */
1235         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);
1236
1237         /*
1238          * Leave IQK mode
1239          */
1240         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1241         u32p_replace_bits(&val32, 0, 0xffffff00);
1242         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1243
1244         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA);
1245         val32 &= ~BIT(11);
1246         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, val32);
1247
1248         /* reload LOK value */
1249         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXM_IDAC, lok_result);
1250
1251         /* Check failed */
1252         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1253         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
1254
1255         tmp = (reg_eac & 0x03ff0000) >> 16;
1256         if ((tmp & 0x200) > 0)
1257                 tmp = 0x400 - tmp;
1258
1259         if (!(reg_eac & BIT(27)) &&
1260             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
1261             ((reg_eac & 0x03ff0000) != 0x00360000) &&
1262             (((reg_ea4 & 0x03ff0000) >> 16) < 0x11a) &&
1263             (((reg_ea4 & 0x03ff0000) >> 16) > 0xe6) &&
1264             (tmp < 0x1a))
1265                 result |= 0x02;
1266
1267         return result;
1268 }
1269
1270 static void rtl8710bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1271                                       int result[][8], int t)
1272 {
1273         struct device *dev = &priv->udev->dev;
1274         u32 i, val32, rx_initial_gain, lok_result;
1275         u32 path_sel_bb, path_sel_rf;
1276         int path_a_ok;
1277         int retry = 2;
1278         static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1279                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1280                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1281                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1282                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1283                 REG_TX_TO_TX, REG_RX_CCK,
1284                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1285                 REG_RX_TO_RX, REG_STANDBY,
1286                 REG_SLEEP, REG_PMPD_ANAEN
1287         };
1288         static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1289                 REG_TXPAUSE, REG_BEACON_CTRL,
1290                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1291         };
1292         static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1293                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1294                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1295                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1296                 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1297         };
1298
1299         /*
1300          * Note: IQ calibration must be performed after loading
1301          *       PHY_REG.txt , and radio_a, radio_b.txt
1302          */
1303
1304         rx_initial_gain = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1305
1306         if (t == 0) {
1307                 /* Save ADDA parameters, turn Path A ADDA on */
1308                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1309                                    RTL8XXXU_ADDA_REGS);
1310                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1311                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
1312                                    priv->bb_backup, RTL8XXXU_BB_REGS);
1313         }
1314
1315         rtl8xxxu_path_adda_on(priv, adda_regs, true);
1316
1317         if (t == 0) {
1318                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
1319                 priv->pi_enabled = u32_get_bits(val32, FPGA0_HSSI_PARM1_PI);
1320         }
1321
1322         if (!priv->pi_enabled) {
1323                 /* Switch BB to PI mode to do IQ Calibration */
1324                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
1325                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
1326         }
1327
1328         /* MAC settings */
1329         val32 = rtl8xxxu_read32(priv, REG_TX_PTCL_CTRL);
1330         val32 |= 0x00ff0000;
1331         rtl8xxxu_write32(priv, REG_TX_PTCL_CTRL, val32);
1332
1333         /* save RF path */
1334         path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1335         path_sel_rf = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_S0S1);
1336
1337         /* BB setting */
1338         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1339         val32 |= 0x0f000000;
1340         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1341         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x03c00010);
1342         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05601);
1343         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1344         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000);
1345
1346         /* IQ calibration setting */
1347         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1348         u32p_replace_bits(&val32, 0x808000, 0xffffff00);
1349         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1350         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1351         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1352
1353         for (i = 0; i < retry; i++) {
1354                 path_a_ok = rtl8710bu_iqk_path_a(priv, &lok_result);
1355
1356                 if (path_a_ok == 0x01) {
1357                         val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
1358                         result[t][0] = (val32 >> 16) & 0x3ff;
1359
1360                         val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
1361                         result[t][1] = (val32 >> 16) & 0x3ff;
1362                         break;
1363                 } else {
1364                         result[t][0] = 0x100;
1365                         result[t][1] = 0x0;
1366                 }
1367         }
1368
1369         for (i = 0; i < retry; i++) {
1370                 path_a_ok = rtl8710bu_rx_iqk_path_a(priv, lok_result);
1371
1372                 if (path_a_ok == 0x03) {
1373                         val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
1374                         result[t][2] = (val32 >> 16) & 0x3ff;
1375
1376                         val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1377                         result[t][3] = (val32 >> 16) & 0x3ff;
1378                         break;
1379                 } else {
1380                         result[t][2] = 0x100;
1381                         result[t][3] = 0x0;
1382                 }
1383         }
1384
1385         if (!path_a_ok)
1386                 dev_warn(dev, "%s: Path A IQK failed!\n", __func__);
1387
1388         /* Back to BB mode, load original value */
1389         val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK);
1390         u32p_replace_bits(&val32, 0, 0xffffff00);
1391         rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32);
1392
1393         if (t == 0)
1394                 return;
1395
1396         /* Reload ADDA power saving parameters */
1397         rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, RTL8XXXU_ADDA_REGS);
1398
1399         /* Reload MAC parameters */
1400         rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1401
1402         /* Reload BB parameters */
1403         rtl8xxxu_restore_regs(priv, iqk_bb_regs, priv->bb_backup, RTL8XXXU_BB_REGS);
1404
1405         /* Reload RF path */
1406         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);
1407         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, path_sel_rf);
1408
1409         /* Restore RX initial gain */
1410         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1411         u32p_replace_bits(&val32, 0x50, 0x000000ff);
1412         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32);
1413         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1414         u32p_replace_bits(&val32, rx_initial_gain & 0xff, 0x000000ff);
1415         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32);
1416
1417         /* Load 0xe30 IQC default value */
1418         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1419         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1420 }
1421
1422 static void rtl8710bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1423 {
1424         struct device *dev = &priv->udev->dev;
1425         int result[4][8]; /* last is final result */
1426         int i, candidate;
1427         bool path_a_ok;
1428         s32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1429         s32 reg_tmp = 0;
1430         bool simu;
1431         u32 path_sel_bb;
1432
1433         /* Save RF path */
1434         path_sel_bb = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH);
1435
1436         memset(result, 0, sizeof(result));
1437         candidate = -1;
1438
1439         path_a_ok = false;
1440
1441         for (i = 0; i < 3; i++) {
1442                 rtl8710bu_phy_iqcalibrate(priv, result, i);
1443
1444                 if (i == 1) {
1445                         simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 1);
1446                         if (simu) {
1447                                 candidate = 0;
1448                                 break;
1449                         }
1450                 }
1451
1452                 if (i == 2) {
1453                         simu = rtl8xxxu_gen2_simularity_compare(priv, result, 0, 2);
1454                         if (simu) {
1455                                 candidate = 0;
1456                                 break;
1457                         }
1458
1459                         simu = rtl8xxxu_gen2_simularity_compare(priv, result, 1, 2);
1460                         if (simu) {
1461                                 candidate = 1;
1462                         } else {
1463                                 for (i = 0; i < 8; i++)
1464                                         reg_tmp += result[3][i];
1465
1466                                 if (reg_tmp)
1467                                         candidate = 3;
1468                                 else
1469                                         candidate = -1;
1470                         }
1471                 }
1472         }
1473
1474         if (candidate >= 0) {
1475                 reg_e94 = result[candidate][0];
1476                 reg_e9c = result[candidate][1];
1477                 reg_ea4 = result[candidate][2];
1478                 reg_eac = result[candidate][3];
1479
1480                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1481                 dev_dbg(dev, "%s: e94=%x e9c=%x ea4=%x eac=%x\n",
1482                         __func__, reg_e94, reg_e9c, reg_ea4, reg_eac);
1483
1484                 path_a_ok = true;
1485
1486                 if (reg_e94)
1487                         rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1488                                                    candidate, (reg_ea4 == 0));
1489         }
1490
1491         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1492                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1493
1494         rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel_bb);
1495 }
1496
1497 static int rtl8710b_emu_to_active(struct rtl8xxxu_priv *priv)
1498 {
1499         u8 val8;
1500         int count, ret = 0;
1501
1502         /* AFE power mode selection: 1: LDO mode, 0: Power-cut mode */
1503         val8 = rtl8xxxu_read8(priv, 0x5d);
1504         val8 &= ~BIT(0);
1505         rtl8xxxu_write8(priv, 0x5d, val8);
1506
1507         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B);
1508         val8 |= BIT(0);
1509         rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8);
1510
1511         rtl8xxxu_write8(priv, 0x56, 0x0e);
1512
1513         val8 = rtl8xxxu_read8(priv, 0x20);
1514         val8 |= BIT(0);
1515         rtl8xxxu_write8(priv, 0x20, val8);
1516
1517         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1518                 val8 = rtl8xxxu_read8(priv, 0x20);
1519                 if (!(val8 & BIT(0)))
1520                         break;
1521
1522                 udelay(10);
1523         }
1524
1525         if (!count)
1526                 ret = -EBUSY;
1527
1528         return ret;
1529 }
1530
1531 static int rtl8710bu_active_to_emu(struct rtl8xxxu_priv *priv)
1532 {
1533         u8 val8;
1534         u32 val32;
1535         int count, ret = 0;
1536
1537         /* Turn off RF */
1538         val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);
1539         val32 &= ~GENMASK(26, 24);
1540         rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);
1541
1542         /* BB reset */
1543         val32 = rtl8xxxu_read32(priv, REG_SYS_FUNC_8710B);
1544         val32 &= ~GENMASK(17, 16);
1545         rtl8xxxu_write32(priv, REG_SYS_FUNC_8710B, val32);
1546
1547         /* Turn off MAC by HW state machine */
1548         val8 = rtl8xxxu_read8(priv, 0x20);
1549         val8 |= BIT(1);
1550         rtl8xxxu_write8(priv, 0x20, val8);
1551
1552         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1553                 val8 = rtl8xxxu_read8(priv, 0x20);
1554                 if ((val8 & BIT(1)) == 0) {
1555                         ret = 0;
1556                         break;
1557                 }
1558                 udelay(10);
1559         }
1560
1561         if (!count)
1562                 ret = -EBUSY;
1563
1564         return ret;
1565 }
1566
1567 static int rtl8710bu_active_to_lps(struct rtl8xxxu_priv *priv)
1568 {
1569         struct device *dev = &priv->udev->dev;
1570         u8 val8;
1571         u16 val16;
1572         u32 val32;
1573         int retry, retval;
1574
1575         /* Tx Pause */
1576         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1577
1578         retry = 100;
1579         retval = -EBUSY;
1580         /*
1581          * Poll 32 bit wide REG_SCH_TX_CMD for 0x00000000 to ensure no TX is pending.
1582          */
1583         do {
1584                 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1585                 if (!val32) {
1586                         retval = 0;
1587                         break;
1588                 }
1589                 udelay(10);
1590         } while (retry--);
1591
1592         if (!retry) {
1593                 dev_warn(dev, "Failed to flush TX queue\n");
1594                 retval = -EBUSY;
1595                 return retval;
1596         }
1597
1598         /* Disable CCK and OFDM, clock gated */
1599         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1600         val8 &= ~SYS_FUNC_BBRSTB;
1601         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1602
1603         udelay(2);
1604
1605         /* Whole BB is reset */
1606         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1607         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1608         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1609
1610         /* Reset MAC TRX */
1611         val16 = rtl8xxxu_read16(priv, REG_CR);
1612         val16 &= 0xff00;
1613         val16 |= CR_HCI_RXDMA_ENABLE | CR_HCI_TXDMA_ENABLE;
1614         val16 &= ~CR_SECURITY_ENABLE;
1615         rtl8xxxu_write16(priv, REG_CR, val16);
1616
1617         /* Respond TxOK to scheduler */
1618         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1619         val8 |= DUAL_TSF_TX_OK;
1620         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1621
1622         return retval;
1623 }
1624
1625 static int rtl8710bu_power_on(struct rtl8xxxu_priv *priv)
1626 {
1627         u32 val32;
1628         u16 val16;
1629         u8 val8;
1630         int ret;
1631
1632         rtl8xxxu_write8(priv, REG_USB_ACCESS_TIMEOUT, 0x80);
1633
1634         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
1635         val8 &= ~BIT(5);
1636         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
1637
1638         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC_8710B);
1639         val8 |= BIT(0);
1640         rtl8xxxu_write8(priv, REG_SYS_FUNC_8710B, val8);
1641
1642         val8 = rtl8xxxu_read8(priv, 0x20);
1643         val8 |= BIT(0);
1644         rtl8xxxu_write8(priv, 0x20, val8);
1645
1646         rtl8xxxu_write8(priv, REG_AFE_CTRL_8710B, 0);
1647
1648         val8 = rtl8xxxu_read8(priv, REG_WL_STATUS_8710B);
1649         val8 |= BIT(1);
1650         rtl8xxxu_write8(priv, REG_WL_STATUS_8710B, val8);
1651
1652         ret = rtl8710b_emu_to_active(priv);
1653         if (ret)
1654                 return ret;
1655
1656         rtl8xxxu_write16(priv, REG_CR, 0);
1657
1658         val16 = rtl8xxxu_read16(priv, REG_CR);
1659
1660         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1661                  CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1662                  CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1663                  CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE;
1664         rtl8xxxu_write16(priv, REG_CR, val16);
1665
1666         /* Enable hardware sequence number. */
1667         val8 = rtl8xxxu_read8(priv, REG_HWSEQ_CTRL);
1668         val8 |= 0x7f;
1669         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, val8);
1670
1671         udelay(2);
1672
1673         /*
1674          * Technically the rest was in the rtl8710bu_hal_init function,
1675          * not the power_on function, but it's fine because we only
1676          * call power_on from init_device.
1677          */
1678
1679         val8 = rtl8xxxu_read8(priv, 0xfef9);
1680         val8 &= ~BIT(0);
1681         rtl8xxxu_write8(priv, 0xfef9, val8);
1682
1683         /* Clear the 0x40000138[5] to prevent CM4 Suspend */
1684         val32 = rtl8710b_read_syson_reg(priv, 0x138);
1685         val32 &= ~BIT(5);
1686         rtl8710b_write_syson_reg(priv, 0x138, val32);
1687
1688         return ret;
1689 }
1690
1691 static void rtl8710bu_power_off(struct rtl8xxxu_priv *priv)
1692 {
1693         u32 val32;
1694         u8 val8;
1695
1696         rtl8xxxu_flush_fifo(priv);
1697
1698         rtl8xxxu_write32(priv, REG_HISR0_8710B, 0xffffffff);
1699         rtl8xxxu_write32(priv, REG_HIMR0_8710B, 0x0);
1700
1701         /* Set the 0x40000138[5] to allow CM4 Suspend */
1702         val32 = rtl8710b_read_syson_reg(priv, 0x138);
1703         val32 |= BIT(5);
1704         rtl8710b_write_syson_reg(priv, 0x138, val32);
1705
1706         /* Stop rx */
1707         rtl8xxxu_write8(priv, REG_CR, 0x00);
1708
1709         rtl8710bu_active_to_lps(priv);
1710
1711         /* Reset MCU ? */
1712         val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);
1713         val8 &= ~BIT(0);
1714         rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);
1715
1716         /* Reset MCU ready status */
1717         rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B, 0x00);
1718
1719         rtl8710bu_active_to_emu(priv);
1720 }
1721
1722 static void rtl8710b_reset_8051(struct rtl8xxxu_priv *priv)
1723 {
1724         u8 val8;
1725
1726         val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);
1727         val8 &= ~BIT(0);
1728         rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);
1729
1730         udelay(50);
1731
1732         val8 = rtl8xxxu_read8(priv, REG_8051FW_CTRL_V1_8710B + 3);
1733         val8 |= BIT(0);
1734         rtl8xxxu_write8(priv, REG_8051FW_CTRL_V1_8710B + 3, val8);
1735 }
1736
1737 static void rtl8710b_enable_rf(struct rtl8xxxu_priv *priv)
1738 {
1739         u32 val32;
1740
1741         rtl8xxxu_write8(priv, REG_RF_CTRL, RF_ENABLE | RF_RSTB | RF_SDMRSTB);
1742
1743         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1744         val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
1745         val32 |= OFDM_RF_PATH_RX_A | OFDM_RF_PATH_TX_A;
1746         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1747
1748         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1749 }
1750
1751 static void rtl8710b_disable_rf(struct rtl8xxxu_priv *priv)
1752 {
1753         u32 val32;
1754
1755         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1756         val32 &= ~OFDM_RF_PATH_TX_MASK;
1757         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1758
1759         /* Power down RF module */
1760         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1761 }
1762
1763 static void rtl8710b_usb_quirks(struct rtl8xxxu_priv *priv)
1764 {
1765         u16 val16;
1766
1767         rtl8xxxu_gen2_usb_quirks(priv);
1768
1769         val16 = rtl8xxxu_read16(priv, REG_CR);
1770         val16 |= (CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE);
1771         rtl8xxxu_write16(priv, REG_CR, val16);
1772 }
1773
1774 #define XTAL1   GENMASK(29, 24)
1775 #define XTAL0   GENMASK(23, 18)
1776
1777 static void rtl8710b_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap)
1778 {
1779         struct rtl8xxxu_cfo_tracking *cfo = &priv->cfo_tracking;
1780         u32 val32;
1781
1782         if (crystal_cap == cfo->crystal_cap)
1783                 return;
1784
1785         val32 = rtl8710b_read_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B);
1786
1787         dev_dbg(&priv->udev->dev,
1788                 "%s: Adjusting crystal cap from 0x%x (actually 0x%x 0x%x) to 0x%x\n",
1789                 __func__,
1790                 cfo->crystal_cap,
1791                 u32_get_bits(val32, XTAL1),
1792                 u32_get_bits(val32, XTAL0),
1793                 crystal_cap);
1794
1795         u32p_replace_bits(&val32, crystal_cap, XTAL1);
1796         u32p_replace_bits(&val32, crystal_cap, XTAL0);
1797         rtl8710b_write_syson_reg(priv, REG_SYS_XTAL_CTRL0_8710B, val32);
1798
1799         cfo->crystal_cap = crystal_cap;
1800 }
1801
1802 static s8 rtl8710b_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
1803 {
1804         struct jaguar2_phy_stats_type0 *phy_stats0 = (struct jaguar2_phy_stats_type0 *)phy_stats;
1805         u8 lna_idx = (phy_stats0->lna_h << 3) | phy_stats0->lna_l;
1806         u8 vga_idx = phy_stats0->vga;
1807         s8 rx_pwr_all = 0x00;
1808
1809         switch (lna_idx) {
1810         case 7:
1811                 rx_pwr_all = -52 - (2 * vga_idx);
1812                 break;
1813         case 6:
1814                 rx_pwr_all = -42 - (2 * vga_idx);
1815                 break;
1816         case 5:
1817                 rx_pwr_all = -36 - (2 * vga_idx);
1818                 break;
1819         case 3:
1820                 rx_pwr_all = -12 - (2 * vga_idx);
1821                 break;
1822         case 2:
1823                 rx_pwr_all = 0 - (2 * vga_idx);
1824                 break;
1825         default:
1826                 rx_pwr_all = 0;
1827                 break;
1828         }
1829
1830         return rx_pwr_all;
1831 }
1832
1833 struct rtl8xxxu_fileops rtl8710bu_fops = {
1834         .identify_chip = rtl8710bu_identify_chip,
1835         .parse_efuse = rtl8710bu_parse_efuse,
1836         .load_firmware = rtl8710bu_load_firmware,
1837         .power_on = rtl8710bu_power_on,
1838         .power_off = rtl8710bu_power_off,
1839         .read_efuse = rtl8710b_read_efuse,
1840         .reset_8051 = rtl8710b_reset_8051,
1841         .llt_init = rtl8xxxu_auto_llt_table,
1842         .init_phy_bb = rtl8710bu_init_phy_bb,
1843         .init_phy_rf = rtl8710bu_init_phy_rf,
1844         .phy_lc_calibrate = rtl8188f_phy_lc_calibrate,
1845         .phy_iq_calibrate = rtl8710bu_phy_iq_calibrate,
1846         .config_channel = rtl8710bu_config_channel,
1847         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1848         .parse_phystats = jaguar2_rx_parse_phystats,
1849         .init_aggregation = rtl8710bu_init_aggregation,
1850         .init_statistics = rtl8710bu_init_statistics,
1851         .init_burst = rtl8xxxu_init_burst,
1852         .enable_rf = rtl8710b_enable_rf,
1853         .disable_rf = rtl8710b_disable_rf,
1854         .usb_quirks = rtl8710b_usb_quirks,
1855         .set_tx_power = rtl8188f_set_tx_power,
1856         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1857         .report_connect = rtl8xxxu_gen2_report_connect,
1858         .report_rssi = rtl8xxxu_gen2_report_rssi,
1859         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1860         .set_crystal_cap = rtl8710b_set_crystal_cap,
1861         .cck_rssi = rtl8710b_cck_rssi,
1862         .writeN_block_size = 4,
1863         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1864         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1865         .has_tx_report = 1,
1866         .gen2_thermal_meter = 1,
1867         .needs_full_init = 1,
1868         .init_reg_rxfltmap = 1,
1869         .init_reg_pkt_life_time = 1,
1870         .init_reg_hmtfr = 1,
1871         .ampdu_max_time = 0x5e,
1872         /*
1873          * The RTL8710BU vendor driver uses 0x50 here and it works fine,
1874          * but in rtl8xxxu 0x50 causes slow upload and random packet loss. Why?
1875          */
1876         .ustime_tsf_edca = 0x28,
1877         .max_aggr_num = 0x0c14,
1878         .supports_ap = 1,
1879         .max_macid_num = 16,
1880         .adda_1t_init = 0x03c00016,
1881         .adda_1t_path_on = 0x03c00016,
1882         .trxff_boundary = 0x3f7f,
1883         .pbp_rx = PBP_PAGE_SIZE_256,
1884         .pbp_tx = PBP_PAGE_SIZE_256,
1885         .mactable = rtl8710b_mac_init_table,
1886         .total_page_num = TX_TOTAL_PAGE_NUM_8723B,
1887         .page_num_hi = TX_PAGE_NUM_HI_PQ_8723B,
1888         .page_num_lo = TX_PAGE_NUM_LO_PQ_8723B,
1889         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8723B,
1890 };