drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
   4  *
   5  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   6  *
   7  * Portions, notably calibration code:
   8  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   9  *
  10  * This driver was written as a replacement for the vendor provided
  11  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  12  * their programming interface, I have started adding support for
  13  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  14  */
  15
  16 #include <linux/init.h>
  17 #include <linux/kernel.h>
  18 #include <linux/sched.h>
  19 #include <linux/errno.h>
  20 #include <linux/slab.h>
  21 #include <linux/module.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/list.h>
  24 #include <linux/usb.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/etherdevice.h>
  27 #include <linux/ethtool.h>
  28 #include <linux/wireless.h>
  29 #include <linux/firmware.h>
  30 #include <linux/moduleparam.h>
  31 #include <net/mac80211.h>
  32 #include "rtl8xxxu.h"
  33 #include "rtl8xxxu_regs.h"
  34
  35 static const struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
  36         {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
  37         {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
  38         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
  39         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
  40         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
  41         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
  42         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
  43         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
  44         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
  45         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
  46         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
  47         {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
  48         {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
  49         {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
  50         {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
  51         {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
  52         {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
  53         {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
  54         {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
  55         {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
  56         {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
  57         {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
  58         {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
  59         {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
  60         {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
  61         {0x70b, 0x87},
  62         {0xffff, 0xff},
  63 };
  64
  65 static const struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
  66         {0x800, 0x80040000}, {0x804, 0x00000003},
  67         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
  68         {0x810, 0x10001331}, {0x814, 0x020c3d10},
  69         {0x818, 0x02220385}, {0x81c, 0x00000000},
  70         {0x820, 0x01000100}, {0x824, 0x00390204},
  71         {0x828, 0x01000100}, {0x82c, 0x00390204},
  72         {0x830, 0x32323232}, {0x834, 0x30303030},
  73         {0x838, 0x30303030}, {0x83c, 0x30303030},
  74         {0x840, 0x00010000}, {0x844, 0x00010000},
  75         {0x848, 0x28282828}, {0x84c, 0x28282828},
  76         {0x850, 0x00000000}, {0x854, 0x00000000},
  77         {0x858, 0x009a009a}, {0x85c, 0x01000014},
  78         {0x860, 0x66f60000}, {0x864, 0x061f0000},
  79         {0x868, 0x30303030}, {0x86c, 0x30303030},
  80         {0x870, 0x00000000}, {0x874, 0x55004200},
  81         {0x878, 0x08080808}, {0x87c, 0x00000000},
  82         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
  83         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
  84         {0x890, 0x00000800}, {0x894, 0xfffffffe},
  85         {0x898, 0x40302010}, {0x900, 0x00000000},
  86         {0x904, 0x00000023}, {0x908, 0x00000000},
  87         {0x90c, 0x81121313}, {0x910, 0x806c0001},
  88         {0x914, 0x00000001}, {0x918, 0x00000000},
  89         {0x91c, 0x00010000}, {0x924, 0x00000001},
  90         {0x928, 0x00000000}, {0x92c, 0x00000000},
  91         {0x930, 0x00000000}, {0x934, 0x00000000},
  92         {0x938, 0x00000000}, {0x93c, 0x00000000},
  93         {0x940, 0x00000000}, {0x944, 0x00000000},
  94         {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
  95         {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
  96         {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
  97         {0xa14, 0x1114d028}, {0xa18, 0x00881117},
  98         {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
  99         {0xa24, 0x090e1317}, {0xa28, 0x00000204},
 100         {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
 101         {0xa74, 0x00000007}, {0xa78, 0x00000900},
 102         {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
 103         {0xb38, 0x00000000}, {0xc00, 0x48071d40},
 104         {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
 105         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 106         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 107         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 108         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 109         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
 110         {0xc34, 0x469652af}, {0xc38, 0x49795994},
 111         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 112         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 113         {0xc4c, 0x007f037f},
 114 #ifdef EXT_PA_8192EU
 115         /* External PA or external LNA */
 116         {0xc50, 0x00340220},
 117 #else
 118         {0xc50, 0x00340020},
 119 #endif
 120         {0xc54, 0x0080801f},
 121 #ifdef EXT_PA_8192EU
 122         /* External PA or external LNA */
 123         {0xc58, 0x00000220},
 124 #else
 125         {0xc58, 0x00000020},
 126 #endif
 127         {0xc5c, 0x00248492}, {0xc60, 0x00000000},
 128         {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
 129         {0xc6c, 0x00000036}, {0xc70, 0x00000600},
 130         {0xc74, 0x02013169}, {0xc78, 0x0000001f},
 131         {0xc7c, 0x00b91612},
 132 #ifdef EXT_PA_8192EU
 133         /* External PA or external LNA */
 134         {0xc80, 0x2d4000b5},
 135 #else
 136         {0xc80, 0x40000100},
 137 #endif
 138         {0xc84, 0x21f60000},
 139 #ifdef EXT_PA_8192EU
 140         /* External PA or external LNA */
 141         {0xc88, 0x2d4000b5},
 142 #else
 143         {0xc88, 0x40000100},
 144 #endif
 145         {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
 146         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 147         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 148         {0xca4, 0x000300a0}, {0xca8, 0x00000000},
 149         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 150         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 151         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 152         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 153         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 154         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 155         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 156         {0xce4, 0x00040000}, {0xce8, 0x77644302},
 157         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 158         {0xd04, 0x00020403}, {0xd08, 0x0000907f},
 159         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 160         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 161         {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
 162         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 163         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 164         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 165         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 166         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 167         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 168         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 169         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 170         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 171         {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
 172         {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
 173         {0xe00, 0x30303030}, {0xe04, 0x30303030},
 174         {0xe08, 0x03903030}, {0xe10, 0x30303030},
 175         {0xe14, 0x30303030}, {0xe18, 0x30303030},
 176         {0xe1c, 0x30303030}, {0xe28, 0x00000000},
 177         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 178         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 179         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 180         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 181         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 182         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 183         {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
 184         {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
 185         {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
 186         {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
 187         {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
 188         {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
 189         {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
 190         {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
 191         {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
 192         {0xee8, 0x00000001}, {0xf14, 0x00000003},
 193         {0xf4c, 0x00000000}, {0xf00, 0x00000300},
 194         {0xffff, 0xffffffff},
 195 };
 196
 197 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
 198         {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
 199         {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
 200         {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
 201         {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
 202         {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
 203         {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
 204         {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
 205         {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
 206         {0xc78, 0xf0100001}, {0xc78, 0xef110001},
 207         {0xc78, 0xee120001}, {0xc78, 0xed130001},
 208         {0xc78, 0xec140001}, {0xc78, 0xeb150001},
 209         {0xc78, 0xea160001}, {0xc78, 0xe9170001},
 210         {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
 211         {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
 212         {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
 213         {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
 214         {0xc78, 0x04200001}, {0xc78, 0x03210001},
 215         {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
 216         {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
 217         {0xc78, 0xa6260001}, {0xc78, 0x85270001},
 218         {0xc78, 0x84280001}, {0xc78, 0x83290001},
 219         {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
 220         {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
 221         {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
 222         {0xc78, 0x65300001}, {0xc78, 0x64310001},
 223         {0xc78, 0x63320001}, {0xc78, 0x62330001},
 224         {0xc78, 0x61340001}, {0xc78, 0x45350001},
 225         {0xc78, 0x44360001}, {0xc78, 0x43370001},
 226         {0xc78, 0x42380001}, {0xc78, 0x41390001},
 227         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 228         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 229         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 230         {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
 231         {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
 232         {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
 233         {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
 234         {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
 235         {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
 236         {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
 237         {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
 238         {0xc78, 0xf0500001}, {0xc78, 0xef510001},
 239         {0xc78, 0xee520001}, {0xc78, 0xed530001},
 240         {0xc78, 0xec540001}, {0xc78, 0xeb550001},
 241         {0xc78, 0xea560001}, {0xc78, 0xe9570001},
 242         {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
 243         {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
 244         {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
 245         {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
 246         {0xc78, 0x8a600001}, {0xc78, 0x89610001},
 247         {0xc78, 0x88620001}, {0xc78, 0x87630001},
 248         {0xc78, 0x86640001}, {0xc78, 0x85650001},
 249         {0xc78, 0x84660001}, {0xc78, 0x83670001},
 250         {0xc78, 0x82680001}, {0xc78, 0x6b690001},
 251         {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
 252         {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
 253         {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
 254         {0xc78, 0x64700001}, {0xc78, 0x63710001},
 255         {0xc78, 0x62720001}, {0xc78, 0x61730001},
 256         {0xc78, 0x49740001}, {0xc78, 0x48750001},
 257         {0xc78, 0x47760001}, {0xc78, 0x46770001},
 258         {0xc78, 0x45780001}, {0xc78, 0x44790001},
 259         {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
 260         {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
 261         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 262         {0xc50, 0x00040022}, {0xc50, 0x00040020},
 263         {0xffff, 0xffffffff}
 264 };
 265
 266 static const struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
 267         {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
 268         {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
 269         {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
 270         {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
 271         {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
 272         {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
 273         {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
 274         {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
 275         {0xc78, 0xea100001}, {0xc78, 0xe9110001},
 276         {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
 277         {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
 278         {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
 279         {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
 280         {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
 281         {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
 282         {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
 283         {0xc78, 0x84200001}, {0xc78, 0x83210001},
 284         {0xc78, 0x82220001}, {0xc78, 0x6a230001},
 285         {0xc78, 0x69240001}, {0xc78, 0x68250001},
 286         {0xc78, 0x67260001}, {0xc78, 0x66270001},
 287         {0xc78, 0x65280001}, {0xc78, 0x64290001},
 288         {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
 289         {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
 290         {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
 291         {0xc78, 0x45300001}, {0xc78, 0x44310001},
 292         {0xc78, 0x43320001}, {0xc78, 0x42330001},
 293         {0xc78, 0x41340001}, {0xc78, 0x40350001},
 294         {0xc78, 0x40360001}, {0xc78, 0x40370001},
 295         {0xc78, 0x40380001}, {0xc78, 0x40390001},
 296         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 297         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 298         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 299         {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
 300         {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
 301         {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
 302         {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
 303         {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
 304         {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
 305         {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
 306         {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
 307         {0xc78, 0xea500001}, {0xc78, 0xe9510001},
 308         {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
 309         {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
 310         {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
 311         {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
 312         {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
 313         {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
 314         {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
 315         {0xc78, 0x84600001}, {0xc78, 0x83610001},
 316         {0xc78, 0x82620001}, {0xc78, 0x6a630001},
 317         {0xc78, 0x69640001}, {0xc78, 0x68650001},
 318         {0xc78, 0x67660001}, {0xc78, 0x66670001},
 319         {0xc78, 0x65680001}, {0xc78, 0x64690001},
 320         {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
 321         {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
 322         {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
 323         {0xc78, 0x45700001}, {0xc78, 0x44710001},
 324         {0xc78, 0x43720001}, {0xc78, 0x42730001},
 325         {0xc78, 0x41740001}, {0xc78, 0x40750001},
 326         {0xc78, 0x40760001}, {0xc78, 0x40770001},
 327         {0xc78, 0x40780001}, {0xc78, 0x40790001},
 328         {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
 329         {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
 330         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 331         {0xc50, 0x00040222}, {0xc50, 0x00040220},
 332         {0xffff, 0xffffffff}
 333 };
 334
 335 static const struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
 336         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 337         {0x00, 0x00030000}, {0x08, 0x00008400},
 338         {0x18, 0x00000407}, {0x19, 0x00000012},
 339         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 340         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 341         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 342         {0x57, 0x000d0000}, {0x58, 0x000be180},
 343         {0x67, 0x00001552}, {0x83, 0x00000000},
 344         {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
 345         {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
 346         {0xb5, 0x00008166}, {0xb6, 0x0000803e},
 347         {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
 348         {0xb9, 0x00080001}, {0xba, 0x00040001},
 349         {0xbb, 0x00000400}, {0xbf, 0x000c0000},
 350         {0xc2, 0x00002400}, {0xc3, 0x00000009},
 351         {0xc4, 0x00040c91}, {0xc5, 0x00099999},
 352         {0xc6, 0x000000a3}, {0xc7, 0x00088820},
 353         {0xc8, 0x00076c06}, {0xc9, 0x00000000},
 354         {0xca, 0x00080000}, {0xdf, 0x00000180},
 355         {0xef, 0x000001a0}, {0x51, 0x00069545},
 356         {0x52, 0x0007e45e}, {0x53, 0x00000071},
 357         {0x56, 0x00051ff3}, {0x35, 0x000000a8},
 358         {0x35, 0x000001e2}, {0x35, 0x000002a8},
 359         {0x36, 0x00001c24}, {0x36, 0x00009c24},
 360         {0x36, 0x00011c24}, {0x36, 0x00019c24},
 361         {0x18, 0x00000c07}, {0x5a, 0x00048000},
 362         {0x19, 0x000739d0},
 363 #ifdef EXT_PA_8192EU
 364         /* External PA or external LNA */
 365         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 366         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 367         {0x34, 0x0000604a}, {0x34, 0x00005047},
 368         {0x34, 0x0000400a}, {0x34, 0x00003007},
 369         {0x34, 0x00002004}, {0x34, 0x00001001},
 370         {0x34, 0x00000000},
 371 #else
 372         /* Regular */
 373         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 374         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 375         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 376         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 377         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 378         {0x34, 0x00000014},
 379 #endif
 380         {0x00, 0x00030159},
 381         {0x84, 0x00068180},
 382         {0x86, 0x0000014e},
 383         {0x87, 0x00048e00},
 384         {0x8e, 0x00065540},
 385         {0x8f, 0x00088000},
 386         {0xef, 0x000020a0},
 387 #ifdef EXT_PA_8192EU
 388         /* External PA or external LNA */
 389         {0x3b, 0x000f07b0},
 390 #else
 391         {0x3b, 0x000f02b0},
 392 #endif
 393         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 394         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 395         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 396         {0x3b, 0x0008f780},
 397 #ifdef EXT_PA_8192EU
 398         /* External PA or external LNA */
 399         {0x3b, 0x000787b0},
 400 #else
 401         {0x3b, 0x00078730},
 402 #endif
 403         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 404         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 405         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 406         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 407         {0xfe, 0x00000000}, {0x18, 0x0000fc07},
 408         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 409         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 410         {0x1e, 0x00000001}, {0x1f, 0x00080000},
 411         {0x00, 0x00033e70},
 412         {0xff, 0xffffffff}
 413 };
 414
 415 static const struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
 416         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 417         {0x00, 0x00030000}, {0x08, 0x00008400},
 418         {0x18, 0x00000407}, {0x19, 0x00000012},
 419         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 420         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 421         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 422         {0x57, 0x000d0000}, {0x58, 0x000be180},
 423         {0x67, 0x00001552}, {0x7f, 0x00000082},
 424         {0x81, 0x0003f000}, {0x83, 0x00000000},
 425         {0xdf, 0x00000180}, {0xef, 0x000001a0},
 426         {0x51, 0x00069545}, {0x52, 0x0007e42e},
 427         {0x53, 0x00000071}, {0x56, 0x00051ff3},
 428         {0x35, 0x000000a8}, {0x35, 0x000001e0},
 429         {0x35, 0x000002a8}, {0x36, 0x00001ca8},
 430         {0x36, 0x00009c24}, {0x36, 0x00011c24},
 431         {0x36, 0x00019c24}, {0x18, 0x00000c07},
 432         {0x5a, 0x00048000}, {0x19, 0x000739d0},
 433 #ifdef EXT_PA_8192EU
 434         /* External PA or external LNA */
 435         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 436         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 437         {0x34, 0x0000604a}, {0x34, 0x00005047},
 438         {0x34, 0x0000400a}, {0x34, 0x00003007},
 439         {0x34, 0x00002004}, {0x34, 0x00001001},
 440         {0x34, 0x00000000},
 441 #else
 442         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 443         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 444         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 445         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 446         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 447         {0x34, 0x00000014},
 448 #endif
 449         {0x00, 0x00030159}, {0x84, 0x00068180},
 450         {0x86, 0x000000ce}, {0x87, 0x00048a00},
 451         {0x8e, 0x00065540}, {0x8f, 0x00088000},
 452         {0xef, 0x000020a0},
 453 #ifdef EXT_PA_8192EU
 454         /* External PA or external LNA */
 455         {0x3b, 0x000f07b0},
 456 #else
 457         {0x3b, 0x000f02b0},
 458 #endif
 459
 460         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 461         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 462         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 463         {0x3b, 0x0008f780},
 464 #ifdef EXT_PA_8192EU
 465         /* External PA or external LNA */
 466         {0x3b, 0x000787b0},
 467 #else
 468         {0x3b, 0x00078730},
 469 #endif
 470         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 471         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 472         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 473         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 474         {0x00, 0x00010159}, {0xfe, 0x00000000},
 475         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 476         {0xfe, 0x00000000}, {0x1e, 0x00000001},
 477         {0x1f, 0x00080000}, {0x00, 0x00033e70},
 478         {0xff, 0xffffffff}
 479 };
 480
 481 static int rtl8192eu_identify_chip(struct rtl8xxxu_priv *priv)
 482 {
 483         struct device *dev = &priv->udev->dev;
 484         u32 val32, bonding, sys_cfg, vendor;
 485         int ret = 0;
 486
 487         sys_cfg = rtl8xxxu_read32(priv, REG_SYS_CFG);
 488         priv->chip_cut = u32_get_bits(sys_cfg, SYS_CFG_CHIP_VERSION_MASK);
 489         if (sys_cfg & SYS_CFG_TRP_VAUX_EN) {
 490                 dev_info(dev, "Unsupported test chip\n");
 491                 ret = -ENOTSUPP;
 492                 goto out;
 493         }
 494
 495         bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
 496         bonding &= HPON_FSM_BONDING_MASK;
 497         if (bonding == HPON_FSM_BONDING_1T2R) {
 498                 strscpy(priv->chip_name, "8191EU", sizeof(priv->chip_name));
 499                 priv->tx_paths = 1;
 500                 priv->rtl_chip = RTL8191E;
 501         } else {
 502                 strscpy(priv->chip_name, "8192EU", sizeof(priv->chip_name));
 503                 priv->tx_paths = 2;
 504                 priv->rtl_chip = RTL8192E;
 505         }
 506         priv->rf_paths = 2;
 507         priv->rx_paths = 2;
 508         priv->has_wifi = 1;
 509
 510         vendor = sys_cfg & SYS_CFG_VENDOR_EXT_MASK;
 511         rtl8xxxu_identify_vendor_2bits(priv, vendor);
 512
 513         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
 514         priv->rom_rev = u32_get_bits(val32, GPIO_RF_RL_ID);
 515
 516         rtl8xxxu_config_endpoints_sie(priv);
 517
 518         /*
 519          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
 520          */
 521         if (!priv->ep_tx_count)
 522                 ret = rtl8xxxu_config_endpoints_no_sie(priv);
 523
 524 out:
 525         return ret;
 526 }
 527
 528 static void
 529 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
 530 {
 531         u32 val32, ofdm, mcs;
 532         u8 cck, ofdmbase, mcsbase;
 533         int group, tx_idx;
 534
 535         tx_idx = 0;
 536         group = rtl8xxxu_gen2_channel_to_group(channel);
 537
 538         cck = priv->cck_tx_power_index_A[group];
 539
 540         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
 541         val32 &= 0xffff00ff;
 542         val32 |= (cck << 8);
 543         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
 544
 545         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 546         val32 &= 0xff;
 547         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 548         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 549
 550         ofdmbase = priv->ht40_1s_tx_power_index_A[group];
 551         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
 552         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
 553
 554         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
 555         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
 556
 557         mcsbase = priv->ht40_1s_tx_power_index_A[group];
 558         if (ht40)
 559                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
 560         else
 561                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
 562         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 563
 564         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
 565         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
 566         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
 567         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
 568
 569         if (priv->tx_paths > 1) {
 570                 cck = priv->cck_tx_power_index_B[group];
 571
 572                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
 573                 val32 &= 0xff;
 574                 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 575                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
 576
 577                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 578                 val32 &= 0xffffff00;
 579                 val32 |= cck;
 580                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 581
 582                 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
 583                 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
 584                 ofdm = ofdmbase | ofdmbase << 8 |
 585                         ofdmbase << 16 | ofdmbase << 24;
 586
 587                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
 588                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
 589
 590                 mcsbase = priv->ht40_1s_tx_power_index_B[group];
 591                 if (ht40)
 592                         mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
 593                 else
 594                         mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
 595                 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 596
 597                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
 598                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
 599                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
 600                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
 601         }
 602 }
 603
 604 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
 605 {
 606         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
 607         int i;
 608
 609         if (efuse->rtl_id != cpu_to_le16(0x8129))
 610                 return -EINVAL;
 611
 612         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 613
 614         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 615                sizeof(efuse->tx_power_index_A.cck_base));
 616         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
 617                sizeof(efuse->tx_power_index_B.cck_base));
 618
 619         memcpy(priv->ht40_1s_tx_power_index_A,
 620                efuse->tx_power_index_A.ht40_base,
 621                sizeof(efuse->tx_power_index_A.ht40_base));
 622         memcpy(priv->ht40_1s_tx_power_index_B,
 623                efuse->tx_power_index_B.ht40_base,
 624                sizeof(efuse->tx_power_index_B.ht40_base));
 625
 626         priv->ht20_tx_power_diff[0].a =
 627                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 628         priv->ht20_tx_power_diff[0].b =
 629                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
 630
 631         priv->ht40_tx_power_diff[0].a = 0;
 632         priv->ht40_tx_power_diff[0].b = 0;
 633
 634         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
 635                 priv->ofdm_tx_power_diff[i].a =
 636                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
 637                 priv->ofdm_tx_power_diff[i].b =
 638                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
 639
 640                 priv->ht20_tx_power_diff[i].a =
 641                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
 642                 priv->ht20_tx_power_diff[i].b =
 643                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
 644
 645                 priv->ht40_tx_power_diff[i].a =
 646                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
 647                 priv->ht40_tx_power_diff[i].b =
 648                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
 649         }
 650
 651         priv->default_crystal_cap = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
 652
 653         return 0;
 654 }
 655
 656 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
 657 {
 658         const char *fw_name;
 659         int ret;
 660
 661         fw_name = "/*(DEBLOBBED)*/";
 662
 663         ret = rtl8xxxu_load_firmware(priv, fw_name);
 664
 665         return ret;
 666 }
 667
 668 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
 669 {
 670         u8 val8;
 671         u16 val16;
 672
 673         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 674         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
 675         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 676
 677         /* 6. 0x1f[7:0] = 0x07 */
 678         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 679         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 680
 681         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 682         val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
 683                   SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
 684         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 685         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 686         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 687         rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
 688
 689         if (priv->hi_pa)
 690                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
 691         else
 692                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
 693 }
 694
 695 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
 696 {
 697         int ret;
 698
 699         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
 700         if (ret)
 701                 goto exit;
 702
 703         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
 704
 705 exit:
 706         return ret;
 707 }
 708
 709 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
 710 {
 711         u32 reg_eac, reg_e94, reg_e9c;
 712         int result = 0;
 713
 714         /*
 715          * TX IQK
 716          * PA/PAD controlled by 0x0
 717          */
 718         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 719         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00180);
 720
 721         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 722         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000);
 723         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 724         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0x07f77);
 725
 726         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 727
 728         /* Path A IQK setting */
 729         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 730         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 731         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 732         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 733
 734         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
 735         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
 736
 737         /* LO calibration setting */
 738         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 739
 740         /* One shot, path A LOK & IQK */
 741         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 742         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 743
 744         mdelay(10);
 745
 746         /* Check failed */
 747         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 748         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 749         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 750
 751         if (!(reg_eac & BIT(28)) &&
 752             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 753             ((reg_e9c & 0x03ff0000) != 0x00420000))
 754                 result |= 0x01;
 755
 756         return result;
 757 }
 758
 759 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
 760 {
 761         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
 762         int result = 0;
 763
 764         /* Leave IQK mode */
 765         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
 766
 767         /* Enable path A PA in TX IQK mode */
 768         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 769         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 770         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 771         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
 772
 773         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 774         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 775         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 776         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);
 777
 778         /* PA/PAD control by 0x56, and set = 0x0 */
 779         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);
 780         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x511e0);
 781
 782         /* Enter IQK mode */
 783         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 784
 785         /* TX IQK setting */
 786         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 787         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 788
 789         /* path-A IQK setting */
 790         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 791         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 792         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 793         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 794
 795         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x8216031f);
 796         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x6816031f);
 797
 798         /* LO calibration setting */
 799         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 800
 801         /* One shot, path A LOK & IQK */
 802         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 803         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 804
 805         mdelay(10);
 806
 807         /* Check failed */
 808         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 809         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 810         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 811
 812         if (!(reg_eac & BIT(28)) &&
 813             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 814             ((reg_e9c & 0x03ff0000) != 0x00420000)) {
 815                 result |= 0x01;
 816         } else {
 817                 /* PA/PAD controlled by 0x0 */
 818                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 819                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
 820                 goto out;
 821         }
 822
 823         val32 = 0x80007c00 |
 824                 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
 825         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 826
 827         /* Modify RX IQK mode table */
 828         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 829
 830         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 831         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 832         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 833         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);
 834
 835         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 836         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 837         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 838         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);
 839
 840         /* PA/PAD control by 0x56, and set = 0x0 */
 841         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x00980);
 842         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_PAD_TXG, 0x510e0);
 843
 844         /* Enter IQK mode */
 845         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 846
 847         /* IQK setting */
 848         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 849
 850         /* Path A IQK setting */
 851         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 852         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
 853         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 854         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 855
 856         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);
 857         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);
 858
 859         /* LO calibration setting */
 860         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
 861
 862         /* One shot, path A LOK & IQK */
 863         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 864         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 865
 866         mdelay(10);
 867
 868         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 869         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
 870
 871         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 872         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_GAIN_CCA, 0x180);
 873
 874         if (!(reg_eac & BIT(27)) &&
 875             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
 876             ((reg_eac & 0x03ff0000) != 0x00360000))
 877                 result |= 0x02;
 878         else
 879                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
 880                          __func__);
 881
 882 out:
 883         return result;
 884 }
 885
 886 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
 887 {
 888         u32 reg_eac, reg_eb4, reg_ebc;
 889         int result = 0;
 890
 891         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 892         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00180);
 893
 894         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 895         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x20000);
 896         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 897         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0x07f77);
 898
 899         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 900
 901         /* Path B IQK setting */
 902         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 903         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 904         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 905         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 906
 907         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140303);
 908         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
 909
 910         /* LO calibration setting */
 911         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 912
 913         /* One shot, path A LOK & IQK */
 914         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 915         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 916
 917         mdelay(1);
 918
 919         /* Check failed */
 920         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 921         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 922         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 923
 924         if (!(reg_eac & BIT(31)) &&
 925             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 926             ((reg_ebc & 0x03ff0000) != 0x00420000))
 927                 result |= 0x01;
 928         else
 929                 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
 930                          __func__);
 931
 932         return result;
 933 }
 934
 935 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
 936 {
 937         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
 938         int result = 0;
 939
 940         /* Leave IQK mode */
 941         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 942
 943         /* Enable path A PA in TX IQK mode */
 944         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 945         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 946         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 947         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf1173);
 948
 949         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 950         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 951         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 952         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf1173);
 953
 954         /* PA/PAD control by 0x56, and set = 0x0 */
 955         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);
 956         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x511e0);
 957
 958         /* Enter IQK mode */
 959         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 960
 961         /* TX IQK setting */
 962         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 963         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 964
 965         /* path-A IQK setting */
 966         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 967         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 968         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 969         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 970
 971         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x8216031f);
 972         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x6816031f);
 973
 974         /* LO calibration setting */
 975         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 976
 977         /* One shot, path A LOK & IQK */
 978         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 979         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 980
 981         mdelay(10);
 982
 983         /* Check failed */
 984         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 985         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 986         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 987
 988         if (!(reg_eac & BIT(31)) &&
 989             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 990             ((reg_ebc & 0x03ff0000) != 0x00420000)) {
 991                 result |= 0x01;
 992         } else {
 993                 /*
 994                  * PA/PAD controlled by 0x0
 995                  * Vendor driver restores RF_A here which I believe is a bug
 996                  */
 997                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 998                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);
 999                 goto out;
1000         }
1001
1002         val32 = 0x80007c00 |
1003                 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
1004         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
1005
1006         /* Modify RX IQK mode table */
1007         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1008
1009         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
1010         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
1011         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
1012         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ff2);
1013
1014         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
1015         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
1016         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
1017         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ff2);
1018
1019         /* PA/PAD control by 0x56, and set = 0x0 */
1020         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x00980);
1021         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_PAD_TXG, 0x510e0);
1022
1023         /* Enter IQK mode */
1024         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1025
1026         /* IQK setting */
1027         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1028
1029         /* Path A IQK setting */
1030         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
1031         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1032         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
1033         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
1034
1035         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821608ff);
1036         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x281608ff);
1037
1038         /* LO calibration setting */
1039         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
1040
1041         /* One shot, path A LOK & IQK */
1042         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
1043         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1044
1045         mdelay(10);
1046
1047         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1048         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
1049         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
1050
1051         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1052         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_GAIN_CCA, 0x180);
1053
1054         if (!(reg_eac & BIT(30)) &&
1055             ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
1056             ((reg_ecc & 0x03ff0000) != 0x00360000))
1057                 result |= 0x02;
1058         else
1059                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
1060                          __func__);
1061
1062 out:
1063         return result;
1064 }
1065
1066 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1067                                       int result[][8], int t)
1068 {
1069         struct device *dev = &priv->udev->dev;
1070         u32 i, val32;
1071         int path_a_ok, path_b_ok;
1072         int retry = 2;
1073         static const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1074                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1075                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1076                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1077                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1078                 REG_TX_TO_TX, REG_RX_CCK,
1079                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1080                 REG_RX_TO_RX, REG_STANDBY,
1081                 REG_SLEEP, REG_PMPD_ANAEN
1082         };
1083         static const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1084                 REG_TXPAUSE, REG_BEACON_CTRL,
1085                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1086         };
1087         static const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1088                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1089                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1090                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1091                 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1092         };
1093         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
1094         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
1095
1096         /*
1097          * Note: IQ calibration must be performed after loading
1098          *       PHY_REG.txt , and radio_a, radio_b.txt
1099          */
1100
1101         if (t == 0) {
1102                 /* Save ADDA parameters, turn Path A ADDA on */
1103                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1104                                    RTL8XXXU_ADDA_REGS);
1105                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1106                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
1107                                    priv->bb_backup, RTL8XXXU_BB_REGS);
1108         }
1109
1110         rtl8xxxu_path_adda_on(priv, adda_regs, true);
1111
1112         /* MAC settings */
1113         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
1114
1115         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1116         val32 |= 0x0f000000;
1117         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1118
1119         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
1120         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1121         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
1122
1123         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
1124         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
1125         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
1126
1127         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
1128         val32 |= BIT(10);
1129         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
1130         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
1131         val32 |= BIT(10);
1132         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
1133
1134         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1135         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1136         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1137
1138         for (i = 0; i < retry; i++) {
1139                 path_a_ok = rtl8192eu_iqk_path_a(priv);
1140                 if (path_a_ok == 0x01) {
1141                         val32 = rtl8xxxu_read32(priv,
1142                                                 REG_TX_POWER_BEFORE_IQK_A);
1143                         result[t][0] = (val32 >> 16) & 0x3ff;
1144                         val32 = rtl8xxxu_read32(priv,
1145                                                 REG_TX_POWER_AFTER_IQK_A);
1146                         result[t][1] = (val32 >> 16) & 0x3ff;
1147
1148                         break;
1149                 }
1150         }
1151
1152         if (!path_a_ok)
1153                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1154
1155         for (i = 0; i < retry; i++) {
1156                 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
1157                 if (path_a_ok == 0x03) {
1158                         val32 = rtl8xxxu_read32(priv,
1159                                                 REG_RX_POWER_BEFORE_IQK_A_2);
1160                         result[t][2] = (val32 >> 16) & 0x3ff;
1161                         val32 = rtl8xxxu_read32(priv,
1162                                                 REG_RX_POWER_AFTER_IQK_A_2);
1163                         result[t][3] = (val32 >> 16) & 0x3ff;
1164
1165                         break;
1166                 }
1167         }
1168
1169         if (!path_a_ok)
1170                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1171
1172         if (priv->rf_paths > 1) {
1173                 /* Path A into standby */
1174                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1175                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1176                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1177
1178                 /* Turn Path B ADDA on */
1179                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1180
1181                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1182                 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1183                 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1184
1185                 for (i = 0; i < retry; i++) {
1186                         path_b_ok = rtl8192eu_iqk_path_b(priv);
1187                         if (path_b_ok == 0x01) {
1188                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1189                                 result[t][4] = (val32 >> 16) & 0x3ff;
1190                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1191                                 result[t][5] = (val32 >> 16) & 0x3ff;
1192                                 break;
1193                         }
1194                 }
1195
1196                 if (!path_b_ok)
1197                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1198
1199                 for (i = 0; i < retry; i++) {
1200                         path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
1201                         if (path_b_ok == 0x03) {
1202                                 val32 = rtl8xxxu_read32(priv,
1203                                                         REG_RX_POWER_BEFORE_IQK_B_2);
1204                                 result[t][6] = (val32 >> 16) & 0x3ff;
1205                                 val32 = rtl8xxxu_read32(priv,
1206                                                         REG_RX_POWER_AFTER_IQK_B_2);
1207                                 result[t][7] = (val32 >> 16) & 0x3ff;
1208                                 break;
1209                         }
1210                 }
1211
1212                 if (!path_b_ok)
1213                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1214         }
1215
1216         /* Back to BB mode, load original value */
1217         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1218
1219         if (t) {
1220                 /* Reload ADDA power saving parameters */
1221                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1222                                       RTL8XXXU_ADDA_REGS);
1223
1224                 /* Reload MAC parameters */
1225                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1226
1227                 /* Reload BB parameters */
1228                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1229                                       priv->bb_backup, RTL8XXXU_BB_REGS);
1230
1231                 /* Restore RX initial gain */
1232                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1233                 val32 &= 0xffffff00;
1234                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1235                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1236
1237                 if (priv->rf_paths > 1) {
1238                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1239                         val32 &= 0xffffff00;
1240                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1241                                          val32 | 0x50);
1242                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1243                                          val32 | xb_agc);
1244                 }
1245
1246                 /* Load 0xe30 IQC default value */
1247                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1248                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1249         }
1250 }
1251
1252 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1253 {
1254         struct device *dev = &priv->udev->dev;
1255         int result[4][8];       /* last is final result */
1256         int i, candidate;
1257         bool path_a_ok, path_b_ok;
1258         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1259         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1260         bool simu;
1261
1262         memset(result, 0, sizeof(result));
1263         candidate = -1;
1264
1265         path_a_ok = false;
1266         path_b_ok = false;
1267
1268         for (i = 0; i < 3; i++) {
1269                 rtl8192eu_phy_iqcalibrate(priv, result, i);
1270
1271                 if (i == 1) {
1272                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1273                                                                 result, 0, 1);
1274                         if (simu) {
1275                                 candidate = 0;
1276                                 break;
1277                         }
1278                 }
1279
1280                 if (i == 2) {
1281                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1282                                                                 result, 0, 2);
1283                         if (simu) {
1284                                 candidate = 0;
1285                                 break;
1286                         }
1287
1288                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1289                                                                 result, 1, 2);
1290                         if (simu)
1291                                 candidate = 1;
1292                         else
1293                                 candidate = 3;
1294                 }
1295         }
1296
1297         for (i = 0; i < 4; i++) {
1298                 reg_e94 = result[i][0];
1299                 reg_e9c = result[i][1];
1300                 reg_ea4 = result[i][2];
1301                 reg_eb4 = result[i][4];
1302                 reg_ebc = result[i][5];
1303                 reg_ec4 = result[i][6];
1304         }
1305
1306         if (candidate >= 0) {
1307                 reg_e94 = result[candidate][0];
1308                 priv->rege94 =  reg_e94;
1309                 reg_e9c = result[candidate][1];
1310                 priv->rege9c = reg_e9c;
1311                 reg_ea4 = result[candidate][2];
1312                 reg_eac = result[candidate][3];
1313                 reg_eb4 = result[candidate][4];
1314                 priv->regeb4 = reg_eb4;
1315                 reg_ebc = result[candidate][5];
1316                 priv->regebc = reg_ebc;
1317                 reg_ec4 = result[candidate][6];
1318                 reg_ecc = result[candidate][7];
1319                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1320                 dev_dbg(dev,
1321                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1322                         __func__, reg_e94, reg_e9c,
1323                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1324                 path_a_ok = true;
1325                 path_b_ok = true;
1326         } else {
1327                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1328                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1329         }
1330
1331         if (reg_e94 && candidate >= 0)
1332                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1333                                            candidate, (reg_ea4 == 0));
1334
1335         if (priv->rf_paths > 1)
1336                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1337                                            candidate, (reg_ec4 == 0));
1338
1339         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1340                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1341 }
1342
1343 /*
1344  * This is needed for 8723bu as well, presumable
1345  */
1346 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
1347 {
1348         u8 val8;
1349         u32 val32;
1350
1351         /*
1352          * 40Mhz crystal source, MAC 0x28[2]=0
1353          */
1354         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1355         val8 &= 0xfb;
1356         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1357
1358         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1359         val32 &= 0xfffffc7f;
1360         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1361
1362         /*
1363          * 92e AFE parameter
1364          * AFE PLL KVCO selection, MAC 0x28[6]=1
1365          */
1366         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1367         val8 &= 0xbf;
1368         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1369
1370         /*
1371          * AFE PLL KVCO selection, MAC 0x78[21]=0
1372          */
1373         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1374         val32 &= 0xffdfffff;
1375         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1376 }
1377
1378 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
1379 {
1380         u8 val8;
1381
1382         /* Clear suspend enable and power down enable*/
1383         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1384         val8 &= ~(BIT(3) | BIT(4));
1385         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1386 }
1387
1388 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
1389 {
1390         u8 val8;
1391         u32 val32;
1392         int count, ret = 0;
1393
1394         /* disable HWPDN 0x04[15]=0*/
1395         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1396         val8 &= ~BIT(7);
1397         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1398
1399         /* disable SW LPS 0x04[10]= 0 */
1400         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1401         val8 &= ~BIT(2);
1402         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1403
1404         /* disable WL suspend*/
1405         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1406         val8 &= ~(BIT(3) | BIT(4));
1407         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1408
1409         /* wait till 0x04[17] = 1 power ready*/
1410         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1411                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1412                 if (val32 & BIT(17))
1413                         break;
1414
1415                 udelay(10);
1416         }
1417
1418         if (!count) {
1419                 ret = -EBUSY;
1420                 goto exit;
1421         }
1422
1423         /* We should be able to optimize the following three entries into one */
1424
1425         /* release WLON reset 0x04[16]= 1*/
1426         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1427         val8 |= BIT(0);
1428         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1429
1430         /* set, then poll until 0 */
1431         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1432         val32 |= APS_FSMCO_MAC_ENABLE;
1433         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1434
1435         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1436                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1437                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1438                         ret = 0;
1439                         break;
1440                 }
1441                 udelay(10);
1442         }
1443
1444         if (!count) {
1445                 ret = -EBUSY;
1446                 goto exit;
1447         }
1448
1449 exit:
1450         return ret;
1451 }
1452
1453 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
1454 {
1455         struct device *dev = &priv->udev->dev;
1456         u8 val8;
1457         u16 val16;
1458         u32 val32;
1459         int retry, retval;
1460
1461         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1462
1463         retry = 100;
1464         retval = -EBUSY;
1465         /*
1466          * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
1467          */
1468         do {
1469                 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1470                 if (!val32) {
1471                         retval = 0;
1472                         break;
1473                 }
1474         } while (retry--);
1475
1476         if (!retry) {
1477                 dev_warn(dev, "Failed to flush TX queue\n");
1478                 retval = -EBUSY;
1479                 goto out;
1480         }
1481
1482         /* Disable CCK and OFDM, clock gated */
1483         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1484         val8 &= ~SYS_FUNC_BBRSTB;
1485         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1486
1487         udelay(2);
1488
1489         /* Reset whole BB */
1490         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1491         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1492         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1493
1494         /* Reset MAC TRX */
1495         val16 = rtl8xxxu_read16(priv, REG_CR);
1496         val16 &= 0xff00;
1497         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
1498         rtl8xxxu_write16(priv, REG_CR, val16);
1499
1500         val16 = rtl8xxxu_read16(priv, REG_CR);
1501         val16 &= ~CR_SECURITY_ENABLE;
1502         rtl8xxxu_write16(priv, REG_CR, val16);
1503
1504         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1505         val8 |= DUAL_TSF_TX_OK;
1506         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1507
1508 out:
1509         return retval;
1510 }
1511
1512 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
1513 {
1514         u8 val8;
1515         int count, ret = 0;
1516
1517         /* Turn off RF */
1518         val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1519         val8 &= ~RF_ENABLE;
1520         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1521
1522         /* Switch DPDT_SEL_P output from register 0x65[2] */
1523         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1524         val8 &= ~LEDCFG2_DPDT_SELECT;
1525         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1526
1527         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1528         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1529         val8 |= BIT(1);
1530         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1531
1532         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1533                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1534                 if ((val8 & BIT(1)) == 0)
1535                         break;
1536                 udelay(10);
1537         }
1538
1539         if (!count) {
1540                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1541                          __func__);
1542                 ret = -EBUSY;
1543                 goto exit;
1544         }
1545
1546 exit:
1547         return ret;
1548 }
1549
1550 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1551 {
1552         u8 val8;
1553
1554         /* 0x04[12:11] = 01 enable WL suspend */
1555         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1556         val8 &= ~(BIT(3) | BIT(4));
1557         val8 |= BIT(3);
1558         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1559
1560         return 0;
1561 }
1562
1563 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
1564 {
1565         u16 val16;
1566         u32 val32;
1567         int ret;
1568
1569         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1570         if (val32 & SYS_CFG_SPS_LDO_SEL) {
1571                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
1572         } else {
1573                 /*
1574                  * Raise 1.2V voltage
1575                  */
1576                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
1577                 val32 &= 0xff0fffff;
1578                 val32 |= 0x00500000;
1579                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
1580                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
1581         }
1582
1583         /*
1584          * Adjust AFE before enabling PLL
1585          */
1586         rtl8192e_crystal_afe_adjust(priv);
1587         rtl8192e_disabled_to_emu(priv);
1588
1589         ret = rtl8192e_emu_to_active(priv);
1590         if (ret)
1591                 goto exit;
1592
1593         rtl8xxxu_write16(priv, REG_CR, 0x0000);
1594
1595         /*
1596          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1597          * Set CR bit10 to enable 32k calibration.
1598          */
1599         val16 = rtl8xxxu_read16(priv, REG_CR);
1600         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1601                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1602                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1603                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1604                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1605         rtl8xxxu_write16(priv, REG_CR, val16);
1606
1607 exit:
1608         return ret;
1609 }
1610
1611 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
1612 {
1613         u8 val8;
1614         u16 val16;
1615
1616         rtl8xxxu_flush_fifo(priv);
1617
1618         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1619         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1620         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1621
1622         /* Turn off RF */
1623         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
1624
1625         rtl8192eu_active_to_lps(priv);
1626
1627         /* Reset Firmware if running in RAM */
1628         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1629                 rtl8xxxu_firmware_self_reset(priv);
1630
1631         /* Reset MCU */
1632         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1633         val16 &= ~SYS_FUNC_CPU_ENABLE;
1634         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1635
1636         /* Reset MCU ready status */
1637         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1638
1639         rtl8xxxu_reset_8051(priv);
1640
1641         rtl8192eu_active_to_emu(priv);
1642         rtl8192eu_emu_to_disabled(priv);
1643 }
1644
1645 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
1646 {
1647         u32 val32;
1648         u8 val8;
1649
1650         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1651         val32 |= (BIT(22) | BIT(23));
1652         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1653
1654         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1655         val8 |= BIT(5);
1656         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1657
1658         /*
1659          * WLAN action by PTA
1660          */
1661         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1662
1663         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1664         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1665         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1666
1667         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1668         val32 |= (BIT(0) | BIT(1));
1669         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1670
1671         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1672
1673         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1674         val32 &= ~BIT(24);
1675         val32 |= BIT(23);
1676         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1677
1678         /*
1679          * Fix external switch Main->S1, Aux->S0
1680          */
1681         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1682         val8 &= ~BIT(0);
1683         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1684
1685         /*
1686          * Fix transmission failure of rtl8192e.
1687          */
1688         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1689 }
1690
1691 static s8 rtl8192e_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats)
1692 {
1693         static const s8 lna_gain_table_0[8] = {15, 9, -10, -21, -23, -27, -43, -44};
1694         static const s8 lna_gain_table_1[8] = {24, 18, 13, -4, -11, -18, -31, -36};
1695
1696         u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
1697         s8 rx_pwr_all = 0x00;
1698         u8 vga_idx, lna_idx;
1699         s8 lna_gain = 0;
1700
1701         lna_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_LNA_IDX_MASK);
1702         vga_idx = u8_get_bits(cck_agc_rpt, CCK_AGC_RPT_VGA_IDX_MASK);
1703
1704         if (priv->cck_agc_report_type == 0)
1705                 lna_gain = lna_gain_table_0[lna_idx];
1706         else
1707                 lna_gain = lna_gain_table_1[lna_idx];
1708
1709         rx_pwr_all = lna_gain - (2 * vga_idx);
1710
1711         return rx_pwr_all;
1712 }
1713
1714 static int rtl8192eu_led_brightness_set(struct led_classdev *led_cdev,
1715                                         enum led_brightness brightness)
1716 {
1717         struct rtl8xxxu_priv *priv = container_of(led_cdev,
1718                                                   struct rtl8xxxu_priv,
1719                                                   led_cdev);
1720         u8 ledcfg = rtl8xxxu_read8(priv, REG_LEDCFG1);
1721
1722         if (brightness == LED_OFF) {
1723                 ledcfg &= ~LEDCFG1_HW_LED_CONTROL;
1724                 ledcfg |= LEDCFG1_LED_DISABLE;
1725         } else if (brightness == LED_ON) {
1726                 ledcfg &= ~(LEDCFG1_HW_LED_CONTROL | LEDCFG1_LED_DISABLE);
1727         } else if (brightness == RTL8XXXU_HW_LED_CONTROL) {
1728                 ledcfg &= ~LEDCFG1_LED_DISABLE;
1729                 ledcfg |= LEDCFG1_HW_LED_CONTROL;
1730         }
1731
1732         rtl8xxxu_write8(priv, REG_LEDCFG1, ledcfg);
1733
1734         return 0;
1735 }
1736
1737 struct rtl8xxxu_fileops rtl8192eu_fops = {
1738         .identify_chip = rtl8192eu_identify_chip,
1739         .parse_efuse = rtl8192eu_parse_efuse,
1740         .load_firmware = rtl8192eu_load_firmware,
1741         .power_on = rtl8192eu_power_on,
1742         .power_off = rtl8192eu_power_off,
1743         .read_efuse = rtl8xxxu_read_efuse,
1744         .reset_8051 = rtl8xxxu_reset_8051,
1745         .llt_init = rtl8xxxu_auto_llt_table,
1746         .init_phy_bb = rtl8192eu_init_phy_bb,
1747         .init_phy_rf = rtl8192eu_init_phy_rf,
1748         .phy_lc_calibrate = rtl8723a_phy_lc_calibrate,
1749         .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
1750         .config_channel = rtl8xxxu_gen2_config_channel,
1751         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1752         .parse_phystats = rtl8723au_rx_parse_phystats,
1753         .enable_rf = rtl8192e_enable_rf,
1754         .disable_rf = rtl8xxxu_gen2_disable_rf,
1755         .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1756         .set_tx_power = rtl8192e_set_tx_power,
1757         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1758         .report_connect = rtl8xxxu_gen2_report_connect,
1759         .report_rssi = rtl8xxxu_gen2_report_rssi,
1760         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1761         .set_crystal_cap = rtl8723a_set_crystal_cap,
1762         .cck_rssi = rtl8192e_cck_rssi,
1763         .led_classdev_brightness_set = rtl8192eu_led_brightness_set,
1764         .writeN_block_size = 128,
1765         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1766         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1767         .has_s0s1 = 0,
1768         .gen2_thermal_meter = 1,
1769         .needs_full_init = 1,
1770         .supports_ap = 1,
1771         .max_macid_num = 128,
1772         .adda_1t_init = 0x0fc01616,
1773         .adda_1t_path_on = 0x0fc01616,
1774         .adda_2t_path_on_a = 0x0fc01616,
1775         .adda_2t_path_on_b = 0x0fc01616,
1776         .trxff_boundary = 0x3cff,
1777         .mactable = rtl8192e_mac_init_table,
1778         .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
1779         .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
1780         .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
1781         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
1782 };