drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu_8192e.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver - 8192e specific subdriver
   3  *
   4  * Copyright (c) 2014 - 2017 Jes Sorensen <Jes.Sorensen@gmail.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = {
  44         {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7},
  45         {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00},
  46         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
  47         {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05},
  48         {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01},
  49         {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00},
  50         {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f},
  51         {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00},
  52         {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f},
  53         {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66},
  54         {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff},
  55         {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f},
  56         {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e},
  57         {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e},
  58         {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00},
  59         {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a},
  60         {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10},
  61         {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff},
  62         {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff},
  63         {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff},
  64         {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50},
  65         {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e},
  66         {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8},
  67         {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65},
  68         {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65},
  69         {0x70b, 0x87},
  70         {0xffff, 0xff},
  71 };
  72
  73 static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = {
  74         {0x800, 0x80040000}, {0x804, 0x00000003},
  75         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
  76         {0x810, 0x10001331}, {0x814, 0x020c3d10},
  77         {0x818, 0x02220385}, {0x81c, 0x00000000},
  78         {0x820, 0x01000100}, {0x824, 0x00390204},
  79         {0x828, 0x01000100}, {0x82c, 0x00390204},
  80         {0x830, 0x32323232}, {0x834, 0x30303030},
  81         {0x838, 0x30303030}, {0x83c, 0x30303030},
  82         {0x840, 0x00010000}, {0x844, 0x00010000},
  83         {0x848, 0x28282828}, {0x84c, 0x28282828},
  84         {0x850, 0x00000000}, {0x854, 0x00000000},
  85         {0x858, 0x009a009a}, {0x85c, 0x01000014},
  86         {0x860, 0x66f60000}, {0x864, 0x061f0000},
  87         {0x868, 0x30303030}, {0x86c, 0x30303030},
  88         {0x870, 0x00000000}, {0x874, 0x55004200},
  89         {0x878, 0x08080808}, {0x87c, 0x00000000},
  90         {0x880, 0xb0000c1c}, {0x884, 0x00000001},
  91         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
  92         {0x890, 0x00000800}, {0x894, 0xfffffffe},
  93         {0x898, 0x40302010}, {0x900, 0x00000000},
  94         {0x904, 0x00000023}, {0x908, 0x00000000},
  95         {0x90c, 0x81121313}, {0x910, 0x806c0001},
  96         {0x914, 0x00000001}, {0x918, 0x00000000},
  97         {0x91c, 0x00010000}, {0x924, 0x00000001},
  98         {0x928, 0x00000000}, {0x92c, 0x00000000},
  99         {0x930, 0x00000000}, {0x934, 0x00000000},
 100         {0x938, 0x00000000}, {0x93c, 0x00000000},
 101         {0x940, 0x00000000}, {0x944, 0x00000000},
 102         {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8},
 103         {0xa04, 0x81ff000c}, {0xa08, 0x8c838300},
 104         {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78},
 105         {0xa14, 0x1114d028}, {0xa18, 0x00881117},
 106         {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000},
 107         {0xa24, 0x090e1317}, {0xa28, 0x00000204},
 108         {0xa2c, 0x00d30000}, {0xa70, 0x101fff00},
 109         {0xa74, 0x00000007}, {0xa78, 0x00000900},
 110         {0xa7c, 0x225b0606}, {0xa80, 0x218075b1},
 111         {0xb38, 0x00000000}, {0xc00, 0x48071d40},
 112         {0xc04, 0x03a05633}, {0xc08, 0x000000e4},
 113         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 114         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 115         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 116         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 117         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47},
 118         {0xc34, 0x469652af}, {0xc38, 0x49795994},
 119         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 120         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 121         {0xc4c, 0x007f037f},
 122 #ifdef EXT_PA_8192EU
 123         /* External PA or external LNA */
 124         {0xc50, 0x00340220},
 125 #else
 126         {0xc50, 0x00340020},
 127 #endif
 128         {0xc54, 0x0080801f},
 129 #ifdef EXT_PA_8192EU
 130         /* External PA or external LNA */
 131         {0xc58, 0x00000220},
 132 #else
 133         {0xc58, 0x00000020},
 134 #endif
 135         {0xc5c, 0x00248492}, {0xc60, 0x00000000},
 136         {0xc64, 0x7112848b}, {0xc68, 0x47c00bff},
 137         {0xc6c, 0x00000036}, {0xc70, 0x00000600},
 138         {0xc74, 0x02013169}, {0xc78, 0x0000001f},
 139         {0xc7c, 0x00b91612},
 140 #ifdef EXT_PA_8192EU
 141         /* External PA or external LNA */
 142         {0xc80, 0x2d4000b5},
 143 #else
 144         {0xc80, 0x40000100},
 145 #endif
 146         {0xc84, 0x21f60000},
 147 #ifdef EXT_PA_8192EU
 148         /* External PA or external LNA */
 149         {0xc88, 0x2d4000b5},
 150 #else
 151         {0xc88, 0x40000100},
 152 #endif
 153         {0xc8c, 0xa0e40000}, {0xc90, 0x00121820},
 154         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 155         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 156         {0xca4, 0x000300a0}, {0xca8, 0x00000000},
 157         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 158         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 159         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 160         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 161         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 162         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 163         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 164         {0xce4, 0x00040000}, {0xce8, 0x77644302},
 165         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 166         {0xd04, 0x00020403}, {0xd08, 0x0000907f},
 167         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 168         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 169         {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975},
 170         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 171         {0xd38, 0x00000000}, {0xd3c, 0x00127353},
 172         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 173         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 174         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 175         {0xd58, 0x00000282}, {0xd5c, 0x30032064},
 176         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 177         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 178         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 179         {0xd78, 0x000e3c24}, {0xd80, 0x01081008},
 180         {0xd84, 0x00000800}, {0xd88, 0xf0b50000},
 181         {0xe00, 0x30303030}, {0xe04, 0x30303030},
 182         {0xe08, 0x03903030}, {0xe10, 0x30303030},
 183         {0xe14, 0x30303030}, {0xe18, 0x30303030},
 184         {0xe1c, 0x30303030}, {0xe28, 0x00000000},
 185         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 186         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 187         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 188         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 189         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 190         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 191         {0xe60, 0x00000008}, {0xe68, 0x0fc05656},
 192         {0xe6c, 0x03c09696}, {0xe70, 0x03c09696},
 193         {0xe74, 0x0c005656}, {0xe78, 0x0c005656},
 194         {0xe7c, 0x0c005656}, {0xe80, 0x0c005656},
 195         {0xe84, 0x03c09696}, {0xe88, 0x0c005656},
 196         {0xe8c, 0x03c09696}, {0xed0, 0x03c09696},
 197         {0xed4, 0x03c09696}, {0xed8, 0x03c09696},
 198         {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6},
 199         {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c},
 200         {0xee8, 0x00000001}, {0xf14, 0x00000003},
 201         {0xf4c, 0x00000000}, {0xf00, 0x00000300},
 202         {0xffff, 0xffffffff},
 203 };
 204
 205 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = {
 206         {0xc78, 0xfb000001}, {0xc78, 0xfb010001},
 207         {0xc78, 0xfb020001}, {0xc78, 0xfb030001},
 208         {0xc78, 0xfb040001}, {0xc78, 0xfb050001},
 209         {0xc78, 0xfa060001}, {0xc78, 0xf9070001},
 210         {0xc78, 0xf8080001}, {0xc78, 0xf7090001},
 211         {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001},
 212         {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001},
 213         {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001},
 214         {0xc78, 0xf0100001}, {0xc78, 0xef110001},
 215         {0xc78, 0xee120001}, {0xc78, 0xed130001},
 216         {0xc78, 0xec140001}, {0xc78, 0xeb150001},
 217         {0xc78, 0xea160001}, {0xc78, 0xe9170001},
 218         {0xc78, 0xe8180001}, {0xc78, 0xe7190001},
 219         {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001},
 220         {0xc78, 0xc61c0001}, {0xc78, 0x071d0001},
 221         {0xc78, 0x061e0001}, {0xc78, 0x051f0001},
 222         {0xc78, 0x04200001}, {0xc78, 0x03210001},
 223         {0xc78, 0xaa220001}, {0xc78, 0xa9230001},
 224         {0xc78, 0xa8240001}, {0xc78, 0xa7250001},
 225         {0xc78, 0xa6260001}, {0xc78, 0x85270001},
 226         {0xc78, 0x84280001}, {0xc78, 0x83290001},
 227         {0xc78, 0x252a0001}, {0xc78, 0x242b0001},
 228         {0xc78, 0x232c0001}, {0xc78, 0x222d0001},
 229         {0xc78, 0x672e0001}, {0xc78, 0x662f0001},
 230         {0xc78, 0x65300001}, {0xc78, 0x64310001},
 231         {0xc78, 0x63320001}, {0xc78, 0x62330001},
 232         {0xc78, 0x61340001}, {0xc78, 0x45350001},
 233         {0xc78, 0x44360001}, {0xc78, 0x43370001},
 234         {0xc78, 0x42380001}, {0xc78, 0x41390001},
 235         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 236         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 237         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 238         {0xc78, 0xfb400001}, {0xc78, 0xfb410001},
 239         {0xc78, 0xfb420001}, {0xc78, 0xfb430001},
 240         {0xc78, 0xfb440001}, {0xc78, 0xfb450001},
 241         {0xc78, 0xfa460001}, {0xc78, 0xf9470001},
 242         {0xc78, 0xf8480001}, {0xc78, 0xf7490001},
 243         {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001},
 244         {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001},
 245         {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001},
 246         {0xc78, 0xf0500001}, {0xc78, 0xef510001},
 247         {0xc78, 0xee520001}, {0xc78, 0xed530001},
 248         {0xc78, 0xec540001}, {0xc78, 0xeb550001},
 249         {0xc78, 0xea560001}, {0xc78, 0xe9570001},
 250         {0xc78, 0xe8580001}, {0xc78, 0xe7590001},
 251         {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001},
 252         {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001},
 253         {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001},
 254         {0xc78, 0x8a600001}, {0xc78, 0x89610001},
 255         {0xc78, 0x88620001}, {0xc78, 0x87630001},
 256         {0xc78, 0x86640001}, {0xc78, 0x85650001},
 257         {0xc78, 0x84660001}, {0xc78, 0x83670001},
 258         {0xc78, 0x82680001}, {0xc78, 0x6b690001},
 259         {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001},
 260         {0xc78, 0x686c0001}, {0xc78, 0x676d0001},
 261         {0xc78, 0x666e0001}, {0xc78, 0x656f0001},
 262         {0xc78, 0x64700001}, {0xc78, 0x63710001},
 263         {0xc78, 0x62720001}, {0xc78, 0x61730001},
 264         {0xc78, 0x49740001}, {0xc78, 0x48750001},
 265         {0xc78, 0x47760001}, {0xc78, 0x46770001},
 266         {0xc78, 0x45780001}, {0xc78, 0x44790001},
 267         {0xc78, 0x437a0001}, {0xc78, 0x427b0001},
 268         {0xc78, 0x417c0001}, {0xc78, 0x407d0001},
 269         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 270         {0xc50, 0x00040022}, {0xc50, 0x00040020},
 271         {0xffff, 0xffffffff}
 272 };
 273
 274 static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = {
 275         {0xc78, 0xfa000001}, {0xc78, 0xf9010001},
 276         {0xc78, 0xf8020001}, {0xc78, 0xf7030001},
 277         {0xc78, 0xf6040001}, {0xc78, 0xf5050001},
 278         {0xc78, 0xf4060001}, {0xc78, 0xf3070001},
 279         {0xc78, 0xf2080001}, {0xc78, 0xf1090001},
 280         {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001},
 281         {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001},
 282         {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001},
 283         {0xc78, 0xea100001}, {0xc78, 0xe9110001},
 284         {0xc78, 0xe8120001}, {0xc78, 0xe7130001},
 285         {0xc78, 0xe6140001}, {0xc78, 0xe5150001},
 286         {0xc78, 0xe4160001}, {0xc78, 0xe3170001},
 287         {0xc78, 0xe2180001}, {0xc78, 0xe1190001},
 288         {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001},
 289         {0xc78, 0x881c0001}, {0xc78, 0x871d0001},
 290         {0xc78, 0x861e0001}, {0xc78, 0x851f0001},
 291         {0xc78, 0x84200001}, {0xc78, 0x83210001},
 292         {0xc78, 0x82220001}, {0xc78, 0x6a230001},
 293         {0xc78, 0x69240001}, {0xc78, 0x68250001},
 294         {0xc78, 0x67260001}, {0xc78, 0x66270001},
 295         {0xc78, 0x65280001}, {0xc78, 0x64290001},
 296         {0xc78, 0x632a0001}, {0xc78, 0x622b0001},
 297         {0xc78, 0x612c0001}, {0xc78, 0x602d0001},
 298         {0xc78, 0x472e0001}, {0xc78, 0x462f0001},
 299         {0xc78, 0x45300001}, {0xc78, 0x44310001},
 300         {0xc78, 0x43320001}, {0xc78, 0x42330001},
 301         {0xc78, 0x41340001}, {0xc78, 0x40350001},
 302         {0xc78, 0x40360001}, {0xc78, 0x40370001},
 303         {0xc78, 0x40380001}, {0xc78, 0x40390001},
 304         {0xc78, 0x403a0001}, {0xc78, 0x403b0001},
 305         {0xc78, 0x403c0001}, {0xc78, 0x403d0001},
 306         {0xc78, 0x403e0001}, {0xc78, 0x403f0001},
 307         {0xc78, 0xfa400001}, {0xc78, 0xf9410001},
 308         {0xc78, 0xf8420001}, {0xc78, 0xf7430001},
 309         {0xc78, 0xf6440001}, {0xc78, 0xf5450001},
 310         {0xc78, 0xf4460001}, {0xc78, 0xf3470001},
 311         {0xc78, 0xf2480001}, {0xc78, 0xf1490001},
 312         {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001},
 313         {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001},
 314         {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001},
 315         {0xc78, 0xea500001}, {0xc78, 0xe9510001},
 316         {0xc78, 0xe8520001}, {0xc78, 0xe7530001},
 317         {0xc78, 0xe6540001}, {0xc78, 0xe5550001},
 318         {0xc78, 0xe4560001}, {0xc78, 0xe3570001},
 319         {0xc78, 0xe2580001}, {0xc78, 0xe1590001},
 320         {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001},
 321         {0xc78, 0x885c0001}, {0xc78, 0x875d0001},
 322         {0xc78, 0x865e0001}, {0xc78, 0x855f0001},
 323         {0xc78, 0x84600001}, {0xc78, 0x83610001},
 324         {0xc78, 0x82620001}, {0xc78, 0x6a630001},
 325         {0xc78, 0x69640001}, {0xc78, 0x68650001},
 326         {0xc78, 0x67660001}, {0xc78, 0x66670001},
 327         {0xc78, 0x65680001}, {0xc78, 0x64690001},
 328         {0xc78, 0x636a0001}, {0xc78, 0x626b0001},
 329         {0xc78, 0x616c0001}, {0xc78, 0x606d0001},
 330         {0xc78, 0x476e0001}, {0xc78, 0x466f0001},
 331         {0xc78, 0x45700001}, {0xc78, 0x44710001},
 332         {0xc78, 0x43720001}, {0xc78, 0x42730001},
 333         {0xc78, 0x41740001}, {0xc78, 0x40750001},
 334         {0xc78, 0x40760001}, {0xc78, 0x40770001},
 335         {0xc78, 0x40780001}, {0xc78, 0x40790001},
 336         {0xc78, 0x407a0001}, {0xc78, 0x407b0001},
 337         {0xc78, 0x407c0001}, {0xc78, 0x407d0001},
 338         {0xc78, 0x407e0001}, {0xc78, 0x407f0001},
 339         {0xc50, 0x00040222}, {0xc50, 0x00040220},
 340         {0xffff, 0xffffffff}
 341 };
 342
 343 static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = {
 344         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 345         {0x00, 0x00030000}, {0x08, 0x00008400},
 346         {0x18, 0x00000407}, {0x19, 0x00000012},
 347         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 348         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 349         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 350         {0x57, 0x000d0000}, {0x58, 0x000be180},
 351         {0x67, 0x00001552}, {0x83, 0x00000000},
 352         {0xb0, 0x000ff9f1}, {0xb1, 0x00055418},
 353         {0xb2, 0x0008cc00}, {0xb4, 0x00043083},
 354         {0xb5, 0x00008166}, {0xb6, 0x0000803e},
 355         {0xb7, 0x0001c69f}, {0xb8, 0x0000407f},
 356         {0xb9, 0x00080001}, {0xba, 0x00040001},
 357         {0xbb, 0x00000400}, {0xbf, 0x000c0000},
 358         {0xc2, 0x00002400}, {0xc3, 0x00000009},
 359         {0xc4, 0x00040c91}, {0xc5, 0x00099999},
 360         {0xc6, 0x000000a3}, {0xc7, 0x00088820},
 361         {0xc8, 0x00076c06}, {0xc9, 0x00000000},
 362         {0xca, 0x00080000}, {0xdf, 0x00000180},
 363         {0xef, 0x000001a0}, {0x51, 0x00069545},
 364         {0x52, 0x0007e45e}, {0x53, 0x00000071},
 365         {0x56, 0x00051ff3}, {0x35, 0x000000a8},
 366         {0x35, 0x000001e2}, {0x35, 0x000002a8},
 367         {0x36, 0x00001c24}, {0x36, 0x00009c24},
 368         {0x36, 0x00011c24}, {0x36, 0x00019c24},
 369         {0x18, 0x00000c07}, {0x5a, 0x00048000},
 370         {0x19, 0x000739d0},
 371 #ifdef EXT_PA_8192EU
 372         /* External PA or external LNA */
 373         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 374         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 375         {0x34, 0x0000604a}, {0x34, 0x00005047},
 376         {0x34, 0x0000400a}, {0x34, 0x00003007},
 377         {0x34, 0x00002004}, {0x34, 0x00001001},
 378         {0x34, 0x00000000},
 379 #else
 380         /* Regular */
 381         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 382         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 383         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 384         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 385         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 386         {0x34, 0x00000014},
 387 #endif
 388         {0x00, 0x00030159},
 389         {0x84, 0x00068180},
 390         {0x86, 0x0000014e},
 391         {0x87, 0x00048e00},
 392         {0x8e, 0x00065540},
 393         {0x8f, 0x00088000},
 394         {0xef, 0x000020a0},
 395 #ifdef EXT_PA_8192EU
 396         /* External PA or external LNA */
 397         {0x3b, 0x000f07b0},
 398 #else
 399         {0x3b, 0x000f02b0},
 400 #endif
 401         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 402         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 403         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 404         {0x3b, 0x0008f780},
 405 #ifdef EXT_PA_8192EU
 406         /* External PA or external LNA */
 407         {0x3b, 0x000787b0},
 408 #else
 409         {0x3b, 0x00078730},
 410 #endif
 411         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 412         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 413         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 414         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 415         {0xfe, 0x00000000}, {0x18, 0x0000fc07},
 416         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 417         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 418         {0x1e, 0x00000001}, {0x1f, 0x00080000},
 419         {0x00, 0x00033e70},
 420         {0xff, 0xffffffff}
 421 };
 422
 423 static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = {
 424         {0x7f, 0x00000082}, {0x81, 0x0003fc00},
 425         {0x00, 0x00030000}, {0x08, 0x00008400},
 426         {0x18, 0x00000407}, {0x19, 0x00000012},
 427         {0x1b, 0x00000064}, {0x1e, 0x00080009},
 428         {0x1f, 0x00000880}, {0x2f, 0x0001a060},
 429         {0x3f, 0x00000000}, {0x42, 0x000060c0},
 430         {0x57, 0x000d0000}, {0x58, 0x000be180},
 431         {0x67, 0x00001552}, {0x7f, 0x00000082},
 432         {0x81, 0x0003f000}, {0x83, 0x00000000},
 433         {0xdf, 0x00000180}, {0xef, 0x000001a0},
 434         {0x51, 0x00069545}, {0x52, 0x0007e42e},
 435         {0x53, 0x00000071}, {0x56, 0x00051ff3},
 436         {0x35, 0x000000a8}, {0x35, 0x000001e0},
 437         {0x35, 0x000002a8}, {0x36, 0x00001ca8},
 438         {0x36, 0x00009c24}, {0x36, 0x00011c24},
 439         {0x36, 0x00019c24}, {0x18, 0x00000c07},
 440         {0x5a, 0x00048000}, {0x19, 0x000739d0},
 441 #ifdef EXT_PA_8192EU
 442         /* External PA or external LNA */
 443         {0x34, 0x0000a093}, {0x34, 0x0000908f},
 444         {0x34, 0x0000808c}, {0x34, 0x0000704d},
 445         {0x34, 0x0000604a}, {0x34, 0x00005047},
 446         {0x34, 0x0000400a}, {0x34, 0x00003007},
 447         {0x34, 0x00002004}, {0x34, 0x00001001},
 448         {0x34, 0x00000000},
 449 #else
 450         {0x34, 0x0000add7}, {0x34, 0x00009dd4},
 451         {0x34, 0x00008dd1}, {0x34, 0x00007dce},
 452         {0x34, 0x00006dcb}, {0x34, 0x00005dc8},
 453         {0x34, 0x00004dc5}, {0x34, 0x000034cc},
 454         {0x34, 0x0000244f}, {0x34, 0x0000144c},
 455         {0x34, 0x00000014},
 456 #endif
 457         {0x00, 0x00030159}, {0x84, 0x00068180},
 458         {0x86, 0x000000ce}, {0x87, 0x00048a00},
 459         {0x8e, 0x00065540}, {0x8f, 0x00088000},
 460         {0xef, 0x000020a0},
 461 #ifdef EXT_PA_8192EU
 462         /* External PA or external LNA */
 463         {0x3b, 0x000f07b0},
 464 #else
 465         {0x3b, 0x000f02b0},
 466 #endif
 467
 468         {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0},
 469         {0x3b, 0x000cf060}, {0x3b, 0x000b0090},
 470         {0x3b, 0x000a0080}, {0x3b, 0x00090080},
 471         {0x3b, 0x0008f780},
 472 #ifdef EXT_PA_8192EU
 473         /* External PA or external LNA */
 474         {0x3b, 0x000787b0},
 475 #else
 476         {0x3b, 0x00078730},
 477 #endif
 478         {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0},
 479         {0x3b, 0x00040620}, {0x3b, 0x00037090},
 480         {0x3b, 0x00020080}, {0x3b, 0x0001f060},
 481         {0x3b, 0x0000ffb0}, {0xef, 0x000000a0},
 482         {0x00, 0x00010159}, {0xfe, 0x00000000},
 483         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 484         {0xfe, 0x00000000}, {0x1e, 0x00000001},
 485         {0x1f, 0x00080000}, {0x00, 0x00033e70},
 486         {0xff, 0xffffffff}
 487 };
 488
 489 static void
 490 rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
 491 {
 492         u32 val32, ofdm, mcs;
 493         u8 cck, ofdmbase, mcsbase;
 494         int group, tx_idx;
 495
 496         tx_idx = 0;
 497         group = rtl8xxxu_gen2_channel_to_group(channel);
 498
 499         cck = priv->cck_tx_power_index_A[group];
 500
 501         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
 502         val32 &= 0xffff00ff;
 503         val32 |= (cck << 8);
 504         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
 505
 506         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 507         val32 &= 0xff;
 508         val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 509         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 510
 511         ofdmbase = priv->ht40_1s_tx_power_index_A[group];
 512         ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a;
 513         ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24;
 514
 515         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm);
 516         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm);
 517
 518         mcsbase = priv->ht40_1s_tx_power_index_A[group];
 519         if (ht40)
 520                 mcsbase += priv->ht40_tx_power_diff[tx_idx++].a;
 521         else
 522                 mcsbase += priv->ht20_tx_power_diff[tx_idx++].a;
 523         mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 524
 525         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs);
 526         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs);
 527         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs);
 528         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs);
 529
 530         if (priv->tx_paths > 1) {
 531                 cck = priv->cck_tx_power_index_B[group];
 532
 533                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
 534                 val32 &= 0xff;
 535                 val32 |= ((cck << 8) | (cck << 16) | (cck << 24));
 536                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
 537
 538                 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
 539                 val32 &= 0xffffff00;
 540                 val32 |= cck;
 541                 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
 542
 543                 ofdmbase = priv->ht40_1s_tx_power_index_B[group];
 544                 ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b;
 545                 ofdm = ofdmbase | ofdmbase << 8 |
 546                         ofdmbase << 16 | ofdmbase << 24;
 547
 548                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm);
 549                 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm);
 550
 551                 mcsbase = priv->ht40_1s_tx_power_index_B[group];
 552                 if (ht40)
 553                         mcsbase += priv->ht40_tx_power_diff[tx_idx++].b;
 554                 else
 555                         mcsbase += priv->ht20_tx_power_diff[tx_idx++].b;
 556                 mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24;
 557
 558                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs);
 559                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs);
 560                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs);
 561                 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs);
 562         }
 563 }
 564
 565 static void rtl8192eu_log_next_device_info(struct rtl8xxxu_priv *priv,
 566                                            char *record_name,
 567                                            char *device_info,
 568                                            unsigned int *record_offset)
 569 {
 570         char *record = device_info + *record_offset;
 571
 572         /* A record is [ total length | 0x03 | value ] */
 573         unsigned char l = record[0];
 574
 575         /*
 576          * The whole device info section seems to be 80 characters, make sure
 577          * we don't read further.
 578          */
 579         if (*record_offset + l > 80) {
 580                 dev_warn(&priv->udev->dev,
 581                          "invalid record length %d while parsing \"%s\" at offset %u.\n",
 582                          l, record_name, *record_offset);
 583                 return;
 584         }
 585
 586         if (l >= 2) {
 587                 char value[80];
 588
 589                 memcpy(value, &record[2], l - 2);
 590                 value[l - 2] = '\0';
 591                 dev_info(&priv->udev->dev, "%s: %s\n", record_name, value);
 592                 *record_offset = *record_offset + l;
 593         } else {
 594                 dev_info(&priv->udev->dev, "%s not available.\n", record_name);
 595         }
 596 }
 597
 598 static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
 599 {
 600         struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu;
 601         unsigned int record_offset;
 602         int i;
 603
 604         if (efuse->rtl_id != cpu_to_le16(0x8129))
 605                 return -EINVAL;
 606
 607         ether_addr_copy(priv->mac_addr, efuse->mac_addr);
 608
 609         memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base,
 610                sizeof(efuse->tx_power_index_A.cck_base));
 611         memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base,
 612                sizeof(efuse->tx_power_index_B.cck_base));
 613
 614         memcpy(priv->ht40_1s_tx_power_index_A,
 615                efuse->tx_power_index_A.ht40_base,
 616                sizeof(efuse->tx_power_index_A.ht40_base));
 617         memcpy(priv->ht40_1s_tx_power_index_B,
 618                efuse->tx_power_index_B.ht40_base,
 619                sizeof(efuse->tx_power_index_B.ht40_base));
 620
 621         priv->ht20_tx_power_diff[0].a =
 622                 efuse->tx_power_index_A.ht20_ofdm_1s_diff.b;
 623         priv->ht20_tx_power_diff[0].b =
 624                 efuse->tx_power_index_B.ht20_ofdm_1s_diff.b;
 625
 626         priv->ht40_tx_power_diff[0].a = 0;
 627         priv->ht40_tx_power_diff[0].b = 0;
 628
 629         for (i = 1; i < RTL8723B_TX_COUNT; i++) {
 630                 priv->ofdm_tx_power_diff[i].a =
 631                         efuse->tx_power_index_A.pwr_diff[i - 1].ofdm;
 632                 priv->ofdm_tx_power_diff[i].b =
 633                         efuse->tx_power_index_B.pwr_diff[i - 1].ofdm;
 634
 635                 priv->ht20_tx_power_diff[i].a =
 636                         efuse->tx_power_index_A.pwr_diff[i - 1].ht20;
 637                 priv->ht20_tx_power_diff[i].b =
 638                         efuse->tx_power_index_B.pwr_diff[i - 1].ht20;
 639
 640                 priv->ht40_tx_power_diff[i].a =
 641                         efuse->tx_power_index_A.pwr_diff[i - 1].ht40;
 642                 priv->ht40_tx_power_diff[i].b =
 643                         efuse->tx_power_index_B.pwr_diff[i - 1].ht40;
 644         }
 645
 646         priv->has_xtalk = 1;
 647         priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f;
 648
 649         /*
 650          * device_info section seems to be laid out as records
 651          * [ total length | 0x03 | value ] so:
 652          * - vendor length + 2
 653          * - 0x03
 654          * - vendor string (not null terminated)
 655          * - product length + 2
 656          * - 0x03
 657          * - product string (not null terminated)
 658          * Then there is one or 2 0x00 on all the 4 devices I own or found
 659          * dumped online.
 660          * As previous version of the code handled an optional serial
 661          * string, I now assume there may be a third record if the
 662          * length is not 0.
 663          */
 664         record_offset = 0;
 665         rtl8192eu_log_next_device_info(priv, "Vendor", efuse->device_info, &record_offset);
 666         rtl8192eu_log_next_device_info(priv, "Product", efuse->device_info, &record_offset);
 667         rtl8192eu_log_next_device_info(priv, "Serial", efuse->device_info, &record_offset);
 668
 669         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
 670                 unsigned char *raw = priv->efuse_wifi.raw;
 671
 672                 dev_info(&priv->udev->dev,
 673                          "%s: dumping efuse (0x%02zx bytes):\n",
 674                          __func__, sizeof(struct rtl8192eu_efuse));
 675                 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8)
 676                         dev_info(&priv->udev->dev, "%02x: %8ph\n", i, &raw[i]);
 677         }
 678         return 0;
 679 }
 680
 681 static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
 682 {
 683         char *fw_name;
 684         int ret;
 685
 686         fw_name = "/*(DEBLOBBED)*/";
 687
 688         ret = rtl8xxxu_load_firmware(priv, fw_name);
 689
 690         return ret;
 691 }
 692
 693 static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv)
 694 {
 695         u8 val8;
 696         u16 val16;
 697
 698         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 699         val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF;
 700         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 701
 702         /* 6. 0x1f[7:0] = 0x07 */
 703         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 704         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 705
 706         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
 707         val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF |
 708                   SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB);
 709         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
 710         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
 711         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
 712         rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table);
 713
 714         if (priv->hi_pa)
 715                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table);
 716         else
 717                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table);
 718 }
 719
 720 static int rtl8192eu_init_phy_rf(struct rtl8xxxu_priv *priv)
 721 {
 722         int ret;
 723
 724         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radioa_init_table, RF_A);
 725         if (ret)
 726                 goto exit;
 727
 728         ret = rtl8xxxu_init_phy_rf(priv, rtl8192eu_radiob_init_table, RF_B);
 729
 730 exit:
 731         return ret;
 732 }
 733
 734 static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv)
 735 {
 736         u32 reg_eac, reg_e94, reg_e9c;
 737         int result = 0;
 738
 739         /*
 740          * TX IQK
 741          * PA/PAD controlled by 0x0
 742          */
 743         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 744         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180);
 745         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 746
 747         /* Path A IQK setting */
 748         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 749         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 750         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 751         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 752
 753         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303);
 754         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000);
 755
 756         /* LO calibration setting */
 757         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911);
 758
 759         /* One shot, path A LOK & IQK */
 760         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
 761         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 762
 763         mdelay(10);
 764
 765         /* Check failed */
 766         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 767         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 768         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 769
 770         if (!(reg_eac & BIT(28)) &&
 771             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 772             ((reg_e9c & 0x03ff0000) != 0x00420000))
 773                 result |= 0x01;
 774
 775         return result;
 776 }
 777
 778 static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv)
 779 {
 780         u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32;
 781         int result = 0;
 782
 783         /* Leave IQK mode */
 784         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00);
 785
 786         /* Enable path A PA in TX IQK mode */
 787         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 788         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 789         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 790         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b);
 791
 792         /* PA/PAD control by 0x56, and set = 0x0 */
 793         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
 794         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
 795
 796         /* Enter IQK mode */
 797         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 798
 799         /* TX IQK setting */
 800         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 801         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 802
 803         /* path-A IQK setting */
 804         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c);
 805         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 806         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 807         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 808
 809         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
 810         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f);
 811
 812         /* LO calibration setting */
 813         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 814
 815         /* One shot, path A LOK & IQK */
 816         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 817         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 818
 819         mdelay(10);
 820
 821         /* Check failed */
 822         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 823         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
 824         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
 825
 826         if (!(reg_eac & BIT(28)) &&
 827             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
 828             ((reg_e9c & 0x03ff0000) != 0x00420000)) {
 829                 result |= 0x01;
 830         } else {
 831                 /* PA/PAD controlled by 0x0 */
 832                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 833                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
 834                 goto out;
 835         }
 836
 837         val32 = 0x80007c00 |
 838                 (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff);
 839         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
 840
 841         /* Modify RX IQK mode table */
 842         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 843
 844         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0);
 845         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000);
 846         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f);
 847         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa);
 848
 849         /* PA/PAD control by 0x56, and set = 0x0 */
 850         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980);
 851         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000);
 852
 853         /* Enter IQK mode */
 854         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 855
 856         /* IQK setting */
 857         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 858
 859         /* Path A IQK setting */
 860         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 861         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c);
 862         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
 863         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 864
 865         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
 866         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
 867
 868         /* LO calibration setting */
 869         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
 870
 871         /* One shot, path A LOK & IQK */
 872         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 873         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 874
 875         mdelay(10);
 876
 877         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 878         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
 879
 880         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 881         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180);
 882
 883         if (!(reg_eac & BIT(27)) &&
 884             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
 885             ((reg_eac & 0x03ff0000) != 0x00360000))
 886                 result |= 0x02;
 887         else
 888                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
 889                          __func__);
 890
 891 out:
 892         return result;
 893 }
 894
 895 static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv)
 896 {
 897         u32 reg_eac, reg_eb4, reg_ebc;
 898         int result = 0;
 899
 900         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 901         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180);
 902         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 903
 904         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 905         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 906
 907         /* Path B IQK setting */
 908         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 909         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 910         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 911         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 912
 913         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2);
 914         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000);
 915
 916         /* LO calibration setting */
 917         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911);
 918
 919         /* One shot, path A LOK & IQK */
 920         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 921         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 922
 923         mdelay(1);
 924
 925         /* Check failed */
 926         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 927         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 928         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 929
 930         if (!(reg_eac & BIT(31)) &&
 931             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 932             ((reg_ebc & 0x03ff0000) != 0x00420000))
 933                 result |= 0x01;
 934         else
 935                 dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n",
 936                          __func__);
 937
 938         return result;
 939 }
 940
 941 static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv)
 942 {
 943         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32;
 944         int result = 0;
 945
 946         /* Leave IQK mode */
 947         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 948
 949         /* Enable path A PA in TX IQK mode */
 950         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
 951         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
 952         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
 953         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b);
 954
 955         /* PA/PAD control by 0x56, and set = 0x0 */
 956         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
 957         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
 958
 959         /* Enter IQK mode */
 960         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
 961
 962         /* TX IQK setting */
 963         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
 964         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
 965
 966         /* path-A IQK setting */
 967         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
 968         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
 969         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c);
 970         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c);
 971
 972         rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f);
 973         rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f);
 974
 975         /* LO calibration setting */
 976         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911);
 977
 978         /* One shot, path A LOK & IQK */
 979         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
 980         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
 981
 982         mdelay(10);
 983
 984         /* Check failed */
 985         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
 986         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
 987         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
 988
 989         if (!(reg_eac & BIT(31)) &&
 990             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
 991             ((reg_ebc & 0x03ff0000) != 0x00420000)) {
 992                 result |= 0x01;
 993         } else {
 994                 /*
 995                  * PA/PAD controlled by 0x0
 996                  * Vendor driver restores RF_A here which I believe is a bug
 997                  */
 998                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
 999                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
1000                 goto out;
1001         }
1002
1003         val32 = 0x80007c00 |
1004                 (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff);
1005         rtl8xxxu_write32(priv, REG_TX_IQK, val32);
1006
1007         /* Modify RX IQK mode table */
1008         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1009
1010         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0);
1011         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000);
1012         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f);
1013         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa);
1014
1015         /* PA/PAD control by 0x56, and set = 0x0 */
1016         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980);
1017         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000);
1018
1019         /* Enter IQK mode */
1020         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1021
1022         /* IQK setting */
1023         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1024
1025         /* Path A IQK setting */
1026         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c);
1027         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c);
1028         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c);
1029         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c);
1030
1031         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f);
1032         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f);
1033
1034         /* LO calibration setting */
1035         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891);
1036
1037         /* One shot, path A LOK & IQK */
1038         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000);
1039         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
1040
1041         mdelay(10);
1042
1043         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
1044         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
1045         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
1046
1047         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1048         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180);
1049
1050         if (!(reg_eac & BIT(30)) &&
1051             ((reg_ec4 & 0x03ff0000) != 0x01320000) &&
1052             ((reg_ecc & 0x03ff0000) != 0x00360000))
1053                 result |= 0x02;
1054         else
1055                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
1056                          __func__);
1057
1058 out:
1059         return result;
1060 }
1061
1062 static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
1063                                       int result[][8], int t)
1064 {
1065         struct device *dev = &priv->udev->dev;
1066         u32 i, val32;
1067         int path_a_ok, path_b_ok;
1068         int retry = 2;
1069         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
1070                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
1071                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
1072                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
1073                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
1074                 REG_TX_TO_TX, REG_RX_CCK,
1075                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
1076                 REG_RX_TO_RX, REG_STANDBY,
1077                 REG_SLEEP, REG_PMPD_ANAEN
1078         };
1079         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
1080                 REG_TXPAUSE, REG_BEACON_CTRL,
1081                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
1082         };
1083         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
1084                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
1085                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
1086                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
1087                 REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING
1088         };
1089         u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff;
1090         u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff;
1091
1092         /*
1093          * Note: IQ calibration must be performed after loading
1094          *       PHY_REG.txt , and radio_a, radio_b.txt
1095          */
1096
1097         if (t == 0) {
1098                 /* Save ADDA parameters, turn Path A ADDA on */
1099                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
1100                                    RTL8XXXU_ADDA_REGS);
1101                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1102                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
1103                                    priv->bb_backup, RTL8XXXU_BB_REGS);
1104         }
1105
1106         rtl8xxxu_path_adda_on(priv, adda_regs, true);
1107
1108         /* MAC settings */
1109         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
1110
1111         val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
1112         val32 |= 0x0f000000;
1113         rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
1114
1115         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
1116         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
1117         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200);
1118
1119         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
1120         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
1121         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
1122
1123         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
1124         val32 |= BIT(10);
1125         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
1126         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
1127         val32 |= BIT(10);
1128         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
1129
1130         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1131         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1132         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1133
1134         for (i = 0; i < retry; i++) {
1135                 path_a_ok = rtl8192eu_iqk_path_a(priv);
1136                 if (path_a_ok == 0x01) {
1137                         val32 = rtl8xxxu_read32(priv,
1138                                                 REG_TX_POWER_BEFORE_IQK_A);
1139                         result[t][0] = (val32 >> 16) & 0x3ff;
1140                         val32 = rtl8xxxu_read32(priv,
1141                                                 REG_TX_POWER_AFTER_IQK_A);
1142                         result[t][1] = (val32 >> 16) & 0x3ff;
1143
1144                         break;
1145                 }
1146         }
1147
1148         if (!path_a_ok)
1149                 dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__);
1150
1151         for (i = 0; i < retry; i++) {
1152                 path_a_ok = rtl8192eu_rx_iqk_path_a(priv);
1153                 if (path_a_ok == 0x03) {
1154                         val32 = rtl8xxxu_read32(priv,
1155                                                 REG_RX_POWER_BEFORE_IQK_A_2);
1156                         result[t][2] = (val32 >> 16) & 0x3ff;
1157                         val32 = rtl8xxxu_read32(priv,
1158                                                 REG_RX_POWER_AFTER_IQK_A_2);
1159                         result[t][3] = (val32 >> 16) & 0x3ff;
1160
1161                         break;
1162                 }
1163         }
1164
1165         if (!path_a_ok)
1166                 dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__);
1167
1168         if (priv->rf_paths > 1) {
1169                 /* Path A into standby */
1170                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1171                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000);
1172                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1173
1174                 /* Turn Path B ADDA on */
1175                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
1176
1177                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
1178                 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
1179                 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
1180
1181                 for (i = 0; i < retry; i++) {
1182                         path_b_ok = rtl8192eu_iqk_path_b(priv);
1183                         if (path_b_ok == 0x01) {
1184                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
1185                                 result[t][4] = (val32 >> 16) & 0x3ff;
1186                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
1187                                 result[t][5] = (val32 >> 16) & 0x3ff;
1188                                 break;
1189                         }
1190                 }
1191
1192                 if (!path_b_ok)
1193                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
1194
1195                 for (i = 0; i < retry; i++) {
1196                         path_b_ok = rtl8192eu_rx_iqk_path_b(priv);
1197                         if (path_b_ok == 0x03) {
1198                                 val32 = rtl8xxxu_read32(priv,
1199                                                         REG_RX_POWER_BEFORE_IQK_B_2);
1200                                 result[t][6] = (val32 >> 16) & 0x3ff;
1201                                 val32 = rtl8xxxu_read32(priv,
1202                                                         REG_RX_POWER_AFTER_IQK_B_2);
1203                                 result[t][7] = (val32 >> 16) & 0x3ff;
1204                                 break;
1205                         }
1206                 }
1207
1208                 if (!path_b_ok)
1209                         dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__);
1210         }
1211
1212         /* Back to BB mode, load original value */
1213         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000);
1214
1215         if (t) {
1216                 /* Reload ADDA power saving parameters */
1217                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
1218                                       RTL8XXXU_ADDA_REGS);
1219
1220                 /* Reload MAC parameters */
1221                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
1222
1223                 /* Reload BB parameters */
1224                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
1225                                       priv->bb_backup, RTL8XXXU_BB_REGS);
1226
1227                 /* Restore RX initial gain */
1228                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
1229                 val32 &= 0xffffff00;
1230                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50);
1231                 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc);
1232
1233                 if (priv->rf_paths > 1) {
1234                         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1);
1235                         val32 &= 0xffffff00;
1236                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1237                                          val32 | 0x50);
1238                         rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1,
1239                                          val32 | xb_agc);
1240                 }
1241
1242                 /* Load 0xe30 IQC default value */
1243                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
1244                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
1245         }
1246 }
1247
1248 static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
1249 {
1250         struct device *dev = &priv->udev->dev;
1251         int result[4][8];       /* last is final result */
1252         int i, candidate;
1253         bool path_a_ok, path_b_ok;
1254         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
1255         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
1256         bool simu;
1257
1258         memset(result, 0, sizeof(result));
1259         candidate = -1;
1260
1261         path_a_ok = false;
1262         path_b_ok = false;
1263
1264         for (i = 0; i < 3; i++) {
1265                 rtl8192eu_phy_iqcalibrate(priv, result, i);
1266
1267                 if (i == 1) {
1268                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1269                                                                 result, 0, 1);
1270                         if (simu) {
1271                                 candidate = 0;
1272                                 break;
1273                         }
1274                 }
1275
1276                 if (i == 2) {
1277                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1278                                                                 result, 0, 2);
1279                         if (simu) {
1280                                 candidate = 0;
1281                                 break;
1282                         }
1283
1284                         simu = rtl8xxxu_gen2_simularity_compare(priv,
1285                                                                 result, 1, 2);
1286                         if (simu)
1287                                 candidate = 1;
1288                         else
1289                                 candidate = 3;
1290                 }
1291         }
1292
1293         for (i = 0; i < 4; i++) {
1294                 reg_e94 = result[i][0];
1295                 reg_e9c = result[i][1];
1296                 reg_ea4 = result[i][2];
1297                 reg_eb4 = result[i][4];
1298                 reg_ebc = result[i][5];
1299                 reg_ec4 = result[i][6];
1300         }
1301
1302         if (candidate >= 0) {
1303                 reg_e94 = result[candidate][0];
1304                 priv->rege94 =  reg_e94;
1305                 reg_e9c = result[candidate][1];
1306                 priv->rege9c = reg_e9c;
1307                 reg_ea4 = result[candidate][2];
1308                 reg_eac = result[candidate][3];
1309                 reg_eb4 = result[candidate][4];
1310                 priv->regeb4 = reg_eb4;
1311                 reg_ebc = result[candidate][5];
1312                 priv->regebc = reg_ebc;
1313                 reg_ec4 = result[candidate][6];
1314                 reg_ecc = result[candidate][7];
1315                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
1316                 dev_dbg(dev,
1317                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x ecc=%x\n",
1318                         __func__, reg_e94, reg_e9c,
1319                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
1320                 path_a_ok = true;
1321                 path_b_ok = true;
1322         } else {
1323                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
1324                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
1325         }
1326
1327         if (reg_e94 && candidate >= 0)
1328                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
1329                                            candidate, (reg_ea4 == 0));
1330
1331         if (priv->rf_paths > 1)
1332                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
1333                                            candidate, (reg_ec4 == 0));
1334
1335         rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
1336                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
1337 }
1338
1339 /*
1340  * This is needed for 8723bu as well, presumable
1341  */
1342 static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv)
1343 {
1344         u8 val8;
1345         u32 val32;
1346
1347         /*
1348          * 40Mhz crystal source, MAC 0x28[2]=0
1349          */
1350         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1351         val8 &= 0xfb;
1352         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1353
1354         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1355         val32 &= 0xfffffc7f;
1356         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1357
1358         /*
1359          * 92e AFE parameter
1360          * AFE PLL KVCO selection, MAC 0x28[6]=1
1361          */
1362         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
1363         val8 &= 0xbf;
1364         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
1365
1366         /*
1367          * AFE PLL KVCO selection, MAC 0x78[21]=0
1368          */
1369         val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4);
1370         val32 &= 0xffdfffff;
1371         rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32);
1372 }
1373
1374 static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv)
1375 {
1376         u8 val8;
1377
1378         /* Clear suspend enable and power down enable*/
1379         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1380         val8 &= ~(BIT(3) | BIT(4));
1381         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1382 }
1383
1384 static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv)
1385 {
1386         u8 val8;
1387         u32 val32;
1388         int count, ret = 0;
1389
1390         /* disable HWPDN 0x04[15]=0*/
1391         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1392         val8 &= ~BIT(7);
1393         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1394
1395         /* disable SW LPS 0x04[10]= 0 */
1396         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1397         val8 &= ~BIT(2);
1398         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1399
1400         /* disable WL suspend*/
1401         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1402         val8 &= ~(BIT(3) | BIT(4));
1403         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1404
1405         /* wait till 0x04[17] = 1 power ready*/
1406         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1407                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1408                 if (val32 & BIT(17))
1409                         break;
1410
1411                 udelay(10);
1412         }
1413
1414         if (!count) {
1415                 ret = -EBUSY;
1416                 goto exit;
1417         }
1418
1419         /* We should be able to optimize the following three entries into one */
1420
1421         /* release WLON reset 0x04[16]= 1*/
1422         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
1423         val8 |= BIT(0);
1424         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
1425
1426         /* set, then poll until 0 */
1427         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1428         val32 |= APS_FSMCO_MAC_ENABLE;
1429         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
1430
1431         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1432                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
1433                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
1434                         ret = 0;
1435                         break;
1436                 }
1437                 udelay(10);
1438         }
1439
1440         if (!count) {
1441                 ret = -EBUSY;
1442                 goto exit;
1443         }
1444
1445 exit:
1446         return ret;
1447 }
1448
1449 static int rtl8192eu_active_to_lps(struct rtl8xxxu_priv *priv)
1450 {
1451         struct device *dev = &priv->udev->dev;
1452         u8 val8;
1453         u16 val16;
1454         u32 val32;
1455         int retry, retval;
1456
1457         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1458
1459         retry = 100;
1460         retval = -EBUSY;
1461         /*
1462          * Poll 32 bit wide 0x05f8 for 0x00000000 to ensure no TX is pending.
1463          */
1464         do {
1465                 val32 = rtl8xxxu_read32(priv, REG_SCH_TX_CMD);
1466                 if (!val32) {
1467                         retval = 0;
1468                         break;
1469                 }
1470         } while (retry--);
1471
1472         if (!retry) {
1473                 dev_warn(dev, "Failed to flush TX queue\n");
1474                 retval = -EBUSY;
1475                 goto out;
1476         }
1477
1478         /* Disable CCK and OFDM, clock gated */
1479         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1480         val8 &= ~SYS_FUNC_BBRSTB;
1481         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1482
1483         udelay(2);
1484
1485         /* Reset whole BB */
1486         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
1487         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
1488         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
1489
1490         /* Reset MAC TRX */
1491         val16 = rtl8xxxu_read16(priv, REG_CR);
1492         val16 &= 0xff00;
1493         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE);
1494         rtl8xxxu_write16(priv, REG_CR, val16);
1495
1496         val16 = rtl8xxxu_read16(priv, REG_CR);
1497         val16 &= ~CR_SECURITY_ENABLE;
1498         rtl8xxxu_write16(priv, REG_CR, val16);
1499
1500         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
1501         val8 |= DUAL_TSF_TX_OK;
1502         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
1503
1504 out:
1505         return retval;
1506 }
1507
1508 static int rtl8192eu_active_to_emu(struct rtl8xxxu_priv *priv)
1509 {
1510         u8 val8;
1511         int count, ret = 0;
1512
1513         /* Turn off RF */
1514         val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);
1515         val8 &= ~RF_ENABLE;
1516         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
1517
1518         /* Switch DPDT_SEL_P output from register 0x65[2] */
1519         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
1520         val8 &= ~LEDCFG2_DPDT_SELECT;
1521         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
1522
1523         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
1524         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1525         val8 |= BIT(1);
1526         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1527
1528         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
1529                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1530                 if ((val8 & BIT(1)) == 0)
1531                         break;
1532                 udelay(10);
1533         }
1534
1535         if (!count) {
1536                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
1537                          __func__);
1538                 ret = -EBUSY;
1539                 goto exit;
1540         }
1541
1542 exit:
1543         return ret;
1544 }
1545
1546 static int rtl8192eu_emu_to_disabled(struct rtl8xxxu_priv *priv)
1547 {
1548         u8 val8;
1549
1550         /* 0x04[12:11] = 01 enable WL suspend */
1551         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
1552         val8 &= ~(BIT(3) | BIT(4));
1553         val8 |= BIT(3);
1554         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
1555
1556         return 0;
1557 }
1558
1559 static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv)
1560 {
1561         u16 val16;
1562         u32 val32;
1563         int ret;
1564
1565         ret = 0;
1566
1567         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1568         if (val32 & SYS_CFG_SPS_LDO_SEL) {
1569                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3);
1570         } else {
1571                 /*
1572                  * Raise 1.2V voltage
1573                  */
1574                 val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL);
1575                 val32 &= 0xff0fffff;
1576                 val32 |= 0x00500000;
1577                 rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32);
1578                 rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83);
1579         }
1580
1581         /*
1582          * Adjust AFE before enabling PLL
1583          */
1584         rtl8192e_crystal_afe_adjust(priv);
1585         rtl8192e_disabled_to_emu(priv);
1586
1587         ret = rtl8192e_emu_to_active(priv);
1588         if (ret)
1589                 goto exit;
1590
1591         rtl8xxxu_write16(priv, REG_CR, 0x0000);
1592
1593         /*
1594          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
1595          * Set CR bit10 to enable 32k calibration.
1596          */
1597         val16 = rtl8xxxu_read16(priv, REG_CR);
1598         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
1599                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
1600                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
1601                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
1602                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
1603         rtl8xxxu_write16(priv, REG_CR, val16);
1604
1605 exit:
1606         return ret;
1607 }
1608
1609 static void rtl8192eu_power_off(struct rtl8xxxu_priv *priv)
1610 {
1611         u8 val8;
1612         u16 val16;
1613
1614         rtl8xxxu_flush_fifo(priv);
1615
1616         val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
1617         val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;
1618         rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
1619
1620         /* Turn off RF */
1621         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
1622
1623         rtl8192eu_active_to_lps(priv);
1624
1625         /* Reset Firmware if running in RAM */
1626         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
1627                 rtl8xxxu_firmware_self_reset(priv);
1628
1629         /* Reset MCU */
1630         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1631         val16 &= ~SYS_FUNC_CPU_ENABLE;
1632         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1633
1634         /* Reset MCU ready status */
1635         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
1636
1637         rtl8xxxu_reset_8051(priv);
1638
1639         rtl8192eu_active_to_emu(priv);
1640         rtl8192eu_emu_to_disabled(priv);
1641 }
1642
1643 static void rtl8192e_enable_rf(struct rtl8xxxu_priv *priv)
1644 {
1645         u32 val32;
1646         u8 val8;
1647
1648         val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
1649         val32 |= (BIT(22) | BIT(23));
1650         rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
1651
1652         val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);
1653         val8 |= BIT(5);
1654         rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);
1655
1656         /*
1657          * WLAN action by PTA
1658          */
1659         rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04);
1660
1661         val32 = rtl8xxxu_read32(priv, REG_PWR_DATA);
1662         val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN;
1663         rtl8xxxu_write32(priv, REG_PWR_DATA, val32);
1664
1665         val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER);
1666         val32 |= (BIT(0) | BIT(1));
1667         rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32);
1668
1669         rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77);
1670
1671         val32 = rtl8xxxu_read32(priv, REG_LEDCFG0);
1672         val32 &= ~BIT(24);
1673         val32 |= BIT(23);
1674         rtl8xxxu_write32(priv, REG_LEDCFG0, val32);
1675
1676         /*
1677          * Fix external switch Main->S1, Aux->S0
1678          */
1679         val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);
1680         val8 &= ~BIT(0);
1681         rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);
1682 }
1683
1684 struct rtl8xxxu_fileops rtl8192eu_fops = {
1685         .parse_efuse = rtl8192eu_parse_efuse,
1686         .load_firmware = rtl8192eu_load_firmware,
1687         .power_on = rtl8192eu_power_on,
1688         .power_off = rtl8192eu_power_off,
1689         .reset_8051 = rtl8xxxu_reset_8051,
1690         .llt_init = rtl8xxxu_auto_llt_table,
1691         .init_phy_bb = rtl8192eu_init_phy_bb,
1692         .init_phy_rf = rtl8192eu_init_phy_rf,
1693         .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate,
1694         .config_channel = rtl8xxxu_gen2_config_channel,
1695         .parse_rx_desc = rtl8xxxu_parse_rxdesc24,
1696         .enable_rf = rtl8192e_enable_rf,
1697         .disable_rf = rtl8xxxu_gen2_disable_rf,
1698         .usb_quirks = rtl8xxxu_gen2_usb_quirks,
1699         .set_tx_power = rtl8192e_set_tx_power,
1700         .update_rate_mask = rtl8xxxu_gen2_update_rate_mask,
1701         .report_connect = rtl8xxxu_gen2_report_connect,
1702         .fill_txdesc = rtl8xxxu_fill_txdesc_v2,
1703         .writeN_block_size = 128,
1704         .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40),
1705         .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24),
1706         .has_s0s1 = 0,
1707         .gen2_thermal_meter = 1,
1708         .adda_1t_init = 0x0fc01616,
1709         .adda_1t_path_on = 0x0fc01616,
1710         .adda_2t_path_on_a = 0x0fc01616,
1711         .adda_2t_path_on_b = 0x0fc01616,
1712         .trxff_boundary = 0x3cff,
1713         .mactable = rtl8192e_mac_init_table,
1714         .total_page_num = TX_TOTAL_PAGE_NUM_8192E,
1715         .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E,
1716         .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E,
1717         .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E,
1718 };