drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.h

   1 /*
   2  * Copyright (c) 2014 - 2016 Jes Sorensen <Jes.Sorensen@redhat.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of version 2 of the GNU General Public License as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11  * more details.
  12  *
  13  * Register definitions taken from original Realtek rtl8723au driver
  14  */
  15
  16 #include <asm/byteorder.h>
  17
  18 #define RTL8XXXU_DEBUG_REG_WRITE        0x01
  19 #define RTL8XXXU_DEBUG_REG_READ         0x02
  20 #define RTL8XXXU_DEBUG_RFREG_WRITE      0x04
  21 #define RTL8XXXU_DEBUG_RFREG_READ       0x08
  22 #define RTL8XXXU_DEBUG_CHANNEL          0x10
  23 #define RTL8XXXU_DEBUG_TX               0x20
  24 #define RTL8XXXU_DEBUG_TX_DUMP          0x40
  25 #define RTL8XXXU_DEBUG_RX               0x80
  26 #define RTL8XXXU_DEBUG_RX_DUMP          0x100
  27 #define RTL8XXXU_DEBUG_USB              0x200
  28 #define RTL8XXXU_DEBUG_KEY              0x400
  29 #define RTL8XXXU_DEBUG_H2C              0x800
  30 #define RTL8XXXU_DEBUG_ACTION           0x1000
  31 #define RTL8XXXU_DEBUG_EFUSE            0x2000
  32 #define RTL8XXXU_DEBUG_INTERRUPT        0x4000
  33
  34 #define RTW_USB_CONTROL_MSG_TIMEOUT     500
  35 #define RTL8XXXU_MAX_REG_POLL           500
  36 #define USB_INTR_CONTENT_LENGTH         56
  37
  38 #define RTL8XXXU_OUT_ENDPOINTS          4
  39
  40 #define REALTEK_USB_READ                0xc0
  41 #define REALTEK_USB_WRITE               0x40
  42 #define REALTEK_USB_CMD_REQ             0x05
  43 #define REALTEK_USB_CMD_IDX             0x00
  44
  45 #define TX_TOTAL_PAGE_NUM               0xf8
  46 #define TX_TOTAL_PAGE_NUM_8192E         0xf3
  47 #define TX_TOTAL_PAGE_NUM_8723B         0xf7
  48 /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */
  49 #define TX_PAGE_NUM_PUBQ                0xe7
  50 #define TX_PAGE_NUM_HI_PQ               0x0c
  51 #define TX_PAGE_NUM_LO_PQ               0x02
  52 #define TX_PAGE_NUM_NORM_PQ             0x02
  53
  54 #define TX_PAGE_NUM_PUBQ_8192E          0xe7
  55 #define TX_PAGE_NUM_HI_PQ_8192E         0x08
  56 #define TX_PAGE_NUM_LO_PQ_8192E         0x0c
  57 #define TX_PAGE_NUM_NORM_PQ_8192E       0x00
  58
  59 #define TX_PAGE_NUM_PUBQ_8723B          0xe7
  60 #define TX_PAGE_NUM_HI_PQ_8723B         0x0c
  61 #define TX_PAGE_NUM_LO_PQ_8723B         0x02
  62 #define TX_PAGE_NUM_NORM_PQ_8723B       0x02
  63
  64 #define RTL_FW_PAGE_SIZE                4096
  65 #define RTL8XXXU_FIRMWARE_POLL_MAX      1000
  66
  67 #define RTL8723A_CHANNEL_GROUPS         3
  68 #define RTL8723A_MAX_RF_PATHS           2
  69 #define RTL8723B_CHANNEL_GROUPS         6
  70 #define RTL8723B_TX_COUNT               4
  71 #define RTL8723B_MAX_RF_PATHS           4
  72 #define RTL8XXXU_MAX_CHANNEL_GROUPS     6
  73 #define RF6052_MAX_TX_PWR               0x3f
  74
  75 #define EFUSE_MAP_LEN                   512
  76 #define EFUSE_MAX_SECTION_8723A         64
  77 #define EFUSE_REAL_CONTENT_LEN_8723A    512
  78 #define EFUSE_BT_MAP_LEN_8723A          1024
  79 #define EFUSE_MAX_WORD_UNIT             4
  80
  81 enum rtl8xxxu_rtl_chip {
  82         RTL8192S = 0x81920,
  83         RTL8191S = 0x81910,
  84         RTL8192C = 0x8192c,
  85         RTL8191C = 0x8191c,
  86         RTL8188C = 0x8188c,
  87         RTL8188R = 0x81889,
  88         RTL8192D = 0x8192d,
  89         RTL8723A = 0x8723a,
  90         RTL8188E = 0x8188e,
  91         RTL8812  = 0x88120,
  92         RTL8821  = 0x88210,
  93         RTL8192E = 0x8192e,
  94         RTL8191E = 0x8191e,
  95         RTL8723B = 0x8723b,
  96         RTL8814A = 0x8814a,
  97         RTL8881A = 0x8881a,
  98         RTL8821B = 0x8821b,
  99         RTL8822B = 0x8822b,
 100         RTL8703B = 0x8703b,
 101         RTL8195A = 0x8195a,
 102         RTL8188F = 0x8188f
 103 };
 104
 105 enum rtl8xxxu_rx_type {
 106         RX_TYPE_DATA_PKT = 0,
 107         RX_TYPE_C2H = 1,
 108         RX_TYPE_ERROR = -1
 109 };
 110
 111 struct rtl8xxxu_rxdesc16 {
 112 #ifdef __LITTLE_ENDIAN
 113         u32 pktlen:14;
 114         u32 crc32:1;
 115         u32 icverr:1;
 116         u32 drvinfo_sz:4;
 117         u32 security:3;
 118         u32 qos:1;
 119         u32 shift:2;
 120         u32 phy_stats:1;
 121         u32 swdec:1;
 122         u32 ls:1;
 123         u32 fs:1;
 124         u32 eor:1;
 125         u32 own:1;
 126
 127         u32 macid:5;
 128         u32 tid:4;
 129         u32 hwrsvd:4;
 130         u32 amsdu:1;
 131         u32 paggr:1;
 132         u32 faggr:1;
 133         u32 a1fit:4;
 134         u32 a2fit:4;
 135         u32 pam:1;
 136         u32 pwr:1;
 137         u32 md:1;
 138         u32 mf:1;
 139         u32 type:2;
 140         u32 mc:1;
 141         u32 bc:1;
 142
 143         u32 seq:12;
 144         u32 frag:4;
 145         u32 pkt_cnt:8;
 146         u32 reserved:6;
 147         u32 nextind:1;
 148         u32 reserved0:1;
 149
 150         u32 rxmcs:6;
 151         u32 rxht:1;
 152         u32 gf:1;
 153         u32 splcp:1;
 154         u32 bw:1;
 155         u32 htc:1;
 156         u32 eosp:1;
 157         u32 bssidfit:2;
 158         u32 reserved1:16;
 159         u32 unicastwake:1;
 160         u32 magicwake:1;
 161
 162         u32 pattern0match:1;
 163         u32 pattern1match:1;
 164         u32 pattern2match:1;
 165         u32 pattern3match:1;
 166         u32 pattern4match:1;
 167         u32 pattern5match:1;
 168         u32 pattern6match:1;
 169         u32 pattern7match:1;
 170         u32 pattern8match:1;
 171         u32 pattern9match:1;
 172         u32 patternamatch:1;
 173         u32 patternbmatch:1;
 174         u32 patterncmatch:1;
 175         u32 reserved2:19;
 176 #else
 177         u32 own:1;
 178         u32 eor:1;
 179         u32 fs:1;
 180         u32 ls:1;
 181         u32 swdec:1;
 182         u32 phy_stats:1;
 183         u32 shift:2;
 184         u32 qos:1;
 185         u32 security:3;
 186         u32 drvinfo_sz:4;
 187         u32 icverr:1;
 188         u32 crc32:1;
 189         u32 pktlen:14;
 190
 191         u32 bc:1;
 192         u32 mc:1;
 193         u32 type:2;
 194         u32 mf:1;
 195         u32 md:1;
 196         u32 pwr:1;
 197         u32 pam:1;
 198         u32 a2fit:4;
 199         u32 a1fit:4;
 200         u32 faggr:1;
 201         u32 paggr:1;
 202         u32 amsdu:1;
 203         u32 hwrsvd:4;
 204         u32 tid:4;
 205         u32 macid:5;
 206
 207         u32 reserved0:1;
 208         u32 nextind:1;
 209         u32 reserved:6;
 210         u32 pkt_cnt:8;
 211         u32 frag:4;
 212         u32 seq:12;
 213
 214         u32 magicwake:1;
 215         u32 unicastwake:1;
 216         u32 reserved1:16;
 217         u32 bssidfit:2;
 218         u32 eosp:1;
 219         u32 htc:1;
 220         u32 bw:1;
 221         u32 splcp:1;
 222         u32 gf:1;
 223         u32 rxht:1;
 224         u32 rxmcs:6;
 225
 226         u32 reserved2:19;
 227         u32 patterncmatch:1;
 228         u32 patternbmatch:1;
 229         u32 patternamatch:1;
 230         u32 pattern9match:1;
 231         u32 pattern8match:1;
 232         u32 pattern7match:1;
 233         u32 pattern6match:1;
 234         u32 pattern5match:1;
 235         u32 pattern4match:1;
 236         u32 pattern3match:1;
 237         u32 pattern2match:1;
 238         u32 pattern1match:1;
 239         u32 pattern0match:1;
 240 #endif
 241         u32 tsfl;
 242 #if 0
 243         u32 bassn:12;
 244         u32 bavld:1;
 245         u32 reserved3:19;
 246 #endif
 247 };
 248
 249 struct rtl8xxxu_rxdesc24 {
 250 #ifdef __LITTLE_ENDIAN
 251         u32 pktlen:14;
 252         u32 crc32:1;
 253         u32 icverr:1;
 254         u32 drvinfo_sz:4;
 255         u32 security:3;
 256         u32 qos:1;
 257         u32 shift:2;
 258         u32 phy_stats:1;
 259         u32 swdec:1;
 260         u32 ls:1;
 261         u32 fs:1;
 262         u32 eor:1;
 263         u32 own:1;
 264
 265         u32 macid:7;
 266         u32 dummy1_0:1;
 267         u32 tid:4;
 268         u32 dummy1_1:1;
 269         u32 amsdu:1;
 270         u32 rxid_match:1;
 271         u32 paggr:1;
 272         u32 a1fit:4;    /* 16 */
 273         u32 chkerr:1;
 274         u32 ipver:1;
 275         u32 tcpudp:1;
 276         u32 chkvld:1;
 277         u32 pam:1;
 278         u32 pwr:1;
 279         u32 more_data:1;
 280         u32 more_frag:1;
 281         u32 type:2;
 282         u32 mc:1;
 283         u32 bc:1;
 284
 285         u32 seq:12;
 286         u32 frag:4;
 287         u32 rx_is_qos:1;        /* 16 */
 288         u32 dummy2_0:1;
 289         u32 wlanhd_iv_len:6;
 290         u32 dummy2_1:4;
 291         u32 rpt_sel:1;
 292         u32 dummy2_2:3;
 293
 294         u32 rxmcs:7;
 295         u32 dummy3_0:3;
 296         u32 htc:1;
 297         u32 eosp:1;
 298         u32 bssidfit:2;
 299         u32 dummy3_1:2;
 300         u32 usb_agg_pktnum:8;   /* 16 */
 301         u32 dummy3_2:5;
 302         u32 pattern_match:1;
 303         u32 unicast_match:1;
 304         u32 magic_match:1;
 305
 306         u32 splcp:1;
 307         u32 ldcp:1;
 308         u32 stbc:1;
 309         u32 dummy4_0:1;
 310         u32 bw:2;
 311         u32 dummy4_1:26;
 312 #else
 313         u32 own:1;
 314         u32 eor:1;
 315         u32 fs:1;
 316         u32 ls:1;
 317         u32 swdec:1;
 318         u32 phy_stats:1;
 319         u32 shift:2;
 320         u32 qos:1;
 321         u32 security:3;
 322         u32 drvinfo_sz:4;
 323         u32 icverr:1;
 324         u32 crc32:1;
 325         u32 pktlen:14;
 326
 327         u32 bc:1;
 328         u32 mc:1;
 329         u32 type:2;
 330         u32 mf:1;
 331         u32 md:1;
 332         u32 pwr:1;
 333         u32 pam:1;
 334         u32 a2fit:4;
 335         u32 a1fit:4;
 336         u32 faggr:1;
 337         u32 paggr:1;
 338         u32 amsdu:1;
 339         u32 hwrsvd:4;
 340         u32 tid:4;
 341         u32 macid:5;
 342
 343         u32 dummy2_2:3;
 344         u32 rpt_sel:1;
 345         u32 dummy2_1:4;
 346         u32 wlanhd_iv_len:6;
 347         u32 dummy2_0:1;
 348         u32 rx_is_qos:1;
 349         u32 frag:4;             /* 16 */
 350         u32 seq:12;
 351
 352         u32 magic_match:1;
 353         u32 unicast_match:1;
 354         u32 pattern_match:1;
 355         u32 dummy3_2:5;
 356         u32 usb_agg_pktnum:8;
 357         u32 dummy3_1:2;         /* 16 */
 358         u32 bssidfit:2;
 359         u32 eosp:1;
 360         u32 htc:1;
 361         u32 dummy3_0:3;
 362         u32 rxmcs:7;
 363
 364         u32 dumm4_1:26;
 365         u32 bw:2;
 366         u32 dummy4_0:1;
 367         u32 stbc:1;
 368         u32 ldcp:1;
 369         u32 splcp:1;
 370 #endif
 371         u32 tsfl;
 372 };
 373
 374 struct rtl8xxxu_txdesc32 {
 375         __le16 pkt_size;
 376         u8 pkt_offset;
 377         u8 txdw0;
 378         __le32 txdw1;
 379         __le32 txdw2;
 380         __le32 txdw3;
 381         __le32 txdw4;
 382         __le32 txdw5;
 383         __le32 txdw6;
 384         __le16 csum;
 385         __le16 txdw7;
 386 };
 387
 388 struct rtl8xxxu_txdesc40 {
 389         __le16 pkt_size;
 390         u8 pkt_offset;
 391         u8 txdw0;
 392         __le32 txdw1;
 393         __le32 txdw2;
 394         __le32 txdw3;
 395         __le32 txdw4;
 396         __le32 txdw5;
 397         __le32 txdw6;
 398         __le16 csum;
 399         __le16 txdw7;
 400         __le32 txdw8;
 401         __le32 txdw9;
 402 };
 403
 404 /*  CCK Rates, TxHT = 0 */
 405 #define DESC_RATE_1M                    0x00
 406 #define DESC_RATE_2M                    0x01
 407 #define DESC_RATE_5_5M                  0x02
 408 #define DESC_RATE_11M                   0x03
 409
 410 /*  OFDM Rates, TxHT = 0 */
 411 #define DESC_RATE_6M                    0x04
 412 #define DESC_RATE_9M                    0x05
 413 #define DESC_RATE_12M                   0x06
 414 #define DESC_RATE_18M                   0x07
 415 #define DESC_RATE_24M                   0x08
 416 #define DESC_RATE_36M                   0x09
 417 #define DESC_RATE_48M                   0x0a
 418 #define DESC_RATE_54M                   0x0b
 419
 420 /*  MCS Rates, TxHT = 1 */
 421 #define DESC_RATE_MCS0                  0x0c
 422 #define DESC_RATE_MCS1                  0x0d
 423 #define DESC_RATE_MCS2                  0x0e
 424 #define DESC_RATE_MCS3                  0x0f
 425 #define DESC_RATE_MCS4                  0x10
 426 #define DESC_RATE_MCS5                  0x11
 427 #define DESC_RATE_MCS6                  0x12
 428 #define DESC_RATE_MCS7                  0x13
 429 #define DESC_RATE_MCS8                  0x14
 430 #define DESC_RATE_MCS9                  0x15
 431 #define DESC_RATE_MCS10                 0x16
 432 #define DESC_RATE_MCS11                 0x17
 433 #define DESC_RATE_MCS12                 0x18
 434 #define DESC_RATE_MCS13                 0x19
 435 #define DESC_RATE_MCS14                 0x1a
 436 #define DESC_RATE_MCS15                 0x1b
 437 #define DESC_RATE_MCS15_SG              0x1c
 438 #define DESC_RATE_MCS32                 0x20
 439
 440 #define TXDESC_OFFSET_SZ                0
 441 #define TXDESC_OFFSET_SHT               16
 442 #if 0
 443 #define TXDESC_BMC                      BIT(24)
 444 #define TXDESC_LSG                      BIT(26)
 445 #define TXDESC_FSG                      BIT(27)
 446 #define TXDESC_OWN                      BIT(31)
 447 #else
 448 #define TXDESC_BROADMULTICAST           BIT(0)
 449 #define TXDESC_HTC                      BIT(1)
 450 #define TXDESC_LAST_SEGMENT             BIT(2)
 451 #define TXDESC_FIRST_SEGMENT            BIT(3)
 452 #define TXDESC_LINIP                    BIT(4)
 453 #define TXDESC_NO_ACM                   BIT(5)
 454 #define TXDESC_GF                       BIT(6)
 455 #define TXDESC_OWN                      BIT(7)
 456 #endif
 457
 458 /* Word 1 */
 459 /*
 460  * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are
 461  * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid.
 462  */
 463 #define TXDESC_PKT_OFFSET_SZ            0
 464 #define TXDESC32_AGG_ENABLE             BIT(5)
 465 #define TXDESC32_AGG_BREAK              BIT(6)
 466 #define TXDESC40_MACID_SHIFT            0
 467 #define TXDESC40_MACID_MASK             0x00f0
 468 #define TXDESC_QUEUE_SHIFT              8
 469 #define TXDESC_QUEUE_MASK               0x1f00
 470 #define TXDESC_QUEUE_BK                 0x2
 471 #define TXDESC_QUEUE_BE                 0x0
 472 #define TXDESC_QUEUE_VI                 0x5
 473 #define TXDESC_QUEUE_VO                 0x7
 474 #define TXDESC_QUEUE_BEACON             0x10
 475 #define TXDESC_QUEUE_HIGH               0x11
 476 #define TXDESC_QUEUE_MGNT               0x12
 477 #define TXDESC_QUEUE_CMD                0x13
 478 #define TXDESC_QUEUE_MAX                (TXDESC_QUEUE_CMD + 1)
 479 #define TXDESC40_RDG_NAV_EXT            BIT(13)
 480 #define TXDESC40_LSIG_TXOP_ENABLE       BIT(14)
 481 #define TXDESC40_PIFS                   BIT(15)
 482
 483 #define DESC_RATE_ID_SHIFT              16
 484 #define DESC_RATE_ID_MASK               0xf
 485 #define TXDESC_NAVUSEHDR                BIT(20)
 486 #define TXDESC_SEC_RC4                  0x00400000
 487 #define TXDESC_SEC_AES                  0x00c00000
 488 #define TXDESC_PKT_OFFSET_SHIFT         26
 489 #define TXDESC_AGG_EN                   BIT(29)
 490 #define TXDESC_HWPC                     BIT(31)
 491
 492 /* Word 2 */
 493 #define TXDESC40_PAID_SHIFT             0
 494 #define TXDESC40_PAID_MASK              0x1ff
 495 #define TXDESC40_CCA_RTS_SHIFT          10
 496 #define TXDESC40_CCA_RTS_MASK           0xc00
 497 #define TXDESC40_AGG_ENABLE             BIT(12)
 498 #define TXDESC40_RDG_ENABLE             BIT(13)
 499 #define TXDESC40_AGG_BREAK              BIT(16)
 500 #define TXDESC40_MORE_FRAG              BIT(17)
 501 #define TXDESC40_RAW                    BIT(18)
 502 #define TXDESC32_ACK_REPORT             BIT(19)
 503 #define TXDESC40_SPE_RPT                BIT(19)
 504 #define TXDESC_AMPDU_DENSITY_SHIFT      20
 505 #define TXDESC40_BT_INT                 BIT(23)
 506 #define TXDESC40_GID_SHIFT              24
 507
 508 /* Word 3 */
 509 #define TXDESC40_USE_DRIVER_RATE        BIT(8)
 510 #define TXDESC40_CTS_SELF_ENABLE        BIT(11)
 511 #define TXDESC40_RTS_CTS_ENABLE         BIT(12)
 512 #define TXDESC40_HW_RTS_ENABLE          BIT(13)
 513 #define TXDESC32_SEQ_SHIFT              16
 514 #define TXDESC32_SEQ_MASK               0x0fff0000
 515
 516 /* Word 4 */
 517 #define TXDESC32_RTS_RATE_SHIFT         0
 518 #define TXDESC32_RTS_RATE_MASK          0x3f
 519 #define TXDESC32_QOS                    BIT(6)
 520 #define TXDESC32_HW_SEQ_ENABLE          BIT(7)
 521 #define TXDESC32_USE_DRIVER_RATE        BIT(8)
 522 #define TXDESC_DISABLE_DATA_FB          BIT(10)
 523 #define TXDESC32_CTS_SELF_ENABLE        BIT(11)
 524 #define TXDESC32_RTS_CTS_ENABLE         BIT(12)
 525 #define TXDESC32_HW_RTS_ENABLE          BIT(13)
 526 #define TXDESC_PRIME_CH_OFF_LOWER       BIT(20)
 527 #define TXDESC_PRIME_CH_OFF_UPPER       BIT(21)
 528 #define TXDESC32_SHORT_PREAMBLE         BIT(24)
 529 #define TXDESC_DATA_BW                  BIT(25)
 530 #define TXDESC_RTS_DATA_BW              BIT(27)
 531 #define TXDESC_RTS_PRIME_CH_OFF_LOWER   BIT(28)
 532 #define TXDESC_RTS_PRIME_CH_OFF_UPPER   BIT(29)
 533 #define TXDESC40_DATA_RATE_FB_SHIFT     8
 534 #define TXDESC40_DATA_RATE_FB_MASK      0x00001f00
 535 #define TXDESC40_RETRY_LIMIT_ENABLE     BIT(17)
 536 #define TXDESC40_RETRY_LIMIT_SHIFT      18
 537 #define TXDESC40_RETRY_LIMIT_MASK       0x00fc0000
 538 #define TXDESC40_RTS_RATE_SHIFT         24
 539 #define TXDESC40_RTS_RATE_MASK          0x3f000000
 540
 541 /* Word 5 */
 542 #define TXDESC40_SHORT_PREAMBLE         BIT(4)
 543 #define TXDESC32_SHORT_GI               BIT(6)
 544 #define TXDESC_CCX_TAG                  BIT(7)
 545 #define TXDESC32_RETRY_LIMIT_ENABLE     BIT(17)
 546 #define TXDESC32_RETRY_LIMIT_SHIFT      18
 547 #define TXDESC32_RETRY_LIMIT_MASK       0x00fc0000
 548
 549 /* Word 6 */
 550 #define TXDESC_MAX_AGG_SHIFT            11
 551
 552 /* Word 8 */
 553 #define TXDESC40_HW_SEQ_ENABLE          BIT(15)
 554
 555 /* Word 9 */
 556 #define TXDESC40_SEQ_SHIFT              12
 557 #define TXDESC40_SEQ_MASK               0x00fff000
 558
 559 struct phy_rx_agc_info {
 560 #ifdef __LITTLE_ENDIAN
 561         u8      gain:7, trsw:1;
 562 #else
 563         u8      trsw:1, gain:7;
 564 #endif
 565 };
 566
 567 struct rtl8723au_phy_stats {
 568         struct phy_rx_agc_info path_agc[RTL8723A_MAX_RF_PATHS];
 569         u8      ch_corr[RTL8723A_MAX_RF_PATHS];
 570         u8      cck_sig_qual_ofdm_pwdb_all;
 571         u8      cck_agc_rpt_ofdm_cfosho_a;
 572         u8      cck_rpt_b_ofdm_cfosho_b;
 573         u8      reserved_1;
 574         u8      noise_power_db_msb;
 575         u8      path_cfotail[RTL8723A_MAX_RF_PATHS];
 576         u8      pcts_mask[RTL8723A_MAX_RF_PATHS];
 577         s8      stream_rxevm[RTL8723A_MAX_RF_PATHS];
 578         u8      path_rxsnr[RTL8723A_MAX_RF_PATHS];
 579         u8      noise_power_db_lsb;
 580         u8      reserved_2[3];
 581         u8      stream_csi[RTL8723A_MAX_RF_PATHS];
 582         u8      stream_target_csi[RTL8723A_MAX_RF_PATHS];
 583         s8      sig_evm;
 584         u8      reserved_3;
 585
 586 #ifdef __LITTLE_ENDIAN
 587         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 588         u8      sgi_en:1;
 589         u8      rxsc:2;
 590         u8      idle_long:1;
 591         u8      r_ant_train_en:1;
 592         u8      antenna_select_b:1;
 593         u8      antenna_select:1;
 594 #else   /*  _BIG_ENDIAN_ */
 595         u8      antenna_select:1;
 596         u8      antenna_select_b:1;
 597         u8      r_ant_train_en:1;
 598         u8      idle_long:1;
 599         u8      rxsc:2;
 600         u8      sgi_en:1;
 601         u8      antsel_rx_keep_2:1;     /* ex_intf_flg:1; */
 602 #endif
 603 };
 604
 605 /*
 606  * Regs to backup
 607  */
 608 #define RTL8XXXU_ADDA_REGS              16
 609 #define RTL8XXXU_MAC_REGS               4
 610 #define RTL8XXXU_BB_REGS                9
 611
 612 struct rtl8xxxu_firmware_header {
 613         __le16  signature;              /*  92C0: test chip; 92C,
 614                                             88C0: test chip;
 615                                             88C1: MP A-cut;
 616                                             92C1: MP A-cut */
 617         u8      category;               /*  AP/NIC and USB/PCI */
 618         u8      function;
 619
 620         __le16  major_version;          /*  FW Version */
 621         u8      minor_version;          /*  FW Subversion, default 0x00 */
 622         u8      reserved1;
 623
 624         u8      month;                  /*  Release time Month field */
 625         u8      date;                   /*  Release time Date field */
 626         u8      hour;                   /*  Release time Hour field */
 627         u8      minute;                 /*  Release time Minute field */
 628
 629         __le16  ramcodesize;            /*  Size of RAM code */
 630         u16     reserved2;
 631
 632         __le32  svn_idx;                /*  SVN entry index */
 633         u32     reserved3;
 634
 635         u32     reserved4;
 636         u32     reserved5;
 637
 638         u8      data[0];
 639 };
 640
 641 /*
 642  * 8723au/8192cu/8188ru required base power index offset tables.
 643  */
 644 struct rtl8xxxu_power_base {
 645         u32 reg_0e00;
 646         u32 reg_0e04;
 647         u32 reg_0e08;
 648         u32 reg_086c;
 649
 650         u32 reg_0e10;
 651         u32 reg_0e14;
 652         u32 reg_0e18;
 653         u32 reg_0e1c;
 654
 655         u32 reg_0830;
 656         u32 reg_0834;
 657         u32 reg_0838;
 658         u32 reg_086c_2;
 659
 660         u32 reg_083c;
 661         u32 reg_0848;
 662         u32 reg_084c;
 663         u32 reg_0868;
 664 };
 665
 666 /*
 667  * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14
 668  */
 669 struct rtl8723au_idx {
 670 #ifdef __LITTLE_ENDIAN
 671         int     a:4;
 672         int     b:4;
 673 #else
 674         int     b:4;
 675         int     a:4;
 676 #endif
 677 } __attribute__((packed));
 678
 679 struct rtl8723au_efuse {
 680         __le16 rtl_id;
 681         u8 res0[0xe];
 682         u8 cck_tx_power_index_A[3];     /* 0x10 */
 683         u8 cck_tx_power_index_B[3];
 684         u8 ht40_1s_tx_power_index_A[3]; /* 0x16 */
 685         u8 ht40_1s_tx_power_index_B[3];
 686         /*
 687          * The following entries are half-bytes split as:
 688          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
 689          */
 690         struct rtl8723au_idx ht20_tx_power_index_diff[3];
 691         struct rtl8723au_idx ofdm_tx_power_index_diff[3];
 692         struct rtl8723au_idx ht40_max_power_offset[3];
 693         struct rtl8723au_idx ht20_max_power_offset[3];
 694         u8 channel_plan;                /* 0x28 */
 695         u8 tssi_a;
 696         u8 thermal_meter;
 697         u8 rf_regulatory;
 698         u8 rf_option_2;
 699         u8 rf_option_3;
 700         u8 rf_option_4;
 701         u8 res7;
 702         u8 version                      /* 0x30 */;
 703         u8 customer_id_major;
 704         u8 customer_id_minor;
 705         u8 xtal_k;
 706         u8 chipset;                     /* 0x34 */
 707         u8 res8[0x82];
 708         u8 vid;                         /* 0xb7 */
 709         u8 res9;
 710         u8 pid;                         /* 0xb9 */
 711         u8 res10[0x0c];
 712         u8 mac_addr[ETH_ALEN];          /* 0xc6 */
 713         u8 res11[2];
 714         u8 vendor_name[7];
 715         u8 res12[2];
 716         u8 device_name[0x29];           /* 0xd7 */
 717 };
 718
 719 struct rtl8192cu_efuse {
 720         __le16 rtl_id;
 721         __le16 hpon;
 722         u8 res0[2];
 723         __le16 clk;
 724         __le16 testr;
 725         __le16 vid;
 726         __le16 did;
 727         __le16 svid;
 728         __le16 smid;                                            /* 0x10 */
 729         u8 res1[4];
 730         u8 mac_addr[ETH_ALEN];                                  /* 0x16 */
 731         u8 res2[2];
 732         u8 vendor_name[7];
 733         u8 res3[3];
 734         u8 device_name[0x14];                                   /* 0x28 */
 735         u8 res4[0x1e];                                          /* 0x3c */
 736         u8 cck_tx_power_index_A[3];                             /* 0x5a */
 737         u8 cck_tx_power_index_B[3];
 738         u8 ht40_1s_tx_power_index_A[3];                         /* 0x60 */
 739         u8 ht40_1s_tx_power_index_B[3];
 740         /*
 741          * The following entries are half-bytes split as:
 742          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
 743          */
 744         struct rtl8723au_idx ht40_2s_tx_power_index_diff[3];
 745         struct rtl8723au_idx ht20_tx_power_index_diff[3];       /* 0x69 */
 746         struct rtl8723au_idx ofdm_tx_power_index_diff[3];
 747         struct rtl8723au_idx ht40_max_power_offset[3];          /* 0x6f */
 748         struct rtl8723au_idx ht20_max_power_offset[3];
 749         u8 channel_plan;                                        /* 0x75 */
 750         u8 tssi_a;
 751         u8 tssi_b;
 752         u8 thermal_meter;       /* xtal_k */                    /* 0x78 */
 753         u8 rf_regulatory;
 754         u8 rf_option_2;
 755         u8 rf_option_3;
 756         u8 rf_option_4;
 757         u8 res5[1];                                             /* 0x7d */
 758         u8 version;
 759         u8 customer_id;
 760 };
 761
 762 struct rtl8723bu_pwr_idx {
 763 #ifdef __LITTLE_ENDIAN
 764         int     ht20:4;
 765         int     ht40:4;
 766         int     ofdm:4;
 767         int     cck:4;
 768 #else
 769         int     cck:4;
 770         int     ofdm:4;
 771         int     ht40:4;
 772         int     ht20:4;
 773 #endif
 774 } __attribute__((packed));
 775
 776 struct rtl8723bu_efuse_tx_power {
 777         u8 cck_base[6];
 778         u8 ht40_base[5];
 779         struct rtl8723au_idx ht20_ofdm_1s_diff;
 780         struct rtl8723bu_pwr_idx pwr_diff[3];
 781         u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
 782 };
 783
 784 struct rtl8723bu_efuse {
 785         __le16 rtl_id;
 786         u8 res0[0x0e];
 787         struct rtl8723bu_efuse_tx_power tx_power_index_A;       /* 0x10 */
 788         struct rtl8723bu_efuse_tx_power tx_power_index_B;       /* 0x3a */
 789         struct rtl8723bu_efuse_tx_power tx_power_index_C;       /* 0x64 */
 790         struct rtl8723bu_efuse_tx_power tx_power_index_D;       /* 0x8e */
 791         u8 channel_plan;                /* 0xb8 */
 792         u8 xtal_k;
 793         u8 thermal_meter;
 794         u8 iqk_lck;
 795         u8 pa_type;                     /* 0xbc */
 796         u8 lna_type_2g;                 /* 0xbd */
 797         u8 res2[3];
 798         u8 rf_board_option;
 799         u8 rf_feature_option;
 800         u8 rf_bt_setting;
 801         u8 eeprom_version;
 802         u8 eeprom_customer_id;
 803         u8 res3[2];
 804         u8 tx_pwr_calibrate_rate;
 805         u8 rf_antenna_option;           /* 0xc9 */
 806         u8 rfe_option;
 807         u8 res4[9];
 808         u8 usb_optional_function;
 809         u8 res5[0x1e];
 810         u8 res6[2];
 811         u8 serial[0x0b];                /* 0xf5 */
 812         u8 vid;                         /* 0x100 */
 813         u8 res7;
 814         u8 pid;
 815         u8 res8[4];
 816         u8 mac_addr[ETH_ALEN];          /* 0x107 */
 817         u8 res9[2];
 818         u8 vendor_name[0x07];
 819         u8 res10[2];
 820         u8 device_name[0x14];
 821         u8 res11[0xcf];
 822         u8 package_type;                /* 0x1fb */
 823         u8 res12[0x4];
 824 };
 825
 826 struct rtl8192eu_efuse_tx_power {
 827         u8 cck_base[6];
 828         u8 ht40_base[5];
 829         struct rtl8723au_idx ht20_ofdm_1s_diff;
 830         struct rtl8723bu_pwr_idx pwr_diff[3];
 831         u8 dummy5g[24]; /* max channel group (14) + power diff offset (10) */
 832 };
 833
 834 struct rtl8192eu_efuse {
 835         __le16 rtl_id;
 836         u8 res0[0x0e];
 837         struct rtl8192eu_efuse_tx_power tx_power_index_A;       /* 0x10 */
 838         struct rtl8192eu_efuse_tx_power tx_power_index_B;       /* 0x3a */
 839         u8 res2[0x54];
 840         u8 channel_plan;                /* 0xb8 */
 841         u8 xtal_k;
 842         u8 thermal_meter;
 843         u8 iqk_lck;
 844         u8 pa_type;                     /* 0xbc */
 845         u8 lna_type_2g;                 /* 0xbd */
 846         u8 res3[1];
 847         u8 lna_type_5g;                 /* 0xbf */
 848         u8 res4[1];
 849         u8 rf_board_option;
 850         u8 rf_feature_option;
 851         u8 rf_bt_setting;
 852         u8 eeprom_version;
 853         u8 eeprom_customer_id;
 854         u8 res5[3];
 855         u8 rf_antenna_option;           /* 0xc9 */
 856         u8 res6[6];
 857         u8 vid;                         /* 0xd0 */
 858         u8 res7[1];
 859         u8 pid;                         /* 0xd2 */
 860         u8 res8[1];
 861         u8 usb_optional_function;
 862         u8 res9[2];
 863         u8 mac_addr[ETH_ALEN];          /* 0xd7 */
 864         u8 res10[2];
 865         u8 vendor_name[7];
 866         u8 res11[2];
 867         u8 device_name[0x0b];           /* 0xe8 */
 868         u8 res12[2];
 869         u8 serial[0x0b];                /* 0xf5 */
 870         u8 res13[0x30];
 871         u8 unknown[0x0d];               /* 0x130 */
 872         u8 res14[0xc3];
 873 };
 874
 875 struct rtl8xxxu_reg8val {
 876         u16 reg;
 877         u8 val;
 878 };
 879
 880 struct rtl8xxxu_reg32val {
 881         u16 reg;
 882         u32 val;
 883 };
 884
 885 struct rtl8xxxu_rfregval {
 886         u8 reg;
 887         u32 val;
 888 };
 889
 890 enum rtl8xxxu_rfpath {
 891         RF_A = 0,
 892         RF_B = 1,
 893 };
 894
 895 struct rtl8xxxu_rfregs {
 896         u16 hssiparm1;
 897         u16 hssiparm2;
 898         u16 lssiparm;
 899         u16 hspiread;
 900         u16 lssiread;
 901         u16 rf_sw_ctrl;
 902 };
 903
 904 #define H2C_MAX_MBOX                    4
 905 #define H2C_EXT                         BIT(7)
 906 #define  H2C_JOIN_BSS_DISCONNECT        0
 907 #define  H2C_JOIN_BSS_CONNECT           1
 908
 909 /*
 910  * H2C (firmware) commands differ between the older generation chips
 911  * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu,
 912  * 8192[de]u, 8192eu, and 8812.
 913  */
 914 enum h2c_cmd_8723a {
 915         H2C_SET_POWER_MODE = 1,
 916         H2C_JOIN_BSS_REPORT = 2,
 917         H2C_SET_RSSI = 5,
 918         H2C_SET_RATE_MASK = (6 | H2C_EXT),
 919 };
 920
 921 enum h2c_cmd_8723b {
 922         /*
 923          * Common Class: 000
 924          */
 925         H2C_8723B_RSVD_PAGE = 0x00,
 926         H2C_8723B_MEDIA_STATUS_RPT = 0x01,
 927         H2C_8723B_SCAN_ENABLE = 0x02,
 928         H2C_8723B_KEEP_ALIVE = 0x03,
 929         H2C_8723B_DISCON_DECISION = 0x04,
 930         H2C_8723B_PSD_OFFLOAD = 0x05,
 931         H2C_8723B_AP_OFFLOAD = 0x08,
 932         H2C_8723B_BCN_RSVDPAGE = 0x09,
 933         H2C_8723B_PROBERSP_RSVDPAGE = 0x0A,
 934         H2C_8723B_FCS_RSVDPAGE = 0x10,
 935         H2C_8723B_FCS_INFO = 0x11,
 936         H2C_8723B_AP_WOW_GPIO_CTRL = 0x13,
 937
 938         /*
 939          * PoweSave Class: 001
 940          */
 941         H2C_8723B_SET_PWR_MODE = 0x20,
 942         H2C_8723B_PS_TUNING_PARA = 0x21,
 943         H2C_8723B_PS_TUNING_PARA2 = 0x22,
 944         H2C_8723B_P2P_LPS_PARAM = 0x23,
 945         H2C_8723B_P2P_PS_OFFLOAD = 0x24,
 946         H2C_8723B_PS_SCAN_ENABLE = 0x25,
 947         H2C_8723B_SAP_PS_ = 0x26,
 948         H2C_8723B_INACTIVE_PS_ = 0x27,
 949         H2C_8723B_FWLPS_IN_IPS_ = 0x28,
 950
 951         /*
 952          * Dynamic Mechanism Class: 010
 953          */
 954         H2C_8723B_MACID_CFG_RAID = 0x40,
 955         H2C_8723B_TXBF = 0x41,
 956         H2C_8723B_RSSI_SETTING = 0x42,
 957         H2C_8723B_AP_REQ_TXRPT = 0x43,
 958         H2C_8723B_INIT_RATE_COLLECT = 0x44,
 959
 960         /*
 961          * BT Class: 011
 962          */
 963         H2C_8723B_B_TYPE_TDMA = 0x60,
 964         H2C_8723B_BT_INFO = 0x61,
 965         H2C_8723B_FORCE_BT_TXPWR = 0x62,
 966         H2C_8723B_BT_IGNORE_WLANACT = 0x63,
 967         H2C_8723B_DAC_SWING_VALUE = 0x64,
 968         H2C_8723B_ANT_SEL_RSV = 0x65,
 969         H2C_8723B_WL_OPMODE = 0x66,
 970         H2C_8723B_BT_MP_OPER = 0x67,
 971         H2C_8723B_BT_CONTROL = 0x68,
 972         H2C_8723B_BT_WIFI_CTRL = 0x69,
 973         H2C_8723B_BT_FW_PATCH = 0x6a,
 974         H2C_8723B_BT_WLAN_CALIBRATION = 0x6d,
 975         H2C_8723B_BT_GRANT = 0x6e,
 976
 977         /*
 978          * WOWLAN Class: 100
 979          */
 980         H2C_8723B_WOWLAN = 0x80,
 981         H2C_8723B_REMOTE_WAKE_CTRL = 0x81,
 982         H2C_8723B_AOAC_GLOBAL_INFO = 0x82,
 983         H2C_8723B_AOAC_RSVD_PAGE = 0x83,
 984         H2C_8723B_AOAC_RSVD_PAGE2 = 0x84,
 985         H2C_8723B_D0_SCAN_OFFLOAD_CTRL = 0x85,
 986         H2C_8723B_D0_SCAN_OFFLOAD_INFO = 0x86,
 987         H2C_8723B_CHNL_SWITCH_OFFLOAD = 0x87,
 988
 989         H2C_8723B_RESET_TSF = 0xC0,
 990 };
 991
 992
 993 struct h2c_cmd {
 994         union {
 995                 struct {
 996                         u8 cmd;
 997                         u8 data[7];
 998                 } __packed cmd;
 999                 struct {
1000                         __le32 data;
1001                         __le16 ext;
1002                 } __packed raw;
1003                 struct {
1004                         __le32 data;
1005                         __le32 ext;
1006                 } __packed raw_wide;
1007                 struct {
1008                         u8 cmd;
1009                         u8 data;
1010                 } __packed joinbss;
1011                 struct {
1012                         u8 cmd;
1013                         __le16 mask_hi;
1014                         u8 arg;
1015                         __le16 mask_lo;
1016                 } __packed ramask;
1017                 struct {
1018                         u8 cmd;
1019                         u8 parm;
1020                         u8 macid;
1021                         u8 macid_end;
1022                 } __packed media_status_rpt;
1023                 struct {
1024                         u8 cmd;
1025                         u8 macid;
1026                         /*
1027                          * [0:4] - RAID
1028                          * [7]   - SGI
1029                          */
1030                         u8 data1;
1031                         /*
1032                          * [0:1] - Bandwidth
1033                          * [3]   - No Update
1034                          * [4:5] - VHT enable
1035                          * [6]   - DISPT
1036                          * [7]   - DISRA
1037                          */
1038                         u8 data2;
1039                         u8 ramask0;
1040                         u8 ramask1;
1041                         u8 ramask2;
1042                         u8 ramask3;
1043                 } __packed b_macid_cfg;
1044                 struct {
1045                         u8 cmd;
1046                         u8 data1;
1047                         u8 data2;
1048                         u8 data3;
1049                         u8 data4;
1050                         u8 data5;
1051                 } __packed b_type_dma;
1052                 struct {
1053                         u8 cmd;
1054                         u8 data;
1055                 } __packed bt_info;
1056                 struct {
1057                         u8 cmd;
1058                         u8 operreq;
1059                         u8 opcode;
1060                         u8 data;
1061                         u8 addr;
1062                 } __packed bt_mp_oper;
1063                 struct {
1064                         u8 cmd;
1065                         u8 data;
1066                 } __packed bt_wlan_calibration;
1067                 struct {
1068                         u8 cmd;
1069                         u8 data;
1070                 } __packed ignore_wlan;
1071                 struct {
1072                         u8 cmd;
1073                         u8 ant_inverse;
1074                         u8 int_switch_type;
1075                 } __packed ant_sel_rsv;
1076                 struct {
1077                         u8 cmd;
1078                         u8 data;
1079                 } __packed bt_grant;
1080         };
1081 };
1082
1083 enum c2h_evt_8723b {
1084         C2H_8723B_DEBUG = 0,
1085         C2H_8723B_TSF = 1,
1086         C2H_8723B_AP_RPT_RSP = 2,
1087         C2H_8723B_CCX_TX_RPT = 3,
1088         C2H_8723B_BT_RSSI = 4,
1089         C2H_8723B_BT_OP_MODE = 5,
1090         C2H_8723B_EXT_RA_RPT = 6,
1091         C2H_8723B_BT_INFO = 9,
1092         C2H_8723B_HW_INFO_EXCH = 0x0a,
1093         C2H_8723B_BT_MP_INFO = 0x0b,
1094         C2H_8723B_RA_REPORT = 0x0c,
1095         C2H_8723B_FW_DEBUG = 0xff,
1096 };
1097
1098 enum bt_info_src_8723b {
1099         BT_INFO_SRC_8723B_WIFI_FW = 0x0,
1100         BT_INFO_SRC_8723B_BT_RSP = 0x1,
1101         BT_INFO_SRC_8723B_BT_ACTIVE_SEND = 0x2,
1102 };
1103
1104 enum bt_mp_oper_opcode_8723b {
1105         BT_MP_OP_GET_BT_VERSION = 0x00,
1106         BT_MP_OP_RESET = 0x01,
1107         BT_MP_OP_TEST_CTRL = 0x02,
1108         BT_MP_OP_SET_BT_MODE = 0x03,
1109         BT_MP_OP_SET_CHNL_TX_GAIN = 0x04,
1110         BT_MP_OP_SET_PKT_TYPE_LEN = 0x05,
1111         BT_MP_OP_SET_PKT_CNT_L_PL_TYPE = 0x06,
1112         BT_MP_OP_SET_PKT_CNT_H_PKT_INTV = 0x07,
1113         BT_MP_OP_SET_PKT_HEADER = 0x08,
1114         BT_MP_OP_SET_WHITENCOEFF = 0x09,
1115         BT_MP_OP_SET_BD_ADDR_L = 0x0a,
1116         BT_MP_OP_SET_BD_ADDR_H = 0x0b,
1117         BT_MP_OP_WRITE_REG_ADDR = 0x0c,
1118         BT_MP_OP_WRITE_REG_VALUE = 0x0d,
1119         BT_MP_OP_GET_BT_STATUS = 0x0e,
1120         BT_MP_OP_GET_BD_ADDR_L = 0x0f,
1121         BT_MP_OP_GET_BD_ADDR_H = 0x10,
1122         BT_MP_OP_READ_REG = 0x11,
1123         BT_MP_OP_SET_TARGET_BD_ADDR_L = 0x12,
1124         BT_MP_OP_SET_TARGET_BD_ADDR_H = 0x13,
1125         BT_MP_OP_SET_TX_POWER_CALIBRATION = 0x14,
1126         BT_MP_OP_GET_RX_PKT_CNT_L = 0x15,
1127         BT_MP_OP_GET_RX_PKT_CNT_H = 0x16,
1128         BT_MP_OP_GET_RX_ERROR_BITS_L = 0x17,
1129         BT_MP_OP_GET_RX_ERROR_BITS_H = 0x18,
1130         BT_MP_OP_GET_RSSI = 0x19,
1131         BT_MP_OP_GET_CFO_HDR_QUALITY_L = 0x1a,
1132         BT_MP_OP_GET_CFO_HDR_QUALITY_H = 0x1b,
1133         BT_MP_OP_GET_TARGET_BD_ADDR_L = 0x1c,
1134         BT_MP_OP_GET_TARGET_BD_ADDR_H = 0x1d,
1135         BT_MP_OP_GET_AFH_MAP_L = 0x1e,
1136         BT_MP_OP_GET_AFH_MAP_M = 0x1f,
1137         BT_MP_OP_GET_AFH_MAP_H = 0x20,
1138         BT_MP_OP_GET_AFH_STATUS = 0x21,
1139         BT_MP_OP_SET_TRACKING_INTERVAL = 0x22,
1140         BT_MP_OP_SET_THERMAL_METER = 0x23,
1141         BT_MP_OP_ENABLE_CFO_TRACKING = 0x24,
1142 };
1143
1144 struct rtl8723bu_c2h {
1145         u8 id;
1146         u8 seq;
1147         union {
1148                 struct {
1149                         u8 payload[0];
1150                 } __packed raw;
1151                 struct {
1152                         u8 ext_id;
1153                         u8 status:4;
1154                         u8 retlen:4;
1155                         u8 opcode_ver:4;
1156                         u8 req_num:4;
1157                         u8 payload[2];
1158                 } __packed bt_mp_info;
1159                 struct {
1160                         u8 response_source:4;
1161                         u8 dummy0_0:4;
1162
1163                         u8 bt_info;
1164
1165                         u8 retry_count:4;
1166                         u8 dummy2_0:1;
1167                         u8 bt_page:1;
1168                         u8 tx_rx_mask:1;
1169                         u8 dummy2_2:1;
1170
1171                         u8 rssi;
1172
1173                         u8 basic_rate:1;
1174                         u8 bt_has_reset:1;
1175                         u8 dummy4_1:1;;
1176                         u8 ignore_wlan:1;
1177                         u8 auto_report:1;
1178                         u8 dummy4_2:3;
1179
1180                         u8 a4;
1181                         u8 a5;
1182                 } __packed bt_info;
1183                 struct {
1184                         u8 rate:7;
1185                         u8 dummy0_0:1;
1186                         u8 macid;
1187                         u8 ldpc:1;
1188                         u8 txbf:1;
1189                         u8 noisy_state:1;
1190                         u8 dummy2_0:5;
1191                         u8 dummy3_0;
1192                 } __packed ra_report;
1193         };
1194 };
1195
1196 struct rtl8xxxu_fileops;
1197
1198 struct rtl8xxxu_priv {
1199         struct ieee80211_hw *hw;
1200         struct usb_device *udev;
1201         struct rtl8xxxu_fileops *fops;
1202
1203         spinlock_t tx_urb_lock;
1204         struct list_head tx_urb_free_list;
1205         int tx_urb_free_count;
1206         bool tx_stopped;
1207
1208         spinlock_t rx_urb_lock;
1209         struct list_head rx_urb_pending_list;
1210         int rx_urb_pending_count;
1211         bool shutdown;
1212         struct work_struct rx_urb_wq;
1213
1214         u8 mac_addr[ETH_ALEN];
1215         char chip_name[8];
1216         char chip_vendor[8];
1217         u8 cck_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1218         u8 cck_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1219         u8 ht40_1s_tx_power_index_A[RTL8XXXU_MAX_CHANNEL_GROUPS];
1220         u8 ht40_1s_tx_power_index_B[RTL8XXXU_MAX_CHANNEL_GROUPS];
1221         /*
1222          * The following entries are half-bytes split as:
1223          * bits 0-3: path A, bits 4-7: path B, all values 4 bits signed
1224          */
1225         struct rtl8723au_idx ht40_2s_tx_power_index_diff[
1226                 RTL8723A_CHANNEL_GROUPS];
1227         struct rtl8723au_idx ht20_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1228         struct rtl8723au_idx ofdm_tx_power_index_diff[RTL8723A_CHANNEL_GROUPS];
1229         struct rtl8723au_idx ht40_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1230         struct rtl8723au_idx ht20_max_power_offset[RTL8723A_CHANNEL_GROUPS];
1231         /*
1232          * Newer generation chips only keep power diffs per TX count,
1233          * not per channel group.
1234          */
1235         struct rtl8723au_idx ofdm_tx_power_diff[RTL8723B_TX_COUNT];
1236         struct rtl8723au_idx ht20_tx_power_diff[RTL8723B_TX_COUNT];
1237         struct rtl8723au_idx ht40_tx_power_diff[RTL8723B_TX_COUNT];
1238         struct rtl8xxxu_power_base *power_base;
1239         u32 chip_cut:4;
1240         u32 rom_rev:4;
1241         u32 is_multi_func:1;
1242         u32 has_wifi:1;
1243         u32 has_bluetooth:1;
1244         u32 enable_bluetooth:1;
1245         u32 has_gps:1;
1246         u32 hi_pa:1;
1247         u32 vendor_umc:1;
1248         u32 vendor_smic:1;
1249         u32 has_polarity_ctrl:1;
1250         u32 has_eeprom:1;
1251         u32 boot_eeprom:1;
1252         u32 usb_interrupts:1;
1253         u32 ep_tx_high_queue:1;
1254         u32 ep_tx_normal_queue:1;
1255         u32 ep_tx_low_queue:1;
1256         u32 has_xtalk:1;
1257         u32 rx_buf_aggregation:1;
1258         u8 xtalk;
1259         unsigned int pipe_interrupt;
1260         unsigned int pipe_in;
1261         unsigned int pipe_out[TXDESC_QUEUE_MAX];
1262         u8 out_ep[RTL8XXXU_OUT_ENDPOINTS];
1263         u8 ep_tx_count;
1264         u8 rf_paths;
1265         u8 rx_paths;
1266         u8 tx_paths;
1267         u32 rege94;
1268         u32 rege9c;
1269         u32 regeb4;
1270         u32 regebc;
1271         int next_mbox;
1272         int nr_out_eps;
1273
1274         struct mutex h2c_mutex;
1275
1276         struct usb_anchor rx_anchor;
1277         struct usb_anchor tx_anchor;
1278         struct usb_anchor int_anchor;
1279         struct rtl8xxxu_firmware_header *fw_data;
1280         size_t fw_size;
1281         struct mutex usb_buf_mutex;
1282         union {
1283                 __le32 val32;
1284                 __le16 val16;
1285                 u8 val8;
1286         } usb_buf;
1287         union {
1288                 u8 raw[EFUSE_MAP_LEN];
1289                 struct rtl8723au_efuse efuse8723;
1290                 struct rtl8723bu_efuse efuse8723bu;
1291                 struct rtl8192cu_efuse efuse8192;
1292                 struct rtl8192eu_efuse efuse8192eu;
1293         } efuse_wifi;
1294         u32 adda_backup[RTL8XXXU_ADDA_REGS];
1295         u32 mac_backup[RTL8XXXU_MAC_REGS];
1296         u32 bb_backup[RTL8XXXU_BB_REGS];
1297         u32 bb_recovery_backup[RTL8XXXU_BB_REGS];
1298         enum rtl8xxxu_rtl_chip rtl_chip;
1299         u8 pi_enabled:1;
1300         u8 no_pape:1;
1301         u8 int_buf[USB_INTR_CONTENT_LENGTH];
1302 };
1303
1304 struct rtl8xxxu_rx_urb {
1305         struct urb urb;
1306         struct ieee80211_hw *hw;
1307         struct list_head list;
1308 };
1309
1310 struct rtl8xxxu_tx_urb {
1311         struct urb urb;
1312         struct ieee80211_hw *hw;
1313         struct list_head list;
1314 };
1315
1316 struct rtl8xxxu_fileops {
1317         int (*parse_efuse) (struct rtl8xxxu_priv *priv);
1318         int (*load_firmware) (struct rtl8xxxu_priv *priv);
1319         int (*power_on) (struct rtl8xxxu_priv *priv);
1320         void (*power_off) (struct rtl8xxxu_priv *priv);
1321         void (*reset_8051) (struct rtl8xxxu_priv *priv);
1322         int (*llt_init) (struct rtl8xxxu_priv *priv);
1323         void (*init_phy_bb) (struct rtl8xxxu_priv *priv);
1324         int (*init_phy_rf) (struct rtl8xxxu_priv *priv);
1325         void (*phy_init_antenna_selection) (struct rtl8xxxu_priv *priv);
1326         void (*phy_iq_calibrate) (struct rtl8xxxu_priv *priv);
1327         void (*config_channel) (struct ieee80211_hw *hw);
1328         int (*parse_rx_desc) (struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1329         void (*init_aggregation) (struct rtl8xxxu_priv *priv);
1330         void (*init_statistics) (struct rtl8xxxu_priv *priv);
1331         void (*enable_rf) (struct rtl8xxxu_priv *priv);
1332         void (*disable_rf) (struct rtl8xxxu_priv *priv);
1333         void (*usb_quirks) (struct rtl8xxxu_priv *priv);
1334         void (*set_tx_power) (struct rtl8xxxu_priv *priv, int channel,
1335                               bool ht40);
1336         void (*update_rate_mask) (struct rtl8xxxu_priv *priv,
1337                                   u32 ramask, int sgi);
1338         void (*report_connect) (struct rtl8xxxu_priv *priv,
1339                                 u8 macid, bool connect);
1340         void (*fill_txdesc) (struct ieee80211_hdr *hdr,
1341                              struct rtl8xxxu_txdesc32 *tx_desc, u32 rate,
1342                              u16 rate_flag, bool sgi, bool short_preamble,
1343                              bool ampdu_enable);
1344         int writeN_block_size;
1345         int rx_agg_buf_size;
1346         char tx_desc_size;
1347         char rx_desc_size;
1348         u8 has_s0s1:1;
1349         u8 has_tx_report:1;
1350         u8 gen2_thermal_meter:1;
1351         u8 needs_full_init:1;
1352         u32 adda_1t_init;
1353         u32 adda_1t_path_on;
1354         u32 adda_2t_path_on_a;
1355         u32 adda_2t_path_on_b;
1356         u16 trxff_boundary;
1357         u8 pbp_rx;
1358         u8 pbp_tx;
1359         struct rtl8xxxu_reg8val *mactable;
1360         u8 total_page_num;
1361         u8 page_num_hi;
1362         u8 page_num_lo;
1363         u8 page_num_norm;
1364 };
1365
1366 extern int rtl8xxxu_debug;
1367
1368 extern struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[];
1369 extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[];
1370 u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr);
1371 u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr);
1372 u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr);
1373 int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val);
1374 int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val);
1375 int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val);
1376 u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1377                         enum rtl8xxxu_rfpath path, u8 reg);
1378 int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1379                          enum rtl8xxxu_rfpath path, u8 reg, u32 data);
1380 void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1381                         u32 *backup, int count);
1382 void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
1383                            u32 *backup, int count);
1384 void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv,
1385                             const u32 *reg, u32 *backup);
1386 void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
1387                                const u32 *reg, u32 *backup);
1388 void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
1389                            bool path_a_on);
1390 void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
1391                               const u32 *regs, u32 *backup);
1392 void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
1393                                 int result[][8], int candidate, bool tx_only);
1394 void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
1395                                 int result[][8], int candidate, bool tx_only);
1396 int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
1397                          struct rtl8xxxu_rfregval *table,
1398                          enum rtl8xxxu_rfpath path);
1399 int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
1400                            struct rtl8xxxu_reg32val *array);
1401 int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name);
1402 void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv);
1403 void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv);
1404 void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv);
1405 int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv);
1406 void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start);
1407 int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv);
1408 int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv,
1409                           struct h2c_cmd *h2c, int len);
1410 int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv);
1411 void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv);
1412 int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv);
1413 void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv);
1414 void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv);
1415 void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv,
1416                                 int channel, bool ht40);
1417 void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw);
1418 void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw);
1419 void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv);
1420 void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv);
1421 void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
1422                                u32 ramask, int sgi);
1423 void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
1424                                     u32 ramask, int sgi);
1425 void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
1426                                   u8 macid, bool connect);
1427 void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
1428                                   u8 macid, bool connect);
1429 void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv);
1430 void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv);
1431 void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv);
1432 void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv);
1433 int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1434 int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb);
1435 int rtl8xxxu_gen2_channel_to_group(int channel);
1436 bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
1437                                       int result[][8], int c1, int c2);
1438 void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hdr *hdr,
1439                              struct rtl8xxxu_txdesc32 *tx_desc, u32 rate,
1440                              u16 rate_flag, bool sgi, bool short_preamble,
1441                              bool ampdu_enable);
1442 void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hdr *hdr,
1443                              struct rtl8xxxu_txdesc32 *tx_desc32, u32 rate,
1444                              u16 rate_flag, bool sgi, bool short_preamble,
1445                              bool ampdu_enable);
1446
1447 extern struct rtl8xxxu_fileops rtl8192cu_fops;
1448 extern struct rtl8xxxu_fileops rtl8192eu_fops;
1449 extern struct rtl8xxxu_fileops rtl8723au_fops;
1450 extern struct rtl8xxxu_fileops rtl8723bu_fops;