drivers/net/wireless/realtek/rtl8xxxu/rtl8xxxu.c

   1 /*
   2  * RTL8XXXU mac80211 USB driver
   3  *
   4  * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
   5  *
   6  * Portions, notably calibration code:
   7  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   8  *
   9  * This driver was written as a replacement for the vendor provided
  10  * rtl8723au driver. As the Realtek 8xxx chips are very similar in
  11  * their programming interface, I have started adding support for
  12  * additional 8xxx chips like the 8192cu, 8188cus, etc.
  13  *
  14  * This program is free software; you can redistribute it and/or modify it
  15  * under the terms of version 2 of the GNU General Public License as
  16  * published by the Free Software Foundation.
  17  *
  18  * This program is distributed in the hope that it will be useful, but WITHOUT
  19  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  20  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  21  * more details.
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/kernel.h>
  26 #include <linux/sched.h>
  27 #include <linux/errno.h>
  28 #include <linux/slab.h>
  29 #include <linux/module.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/list.h>
  32 #include <linux/usb.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/wireless.h>
  37 #include <linux/firmware.h>
  38 #include <linux/moduleparam.h>
  39 #include <net/mac80211.h>
  40 #include "rtl8xxxu.h"
  41 #include "rtl8xxxu_regs.h"
  42
  43 #define DRIVER_NAME "rtl8xxxu"
  44
  45 static int rtl8xxxu_debug;
  46 static bool rtl8xxxu_ht40_2g;
  47
  48 MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
  49 MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
  50 MODULE_LICENSE("GPL");
  51 /*(DEBLOBBED)*/
  52
  53 module_param_named(debug, rtl8xxxu_debug, int, 0600);
  54 MODULE_PARM_DESC(debug, "Set debug mask");
  55 module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
  56 MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
  57
  58 #define USB_VENDOR_ID_REALTEK           0x0bda
  59 /* Minimum IEEE80211_MAX_FRAME_LEN */
  60 #define RTL_RX_BUFFER_SIZE              IEEE80211_MAX_FRAME_LEN
  61 #define RTL8XXXU_RX_URBS                32
  62 #define RTL8XXXU_RX_URB_PENDING_WATER   8
  63 #define RTL8XXXU_TX_URBS                64
  64 #define RTL8XXXU_TX_URB_LOW_WATER       25
  65 #define RTL8XXXU_TX_URB_HIGH_WATER      32
  66
  67 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
  68                                   struct rtl8xxxu_rx_urb *rx_urb);
  69
  70 static struct ieee80211_rate rtl8xxxu_rates[] = {
  71         { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
  72         { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
  73         { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
  74         { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
  75         { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
  76         { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
  77         { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
  78         { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
  79         { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
  80         { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
  81         { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
  82         { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
  83 };
  84
  85 static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
  86         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
  87           .hw_value = 1, .max_power = 30 },
  88         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
  89           .hw_value = 2, .max_power = 30 },
  90         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
  91           .hw_value = 3, .max_power = 30 },
  92         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
  93           .hw_value = 4, .max_power = 30 },
  94         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
  95           .hw_value = 5, .max_power = 30 },
  96         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
  97           .hw_value = 6, .max_power = 30 },
  98         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
  99           .hw_value = 7, .max_power = 30 },
 100         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
 101           .hw_value = 8, .max_power = 30 },
 102         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
 103           .hw_value = 9, .max_power = 30 },
 104         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
 105           .hw_value = 10, .max_power = 30 },
 106         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
 107           .hw_value = 11, .max_power = 30 },
 108         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
 109           .hw_value = 12, .max_power = 30 },
 110         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
 111           .hw_value = 13, .max_power = 30 },
 112         { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
 113           .hw_value = 14, .max_power = 30 }
 114 };
 115
 116 static struct ieee80211_supported_band rtl8xxxu_supported_band = {
 117         .channels = rtl8xxxu_channels_2g,
 118         .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
 119         .bitrates = rtl8xxxu_rates,
 120         .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
 121 };
 122
 123 static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
 124         {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
 125         {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
 126         {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
 127         {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
 128         {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
 129         {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
 130         {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
 131         {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
 132         {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
 133         {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
 134         {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
 135         {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
 136         {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
 137         {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
 138         {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
 139         {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
 140         {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
 141         {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
 142         {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
 143         {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
 144         {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
 145         {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
 146 };
 147
 148 static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
 149         {0x800, 0x80040000}, {0x804, 0x00000003},
 150         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 151         {0x810, 0x10001331}, {0x814, 0x020c3d10},
 152         {0x818, 0x02200385}, {0x81c, 0x00000000},
 153         {0x820, 0x01000100}, {0x824, 0x00390004},
 154         {0x828, 0x00000000}, {0x82c, 0x00000000},
 155         {0x830, 0x00000000}, {0x834, 0x00000000},
 156         {0x838, 0x00000000}, {0x83c, 0x00000000},
 157         {0x840, 0x00010000}, {0x844, 0x00000000},
 158         {0x848, 0x00000000}, {0x84c, 0x00000000},
 159         {0x850, 0x00000000}, {0x854, 0x00000000},
 160         {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
 161         {0x860, 0x66f60110}, {0x864, 0x061f0130},
 162         {0x868, 0x00000000}, {0x86c, 0x32323200},
 163         {0x870, 0x07000760}, {0x874, 0x22004000},
 164         {0x878, 0x00000808}, {0x87c, 0x00000000},
 165         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 166         {0x888, 0x00000000}, {0x88c, 0xccc000c0},
 167         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 168         {0x898, 0x40302010}, {0x89c, 0x00706050},
 169         {0x900, 0x00000000}, {0x904, 0x00000023},
 170         {0x908, 0x00000000}, {0x90c, 0x81121111},
 171         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 172         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 173         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 174         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 175         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 176         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 177         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 178         {0xa78, 0x00000900},
 179         {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
 180         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 181         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 182         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 183         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 184         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 185         {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
 186         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 187         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 188         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 189         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 190         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 191         {0xc60, 0x00000000}, {0xc64, 0x7112848b},
 192         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 193         {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
 194         {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
 195         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 196         {0xc88, 0x40000100}, {0xc8c, 0x20200000},
 197         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 198         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 199         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 200         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 201         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 202         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 203         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 204         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 205         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 206         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 207         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 208         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 209         {0xd00, 0x00080740}, {0xd04, 0x00020401},
 210         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 211         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 212         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 213         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 214         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 215         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 216         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 217         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 218         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 219         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 220         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 221         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 222         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 223         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 224         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 225         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 226         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 227         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 228         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 229         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 230         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 231         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 232         {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
 233         {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
 234         {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
 235         {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
 236         {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
 237         {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
 238         {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
 239         {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
 240         {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
 241         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 242         {0xf00, 0x00000300},
 243         {0xffff, 0xffffffff},
 244 };
 245
 246 static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
 247         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 248         {0x800, 0x80040002}, {0x804, 0x00000003},
 249         {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
 250         {0x810, 0x10000330}, {0x814, 0x020c3d10},
 251         {0x818, 0x02200385}, {0x81c, 0x00000000},
 252         {0x820, 0x01000100}, {0x824, 0x00390004},
 253         {0x828, 0x01000100}, {0x82c, 0x00390004},
 254         {0x830, 0x27272727}, {0x834, 0x27272727},
 255         {0x838, 0x27272727}, {0x83c, 0x27272727},
 256         {0x840, 0x00010000}, {0x844, 0x00010000},
 257         {0x848, 0x27272727}, {0x84c, 0x27272727},
 258         {0x850, 0x00000000}, {0x854, 0x00000000},
 259         {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
 260         {0x860, 0x66e60230}, {0x864, 0x061f0130},
 261         {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
 262         {0x870, 0x07000700}, {0x874, 0x22184000},
 263         {0x878, 0x08080808}, {0x87c, 0x00000000},
 264         {0x880, 0xc0083070}, {0x884, 0x000004d5},
 265         {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
 266         {0x890, 0x00000800}, {0x894, 0xfffffffe},
 267         {0x898, 0x40302010}, {0x89c, 0x00706050},
 268         {0x900, 0x00000000}, {0x904, 0x00000023},
 269         {0x908, 0x00000000}, {0x90c, 0x81121313},
 270         {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
 271         {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
 272         {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
 273         {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
 274         {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
 275         {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
 276         {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
 277         {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
 278         {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
 279         {0xc10, 0x08800000}, {0xc14, 0x40000100},
 280         {0xc18, 0x08800000}, {0xc1c, 0x40000100},
 281         {0xc20, 0x00000000}, {0xc24, 0x00000000},
 282         {0xc28, 0x00000000}, {0xc2c, 0x00000000},
 283         {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
 284         {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
 285         {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
 286         {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
 287         {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
 288         {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
 289         {0xc60, 0x00000000}, {0xc64, 0x5116848b},
 290         {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
 291         {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
 292         {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
 293         {0xc80, 0x40000100}, {0xc84, 0x20f60000},
 294         {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
 295         {0xc90, 0x00121820}, {0xc94, 0x00000000},
 296         {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
 297         {0xca0, 0x00000000}, {0xca4, 0x00000080},
 298         {0xca8, 0x00000000}, {0xcac, 0x00000000},
 299         {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
 300         {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
 301         {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
 302         {0xcc8, 0x00000000}, {0xccc, 0x00000000},
 303         {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
 304         {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
 305         {0xce0, 0x00222222}, {0xce4, 0x00000000},
 306         {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
 307         {0xd00, 0x00080740}, {0xd04, 0x00020403},
 308         {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
 309         {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
 310         {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
 311         {0xd30, 0x00000000}, {0xd34, 0x80608000},
 312         {0xd38, 0x00000000}, {0xd3c, 0x00027293},
 313         {0xd40, 0x00000000}, {0xd44, 0x00000000},
 314         {0xd48, 0x00000000}, {0xd4c, 0x00000000},
 315         {0xd50, 0x6437140a}, {0xd54, 0x00000000},
 316         {0xd58, 0x00000000}, {0xd5c, 0x30032064},
 317         {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
 318         {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
 319         {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
 320         {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
 321         {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
 322         {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
 323         {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
 324         {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
 325         {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
 326         {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
 327         {0xe44, 0x01004800}, {0xe48, 0xfb000000},
 328         {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
 329         {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
 330         {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
 331         {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
 332         {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
 333         {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
 334         {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
 335         {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
 336         {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
 337         {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
 338         {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
 339         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 340         {0xf00, 0x00000300},
 341         {0xffff, 0xffffffff},
 342 };
 343
 344 static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
 345         {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
 346         {0x040, 0x000c0004}, {0x800, 0x80040000},
 347         {0x804, 0x00000001}, {0x808, 0x0000fc00},
 348         {0x80c, 0x0000000a}, {0x810, 0x10005388},
 349         {0x814, 0x020c3d10}, {0x818, 0x02200385},
 350         {0x81c, 0x00000000}, {0x820, 0x01000100},
 351         {0x824, 0x00390204}, {0x828, 0x00000000},
 352         {0x82c, 0x00000000}, {0x830, 0x00000000},
 353         {0x834, 0x00000000}, {0x838, 0x00000000},
 354         {0x83c, 0x00000000}, {0x840, 0x00010000},
 355         {0x844, 0x00000000}, {0x848, 0x00000000},
 356         {0x84c, 0x00000000}, {0x850, 0x00000000},
 357         {0x854, 0x00000000}, {0x858, 0x569a569a},
 358         {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
 359         {0x864, 0x061f0130}, {0x868, 0x00000000},
 360         {0x86c, 0x20202000}, {0x870, 0x03000300},
 361         {0x874, 0x22004000}, {0x878, 0x00000808},
 362         {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
 363         {0x884, 0x000004d5}, {0x888, 0x00000000},
 364         {0x88c, 0xccc000c0}, {0x890, 0x00000800},
 365         {0x894, 0xfffffffe}, {0x898, 0x40302010},
 366         {0x89c, 0x00706050}, {0x900, 0x00000000},
 367         {0x904, 0x00000023}, {0x908, 0x00000000},
 368         {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
 369         {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
 370         {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
 371         {0xa14, 0x11144028}, {0xa18, 0x00881117},
 372         {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
 373         {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
 374         {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
 375         {0xa74, 0x00000007}, {0xc00, 0x48071d40},
 376         {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
 377         {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
 378         {0xc14, 0x40000100}, {0xc18, 0x08800000},
 379         {0xc1c, 0x40000100}, {0xc20, 0x00000000},
 380         {0xc24, 0x00000000}, {0xc28, 0x00000000},
 381         {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
 382         {0xc34, 0x469652cf}, {0xc38, 0x49795994},
 383         {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
 384         {0xc44, 0x000100b7}, {0xc48, 0xec020107},
 385         {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
 386         {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
 387         {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
 388         {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
 389         {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
 390         {0xc74, 0x018610db}, {0xc78, 0x0000001f},
 391         {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
 392         {0xc84, 0x20f60000}, {0xc88, 0x24000090},
 393         {0xc8c, 0x20200000}, {0xc90, 0x00121820},
 394         {0xc94, 0x00000000}, {0xc98, 0x00121820},
 395         {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
 396         {0xca4, 0x00000080}, {0xca8, 0x00000000},
 397         {0xcac, 0x00000000}, {0xcb0, 0x00000000},
 398         {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
 399         {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
 400         {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
 401         {0xccc, 0x00000000}, {0xcd0, 0x00000000},
 402         {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
 403         {0xcdc, 0x00766932}, {0xce0, 0x00222222},
 404         {0xce4, 0x00000000}, {0xce8, 0x37644302},
 405         {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
 406         {0xd04, 0x00020401}, {0xd08, 0x0000907f},
 407         {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
 408         {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
 409         {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
 410         {0xd34, 0x80608000}, {0xd38, 0x00000000},
 411         {0xd3c, 0x00027293}, {0xd40, 0x00000000},
 412         {0xd44, 0x00000000}, {0xd48, 0x00000000},
 413         {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
 414         {0xd54, 0x00000000}, {0xd58, 0x00000000},
 415         {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
 416         {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
 417         {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
 418         {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
 419         {0xe00, 0x24242424}, {0xe04, 0x24242424},
 420         {0xe08, 0x03902024}, {0xe10, 0x24242424},
 421         {0xe14, 0x24242424}, {0xe18, 0x24242424},
 422         {0xe1c, 0x24242424}, {0xe28, 0x00000000},
 423         {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
 424         {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
 425         {0xe40, 0x01007c00}, {0xe44, 0x01004800},
 426         {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
 427         {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
 428         {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
 429         {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
 430         {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
 431         {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
 432         {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
 433         {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
 434         {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
 435         {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
 436         {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
 437         {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
 438         {0xf14, 0x00000003}, {0xf4c, 0x00000000},
 439         {0xf00, 0x00000300},
 440         {0xffff, 0xffffffff},
 441 };
 442
 443 static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
 444         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 445         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 446         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 447         {0xc78, 0x7a060001}, {0xc78, 0x79070001},
 448         {0xc78, 0x78080001}, {0xc78, 0x77090001},
 449         {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
 450         {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
 451         {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
 452         {0xc78, 0x70100001}, {0xc78, 0x6f110001},
 453         {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
 454         {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
 455         {0xc78, 0x6a160001}, {0xc78, 0x69170001},
 456         {0xc78, 0x68180001}, {0xc78, 0x67190001},
 457         {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
 458         {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
 459         {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
 460         {0xc78, 0x60200001}, {0xc78, 0x49210001},
 461         {0xc78, 0x48220001}, {0xc78, 0x47230001},
 462         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 463         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 464         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 465         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 466         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 467         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 468         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 469         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 470         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 471         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 472         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 473         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 474         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 475         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 476         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 477         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 478         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 479         {0xc78, 0x7a460001}, {0xc78, 0x79470001},
 480         {0xc78, 0x78480001}, {0xc78, 0x77490001},
 481         {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
 482         {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
 483         {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
 484         {0xc78, 0x70500001}, {0xc78, 0x6f510001},
 485         {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
 486         {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
 487         {0xc78, 0x6a560001}, {0xc78, 0x69570001},
 488         {0xc78, 0x68580001}, {0xc78, 0x67590001},
 489         {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
 490         {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
 491         {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
 492         {0xc78, 0x60600001}, {0xc78, 0x49610001},
 493         {0xc78, 0x48620001}, {0xc78, 0x47630001},
 494         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 495         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 496         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 497         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 498         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 499         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 500         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 501         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 502         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 503         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 504         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 505         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 506         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 507         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 508         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 509         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 510         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 511         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 512         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 513         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 514         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 515         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 516         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 517         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 518         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 519         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 520         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 521         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 522         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 523         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 524         {0xffff, 0xffffffff}
 525 };
 526
 527 static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
 528         {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
 529         {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
 530         {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
 531         {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
 532         {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
 533         {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
 534         {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
 535         {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
 536         {0xc78, 0x73100001}, {0xc78, 0x72110001},
 537         {0xc78, 0x71120001}, {0xc78, 0x70130001},
 538         {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
 539         {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
 540         {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
 541         {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
 542         {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
 543         {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
 544         {0xc78, 0x63200001}, {0xc78, 0x62210001},
 545         {0xc78, 0x61220001}, {0xc78, 0x60230001},
 546         {0xc78, 0x46240001}, {0xc78, 0x45250001},
 547         {0xc78, 0x44260001}, {0xc78, 0x43270001},
 548         {0xc78, 0x42280001}, {0xc78, 0x41290001},
 549         {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
 550         {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
 551         {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
 552         {0xc78, 0x21300001}, {0xc78, 0x20310001},
 553         {0xc78, 0x06320001}, {0xc78, 0x05330001},
 554         {0xc78, 0x04340001}, {0xc78, 0x03350001},
 555         {0xc78, 0x02360001}, {0xc78, 0x01370001},
 556         {0xc78, 0x00380001}, {0xc78, 0x00390001},
 557         {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
 558         {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
 559         {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
 560         {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
 561         {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
 562         {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
 563         {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
 564         {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
 565         {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
 566         {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
 567         {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
 568         {0xc78, 0x73500001}, {0xc78, 0x72510001},
 569         {0xc78, 0x71520001}, {0xc78, 0x70530001},
 570         {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
 571         {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
 572         {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
 573         {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
 574         {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
 575         {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
 576         {0xc78, 0x63600001}, {0xc78, 0x62610001},
 577         {0xc78, 0x61620001}, {0xc78, 0x60630001},
 578         {0xc78, 0x46640001}, {0xc78, 0x45650001},
 579         {0xc78, 0x44660001}, {0xc78, 0x43670001},
 580         {0xc78, 0x42680001}, {0xc78, 0x41690001},
 581         {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
 582         {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
 583         {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
 584         {0xc78, 0x21700001}, {0xc78, 0x20710001},
 585         {0xc78, 0x06720001}, {0xc78, 0x05730001},
 586         {0xc78, 0x04740001}, {0xc78, 0x03750001},
 587         {0xc78, 0x02760001}, {0xc78, 0x01770001},
 588         {0xc78, 0x00780001}, {0xc78, 0x00790001},
 589         {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
 590         {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
 591         {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
 592         {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
 593         {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
 594         {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
 595         {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
 596         {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
 597         {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
 598         {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
 599         {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
 600         {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
 601         {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
 602         {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
 603         {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
 604         {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
 605         {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
 606         {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
 607         {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
 608         {0xffff, 0xffffffff}
 609 };
 610
 611 static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
 612         {0x00, 0x00030159}, {0x01, 0x00031284},
 613         {0x02, 0x00098000}, {0x03, 0x00039c63},
 614         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 615         {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
 616         {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
 617         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 618         {0x19, 0x00000000}, {0x1a, 0x00030355},
 619         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 620         {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
 621         {0x1f, 0x00000000}, {0x20, 0x0000b614},
 622         {0x21, 0x0006c000}, {0x22, 0x00000000},
 623         {0x23, 0x00001558}, {0x24, 0x00000060},
 624         {0x25, 0x00000483}, {0x26, 0x0004f000},
 625         {0x27, 0x000ec7d9}, {0x28, 0x00057730},
 626         {0x29, 0x00004783}, {0x2a, 0x00000001},
 627         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 628         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 629         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 630         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 631         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 632         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 633         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 634         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 635         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 636         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 637         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 638         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 639         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 640         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 641         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 642         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 643         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 644         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 645         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 646         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 647         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 648         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 649         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 650         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 651         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 652         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 653         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 654         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 655         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 656         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 657         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 658         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 659         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 660         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 661         {0x10, 0x00000000}, {0x11, 0x00000000},
 662         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 663         {0x10, 0x0009000f}, {0x11, 0x00023100},
 664         {0x12, 0x00032000}, {0x12, 0x00071000},
 665         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 666         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 667         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 668         {0x13, 0x00018493}, {0x13, 0x0001429b},
 669         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 670         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 671         {0x13, 0x00000020}, {0x14, 0x0001944c},
 672         {0x14, 0x00059444}, {0x14, 0x0009944c},
 673         {0x14, 0x000d9444}, {0x15, 0x0000f474},
 674         {0x15, 0x0004f477}, {0x15, 0x0008f455},
 675         {0x15, 0x000cf455}, {0x16, 0x00000339},
 676         {0x16, 0x00040339}, {0x16, 0x00080339},
 677         {0x16, 0x000c0366}, {0x00, 0x00010159},
 678         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 679         {0xfe, 0x00000000}, {0x1f, 0x00000003},
 680         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 681         {0x1e, 0x00000247}, {0x1f, 0x00000000},
 682         {0x00, 0x00030159},
 683         {0xff, 0xffffffff}
 684 };
 685
 686 static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
 687         {0x00, 0x00030159}, {0x01, 0x00031284},
 688         {0x02, 0x00098000}, {0x03, 0x00018c63},
 689         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 690         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 691         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 692         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 693         {0x19, 0x00000000}, {0x1a, 0x00010255},
 694         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 695         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 696         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 697         {0x21, 0x0006c000}, {0x22, 0x00000000},
 698         {0x23, 0x00001558}, {0x24, 0x00000060},
 699         {0x25, 0x00000483}, {0x26, 0x0004f000},
 700         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 701         {0x29, 0x00004783}, {0x2a, 0x00000001},
 702         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 703         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 704         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 705         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 706         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 707         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 708         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 709         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 710         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 711         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 712         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 713         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 714         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 715         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 716         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 717         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 718         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 719         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 720         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 721         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 722         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 723         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 724         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 725         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 726         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 727         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 728         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 729         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 730         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 731         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 732         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 733         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 734         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 735         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 736         {0x10, 0x00000000}, {0x11, 0x00000000},
 737         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 738         {0x10, 0x0009000f}, {0x11, 0x00023100},
 739         {0x12, 0x00032000}, {0x12, 0x00071000},
 740         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 741         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 742         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 743         {0x13, 0x00018493}, {0x13, 0x0001429b},
 744         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 745         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 746         {0x13, 0x00000020}, {0x14, 0x0001944c},
 747         {0x14, 0x00059444}, {0x14, 0x0009944c},
 748         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 749         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 750         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 751         {0x16, 0x000a0330}, {0x16, 0x00060330},
 752         {0x16, 0x00020330}, {0x00, 0x00010159},
 753         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 754         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 755         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 756         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 757         {0x00, 0x00030159},
 758         {0xff, 0xffffffff}
 759 };
 760
 761 static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
 762         {0x00, 0x00030159}, {0x01, 0x00031284},
 763         {0x02, 0x00098000}, {0x03, 0x00018c63},
 764         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 765         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 766         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 767         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 768         {0x12, 0x00032000}, {0x12, 0x00071000},
 769         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 770         {0x13, 0x000287af}, {0x13, 0x000244b7},
 771         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 772         {0x13, 0x00018493}, {0x13, 0x00014297},
 773         {0x13, 0x00010295}, {0x13, 0x0000c298},
 774         {0x13, 0x0000819c}, {0x13, 0x000040a8},
 775         {0x13, 0x0000001c}, {0x14, 0x0001944c},
 776         {0x14, 0x00059444}, {0x14, 0x0009944c},
 777         {0x14, 0x000d9444}, {0x15, 0x0000f424},
 778         {0x15, 0x0004f424}, {0x15, 0x0008f424},
 779         {0x15, 0x000cf424}, {0x16, 0x000e0330},
 780         {0x16, 0x000a0330}, {0x16, 0x00060330},
 781         {0x16, 0x00020330},
 782         {0xff, 0xffffffff}
 783 };
 784
 785 static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
 786         {0x00, 0x00030159}, {0x01, 0x00031284},
 787         {0x02, 0x00098000}, {0x03, 0x00018c63},
 788         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 789         {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
 790         {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
 791         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 792         {0x19, 0x00000000}, {0x1a, 0x00010255},
 793         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 794         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 795         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 796         {0x21, 0x0006c000}, {0x22, 0x00000000},
 797         {0x23, 0x00001558}, {0x24, 0x00000060},
 798         {0x25, 0x00000483}, {0x26, 0x0004f000},
 799         {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
 800         {0x29, 0x00004783}, {0x2a, 0x00000001},
 801         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 802         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 803         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 804         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 805         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 806         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 807         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 808         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 809         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 810         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 811         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 812         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 813         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 814         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 815         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 816         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 817         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 818         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 819         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 820         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 821         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 822         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 823         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 824         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 825         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 826         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 827         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 828         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 829         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 830         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 831         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 832         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 833         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 834         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 835         {0x10, 0x00000000}, {0x11, 0x00000000},
 836         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 837         {0x10, 0x0009000f}, {0x11, 0x00023100},
 838         {0x12, 0x00032000}, {0x12, 0x00071000},
 839         {0x12, 0x000b0000}, {0x12, 0x000fc000},
 840         {0x13, 0x000287b3}, {0x13, 0x000244b7},
 841         {0x13, 0x000204ab}, {0x13, 0x0001c49f},
 842         {0x13, 0x00018493}, {0x13, 0x0001429b},
 843         {0x13, 0x00010299}, {0x13, 0x0000c29c},
 844         {0x13, 0x000081a0}, {0x13, 0x000040ac},
 845         {0x13, 0x00000020}, {0x14, 0x0001944c},
 846         {0x14, 0x00059444}, {0x14, 0x0009944c},
 847         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 848         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 849         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 850         {0x16, 0x000a0330}, {0x16, 0x00060330},
 851         {0x16, 0x00020330}, {0x00, 0x00010159},
 852         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 853         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 854         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 855         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 856         {0x00, 0x00030159},
 857         {0xff, 0xffffffff}
 858 };
 859
 860 static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
 861         {0x00, 0x00030159}, {0x01, 0x00031284},
 862         {0x02, 0x00098000}, {0x03, 0x00018c63},
 863         {0x04, 0x000210e7}, {0x09, 0x0002044f},
 864         {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
 865         {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
 866         {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
 867         {0x19, 0x00000000}, {0x1a, 0x00000255},
 868         {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
 869         {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
 870         {0x1f, 0x00080001}, {0x20, 0x0000b614},
 871         {0x21, 0x0006c000}, {0x22, 0x0000083c},
 872         {0x23, 0x00001558}, {0x24, 0x00000060},
 873         {0x25, 0x00000483}, {0x26, 0x0004f000},
 874         {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
 875         {0x29, 0x00004783}, {0x2a, 0x00000001},
 876         {0x2b, 0x00021334}, {0x2a, 0x00000000},
 877         {0x2b, 0x00000054}, {0x2a, 0x00000001},
 878         {0x2b, 0x00000808}, {0x2b, 0x00053333},
 879         {0x2c, 0x0000000c}, {0x2a, 0x00000002},
 880         {0x2b, 0x00000808}, {0x2b, 0x0005b333},
 881         {0x2c, 0x0000000d}, {0x2a, 0x00000003},
 882         {0x2b, 0x00000808}, {0x2b, 0x00063333},
 883         {0x2c, 0x0000000d}, {0x2a, 0x00000004},
 884         {0x2b, 0x00000808}, {0x2b, 0x0006b333},
 885         {0x2c, 0x0000000d}, {0x2a, 0x00000005},
 886         {0x2b, 0x00000808}, {0x2b, 0x00073333},
 887         {0x2c, 0x0000000d}, {0x2a, 0x00000006},
 888         {0x2b, 0x00000709}, {0x2b, 0x0005b333},
 889         {0x2c, 0x0000000d}, {0x2a, 0x00000007},
 890         {0x2b, 0x00000709}, {0x2b, 0x00063333},
 891         {0x2c, 0x0000000d}, {0x2a, 0x00000008},
 892         {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
 893         {0x2c, 0x0000000d}, {0x2a, 0x00000009},
 894         {0x2b, 0x0000060a}, {0x2b, 0x00053333},
 895         {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
 896         {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
 897         {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
 898         {0x2b, 0x0000060a}, {0x2b, 0x00063333},
 899         {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
 900         {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
 901         {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
 902         {0x2b, 0x0000060a}, {0x2b, 0x00073333},
 903         {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
 904         {0x2b, 0x0000050b}, {0x2b, 0x00066666},
 905         {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
 906         {0x10, 0x0004000f}, {0x11, 0x000e31fc},
 907         {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
 908         {0x10, 0x0002000f}, {0x11, 0x000203f9},
 909         {0x10, 0x0003000f}, {0x11, 0x000ff500},
 910         {0x10, 0x00000000}, {0x11, 0x00000000},
 911         {0x10, 0x0008000f}, {0x11, 0x0003f100},
 912         {0x10, 0x0009000f}, {0x11, 0x00023100},
 913         {0x12, 0x000d8000}, {0x12, 0x00090000},
 914         {0x12, 0x00051000}, {0x12, 0x00012000},
 915         {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
 916         {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
 917         {0x13, 0x000183a4}, {0x13, 0x00014398},
 918         {0x13, 0x000101a4}, {0x13, 0x0000c198},
 919         {0x13, 0x000080a4}, {0x13, 0x00004098},
 920         {0x13, 0x00000000}, {0x14, 0x0001944c},
 921         {0x14, 0x00059444}, {0x14, 0x0009944c},
 922         {0x14, 0x000d9444}, {0x15, 0x0000f405},
 923         {0x15, 0x0004f405}, {0x15, 0x0008f405},
 924         {0x15, 0x000cf405}, {0x16, 0x000e0330},
 925         {0x16, 0x000a0330}, {0x16, 0x00060330},
 926         {0x16, 0x00020330}, {0x00, 0x00010159},
 927         {0x18, 0x0000f401}, {0xfe, 0x00000000},
 928         {0xfe, 0x00000000}, {0x1f, 0x00080003},
 929         {0xfe, 0x00000000}, {0xfe, 0x00000000},
 930         {0x1e, 0x00044457}, {0x1f, 0x00080000},
 931         {0x00, 0x00030159},
 932         {0xff, 0xffffffff}
 933 };
 934
 935 static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
 936         {       /* RF_A */
 937                 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
 938                 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
 939                 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
 940                 .hspiread = REG_HSPI_XA_READBACK,
 941                 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
 942                 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
 943         },
 944         {       /* RF_B */
 945                 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
 946                 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
 947                 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
 948                 .hspiread = REG_HSPI_XB_READBACK,
 949                 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
 950                 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
 951         },
 952 };
 953
 954 static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
 955         REG_OFDM0_XA_RX_IQ_IMBALANCE,
 956         REG_OFDM0_XB_RX_IQ_IMBALANCE,
 957         REG_OFDM0_ENERGY_CCA_THRES,
 958         REG_OFDM0_AGCR_SSI_TABLE,
 959         REG_OFDM0_XA_TX_IQ_IMBALANCE,
 960         REG_OFDM0_XB_TX_IQ_IMBALANCE,
 961         REG_OFDM0_XC_TX_AFE,
 962         REG_OFDM0_XD_TX_AFE,
 963         REG_OFDM0_RX_IQ_EXT_ANTA
 964 };
 965
 966 static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
 967 {
 968         struct usb_device *udev = priv->udev;
 969         int len;
 970         u8 data;
 971
 972         mutex_lock(&priv->usb_buf_mutex);
 973         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 974                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 975                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
 976                               RTW_USB_CONTROL_MSG_TIMEOUT);
 977         data = priv->usb_buf.val8;
 978         mutex_unlock(&priv->usb_buf_mutex);
 979
 980         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
 981                 dev_info(&udev->dev, "%s(%04x)   = 0x%02x, len %i\n",
 982                          __func__, addr, data, len);
 983         return data;
 984 }
 985
 986 static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
 987 {
 988         struct usb_device *udev = priv->udev;
 989         int len;
 990         u16 data;
 991
 992         mutex_lock(&priv->usb_buf_mutex);
 993         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
 994                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
 995                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
 996                               RTW_USB_CONTROL_MSG_TIMEOUT);
 997         data = le16_to_cpu(priv->usb_buf.val16);
 998         mutex_unlock(&priv->usb_buf_mutex);
 999
1000         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1001                 dev_info(&udev->dev, "%s(%04x)  = 0x%04x, len %i\n",
1002                          __func__, addr, data, len);
1003         return data;
1004 }
1005
1006 static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1007 {
1008         struct usb_device *udev = priv->udev;
1009         int len;
1010         u32 data;
1011
1012         mutex_lock(&priv->usb_buf_mutex);
1013         len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1014                               REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1015                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1016                               RTW_USB_CONTROL_MSG_TIMEOUT);
1017         data = le32_to_cpu(priv->usb_buf.val32);
1018         mutex_unlock(&priv->usb_buf_mutex);
1019
1020         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1021                 dev_info(&udev->dev, "%s(%04x)  = 0x%08x, len %i\n",
1022                          __func__, addr, data, len);
1023         return data;
1024 }
1025
1026 static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1027 {
1028         struct usb_device *udev = priv->udev;
1029         int ret;
1030
1031         mutex_lock(&priv->usb_buf_mutex);
1032         priv->usb_buf.val8 = val;
1033         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1034                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1035                               addr, 0, &priv->usb_buf.val8, sizeof(u8),
1036                               RTW_USB_CONTROL_MSG_TIMEOUT);
1037
1038         mutex_unlock(&priv->usb_buf_mutex);
1039
1040         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1041                 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1042                          __func__, addr, val);
1043         return ret;
1044 }
1045
1046 static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1047 {
1048         struct usb_device *udev = priv->udev;
1049         int ret;
1050
1051         mutex_lock(&priv->usb_buf_mutex);
1052         priv->usb_buf.val16 = cpu_to_le16(val);
1053         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1054                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1055                               addr, 0, &priv->usb_buf.val16, sizeof(u16),
1056                               RTW_USB_CONTROL_MSG_TIMEOUT);
1057         mutex_unlock(&priv->usb_buf_mutex);
1058
1059         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1060                 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1061                          __func__, addr, val);
1062         return ret;
1063 }
1064
1065 static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1066 {
1067         struct usb_device *udev = priv->udev;
1068         int ret;
1069
1070         mutex_lock(&priv->usb_buf_mutex);
1071         priv->usb_buf.val32 = cpu_to_le32(val);
1072         ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1073                               REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1074                               addr, 0, &priv->usb_buf.val32, sizeof(u32),
1075                               RTW_USB_CONTROL_MSG_TIMEOUT);
1076         mutex_unlock(&priv->usb_buf_mutex);
1077
1078         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1079                 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1080                          __func__, addr, val);
1081         return ret;
1082 }
1083
1084 static int
1085 rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1086 {
1087         struct usb_device *udev = priv->udev;
1088         int blocksize = priv->fops->writeN_block_size;
1089         int ret, i, count, remainder;
1090
1091         count = len / blocksize;
1092         remainder = len % blocksize;
1093
1094         for (i = 0; i < count; i++) {
1095                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1096                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1097                                       addr, 0, buf, blocksize,
1098                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1099                 if (ret != blocksize)
1100                         goto write_error;
1101
1102                 addr += blocksize;
1103                 buf += blocksize;
1104         }
1105
1106         if (remainder) {
1107                 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1108                                       REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1109                                       addr, 0, buf, remainder,
1110                                       RTW_USB_CONTROL_MSG_TIMEOUT);
1111                 if (ret != remainder)
1112                         goto write_error;
1113         }
1114
1115         return len;
1116
1117 write_error:
1118         dev_info(&udev->dev,
1119                  "%s: Failed to write block at addr: %04x size: %04x\n",
1120                  __func__, addr, blocksize);
1121         return -EAGAIN;
1122 }
1123
1124 static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1125                                enum rtl8xxxu_rfpath path, u8 reg)
1126 {
1127         u32 hssia, val32, retval;
1128
1129         hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1130         if (path != RF_A)
1131                 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1132         else
1133                 val32 = hssia;
1134
1135         val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1136         val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1137         val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1138         hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1139         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1140
1141         udelay(10);
1142
1143         rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1144         udelay(100);
1145
1146         hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1147         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1148         udelay(10);
1149
1150         val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1151         if (val32 & FPGA0_HSSI_PARM1_PI)
1152                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1153         else
1154                 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1155
1156         retval &= 0xfffff;
1157
1158         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1159                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1160                          __func__, reg, retval);
1161         return retval;
1162 }
1163
1164 static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1165                                 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1166 {
1167         int ret, retval;
1168         u32 dataaddr;
1169
1170         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1171                 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1172                          __func__, reg, data);
1173
1174         data &= FPGA0_LSSI_PARM_DATA_MASK;
1175         dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1176
1177         /* Use XB for path B */
1178         ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1179         if (ret != sizeof(dataaddr))
1180                 retval = -EIO;
1181         else
1182                 retval = 0;
1183
1184         udelay(1);
1185
1186         return retval;
1187 }
1188
1189 static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1190 {
1191         struct device *dev = &priv->udev->dev;
1192         int mbox_nr, retry, retval = 0;
1193         int mbox_reg, mbox_ext_reg;
1194         u8 val8;
1195
1196         mutex_lock(&priv->h2c_mutex);
1197
1198         mbox_nr = priv->next_mbox;
1199         mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1200         mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1201
1202         /*
1203          * MBOX ready?
1204          */
1205         retry = 100;
1206         do {
1207                 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1208                 if (!(val8 & BIT(mbox_nr)))
1209                         break;
1210         } while (retry--);
1211
1212         if (!retry) {
1213                 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1214                 retval = -EBUSY;
1215                 goto error;
1216         }
1217
1218         /*
1219          * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1220          */
1221         if (h2c->cmd.cmd & H2C_EXT) {
1222                 rtl8xxxu_write16(priv, mbox_ext_reg,
1223                                  le16_to_cpu(h2c->raw.ext));
1224                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1225                         dev_info(dev, "H2C_EXT %04x\n",
1226                                  le16_to_cpu(h2c->raw.ext));
1227         }
1228         rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1229         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1230                 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1231
1232         priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1233
1234 error:
1235         mutex_unlock(&priv->h2c_mutex);
1236         return retval;
1237 }
1238
1239 static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1240 {
1241         u8 val8;
1242         u32 val32;
1243
1244         val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1245         val8 |= BIT(0) | BIT(3);
1246         rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1247
1248         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1249         val32 &= ~(BIT(4) | BIT(5));
1250         val32 |= BIT(3);
1251         if (priv->rf_paths == 2) {
1252                 val32 &= ~(BIT(20) | BIT(21));
1253                 val32 |= BIT(19);
1254         }
1255         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1256
1257         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1258         val32 &= ~OFDM_RF_PATH_TX_MASK;
1259         if (priv->tx_paths == 2)
1260                 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1261         else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1262                 val32 |= OFDM_RF_PATH_TX_B;
1263         else
1264                 val32 |= OFDM_RF_PATH_TX_A;
1265         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1266
1267         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1268         val32 &= ~FPGA_RF_MODE_JAPAN;
1269         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1270
1271         if (priv->rf_paths == 2)
1272                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1273         else
1274                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1275
1276         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1277         if (priv->rf_paths == 2)
1278                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1279
1280         rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1281 }
1282
1283 static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1284 {
1285         u8 sps0;
1286         u32 val32;
1287
1288         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1289
1290         sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1291
1292         /* RF RX code for preamble power saving */
1293         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1294         val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1295         if (priv->rf_paths == 2)
1296                 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1297         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1298
1299         /* Disable TX for four paths */
1300         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1301         val32 &= ~OFDM_RF_PATH_TX_MASK;
1302         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1303
1304         /* Enable power saving */
1305         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1306         val32 |= FPGA_RF_MODE_JAPAN;
1307         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1308
1309         /* AFE control register to power down bits [30:22] */
1310         if (priv->rf_paths == 2)
1311                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1312         else
1313                 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1314
1315         /* Power down RF module */
1316         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1317         if (priv->rf_paths == 2)
1318                 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1319
1320         sps0 &= ~(BIT(0) | BIT(3));
1321         rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1322 }
1323
1324
1325 static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1326 {
1327         u8 val8;
1328
1329         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1330         val8 &= ~BIT(6);
1331         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1332
1333         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1334         val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1335         val8 &= ~BIT(0);
1336         rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1337 }
1338
1339
1340 /*
1341  * The rtl8723a has 3 channel groups for it's efuse settings. It only
1342  * supports the 2.4GHz band, so channels 1 - 14:
1343  *  group 0: channels 1 - 3
1344  *  group 1: channels 4 - 9
1345  *  group 2: channels 10 - 14
1346  *
1347  * Note: We index from 0 in the code
1348  */
1349 static int rtl8723a_channel_to_group(int channel)
1350 {
1351         int group;
1352
1353         if (channel < 4)
1354                 group = 0;
1355         else if (channel < 10)
1356                 group = 1;
1357         else
1358                 group = 2;
1359
1360         return group;
1361 }
1362
1363 static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1364 {
1365         struct rtl8xxxu_priv *priv = hw->priv;
1366         u32 val32, rsr;
1367         u8 val8, opmode;
1368         bool ht = true;
1369         int sec_ch_above, channel;
1370         int i;
1371
1372         opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1373         rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1374         channel = hw->conf.chandef.chan->hw_value;
1375
1376         switch (hw->conf.chandef.width) {
1377         case NL80211_CHAN_WIDTH_20_NOHT:
1378                 ht = false;
1379         case NL80211_CHAN_WIDTH_20:
1380                 opmode |= BW_OPMODE_20MHZ;
1381                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1382
1383                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1384                 val32 &= ~FPGA_RF_MODE;
1385                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1386
1387                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1388                 val32 &= ~FPGA_RF_MODE;
1389                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1390
1391                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1392                 val32 |= FPGA0_ANALOG2_20MHZ;
1393                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1394                 break;
1395         case NL80211_CHAN_WIDTH_40:
1396                 if (hw->conf.chandef.center_freq1 >
1397                     hw->conf.chandef.chan->center_freq) {
1398                         sec_ch_above = 1;
1399                         channel += 2;
1400                 } else {
1401                         sec_ch_above = 0;
1402                         channel -= 2;
1403                 }
1404
1405                 opmode &= ~BW_OPMODE_20MHZ;
1406                 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1407                 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1408                 if (sec_ch_above)
1409                         rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1410                 else
1411                         rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1412                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1413
1414                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1415                 val32 |= FPGA_RF_MODE;
1416                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1417
1418                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1419                 val32 |= FPGA_RF_MODE;
1420                 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1421
1422                 /*
1423                  * Set Control channel to upper or lower. These settings
1424                  * are required only for 40MHz
1425                  */
1426                 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1427                 val32 &= ~CCK0_SIDEBAND;
1428                 if (!sec_ch_above)
1429                         val32 |= CCK0_SIDEBAND;
1430                 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1431
1432                 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1433                 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1434                 if (sec_ch_above)
1435                         val32 |= OFDM_LSTF_PRIME_CH_LOW;
1436                 else
1437                         val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1438                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1439
1440                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1441                 val32 &= ~FPGA0_ANALOG2_20MHZ;
1442                 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1443
1444                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1445                 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1446                 if (sec_ch_above)
1447                         val32 |= FPGA0_PS_UPPER_CHANNEL;
1448                 else
1449                         val32 |= FPGA0_PS_LOWER_CHANNEL;
1450                 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1451                 break;
1452
1453         default:
1454                 break;
1455         }
1456
1457         for (i = RF_A; i < priv->rf_paths; i++) {
1458                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1459                 val32 &= ~MODE_AG_CHANNEL_MASK;
1460                 val32 |= channel;
1461                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1462         }
1463
1464         if (ht)
1465                 val8 = 0x0e;
1466         else
1467                 val8 = 0x0a;
1468
1469         rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1470         rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1471
1472         rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1473         rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1474
1475         for (i = RF_A; i < priv->rf_paths; i++) {
1476                 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1477                 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1478                         val32 &= ~MODE_AG_CHANNEL_20MHZ;
1479                 else
1480                         val32 |= MODE_AG_CHANNEL_20MHZ;
1481                 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1482         }
1483 }
1484
1485 static void
1486 rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1487 {
1488         u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1489         u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1490         u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1491         u8 val8;
1492         int group, i;
1493
1494         group = rtl8723a_channel_to_group(channel);
1495
1496         cck[0] = priv->cck_tx_power_index_A[group];
1497         cck[1] = priv->cck_tx_power_index_B[group];
1498
1499         ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1500         ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1501
1502         ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1503         ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1504
1505         mcsbase[0] = ofdm[0];
1506         mcsbase[1] = ofdm[1];
1507         if (!ht40) {
1508                 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1509                 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1510         }
1511
1512         if (priv->tx_paths > 1) {
1513                 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1514                         ofdm[0] -=  priv->ht40_2s_tx_power_index_diff[group].a;
1515                 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1516                         ofdm[1] -=  priv->ht40_2s_tx_power_index_diff[group].b;
1517         }
1518
1519         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1520                 dev_info(&priv->udev->dev,
1521                          "%s: Setting TX power CCK A: %02x, "
1522                          "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1523                          __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1524
1525         for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1526                 if (cck[i] > RF6052_MAX_TX_PWR)
1527                         cck[i] = RF6052_MAX_TX_PWR;
1528                 if (ofdm[i] > RF6052_MAX_TX_PWR)
1529                         ofdm[i] = RF6052_MAX_TX_PWR;
1530         }
1531
1532         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1533         val32 &= 0xffff00ff;
1534         val32 |= (cck[0] << 8);
1535         rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1536
1537         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1538         val32 &= 0xff;
1539         val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1540         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1541
1542         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1543         val32 &= 0xffffff00;
1544         val32 |= cck[1];
1545         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1546
1547         val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1548         val32 &= 0xff;
1549         val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1550         rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1551
1552         ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1553                 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1554         ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1555                 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1556         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1557         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1558
1559         rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1560         rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1561
1562         mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1563                 mcsbase[0] << 16 | mcsbase[0] << 24;
1564         mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1565                 mcsbase[1] << 16 | mcsbase[1] << 24;
1566
1567         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1568         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1569
1570         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1571         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1572
1573         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1574         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1575
1576         rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1577         for (i = 0; i < 3; i++) {
1578                 if (i != 2)
1579                         val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1580                 else
1581                         val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1582                 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1583         }
1584         rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1585         for (i = 0; i < 3; i++) {
1586                 if (i != 2)
1587                         val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1588                 else
1589                         val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1590                 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1591         }
1592 }
1593
1594 static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1595                                   enum nl80211_iftype linktype)
1596 {
1597         u16 val8;
1598
1599         val8 = rtl8xxxu_read16(priv, REG_MSR);
1600         val8 &= ~MSR_LINKTYPE_MASK;
1601
1602         switch (linktype) {
1603         case NL80211_IFTYPE_UNSPECIFIED:
1604                 val8 |= MSR_LINKTYPE_NONE;
1605                 break;
1606         case NL80211_IFTYPE_ADHOC:
1607                 val8 |= MSR_LINKTYPE_ADHOC;
1608                 break;
1609         case NL80211_IFTYPE_STATION:
1610                 val8 |= MSR_LINKTYPE_STATION;
1611                 break;
1612         case NL80211_IFTYPE_AP:
1613                 val8 |= MSR_LINKTYPE_AP;
1614                 break;
1615         default:
1616                 goto out;
1617         }
1618
1619         rtl8xxxu_write8(priv, REG_MSR, val8);
1620 out:
1621         return;
1622 }
1623
1624 static void
1625 rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1626 {
1627         u16 val16;
1628
1629         val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1630                  RETRY_LIMIT_SHORT_MASK) |
1631                 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1632                  RETRY_LIMIT_LONG_MASK);
1633
1634         rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1635 }
1636
1637 static void
1638 rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1639 {
1640         u16 val16;
1641
1642         val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1643                 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1644
1645         rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1646 }
1647
1648 static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1649 {
1650         struct device *dev = &priv->udev->dev;
1651         char *cut;
1652
1653         switch (priv->chip_cut) {
1654         case 0:
1655                 cut = "A";
1656                 break;
1657         case 1:
1658                 cut = "B";
1659                 break;
1660         default:
1661                 cut = "unknown";
1662         }
1663
1664         dev_info(dev,
1665                  "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1666                  priv->chip_name, cut, priv->vendor_umc ? "UMC" : "TSMC",
1667                  priv->tx_paths, priv->rx_paths, priv->ep_tx_count,
1668                  priv->has_wifi, priv->has_bluetooth, priv->has_gps,
1669                  priv->hi_pa);
1670
1671         dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1672 }
1673
1674 static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1675 {
1676         struct device *dev = &priv->udev->dev;
1677         u32 val32, bonding;
1678         u16 val16;
1679
1680         val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1681         priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1682                 SYS_CFG_CHIP_VERSION_SHIFT;
1683         if (val32 & SYS_CFG_TRP_VAUX_EN) {
1684                 dev_info(dev, "Unsupported test chip\n");
1685                 return -ENOTSUPP;
1686         }
1687
1688         if (val32 & SYS_CFG_BT_FUNC) {
1689                 sprintf(priv->chip_name, "8723AU");
1690                 priv->rf_paths = 1;
1691                 priv->rx_paths = 1;
1692                 priv->tx_paths = 1;
1693                 priv->rtlchip = 0x8723a;
1694
1695                 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1696                 if (val32 & MULTI_WIFI_FUNC_EN)
1697                         priv->has_wifi = 1;
1698                 if (val32 & MULTI_BT_FUNC_EN)
1699                         priv->has_bluetooth = 1;
1700                 if (val32 & MULTI_GPS_FUNC_EN)
1701                         priv->has_gps = 1;
1702         } else if (val32 & SYS_CFG_TYPE_ID) {
1703                 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1704                 bonding &= HPON_FSM_BONDING_MASK;
1705                 if (bonding == HPON_FSM_BONDING_1T2R) {
1706                         sprintf(priv->chip_name, "8191CU");
1707                         priv->rf_paths = 2;
1708                         priv->rx_paths = 2;
1709                         priv->tx_paths = 1;
1710                         priv->rtlchip = 0x8191c;
1711                 } else {
1712                         sprintf(priv->chip_name, "8192CU");
1713                         priv->rf_paths = 2;
1714                         priv->rx_paths = 2;
1715                         priv->tx_paths = 2;
1716                         priv->rtlchip = 0x8192c;
1717                 }
1718                 priv->has_wifi = 1;
1719         } else {
1720                 sprintf(priv->chip_name, "8188CU");
1721                 priv->rf_paths = 1;
1722                 priv->rx_paths = 1;
1723                 priv->tx_paths = 1;
1724                 priv->rtlchip = 0x8188c;
1725                 priv->has_wifi = 1;
1726         }
1727
1728         if (val32 & SYS_CFG_VENDOR_ID)
1729                 priv->vendor_umc = 1;
1730
1731         val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1732         priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1733
1734         val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1735         if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1736                 priv->ep_tx_high_queue = 1;
1737                 priv->ep_tx_count++;
1738         }
1739
1740         if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1741                 priv->ep_tx_normal_queue = 1;
1742                 priv->ep_tx_count++;
1743         }
1744
1745         if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1746                 priv->ep_tx_low_queue = 1;
1747                 priv->ep_tx_count++;
1748         }
1749
1750         /*
1751          * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1752          */
1753         if (!priv->ep_tx_count) {
1754                 switch (priv->nr_out_eps) {
1755                 case 3:
1756                         priv->ep_tx_low_queue = 1;
1757                         priv->ep_tx_count++;
1758                 case 2:
1759                         priv->ep_tx_normal_queue = 1;
1760                         priv->ep_tx_count++;
1761                 case 1:
1762                         priv->ep_tx_high_queue = 1;
1763                         priv->ep_tx_count++;
1764                         break;
1765                 default:
1766                         dev_info(dev, "Unsupported USB TX end-points\n");
1767                         return -ENOTSUPP;
1768                 }
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1775 {
1776         if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1777                 return -EINVAL;
1778
1779         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1780
1781         memcpy(priv->cck_tx_power_index_A,
1782                priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1783                sizeof(priv->cck_tx_power_index_A));
1784         memcpy(priv->cck_tx_power_index_B,
1785                priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1786                sizeof(priv->cck_tx_power_index_B));
1787
1788         memcpy(priv->ht40_1s_tx_power_index_A,
1789                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1790                sizeof(priv->ht40_1s_tx_power_index_A));
1791         memcpy(priv->ht40_1s_tx_power_index_B,
1792                priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1793                sizeof(priv->ht40_1s_tx_power_index_B));
1794
1795         memcpy(priv->ht20_tx_power_index_diff,
1796                priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1797                sizeof(priv->ht20_tx_power_index_diff));
1798         memcpy(priv->ofdm_tx_power_index_diff,
1799                priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1800                sizeof(priv->ofdm_tx_power_index_diff));
1801
1802         memcpy(priv->ht40_max_power_offset,
1803                priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1804                sizeof(priv->ht40_max_power_offset));
1805         memcpy(priv->ht20_max_power_offset,
1806                priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1807                sizeof(priv->ht20_max_power_offset));
1808
1809         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1810                  priv->efuse_wifi.efuse8723.vendor_name);
1811         dev_info(&priv->udev->dev, "Product: %.41s\n",
1812                  priv->efuse_wifi.efuse8723.device_name);
1813         return 0;
1814 }
1815
1816 #ifdef CONFIG_RTL8XXXU_UNTESTED
1817
1818 static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1819 {
1820         int i;
1821
1822         if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1823                 return -EINVAL;
1824
1825         ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1826
1827         memcpy(priv->cck_tx_power_index_A,
1828                priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1829                sizeof(priv->cck_tx_power_index_A));
1830         memcpy(priv->cck_tx_power_index_B,
1831                priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1832                sizeof(priv->cck_tx_power_index_B));
1833
1834         memcpy(priv->ht40_1s_tx_power_index_A,
1835                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1836                sizeof(priv->ht40_1s_tx_power_index_A));
1837         memcpy(priv->ht40_1s_tx_power_index_B,
1838                priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1839                sizeof(priv->ht40_1s_tx_power_index_B));
1840         memcpy(priv->ht40_2s_tx_power_index_diff,
1841                priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1842                sizeof(priv->ht40_2s_tx_power_index_diff));
1843
1844         memcpy(priv->ht20_tx_power_index_diff,
1845                priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1846                sizeof(priv->ht20_tx_power_index_diff));
1847         memcpy(priv->ofdm_tx_power_index_diff,
1848                priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1849                sizeof(priv->ofdm_tx_power_index_diff));
1850
1851         memcpy(priv->ht40_max_power_offset,
1852                priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1853                sizeof(priv->ht40_max_power_offset));
1854         memcpy(priv->ht20_max_power_offset,
1855                priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1856                sizeof(priv->ht20_max_power_offset));
1857
1858         dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1859                  priv->efuse_wifi.efuse8192.vendor_name);
1860         dev_info(&priv->udev->dev, "Product: %.20s\n",
1861                  priv->efuse_wifi.efuse8192.device_name);
1862
1863         if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1864                 sprintf(priv->chip_name, "8188RU");
1865                 priv->hi_pa = 1;
1866         }
1867
1868         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1869                 unsigned char *raw = priv->efuse_wifi.raw;
1870
1871                 dev_info(&priv->udev->dev,
1872                          "%s: dumping efuse (0x%02zx bytes):\n",
1873                          __func__, sizeof(struct rtl8192cu_efuse));
1874                 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1875                         dev_info(&priv->udev->dev, "%02x: "
1876                                  "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1877                                  raw[i], raw[i + 1], raw[i + 2],
1878                                  raw[i + 3], raw[i + 4], raw[i + 5],
1879                                  raw[i + 6], raw[i + 7]);
1880                 }
1881         }
1882         return 0;
1883 }
1884
1885 #endif
1886
1887 static int
1888 rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1889 {
1890         int i;
1891         u8 val8;
1892         u32 val32;
1893
1894         /* Write Address */
1895         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1896         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1897         val8 &= 0xfc;
1898         val8 |= (offset >> 8) & 0x03;
1899         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1900
1901         val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1902         rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1903
1904         /* Poll for data read */
1905         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1906         for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1907                 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1908                 if (val32 & BIT(31))
1909                         break;
1910         }
1911
1912         if (i == RTL8XXXU_MAX_REG_POLL)
1913                 return -EIO;
1914
1915         udelay(50);
1916         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1917
1918         *data = val32 & 0xff;
1919         return 0;
1920 }
1921
1922 static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1923 {
1924         struct device *dev = &priv->udev->dev;
1925         int i, ret = 0;
1926         u8 val8, word_mask, header, extheader;
1927         u16 val16, efuse_addr, offset;
1928         u32 val32;
1929
1930         val16 = rtl8xxxu_read16(priv, REG_9346CR);
1931         if (val16 & EEPROM_ENABLE)
1932                 priv->has_eeprom = 1;
1933         if (val16 & EEPROM_BOOT)
1934                 priv->boot_eeprom = 1;
1935
1936         val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1937         val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1938         rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1939
1940         dev_dbg(dev, "Booting from %s\n",
1941                 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1942
1943         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1944
1945         /*  1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
1946         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1947         if (!(val16 & SYS_ISO_PWC_EV12V)) {
1948                 val16 |= SYS_ISO_PWC_EV12V;
1949                 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1950         }
1951         /*  Reset: 0x0000[28], default valid */
1952         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1953         if (!(val16 & SYS_FUNC_ELDR)) {
1954                 val16 |= SYS_FUNC_ELDR;
1955                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1956         }
1957
1958         /*
1959          * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
1960          */
1961         val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1962         if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1963                 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1964                 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1965         }
1966
1967         /* Default value is 0xff */
1968         memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN_8723A);
1969
1970         efuse_addr = 0;
1971         while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1972                 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1973                 if (ret || header == 0xff)
1974                         goto exit;
1975
1976                 if ((header & 0x1f) == 0x0f) {  /* extended header */
1977                         offset = (header & 0xe0) >> 5;
1978
1979                         ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1980                                                    &extheader);
1981                         if (ret)
1982                                 goto exit;
1983                         /* All words disabled */
1984                         if ((extheader & 0x0f) == 0x0f)
1985                                 continue;
1986
1987                         offset |= ((extheader & 0xf0) >> 1);
1988                         word_mask = extheader & 0x0f;
1989                 } else {
1990                         offset = (header >> 4) & 0x0f;
1991                         word_mask = header & 0x0f;
1992                 }
1993
1994                 if (offset < EFUSE_MAX_SECTION_8723A) {
1995                         u16 map_addr;
1996                         /* Get word enable value from PG header */
1997
1998                         /* We have 8 bits to indicate validity */
1999                         map_addr = offset * 8;
2000                         if (map_addr >= EFUSE_MAP_LEN_8723A) {
2001                                 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2002                                          "efuse corrupt!\n",
2003                                          __func__, map_addr);
2004                                 ret = -EINVAL;
2005                                 goto exit;
2006                         }
2007                         for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2008                                 /* Check word enable condition in the section */
2009                                 if (!(word_mask & BIT(i))) {
2010                                         ret = rtl8xxxu_read_efuse8(priv,
2011                                                                    efuse_addr++,
2012                                                                    &val8);
2013                                         if (ret)
2014                                                 goto exit;
2015                                         priv->efuse_wifi.raw[map_addr++] = val8;
2016
2017                                         ret = rtl8xxxu_read_efuse8(priv,
2018                                                                    efuse_addr++,
2019                                                                    &val8);
2020                                         if (ret)
2021                                                 goto exit;
2022                                         priv->efuse_wifi.raw[map_addr++] = val8;
2023                                 } else
2024                                         map_addr += 2;
2025                         }
2026                 } else {
2027                         dev_warn(dev,
2028                                  "%s: Illegal offset (%04x), efuse corrupt!\n",
2029                                  __func__, offset);
2030                         ret = -EINVAL;
2031                         goto exit;
2032                 }
2033         }
2034
2035 exit:
2036         rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2037
2038         return ret;
2039 }
2040
2041 static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2042 {
2043         struct device *dev = &priv->udev->dev;
2044         int ret = 0, i;
2045         u32 val32;
2046
2047         /* Poll checksum report */
2048         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2049                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2050                 if (val32 & MCU_FW_DL_CSUM_REPORT)
2051                         break;
2052         }
2053
2054         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2055                 dev_warn(dev, "Firmware checksum poll timed out\n");
2056                 ret = -EAGAIN;
2057                 goto exit;
2058         }
2059
2060         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2061         val32 |= MCU_FW_DL_READY;
2062         val32 &= ~MCU_WINT_INIT_READY;
2063         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2064
2065         /* Wait for firmware to become ready */
2066         for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2067                 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2068                 if (val32 & MCU_WINT_INIT_READY)
2069                         break;
2070
2071                 udelay(100);
2072         }
2073
2074         if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2075                 dev_warn(dev, "Firmware failed to start\n");
2076                 ret = -EAGAIN;
2077                 goto exit;
2078         }
2079
2080 exit:
2081         return ret;
2082 }
2083
2084 static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2085 {
2086         int pages, remainder, i, ret;
2087         u8 val8;
2088         u16 val16;
2089         u32 val32;
2090         u8 *fwptr;
2091
2092         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2093         val8 |= 4;
2094         rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2095
2096         /* 8051 enable */
2097         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2098         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16 | SYS_FUNC_CPU_ENABLE);
2099
2100         /* MCU firmware download enable */
2101         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2102         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_ENABLE);
2103
2104         /* 8051 reset */
2105         val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2106         rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32 & ~BIT(19));
2107
2108         /* Reset firmware download checksum */
2109         val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2110         rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8 | MCU_FW_DL_CSUM_REPORT);
2111
2112         pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2113         remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2114
2115         fwptr = priv->fw_data->data;
2116
2117         for (i = 0; i < pages; i++) {
2118                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2119                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2120
2121                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2122                                       fwptr, RTL_FW_PAGE_SIZE);
2123                 if (ret != RTL_FW_PAGE_SIZE) {
2124                         ret = -EAGAIN;
2125                         goto fw_abort;
2126                 }
2127
2128                 fwptr += RTL_FW_PAGE_SIZE;
2129         }
2130
2131         if (remainder) {
2132                 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2133                 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8 | i);
2134                 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2135                                       fwptr, remainder);
2136                 if (ret != remainder) {
2137                         ret = -EAGAIN;
2138                         goto fw_abort;
2139                 }
2140         }
2141
2142         ret = 0;
2143 fw_abort:
2144         /* MCU firmware download disable */
2145         val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2146         rtl8xxxu_write16(priv, REG_MCU_FW_DL,
2147                          val16 & (~MCU_FW_DL_ENABLE & 0xff));
2148
2149         return ret;
2150 }
2151
2152 static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2153 {
2154         struct device *dev = &priv->udev->dev;
2155         const struct firmware *fw;
2156         int ret = 0;
2157         u16 signature;
2158
2159         dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2160         if (reject_firmware(&fw, fw_name, &priv->udev->dev)) {
2161                 dev_warn(dev, "reject_firmware(%s) failed\n", fw_name);
2162                 ret = -EAGAIN;
2163                 goto exit;
2164         }
2165         if (!fw) {
2166                 dev_warn(dev, "Firmware data not available\n");
2167                 ret = -EINVAL;
2168                 goto exit;
2169         }
2170
2171         priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2172         priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2173
2174         signature = le16_to_cpu(priv->fw_data->signature);
2175         switch (signature & 0xfff0) {
2176         case 0x92c0:
2177         case 0x88c0:
2178         case 0x2300:
2179                 break;
2180         default:
2181                 ret = -EINVAL;
2182                 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2183                          __func__, signature);
2184         }
2185
2186         dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2187                  le16_to_cpu(priv->fw_data->major_version),
2188                  priv->fw_data->minor_version, signature);
2189
2190 exit:
2191         release_firmware(fw);
2192         return ret;
2193 }
2194
2195 static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2196 {
2197         char *fw_name;
2198         int ret;
2199
2200         switch (priv->chip_cut) {
2201         case 0:
2202                 fw_name = "/*(DEBLOBBED)*/";
2203                 break;
2204         case 1:
2205                 if (priv->enable_bluetooth)
2206                         fw_name = "/*(DEBLOBBED)*/";
2207                 else
2208                         fw_name = "/*(DEBLOBBED)*/";
2209
2210                 break;
2211         default:
2212                 return -EINVAL;
2213         }
2214
2215         ret = rtl8xxxu_load_firmware(priv, fw_name);
2216         return ret;
2217 }
2218
2219 #ifdef CONFIG_RTL8XXXU_UNTESTED
2220
2221 static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2222 {
2223         char *fw_name;
2224         int ret;
2225
2226         if (!priv->vendor_umc)
2227                 fw_name = "/*(DEBLOBBED)*/";
2228         else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2229                 fw_name = "/*(DEBLOBBED)*/";
2230         else
2231                 fw_name = "/*(DEBLOBBED)*/";
2232
2233         ret = rtl8xxxu_load_firmware(priv, fw_name);
2234
2235         return ret;
2236 }
2237
2238 #endif
2239
2240 static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2241 {
2242         u16 val16;
2243         int i = 100;
2244
2245         /* Inform 8051 to perform reset */
2246         rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2247
2248         for (i = 100; i > 0; i--) {
2249                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2250
2251                 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2252                         dev_dbg(&priv->udev->dev,
2253                                 "%s: Firmware self reset success!\n", __func__);
2254                         break;
2255                 }
2256                 udelay(50);
2257         }
2258
2259         if (!i) {
2260                 /* Force firmware reset */
2261                 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2262                 val16 &= ~SYS_FUNC_CPU_ENABLE;
2263                 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2264         }
2265 }
2266
2267 static int
2268 rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2269 {
2270         int i, ret;
2271         u16 reg;
2272         u8 val;
2273
2274         for (i = 0; ; i++) {
2275                 reg = array[i].reg;
2276                 val = array[i].val;
2277
2278                 if (reg == 0xffff && val == 0xff)
2279                         break;
2280
2281                 ret = rtl8xxxu_write8(priv, reg, val);
2282                 if (ret != 1) {
2283                         dev_warn(&priv->udev->dev,
2284                                  "Failed to initialize MAC\n");
2285                         return -EAGAIN;
2286                 }
2287         }
2288
2289         rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2290
2291         return 0;
2292 }
2293
2294 static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2295                                   struct rtl8xxxu_reg32val *array)
2296 {
2297         int i, ret;
2298         u16 reg;
2299         u32 val;
2300
2301         for (i = 0; ; i++) {
2302                 reg = array[i].reg;
2303                 val = array[i].val;
2304
2305                 if (reg == 0xffff && val == 0xffffffff)
2306                         break;
2307
2308                 ret = rtl8xxxu_write32(priv, reg, val);
2309                 if (ret != sizeof(val)) {
2310                         dev_warn(&priv->udev->dev,
2311                                  "Failed to initialize PHY\n");
2312                         return -EAGAIN;
2313                 }
2314                 udelay(1);
2315         }
2316
2317         return 0;
2318 }
2319
2320 /*
2321  * Most of this is black magic retrieved from the old rtl8723au driver
2322  */
2323 static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2324 {
2325         u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2326         u32 val32;
2327
2328         /*
2329          * Todo: The vendor driver maintains a table of PHY register
2330          *       addresses, which is initialized here. Do we need this?
2331          */
2332
2333         val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2334         udelay(2);
2335         val8 |= AFE_PLL_320_ENABLE;
2336         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2337         udelay(2);
2338
2339         rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2340         udelay(2);
2341
2342         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2343         val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2344         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2345
2346         /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2347         val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2348         val32 &= ~AFE_XTAL_RF_GATE;
2349         if (priv->has_bluetooth)
2350                 val32 &= ~AFE_XTAL_BT_GATE;
2351         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2352
2353         /* 6. 0x1f[7:0] = 0x07 */
2354         val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2355         rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2356
2357         if (priv->hi_pa)
2358                 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2359         else if (priv->tx_paths == 2)
2360                 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2361         else
2362                 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2363
2364
2365         if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2366             priv->vendor_umc && priv->chip_cut == 1)
2367                 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2368
2369         if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2370                 /*
2371                  * For 1T2R boards, patch the registers.
2372                  *
2373                  * It looks like 8191/2 1T2R boards use path B for TX
2374                  */
2375                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2376                 val32 &= ~(BIT(0) | BIT(1));
2377                 val32 |= BIT(1);
2378                 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2379
2380                 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2381                 val32 &= ~0x300033;
2382                 val32 |= 0x200022;
2383                 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2384
2385                 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2386                 val32 &= 0xff000000;
2387                 val32 |= 0x45000000;
2388                 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2389
2390                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2391                 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2392                 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2393                           OFDM_RF_PATH_TX_B);
2394                 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2395
2396                 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2397                 val32 &= ~(BIT(4) | BIT(5));
2398                 val32 |= BIT(4);
2399                 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2400
2401                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2402                 val32 &= ~(BIT(27) | BIT(26));
2403                 val32 |= BIT(27);
2404                 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2405
2406                 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2407                 val32 &= ~(BIT(27) | BIT(26));
2408                 val32 |= BIT(27);
2409                 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2410
2411                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2412                 val32 &= ~(BIT(27) | BIT(26));
2413                 val32 |= BIT(27);
2414                 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2415
2416                 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2417                 val32 &= ~(BIT(27) | BIT(26));
2418                 val32 |= BIT(27);
2419                 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2420
2421                 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2422                 val32 &= ~(BIT(27) | BIT(26));
2423                 val32 |= BIT(27);
2424                 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2425         }
2426
2427         if (priv->hi_pa)
2428                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2429         else
2430                 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2431
2432         if (priv->rtlchip == 0x8723a &&
2433             priv->efuse_wifi.efuse8723.version >= 0x01) {
2434                 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2435
2436                 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2437                 val32 &= 0xff000fff;
2438                 val32 |= ((val8 | (val8 << 6)) << 12);
2439
2440                 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2441         }
2442
2443         ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2444         ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2445         ldohci12 = 0x57;
2446         lpldo = 1;
2447         val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2448
2449         rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2450
2451         return 0;
2452 }
2453
2454 static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2455                                  struct rtl8xxxu_rfregval *array,
2456                                  enum rtl8xxxu_rfpath path)
2457 {
2458         int i, ret;
2459         u8 reg;
2460         u32 val;
2461
2462         for (i = 0; ; i++) {
2463                 reg = array[i].reg;
2464                 val = array[i].val;
2465
2466                 if (reg == 0xff && val == 0xffffffff)
2467                         break;
2468
2469                 switch (reg) {
2470                 case 0xfe:
2471                         msleep(50);
2472                         continue;
2473                 case 0xfd:
2474                         mdelay(5);
2475                         continue;
2476                 case 0xfc:
2477                         mdelay(1);
2478                         continue;
2479                 case 0xfb:
2480                         udelay(50);
2481                         continue;
2482                 case 0xfa:
2483                         udelay(5);
2484                         continue;
2485                 case 0xf9:
2486                         udelay(1);
2487                         continue;
2488                 }
2489
2490                 reg &= 0x3f;
2491
2492                 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2493                 if (ret) {
2494                         dev_warn(&priv->udev->dev,
2495                                  "Failed to initialize RF\n");
2496                         return -EAGAIN;
2497                 }
2498                 udelay(1);
2499         }
2500
2501         return 0;
2502 }
2503
2504 static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2505                                 struct rtl8xxxu_rfregval *table,
2506                                 enum rtl8xxxu_rfpath path)
2507 {
2508         u32 val32;
2509         u16 val16, rfsi_rfenv;
2510         u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2511
2512         switch (path) {
2513         case RF_A:
2514                 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2515                 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2516                 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2517                 break;
2518         case RF_B:
2519                 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2520                 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2521                 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2522                 break;
2523         default:
2524                 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2525                         __func__, path + 'A');
2526                 return -EINVAL;
2527         }
2528         /* For path B, use XB */
2529         rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2530         rfsi_rfenv &= FPGA0_RF_RFENV;
2531
2532         /*
2533          * These two we might be able to optimize into one
2534          */
2535         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2536         val32 |= BIT(20);       /* 0x10 << 16 */
2537         rtl8xxxu_write32(priv, reg_int_oe, val32);
2538         udelay(1);
2539
2540         val32 = rtl8xxxu_read32(priv, reg_int_oe);
2541         val32 |= BIT(4);
2542         rtl8xxxu_write32(priv, reg_int_oe, val32);
2543         udelay(1);
2544
2545         /*
2546          * These two we might be able to optimize into one
2547          */
2548         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2549         val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2550         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2551         udelay(1);
2552
2553         val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2554         val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2555         rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2556         udelay(1);
2557
2558         rtl8xxxu_init_rf_regs(priv, table, path);
2559
2560         /* For path B, use XB */
2561         val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2562         val16 &= ~FPGA0_RF_RFENV;
2563         val16 |= rfsi_rfenv;
2564         rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2565
2566         return 0;
2567 }
2568
2569 static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2570 {
2571         int ret = -EBUSY;
2572         int count = 0;
2573         u32 value;
2574
2575         value = LLT_OP_WRITE | address << 8 | data;
2576
2577         rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2578
2579         do {
2580                 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2581                 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2582                         ret = 0;
2583                         break;
2584                 }
2585         } while (count++ < 20);
2586
2587         return ret;
2588 }
2589
2590 static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2591 {
2592         int ret;
2593         int i;
2594
2595         for (i = 0; i < last_tx_page; i++) {
2596                 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2597                 if (ret)
2598                         goto exit;
2599         }
2600
2601         ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2602         if (ret)
2603                 goto exit;
2604
2605         /* Mark remaining pages as a ring buffer */
2606         for (i = last_tx_page + 1; i < 0xff; i++) {
2607                 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2608                 if (ret)
2609                         goto exit;
2610         }
2611
2612         /*  Let last entry point to the start entry of ring buffer */
2613         ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2614         if (ret)
2615                 goto exit;
2616
2617 exit:
2618         return ret;
2619 }
2620
2621 static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2622 {
2623         u16 val16, hi, lo;
2624         u16 hiq, mgq, bkq, beq, viq, voq;
2625         int hip, mgp, bkp, bep, vip, vop;
2626         int ret = 0;
2627
2628         switch (priv->ep_tx_count) {
2629         case 1:
2630                 if (priv->ep_tx_high_queue) {
2631                         hi = TRXDMA_QUEUE_HIGH;
2632                 } else if (priv->ep_tx_low_queue) {
2633                         hi = TRXDMA_QUEUE_LOW;
2634                 } else if (priv->ep_tx_normal_queue) {
2635                         hi = TRXDMA_QUEUE_NORMAL;
2636                 } else {
2637                         hi = 0;
2638                         ret = -EINVAL;
2639                 }
2640
2641                 hiq = hi;
2642                 mgq = hi;
2643                 bkq = hi;
2644                 beq = hi;
2645                 viq = hi;
2646                 voq = hi;
2647
2648                 hip = 0;
2649                 mgp = 0;
2650                 bkp = 0;
2651                 bep = 0;
2652                 vip = 0;
2653                 vop = 0;
2654                 break;
2655         case 2:
2656                 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2657                         hi = TRXDMA_QUEUE_HIGH;
2658                         lo = TRXDMA_QUEUE_LOW;
2659                 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2660                         hi = TRXDMA_QUEUE_NORMAL;
2661                         lo = TRXDMA_QUEUE_LOW;
2662                 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2663                         hi = TRXDMA_QUEUE_HIGH;
2664                         lo = TRXDMA_QUEUE_NORMAL;
2665                 } else {
2666                         ret = -EINVAL;
2667                         hi = 0;
2668                         lo = 0;
2669                 }
2670
2671                 hiq = hi;
2672                 mgq = hi;
2673                 bkq = lo;
2674                 beq = lo;
2675                 viq = hi;
2676                 voq = hi;
2677
2678                 hip = 0;
2679                 mgp = 0;
2680                 bkp = 1;
2681                 bep = 1;
2682                 vip = 0;
2683                 vop = 0;
2684                 break;
2685         case 3:
2686                 beq = TRXDMA_QUEUE_LOW;
2687                 bkq = TRXDMA_QUEUE_LOW;
2688                 viq = TRXDMA_QUEUE_NORMAL;
2689                 voq = TRXDMA_QUEUE_HIGH;
2690                 mgq = TRXDMA_QUEUE_HIGH;
2691                 hiq = TRXDMA_QUEUE_HIGH;
2692
2693                 hip = hiq ^ 3;
2694                 mgp = mgq ^ 3;
2695                 bkp = bkq ^ 3;
2696                 bep = beq ^ 3;
2697                 vip = viq ^ 3;
2698                 vop = viq ^ 3;
2699                 break;
2700         default:
2701                 ret = -EINVAL;
2702         }
2703
2704         /*
2705          * None of the vendor drivers are configuring the beacon
2706          * queue here .... why?
2707          */
2708         if (!ret) {
2709                 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2710                 val16 &= 0x7;
2711                 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2712                         (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2713                         (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2714                         (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2715                         (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2716                         (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2717                 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2718
2719                 priv->pipe_out[TXDESC_QUEUE_VO] =
2720                         usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2721                 priv->pipe_out[TXDESC_QUEUE_VI] =
2722                         usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2723                 priv->pipe_out[TXDESC_QUEUE_BE] =
2724                         usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2725                 priv->pipe_out[TXDESC_QUEUE_BK] =
2726                         usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2727                 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2728                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2729                 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2730                         usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2731                 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2732                         usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2733                 priv->pipe_out[TXDESC_QUEUE_CMD] =
2734                         usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2735         }
2736
2737         return ret;
2738 }
2739
2740 static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2741                                        bool iqk_ok, int result[][8],
2742                                        int candidate, bool tx_only)
2743 {
2744         u32 oldval, x, tx0_a, reg;
2745         int y, tx0_c;
2746         u32 val32;
2747
2748         if (!iqk_ok)
2749                 return;
2750
2751         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2752         oldval = val32 >> 22;
2753
2754         x = result[candidate][0];
2755         if ((x & 0x00000200) != 0)
2756                 x = x | 0xfffffc00;
2757         tx0_a = (x * oldval) >> 8;
2758
2759         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2760         val32 &= ~0x3ff;
2761         val32 |= tx0_a;
2762         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2763
2764         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2765         val32 &= ~BIT(31);
2766         if ((x * oldval >> 7) & 0x1)
2767                 val32 |= BIT(31);
2768         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2769
2770         y = result[candidate][1];
2771         if ((y & 0x00000200) != 0)
2772                 y = y | 0xfffffc00;
2773         tx0_c = (y * oldval) >> 8;
2774
2775         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2776         val32 &= ~0xf0000000;
2777         val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2778         rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2779
2780         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2781         val32 &= ~0x003f0000;
2782         val32 |= ((tx0_c & 0x3f) << 16);
2783         rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2784
2785         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2786         val32 &= ~BIT(29);
2787         if ((y * oldval >> 7) & 0x1)
2788                 val32 |= BIT(29);
2789         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2790
2791         if (tx_only) {
2792                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2793                 return;
2794         }
2795
2796         reg = result[candidate][2];
2797
2798         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2799         val32 &= ~0x3ff;
2800         val32 |= (reg & 0x3ff);
2801         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2802
2803         reg = result[candidate][3] & 0x3F;
2804
2805         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2806         val32 &= ~0xfc00;
2807         val32 |= ((reg << 10) & 0xfc00);
2808         rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2809
2810         reg = (result[candidate][3] >> 6) & 0xF;
2811
2812         val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2813         val32 &= ~0xf0000000;
2814         val32 |= (reg << 28);
2815         rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2816 }
2817
2818 static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2819                                        bool iqk_ok, int result[][8],
2820                                        int candidate, bool tx_only)
2821 {
2822         u32 oldval, x, tx1_a, reg;
2823         int y, tx1_c;
2824         u32 val32;
2825
2826         if (!iqk_ok)
2827                 return;
2828
2829         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2830         oldval = val32 >> 22;
2831
2832         x = result[candidate][4];
2833         if ((x & 0x00000200) != 0)
2834                 x = x | 0xfffffc00;
2835         tx1_a = (x * oldval) >> 8;
2836
2837         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2838         val32 &= ~0x3ff;
2839         val32 |= tx1_a;
2840         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2841
2842         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2843         val32 &= ~BIT(27);
2844         if ((x * oldval >> 7) & 0x1)
2845                 val32 |= BIT(27);
2846         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2847
2848         y = result[candidate][5];
2849         if ((y & 0x00000200) != 0)
2850                 y = y | 0xfffffc00;
2851         tx1_c = (y * oldval) >> 8;
2852
2853         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2854         val32 &= ~0xf0000000;
2855         val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2856         rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2857
2858         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2859         val32 &= ~0x003f0000;
2860         val32 |= ((tx1_c & 0x3f) << 16);
2861         rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2862
2863         val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2864         val32 &= ~BIT(25);
2865         if ((y * oldval >> 7) & 0x1)
2866                 val32 |= BIT(25);
2867         rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2868
2869         if (tx_only) {
2870                 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2871                 return;
2872         }
2873
2874         reg = result[candidate][6];
2875
2876         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2877         val32 &= ~0x3ff;
2878         val32 |= (reg & 0x3ff);
2879         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2880
2881         reg = result[candidate][7] & 0x3f;
2882
2883         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2884         val32 &= ~0xfc00;
2885         val32 |= ((reg << 10) & 0xfc00);
2886         rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2887
2888         reg = (result[candidate][7] >> 6) & 0xf;
2889
2890         val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2891         val32 &= ~0x0000f000;
2892         val32 |= (reg << 12);
2893         rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2894 }
2895
2896 #define MAX_TOLERANCE           5
2897
2898 static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2899                                         int result[][8], int c1, int c2)
2900 {
2901         u32 i, j, diff, simubitmap, bound = 0;
2902         int candidate[2] = {-1, -1};    /* for path A and path B */
2903         bool retval = true;
2904
2905         if (priv->tx_paths > 1)
2906                 bound = 8;
2907         else
2908                 bound = 4;
2909
2910         simubitmap = 0;
2911
2912         for (i = 0; i < bound; i++) {
2913                 diff = (result[c1][i] > result[c2][i]) ?
2914                         (result[c1][i] - result[c2][i]) :
2915                         (result[c2][i] - result[c1][i]);
2916                 if (diff > MAX_TOLERANCE) {
2917                         if ((i == 2 || i == 6) && !simubitmap) {
2918                                 if (result[c1][i] + result[c1][i + 1] == 0)
2919                                         candidate[(i / 4)] = c2;
2920                                 else if (result[c2][i] + result[c2][i + 1] == 0)
2921                                         candidate[(i / 4)] = c1;
2922                                 else
2923                                         simubitmap = simubitmap | (1 << i);
2924                         } else {
2925                                 simubitmap = simubitmap | (1 << i);
2926                         }
2927                 }
2928         }
2929
2930         if (simubitmap == 0) {
2931                 for (i = 0; i < (bound / 4); i++) {
2932                         if (candidate[i] >= 0) {
2933                                 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2934                                         result[3][j] = result[candidate[i]][j];
2935                                 retval = false;
2936                         }
2937                 }
2938                 return retval;
2939         } else if (!(simubitmap & 0x0f)) {
2940                 /* path A OK */
2941                 for (i = 0; i < 4; i++)
2942                         result[3][i] = result[c1][i];
2943         } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2944                 /* path B OK */
2945                 for (i = 4; i < 8; i++)
2946                         result[3][i] = result[c1][i];
2947         }
2948
2949         return false;
2950 }
2951
2952 static void
2953 rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2954 {
2955         int i;
2956
2957         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2958                 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2959
2960         backup[i] = rtl8xxxu_read32(priv, reg[i]);
2961 }
2962
2963 static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2964                                       const u32 *reg, u32 *backup)
2965 {
2966         int i;
2967
2968         for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2969                 rtl8xxxu_write8(priv, reg[i], backup[i]);
2970
2971         rtl8xxxu_write32(priv, reg[i], backup[i]);
2972 }
2973
2974 static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2975                                u32 *backup, int count)
2976 {
2977         int i;
2978
2979         for (i = 0; i < count; i++)
2980                 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2981 }
2982
2983 static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2984                                   u32 *backup, int count)
2985 {
2986         int i;
2987
2988         for (i = 0; i < count; i++)
2989                 rtl8xxxu_write32(priv, regs[i], backup[i]);
2990 }
2991
2992
2993 static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2994                                   bool path_a_on)
2995 {
2996         u32 path_on;
2997         int i;
2998
2999         path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3000         if (priv->tx_paths == 1) {
3001                 path_on = 0x0bdb25a0;
3002                 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3003         } else {
3004                 rtl8xxxu_write32(priv, regs[0], path_on);
3005         }
3006
3007         for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3008                 rtl8xxxu_write32(priv, regs[i], path_on);
3009 }
3010
3011 static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3012                                      const u32 *regs, u32 *backup)
3013 {
3014         int i = 0;
3015
3016         rtl8xxxu_write8(priv, regs[i], 0x3f);
3017
3018         for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3019                 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3020
3021         rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3022 }
3023
3024 static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3025 {
3026         u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3027         int result = 0;
3028
3029         /* path-A IQK setting */
3030         rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3031         rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3032         rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3033
3034         val32 = (priv->rf_paths > 1) ? 0x28160202 :
3035                 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3036                 0x28160502;
3037         rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3038
3039         /* path-B IQK setting */
3040         if (priv->rf_paths > 1) {
3041                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3042                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3043                 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3044                 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3045         }
3046
3047         /* LO calibration setting */
3048         rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3049
3050         /* One shot, path A LOK & IQK */
3051         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3052         rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3053
3054         mdelay(1);
3055
3056         /* Check failed */
3057         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3058         reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3059         reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3060         reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3061
3062         if (!(reg_eac & BIT(28)) &&
3063             ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3064             ((reg_e9c & 0x03ff0000) != 0x00420000))
3065                 result |= 0x01;
3066         else    /* If TX not OK, ignore RX */
3067                 goto out;
3068
3069         /* If TX is OK, check whether RX is OK */
3070         if (!(reg_eac & BIT(27)) &&
3071             ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3072             ((reg_eac & 0x03ff0000) != 0x00360000))
3073                 result |= 0x02;
3074         else
3075                 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3076                          __func__);
3077 out:
3078         return result;
3079 }
3080
3081 static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3082 {
3083         u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3084         int result = 0;
3085
3086         /* One shot, path B LOK & IQK */
3087         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3088         rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3089
3090         mdelay(1);
3091
3092         /* Check failed */
3093         reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3094         reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3095         reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3096         reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3097         reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3098
3099         if (!(reg_eac & BIT(31)) &&
3100             ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3101             ((reg_ebc & 0x03ff0000) != 0x00420000))
3102                 result |= 0x01;
3103         else
3104                 goto out;
3105
3106         if (!(reg_eac & BIT(30)) &&
3107             (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3108             (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3109                 result |= 0x02;
3110         else
3111                 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3112                          __func__);
3113 out:
3114         return result;
3115 }
3116
3117 static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3118                                      int result[][8], int t)
3119 {
3120         struct device *dev = &priv->udev->dev;
3121         u32 i, val32;
3122         int path_a_ok, path_b_ok;
3123         int retry = 2;
3124         const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3125                 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3126                 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3127                 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3128                 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3129                 REG_TX_TO_TX, REG_RX_CCK,
3130                 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3131                 REG_RX_TO_RX, REG_STANDBY,
3132                 REG_SLEEP, REG_PMPD_ANAEN
3133         };
3134         const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3135                 REG_TXPAUSE, REG_BEACON_CTRL,
3136                 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3137         };
3138         const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3139                 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3140                 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3141                 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3142                 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3143         };
3144
3145         /*
3146          * Note: IQ calibration must be performed after loading
3147          *       PHY_REG.txt , and radio_a, radio_b.txt
3148          */
3149
3150         if (t == 0) {
3151                 /* Save ADDA parameters, turn Path A ADDA on */
3152                 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3153                                    RTL8XXXU_ADDA_REGS);
3154                 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3155                 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3156                                    priv->bb_backup, RTL8XXXU_BB_REGS);
3157         }
3158
3159         rtl8xxxu_path_adda_on(priv, adda_regs, true);
3160
3161         if (t == 0) {
3162                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3163                 if (val32 & FPGA0_HSSI_PARM1_PI)
3164                         priv->pi_enabled = 1;
3165         }
3166
3167         if (!priv->pi_enabled) {
3168                 /* Switch BB to PI mode to do IQ Calibration. */
3169                 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3170                 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3171         }
3172
3173         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3174         val32 &= ~FPGA_RF_MODE_CCK;
3175         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3176
3177         rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3178         rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3179         rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3180
3181         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3182         val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3183         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3184
3185         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3186         val32 &= ~BIT(10);
3187         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3188         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3189         val32 &= ~BIT(10);
3190         rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3191
3192         if (priv->tx_paths > 1) {
3193                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3194                 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3195         }
3196
3197         /* MAC settings */
3198         rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3199
3200         /* Page B init */
3201         rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3202
3203         if (priv->tx_paths > 1)
3204                 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3205
3206         /* IQ calibration setting */
3207         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3208         rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3209         rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3210
3211         for (i = 0; i < retry; i++) {
3212                 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3213                 if (path_a_ok == 0x03) {
3214                         val32 = rtl8xxxu_read32(priv,
3215                                                 REG_TX_POWER_BEFORE_IQK_A);
3216                         result[t][0] = (val32 >> 16) & 0x3ff;
3217                         val32 = rtl8xxxu_read32(priv,
3218                                                 REG_TX_POWER_AFTER_IQK_A);
3219                         result[t][1] = (val32 >> 16) & 0x3ff;
3220                         val32 = rtl8xxxu_read32(priv,
3221                                                 REG_RX_POWER_BEFORE_IQK_A_2);
3222                         result[t][2] = (val32 >> 16) & 0x3ff;
3223                         val32 = rtl8xxxu_read32(priv,
3224                                                 REG_RX_POWER_AFTER_IQK_A_2);
3225                         result[t][3] = (val32 >> 16) & 0x3ff;
3226                         break;
3227                 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3228                         /* TX IQK OK */
3229                         dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3230                                 __func__);
3231
3232                         val32 = rtl8xxxu_read32(priv,
3233                                                 REG_TX_POWER_BEFORE_IQK_A);
3234                         result[t][0] = (val32 >> 16) & 0x3ff;
3235                         val32 = rtl8xxxu_read32(priv,
3236                                                 REG_TX_POWER_AFTER_IQK_A);
3237                         result[t][1] = (val32 >> 16) & 0x3ff;
3238                 }
3239         }
3240
3241         if (!path_a_ok)
3242                 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3243
3244         if (priv->tx_paths > 1) {
3245                 /*
3246                  * Path A into standby
3247                  */
3248                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3249                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3250                 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3251
3252                 /* Turn Path B ADDA on */
3253                 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3254
3255                 for (i = 0; i < retry; i++) {
3256                         path_b_ok = rtl8xxxu_iqk_path_b(priv);
3257                         if (path_b_ok == 0x03) {
3258                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3259                                 result[t][4] = (val32 >> 16) & 0x3ff;
3260                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3261                                 result[t][5] = (val32 >> 16) & 0x3ff;
3262                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3263                                 result[t][6] = (val32 >> 16) & 0x3ff;
3264                                 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3265                                 result[t][7] = (val32 >> 16) & 0x3ff;
3266                                 break;
3267                         } else if (i == (retry - 1) && path_b_ok == 0x01) {
3268                                 /* TX IQK OK */
3269                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3270                                 result[t][4] = (val32 >> 16) & 0x3ff;
3271                                 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3272                                 result[t][5] = (val32 >> 16) & 0x3ff;
3273                         }
3274                 }
3275
3276                 if (!path_b_ok)
3277                         dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3278         }
3279
3280         /* Back to BB mode, load original value */
3281         rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3282
3283         if (t) {
3284                 if (!priv->pi_enabled) {
3285                         /*
3286                          * Switch back BB to SI mode after finishing
3287                          * IQ Calibration
3288                          */
3289                         val32 = 0x01000000;
3290                         rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3291                         rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3292                 }
3293
3294                 /* Reload ADDA power saving parameters */
3295                 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3296                                       RTL8XXXU_ADDA_REGS);
3297
3298                 /* Reload MAC parameters */
3299                 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3300
3301                 /* Reload BB parameters */
3302                 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3303                                       priv->bb_backup, RTL8XXXU_BB_REGS);
3304
3305                 /* Restore RX initial gain */
3306                 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3307
3308                 if (priv->tx_paths > 1) {
3309                         rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3310                                          0x00032ed3);
3311                 }
3312
3313                 /* Load 0xe30 IQC default value */
3314                 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3315                 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3316         }
3317 }
3318
3319 static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3320 {
3321         struct device *dev = &priv->udev->dev;
3322         int result[4][8];       /* last is final result */
3323         int i, candidate;
3324         bool path_a_ok, path_b_ok;
3325         u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3326         u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3327         s32 reg_tmp = 0;
3328         bool simu;
3329
3330         memset(result, 0, sizeof(result));
3331         candidate = -1;
3332
3333         path_a_ok = false;
3334         path_b_ok = false;
3335
3336         rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3337
3338         for (i = 0; i < 3; i++) {
3339                 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3340
3341                 if (i == 1) {
3342                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3343                         if (simu) {
3344                                 candidate = 0;
3345                                 break;
3346                         }
3347                 }
3348
3349                 if (i == 2) {
3350                         simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3351                         if (simu) {
3352                                 candidate = 0;
3353                                 break;
3354                         }
3355
3356                         simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3357                         if (simu) {
3358                                 candidate = 1;
3359                         } else {
3360                                 for (i = 0; i < 8; i++)
3361                                         reg_tmp += result[3][i];
3362
3363                                 if (reg_tmp)
3364                                         candidate = 3;
3365                                 else
3366                                         candidate = -1;
3367                         }
3368                 }
3369         }
3370
3371         for (i = 0; i < 4; i++) {
3372                 reg_e94 = result[i][0];
3373                 reg_e9c = result[i][1];
3374                 reg_ea4 = result[i][2];
3375                 reg_eac = result[i][3];
3376                 reg_eb4 = result[i][4];
3377                 reg_ebc = result[i][5];
3378                 reg_ec4 = result[i][6];
3379                 reg_ecc = result[i][7];
3380         }
3381
3382         if (candidate >= 0) {
3383                 reg_e94 = result[candidate][0];
3384                 priv->rege94 =  reg_e94;
3385                 reg_e9c = result[candidate][1];
3386                 priv->rege9c = reg_e9c;
3387                 reg_ea4 = result[candidate][2];
3388                 reg_eac = result[candidate][3];
3389                 reg_eb4 = result[candidate][4];
3390                 priv->regeb4 = reg_eb4;
3391                 reg_ebc = result[candidate][5];
3392                 priv->regebc = reg_ebc;
3393                 reg_ec4 = result[candidate][6];
3394                 reg_ecc = result[candidate][7];
3395                 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3396                 dev_dbg(dev,
3397                         "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3398                         "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3399                         reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3400                 path_a_ok = true;
3401                 path_b_ok = true;
3402         } else {
3403                 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3404                 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3405         }
3406
3407         if (reg_e94 && candidate >= 0)
3408                 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3409                                            candidate, (reg_ea4 == 0));
3410
3411         if (priv->tx_paths > 1 && reg_eb4)
3412                 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3413                                            candidate, (reg_ec4 == 0));
3414
3415         rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3416                            priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3417 }
3418
3419 static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3420 {
3421         u32 val32;
3422         u32 rf_amode, rf_bmode = 0, lstf;
3423
3424         /* Check continuous TX and Packet TX */
3425         lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3426
3427         if (lstf & OFDM_LSTF_MASK) {
3428                 /* Disable all continuous TX */
3429                 val32 = lstf & ~OFDM_LSTF_MASK;
3430                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3431
3432                 /* Read original RF mode Path A */
3433                 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3434
3435                 /* Set RF mode to standby Path A */
3436                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3437                                      (rf_amode & 0x8ffff) | 0x10000);
3438
3439                 /* Path-B */
3440                 if (priv->tx_paths > 1) {
3441                         rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3442                                                        RF6052_REG_AC);
3443
3444                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3445                                              (rf_bmode & 0x8ffff) | 0x10000);
3446                 }
3447         } else {
3448                 /*  Deal with Packet TX case */
3449                 /*  block all queues */
3450                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3451         }
3452
3453         /* Start LC calibration */
3454         val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3455         val32 |= 0x08000;
3456         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3457
3458         msleep(100);
3459
3460         /* Restore original parameters */
3461         if (lstf & OFDM_LSTF_MASK) {
3462                 /* Path-A */
3463                 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3464                 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3465
3466                 /* Path-B */
3467                 if (priv->tx_paths > 1)
3468                         rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3469                                              rf_bmode);
3470         } else /*  Deal with Packet TX case */
3471                 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3472 }
3473
3474 static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3475 {
3476         int i;
3477         u16 reg;
3478
3479         reg = REG_MACID;
3480
3481         for (i = 0; i < ETH_ALEN; i++)
3482                 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3483
3484         return 0;
3485 }
3486
3487 static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3488 {
3489         int i;
3490         u16 reg;
3491
3492         dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3493
3494         reg = REG_BSSID;
3495
3496         for (i = 0; i < ETH_ALEN; i++)
3497                 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3498
3499         return 0;
3500 }
3501
3502 static void
3503 rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3504 {
3505         u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3506         u8 max_agg = 0xf;
3507         int i;
3508
3509         ampdu_factor = 1 << (ampdu_factor + 2);
3510         if (ampdu_factor > max_agg)
3511                 ampdu_factor = max_agg;
3512
3513         for (i = 0; i < 4; i++) {
3514                 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3515                         vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3516
3517                 if ((vals[i] & 0x0f) > ampdu_factor)
3518                         vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3519
3520                 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3521         }
3522 }
3523
3524 static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3525 {
3526         u8 val8;
3527
3528         val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3529         val8 &= 0xf8;
3530         val8 |= density;
3531         rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3532 }
3533
3534 static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3535 {
3536         u8 val8;
3537         int count, ret;
3538
3539         /* Start of rtl8723AU_card_enable_flow */
3540         /* Act to Cardemu sequence*/
3541         /* Turn off RF */
3542         rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3543
3544         /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3545         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3546         val8 &= ~LEDCFG2_DPDT_SELECT;
3547         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3548
3549         /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3550         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3551         val8 |= BIT(1);
3552         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3553
3554         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3555                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3556                 if ((val8 & BIT(1)) == 0)
3557                         break;
3558                 udelay(10);
3559         }
3560
3561         if (!count) {
3562                 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3563                          __func__);
3564                 ret = -EBUSY;
3565                 goto exit;
3566         }
3567
3568         /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3569         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3570         val8 |= SYS_ISO_ANALOG_IPS;
3571         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3572
3573         /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3574         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3575         val8 &= ~LDOA15_ENABLE;
3576         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3577
3578 exit:
3579         return ret;
3580 }
3581
3582 static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3583 {
3584         u8 val8;
3585         u8 val32;
3586         int count, ret;
3587
3588         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3589
3590         /*
3591          * Poll - wait for RX packet to complete
3592          */
3593         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3594                 val32 = rtl8xxxu_read32(priv, 0x5f8);
3595                 if (!val32)
3596                         break;
3597                 udelay(10);
3598         }
3599
3600         if (!count) {
3601                 dev_warn(&priv->udev->dev,
3602                          "%s: RX poll timed out (0x05f8)\n", __func__);
3603                 ret = -EBUSY;
3604                 goto exit;
3605         }
3606
3607         /* Disable CCK and OFDM, clock gated */
3608         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3609         val8 &= ~SYS_FUNC_BBRSTB;
3610         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3611
3612         udelay(2);
3613
3614         /* Reset baseband */
3615         val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3616         val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3617         rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3618
3619         /* Reset MAC TRX */
3620         val8 = rtl8xxxu_read8(priv, REG_CR);
3621         val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3622         rtl8xxxu_write8(priv, REG_CR, val8);
3623
3624         /* Reset MAC TRX */
3625         val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3626         val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3627         rtl8xxxu_write8(priv, REG_CR + 1, val8);
3628
3629         /* Respond TX OK to scheduler */
3630         val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3631         val8 |= DUAL_TSF_TX_OK;
3632         rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3633
3634 exit:
3635         return ret;
3636 }
3637
3638 static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3639 {
3640         u8 val8;
3641
3642         /* Clear suspend enable and power down enable*/
3643         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3644         val8 &= ~(BIT(3) | BIT(7));
3645         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3646
3647         /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3648         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3649         val8 &= ~BIT(0);
3650         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3651
3652         /* 0x04[12:11] = 11 enable WL suspend*/
3653         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3654         val8 &= ~(BIT(3) | BIT(4));
3655         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3656 }
3657
3658 static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3659 {
3660         u8 val8;
3661         u32 val32;
3662         int count, ret = 0;
3663
3664         /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3665         val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3666         val8 |= LDOA15_ENABLE;
3667         rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3668
3669         /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3670         val8 = rtl8xxxu_read8(priv, 0x0067);
3671         val8 &= ~BIT(4);
3672         rtl8xxxu_write8(priv, 0x0067, val8);
3673
3674         mdelay(1);
3675
3676         /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3677         val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3678         val8 &= ~SYS_ISO_ANALOG_IPS;
3679         rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3680
3681         /* disable SW LPS 0x04[10]= 0 */
3682         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3683         val8 &= ~BIT(2);
3684         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3685
3686         /* wait till 0x04[17] = 1 power ready*/
3687         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3688                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3689                 if (val32 & BIT(17))
3690                         break;
3691
3692                 udelay(10);
3693         }
3694
3695         if (!count) {
3696                 ret = -EBUSY;
3697                 goto exit;
3698         }
3699
3700         /* We should be able to optimize the following three entries into one */
3701
3702         /* release WLON reset 0x04[16]= 1*/
3703         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3704         val8 |= BIT(0);
3705         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3706
3707         /* disable HWPDN 0x04[15]= 0*/
3708         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3709         val8 &= ~BIT(7);
3710         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3711
3712         /* disable WL suspend*/
3713         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3714         val8 &= ~(BIT(3) | BIT(4));
3715         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3716
3717         /* set, then poll until 0 */
3718         val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3719         val32 |= APS_FSMCO_MAC_ENABLE;
3720         rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3721
3722         for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3723                 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3724                 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3725                         ret = 0;
3726                         break;
3727                 }
3728                 udelay(10);
3729         }
3730
3731         if (!count) {
3732                 ret = -EBUSY;
3733                 goto exit;
3734         }
3735
3736         /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3737         /*
3738          * Note: Vendor driver actually clears this bit, despite the
3739          * documentation claims it's being set!
3740          */
3741         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3742         val8 |= LEDCFG2_DPDT_SELECT;
3743         val8 &= ~LEDCFG2_DPDT_SELECT;
3744         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3745
3746 exit:
3747         return ret;
3748 }
3749
3750 static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3751 {
3752         u8 val8;
3753
3754         /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3755         rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3756
3757         /* 0x04[12:11] = 01 enable WL suspend */
3758         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3759         val8 &= ~BIT(4);
3760         val8 |= BIT(3);
3761         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3762
3763         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3764         val8 |= BIT(7);
3765         rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3766
3767         /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3768         val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3769         val8 |= BIT(0);
3770         rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3771
3772         return 0;
3773 }
3774
3775 static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3776 {
3777         u8 val8;
3778         u16 val16;
3779         u32 val32;
3780         int ret;
3781
3782         /*
3783          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3784          */
3785         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3786
3787         rtl8xxxu_disabled_to_emu(priv);
3788
3789         ret = rtl8xxxu_emu_to_active(priv);
3790         if (ret)
3791                 goto exit;
3792
3793         /*
3794          * 0x0004[19] = 1, reset 8051
3795          */
3796         val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3797         val8 |= BIT(3);
3798         rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3799
3800         /*
3801          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3802          * Set CR bit10 to enable 32k calibration.
3803          */
3804         val16 = rtl8xxxu_read16(priv, REG_CR);
3805         val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3806                   CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3807                   CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3808                   CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3809                   CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3810         rtl8xxxu_write16(priv, REG_CR, val16);
3811
3812         /* For EFuse PG */
3813         val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3814         val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3815         val32 |= (0x06 << 28);
3816         rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3817 exit:
3818         return ret;
3819 }
3820
3821 #ifdef CONFIG_RTL8XXXU_UNTESTED
3822
3823 static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3824 {
3825         u8 val8;
3826         u16 val16;
3827         u32 val32;
3828         int i;
3829
3830         for (i = 100; i; i--) {
3831                 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3832                 if (val8 & APS_FSMCO_PFM_ALDN)
3833                         break;
3834         }
3835
3836         if (!i) {
3837                 pr_info("%s: Poll failed\n", __func__);
3838                 return -ENODEV;
3839         }
3840
3841         /*
3842          * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3843          */
3844         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3845         rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
3846         udelay(100);
3847
3848         val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
3849         if (!(val8 & LDOV12D_ENABLE)) {
3850                 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
3851                 val8 |= LDOV12D_ENABLE;
3852                 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
3853
3854                 udelay(100);
3855
3856                 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3857                 val8 &= ~SYS_ISO_MD2PP;
3858                 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3859         }
3860
3861         /*
3862          * Auto enable WLAN
3863          */
3864         val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3865         val16 |= APS_FSMCO_MAC_ENABLE;
3866         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3867
3868         for (i = 1000; i; i--) {
3869                 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
3870                 if (!(val16 & APS_FSMCO_MAC_ENABLE))
3871                         break;
3872         }
3873         if (!i) {
3874                 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
3875                 return -EBUSY;
3876         }
3877
3878         /*
3879          * Enable radio, GPIO, LED
3880          */
3881         val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
3882                 APS_FSMCO_PFM_ALDN;
3883         rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
3884
3885         /*
3886          * Release RF digital isolation
3887          */
3888         val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
3889         val16 &= ~SYS_ISO_DIOR;
3890         rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
3891
3892         val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3893         val8 &= ~APSD_CTRL_OFF;
3894         rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
3895         for (i = 200; i; i--) {
3896                 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
3897                 if (!(val8 & APSD_CTRL_OFF_STATUS))
3898                         break;
3899         }
3900
3901         if (!i) {
3902                 pr_info("%s: APSD_CTRL poll failed\n", __func__);
3903                 return -EBUSY;
3904         }
3905
3906         /*
3907          * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3908          */
3909         val16 = rtl8xxxu_read16(priv, REG_CR);
3910         val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3911                 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
3912                 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
3913         rtl8xxxu_write16(priv, REG_CR, val16);
3914
3915         /*
3916          * Workaround for 8188RU LNA power leakage problem.
3917          */
3918         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3919                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3920                 val32 &= ~BIT(1);
3921                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3922         }
3923         return 0;
3924 }
3925
3926 #endif
3927
3928 static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3929 {
3930         u8 val8;
3931         u16 val16;
3932         u32 val32;
3933
3934         /*
3935          * Workaround for 8188RU LNA power leakage problem.
3936          */
3937         if (priv->rtlchip == 0x8188c && priv->hi_pa) {
3938                 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3939                 val32 |= BIT(1);
3940                 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3941         }
3942
3943         rtl8xxxu_active_to_lps(priv);
3944
3945         /* Turn off RF */
3946         rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3947
3948         /* Reset Firmware if running in RAM */
3949         if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3950                 rtl8xxxu_firmware_self_reset(priv);
3951
3952         /* Reset MCU */
3953         val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3954         val16 &= ~SYS_FUNC_CPU_ENABLE;
3955         rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3956
3957         /* Reset MCU ready status */
3958         rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3959
3960         rtl8xxxu_active_to_emu(priv);
3961         rtl8xxxu_emu_to_disabled(priv);
3962
3963         /* Reset MCU IO Wrapper */
3964         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3965         val8 &= ~BIT(0);
3966         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3967
3968         val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3969         val8 |= BIT(0);
3970         rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3971
3972         /* RSV_CTRL 0x1C[7:0] = 0x0e  lock ISO/CLK/Power control register */
3973         rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3974 }
3975
3976 static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
3977 {
3978         if (!priv->has_bluetooth)
3979                 return;
3980 }
3981
3982 static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3983 {
3984         struct rtl8xxxu_priv *priv = hw->priv;
3985         struct device *dev = &priv->udev->dev;
3986         struct rtl8xxxu_rfregval *rftable;
3987         bool macpower;
3988         int ret;
3989         u8 val8;
3990         u16 val16;
3991         u32 val32;
3992
3993         /* Check if MAC is already powered on */
3994         val8 = rtl8xxxu_read8(priv, REG_CR);
3995
3996         /*
3997          * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
3998          * initialized. First MAC returns 0xea, second MAC returns 0x00
3999          */
4000         if (val8 == 0xea)
4001                 macpower = false;
4002         else
4003                 macpower = true;
4004
4005         ret = priv->fops->power_on(priv);
4006         if (ret < 0) {
4007                 dev_warn(dev, "%s: Failed power on\n", __func__);
4008                 goto exit;
4009         }
4010
4011         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4012         if (!macpower) {
4013                 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4014                 if (ret) {
4015                         dev_warn(dev, "%s: LLT table init failed\n", __func__);
4016                         goto exit;
4017                 }
4018         }
4019
4020         ret = rtl8xxxu_download_firmware(priv);
4021         dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4022         if (ret)
4023                 goto exit;
4024         ret = rtl8xxxu_start_firmware(priv);
4025         dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4026         if (ret)
4027                 goto exit;
4028
4029         ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4030         dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4031         if (ret)
4032                 goto exit;
4033
4034         ret = rtl8xxxu_init_phy_bb(priv);
4035         dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4036         if (ret)
4037                 goto exit;
4038
4039         switch(priv->rtlchip) {
4040         case 0x8723a:
4041                 rftable = rtl8723au_radioa_1t_init_table;
4042                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4043                 break;
4044         case 0x8188c:
4045                 if (priv->hi_pa)
4046                         rftable = rtl8188ru_radioa_1t_highpa_table;
4047                 else
4048                         rftable = rtl8192cu_radioa_1t_init_table;
4049                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4050                 break;
4051         case 0x8191c:
4052                 rftable = rtl8192cu_radioa_1t_init_table;
4053                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4054                 break;
4055         case 0x8192c:
4056                 rftable = rtl8192cu_radioa_2t_init_table;
4057                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4058                 if (ret)
4059                         break;
4060                 rftable = rtl8192cu_radiob_2t_init_table;
4061                 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4062                 break;
4063         default:
4064                 ret = -EINVAL;
4065         }
4066
4067         if (ret)
4068                 goto exit;
4069
4070         /* Reduce 80M spur */
4071         rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4072         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4073         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4074         rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4075
4076         /* RFSW Control - clear bit 14 ?? */
4077         rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4078         /* 0x07000760 */
4079         val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4080                 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4081                 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4082                  FPGA0_RF_BD_CTRL_SHIFT);
4083         rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4084         /* 0x860[6:5]= 00 - why? - this sets antenna B */
4085         rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4086
4087         priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4088                                                   RF6052_REG_MODE_AG);
4089
4090         dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4091         if (!macpower) {
4092                 if (priv->ep_tx_normal_queue)
4093                         val8 = TX_PAGE_NUM_NORM_PQ;
4094                 else
4095                         val8 = 0;
4096
4097                 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4098
4099                 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4100
4101                 if (priv->ep_tx_high_queue)
4102                         val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4103                 if (priv->ep_tx_low_queue)
4104                         val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4105
4106                 rtl8xxxu_write32(priv, REG_RQPN, val32);
4107
4108                 /*
4109                  * Set TX buffer boundary
4110                  */
4111                 val8 = TX_TOTAL_PAGE_NUM + 1;
4112                 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4113                 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4114                 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4115                 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4116                 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4117         }
4118
4119         ret = rtl8xxxu_init_queue_priority(priv);
4120         dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4121         if (ret)
4122                 goto exit;
4123
4124         /*
4125          * Set RX page boundary
4126          */
4127         rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4128         /*
4129          * Transfer page size is always 128
4130          */
4131         val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4132                 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4133         rtl8xxxu_write8(priv, REG_PBP, val8);
4134
4135         /*
4136          * Unit in 8 bytes, not obvious what it is used for
4137          */
4138         rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4139
4140         /*
4141          * Enable all interrupts - not obvious USB needs to do this
4142          */
4143         rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4144         rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4145
4146         rtl8xxxu_set_mac(priv);
4147         rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4148
4149         /*
4150          * Configure initial WMAC settings
4151          */
4152         val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4153                 /* RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON | */
4154                 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4155                 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4156         rtl8xxxu_write32(priv, REG_RCR, val32);
4157
4158         /*
4159          * Accept all multicast
4160          */
4161         rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4162         rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4163
4164         /*
4165          * Init adaptive controls
4166          */
4167         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4168         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4169         val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4170         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4171
4172         /* CCK = 0x0a, OFDM = 0x10 */
4173         rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4174         rtl8xxxu_set_retry(priv, 0x30, 0x30);
4175         rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4176
4177         /*
4178          * Init EDCA
4179          */
4180         rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4181
4182         /* Set CCK SIFS */
4183         rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4184
4185         /* Set OFDM SIFS */
4186         rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4187
4188         /* TXOP */
4189         rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4190         rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4191         rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4192         rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4193
4194         /* Set data auto rate fallback retry count */
4195         rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4196         rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4197         rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4198         rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4199
4200         val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4201         val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4202         rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4203
4204         /*  Set ACK timeout */
4205         rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4206
4207         /*
4208          * Initialize beacon parameters
4209          */
4210         val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4211         rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4212         rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4213         rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4214         rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4215         rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4216
4217         /*
4218          * Enable CCK and OFDM block
4219          */
4220         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4221         val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4222         rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4223
4224         /*
4225          * Invalidate all CAM entries - bit 30 is undocumented
4226          */
4227         rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4228
4229         /*
4230          * Start out with default power levels for channel 6, 20MHz
4231          */
4232         rtl8723a_set_tx_power(priv, 1, false);
4233
4234         /* Let the 8051 take control of antenna setting */
4235         val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4236         val8 |= LEDCFG2_DPDT_SELECT;
4237         rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4238
4239         rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4240
4241         /* Disable BAR - not sure if this has any effect on USB */
4242         rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4243
4244         rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4245
4246         /*
4247          * Not sure if we should get into this at all
4248          */
4249         if (priv->iqk_initialized) {
4250                 rtl8xxxu_restore_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
4251                                       priv->bb_recovery_backup,
4252                                       RTL8XXXU_BB_REGS);
4253         } else {
4254                 rtl8723a_phy_iq_calibrate(priv);
4255                 priv->iqk_initialized = true;
4256         }
4257
4258         /*
4259          * This should enable thermal meter
4260          */
4261         rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4262
4263         rtl8723a_phy_lc_calibrate(priv);
4264
4265         /* fix USB interface interference issue */
4266         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4267         rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4268         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4269         rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4270
4271         /* Solve too many protocol error on USB bus */
4272         /* Can't do this for 8188/8192 UMC A cut parts */
4273         rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4274         rtl8xxxu_write8(priv, 0xfe41, 0x94);
4275         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4276
4277         rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4278         rtl8xxxu_write8(priv, 0xfe41, 0x19);
4279         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4280
4281         rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4282         rtl8xxxu_write8(priv, 0xfe41, 0x91);
4283         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4284
4285         rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4286         rtl8xxxu_write8(priv, 0xfe41, 0x81);
4287         rtl8xxxu_write8(priv, 0xfe42, 0x80);
4288
4289         /* Init BT hw config. */
4290         rtl8xxxu_init_bt(priv);
4291
4292         /*
4293          * Not sure if we really need to save these parameters, but the
4294          * vendor driver does
4295          */
4296         val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4297         if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4298                 priv->path_a_hi_power = 1;
4299
4300         val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4301         priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4302
4303         val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4304         priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4305
4306         /* Set NAV_UPPER to 30000us */
4307         val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4308         rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4309
4310         /*
4311          * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4312          * but we need to fin root cause.
4313          */
4314         val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4315         if ((val32 & 0xff000000) != 0x83000000) {
4316                 val32 |= FPGA_RF_MODE_CCK;
4317                 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4318         }
4319
4320         val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4321         val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4322         /* ack for xmit mgmt frames. */
4323         rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4324
4325 exit:
4326         return ret;
4327 }
4328
4329 static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4330 {
4331         struct rtl8xxxu_priv *priv = hw->priv;
4332
4333         rtl8xxxu_power_off(priv);
4334 }
4335
4336 static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4337                                struct ieee80211_key_conf *key, const u8 *mac)
4338 {
4339         u32 cmd, val32, addr, ctrl;
4340         int j, i, tmp_debug;
4341
4342         tmp_debug = rtl8xxxu_debug;
4343         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4344                 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4345
4346         /*
4347          * This is a bit of a hack - the lower bits of the cipher
4348          * suite selector happens to match the cipher index in the CAM
4349          */
4350         addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4351         ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4352
4353         for (j = 5; j >= 0; j--) {
4354                 switch (j) {
4355                 case 0:
4356                         val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4357                         break;
4358                 case 1:
4359                         val32 = mac[2] | (mac[3] << 8) |
4360                                 (mac[4] << 16) | (mac[5] << 24);
4361                         break;
4362                 default:
4363                         i = (j - 2) << 2;
4364                         val32 = key->key[i] | (key->key[i + 1] << 8) |
4365                                 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4366                         break;
4367                 }
4368
4369                 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4370                 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4371                 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4372                 udelay(100);
4373         }
4374
4375         rtl8xxxu_debug = tmp_debug;
4376 }
4377
4378 static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4379                                    struct ieee80211_vif *vif, const u8* mac)
4380 {
4381         struct rtl8xxxu_priv *priv = hw->priv;
4382         u8 val8;
4383
4384         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4385         val8 |= BEACON_DISABLE_TSF_UPDATE;
4386         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4387 }
4388
4389 static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4390                                       struct ieee80211_vif *vif)
4391 {
4392         struct rtl8xxxu_priv *priv = hw->priv;
4393         u8 val8;
4394
4395         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4396         val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4397         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4398 }
4399
4400 static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4401                                       u32 ramask, int sgi)
4402 {
4403         struct h2c_cmd h2c;
4404
4405         h2c.ramask.cmd = H2C_SET_RATE_MASK;
4406         h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4407         h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4408
4409         h2c.ramask.arg = 0x80;
4410         if (sgi)
4411                 h2c.ramask.arg |= 0x20;
4412
4413         dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4414                 ramask, h2c.ramask.arg);
4415         rtl8723a_h2c_cmd(priv, &h2c);
4416 }
4417
4418 static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4419 {
4420         u32 val32;
4421         u8 rate_idx = 0;
4422
4423         rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4424
4425         val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4426         val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4427         val32 |= rate_cfg;
4428         rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4429
4430         dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4431
4432         while (rate_cfg) {
4433                 rate_cfg = (rate_cfg >> 1);
4434                 rate_idx++;
4435         }
4436         rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4437 }
4438
4439 static void
4440 rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4441                           struct ieee80211_bss_conf *bss_conf, u32 changed)
4442 {
4443         struct rtl8xxxu_priv *priv = hw->priv;
4444         struct device *dev = &priv->udev->dev;
4445         struct ieee80211_sta *sta;
4446         u32 val32;
4447         u8 val8;
4448
4449         if (changed & BSS_CHANGED_ASSOC) {
4450                 struct h2c_cmd h2c;
4451
4452                 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4453
4454                 memset(&h2c, 0, sizeof(struct h2c_cmd));
4455                 rtl8xxxu_set_linktype(priv, vif->type);
4456
4457                 if (bss_conf->assoc) {
4458                         u32 ramask;
4459                         int sgi = 0;
4460
4461                         rcu_read_lock();
4462                         sta = ieee80211_find_sta(vif, bss_conf->bssid);
4463                         if (!sta) {
4464                                 dev_info(dev, "%s: ASSOC no sta found\n",
4465                                          __func__);
4466                                 rcu_read_unlock();
4467                                 goto error;
4468                         }
4469
4470                         if (sta->ht_cap.ht_supported)
4471                                 dev_info(dev, "%s: HT supported\n", __func__);
4472                         if (sta->vht_cap.vht_supported)
4473                                 dev_info(dev, "%s: VHT supported\n", __func__);
4474
4475                         /* TODO: Set bits 28-31 for rate adaptive id */
4476                         ramask = (sta->supp_rates[0] & 0xfff) |
4477                                 sta->ht_cap.mcs.rx_mask[0] << 12 |
4478                                 sta->ht_cap.mcs.rx_mask[1] << 20;
4479                         if (sta->ht_cap.cap &
4480                             (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4481                                 sgi = 1;
4482                         rcu_read_unlock();
4483
4484                         rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4485
4486                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4487                         val32 |= RCR_CHECK_BSSID_MATCH | RCR_CHECK_BSSID_BEACON;
4488                         rtl8xxxu_write32(priv, REG_RCR, val32);
4489
4490                         /* Enable RX of data frames */
4491                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
4492
4493                         rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4494
4495                         rtl8723a_stop_tx_beacon(priv);
4496
4497                         /* joinbss sequence */
4498                         rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4499                                          0xc000 | bss_conf->aid);
4500
4501                         h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4502                 } else {
4503                         val32 = rtl8xxxu_read32(priv, REG_RCR);
4504                         val32 &= ~(RCR_CHECK_BSSID_MATCH |
4505                                    RCR_CHECK_BSSID_BEACON);
4506                         rtl8xxxu_write32(priv, REG_RCR, val32);
4507
4508                         val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4509                         val8 |= BEACON_DISABLE_TSF_UPDATE;
4510                         rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4511
4512                         /* Disable RX of data frames */
4513                         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
4514                         h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4515                 }
4516                 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4517                 rtl8723a_h2c_cmd(priv, &h2c);
4518         }
4519
4520         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4521                 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4522                         bss_conf->use_short_preamble);
4523                 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4524                 if (bss_conf->use_short_preamble)
4525                         val32 |= RSR_ACK_SHORT_PREAMBLE;
4526                 else
4527                         val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4528                 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4529         }
4530
4531         if (changed & BSS_CHANGED_ERP_SLOT) {
4532                 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4533                         bss_conf->use_short_slot);
4534
4535                 if (bss_conf->use_short_slot)
4536                         val8 = 9;
4537                 else
4538                         val8 = 20;
4539                 rtl8xxxu_write8(priv, REG_SLOT, val8);
4540         }
4541
4542         if (changed & BSS_CHANGED_BSSID) {
4543                 dev_dbg(dev, "Changed BSSID!\n");
4544                 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4545         }
4546
4547         if (changed & BSS_CHANGED_BASIC_RATES) {
4548                 dev_dbg(dev, "Changed BASIC_RATES!\n");
4549                 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4550         }
4551 error:
4552         return;
4553 }
4554
4555 static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4556 {
4557         u32 rtlqueue;
4558
4559         switch (queue) {
4560         case IEEE80211_AC_VO:
4561                 rtlqueue = TXDESC_QUEUE_VO;
4562                 break;
4563         case IEEE80211_AC_VI:
4564                 rtlqueue = TXDESC_QUEUE_VI;
4565                 break;
4566         case IEEE80211_AC_BE:
4567                 rtlqueue = TXDESC_QUEUE_BE;
4568                 break;
4569         case IEEE80211_AC_BK:
4570                 rtlqueue = TXDESC_QUEUE_BK;
4571                 break;
4572         default:
4573                 rtlqueue = TXDESC_QUEUE_BE;
4574         }
4575
4576         return rtlqueue;
4577 }
4578
4579 static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4580 {
4581         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4582         u32 queue;
4583
4584         if (ieee80211_is_mgmt(hdr->frame_control))
4585                 queue = TXDESC_QUEUE_MGNT;
4586         else
4587                 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4588
4589         return queue;
4590 }
4591
4592 static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4593 {
4594         __le16 *ptr = (__le16 *)tx_desc;
4595         u16 csum = 0;
4596         int i;
4597
4598         /*
4599          * Clear csum field before calculation, as the csum field is
4600          * in the middle of the struct.
4601          */
4602         tx_desc->csum = cpu_to_le16(0);
4603
4604         for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4605                 csum = csum ^ le16_to_cpu(ptr[i]);
4606
4607         tx_desc->csum |= cpu_to_le16(csum);
4608 }
4609
4610 static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4611 {
4612         struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4613         unsigned long flags;
4614
4615         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4616         list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4617                 list_del(&tx_urb->list);
4618                 priv->tx_urb_free_count--;
4619                 usb_free_urb(&tx_urb->urb);
4620         }
4621         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4622 }
4623
4624 static struct rtl8xxxu_tx_urb *
4625 rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4626 {
4627         struct rtl8xxxu_tx_urb *tx_urb;
4628         unsigned long flags;
4629
4630         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4631         tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4632                                           struct rtl8xxxu_tx_urb, list);
4633         if (tx_urb) {
4634                 list_del(&tx_urb->list);
4635                 priv->tx_urb_free_count--;
4636                 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4637                     !priv->tx_stopped) {
4638                         priv->tx_stopped = true;
4639                         ieee80211_stop_queues(priv->hw);
4640                 }
4641         }
4642
4643         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4644
4645         return tx_urb;
4646 }
4647
4648 static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4649                                  struct rtl8xxxu_tx_urb *tx_urb)
4650 {
4651         unsigned long flags;
4652
4653         INIT_LIST_HEAD(&tx_urb->list);
4654
4655         spin_lock_irqsave(&priv->tx_urb_lock, flags);
4656
4657         list_add(&tx_urb->list, &priv->tx_urb_free_list);
4658         priv->tx_urb_free_count++;
4659         if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4660             priv->tx_stopped) {
4661                 priv->tx_stopped = false;
4662                 ieee80211_wake_queues(priv->hw);
4663         }
4664
4665         spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4666 }
4667
4668 static void rtl8xxxu_tx_complete(struct urb *urb)
4669 {
4670         struct sk_buff *skb = (struct sk_buff *)urb->context;
4671         struct ieee80211_tx_info *tx_info;
4672         struct ieee80211_hw *hw;
4673         struct rtl8xxxu_tx_urb *tx_urb =
4674                 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4675
4676         tx_info = IEEE80211_SKB_CB(skb);
4677         hw = tx_info->rate_driver_data[0];
4678
4679         skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4680
4681         ieee80211_tx_info_clear_status(tx_info);
4682         tx_info->status.rates[0].idx = -1;
4683         tx_info->status.rates[0].count = 0;
4684
4685         if (!urb->status)
4686                 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4687
4688         ieee80211_tx_status_irqsafe(hw, skb);
4689
4690         rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4691 }
4692
4693 static void rtl8xxxu_dump_action(struct device *dev,
4694                                  struct ieee80211_hdr *hdr)
4695 {
4696         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4697         u16 cap, timeout;
4698
4699         if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4700                 return;
4701
4702         switch (mgmt->u.action.u.addba_resp.action_code) {
4703         case WLAN_ACTION_ADDBA_RESP:
4704                 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4705                 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4706                 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4707                          "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4708                          "status %02x\n",
4709                          timeout,
4710                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4711                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4712                          (cap >> 1) & 0x1,
4713                          le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4714                 break;
4715         case WLAN_ACTION_ADDBA_REQ:
4716                 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4717                 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4718                 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4719                          "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4720                          timeout,
4721                          (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4722                          (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4723                          (cap >> 1) & 0x1);
4724                 break;
4725         default:
4726                 dev_info(dev, "action frame %02x\n",
4727                          mgmt->u.action.u.addba_resp.action_code);
4728                 break;
4729         }
4730 }
4731
4732 static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4733                         struct ieee80211_tx_control *control,
4734                         struct sk_buff *skb)
4735 {
4736         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4737         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4738         struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4739         struct rtl8xxxu_priv *priv = hw->priv;
4740         struct rtl8xxxu_tx_desc *tx_desc;
4741         struct rtl8xxxu_tx_urb *tx_urb;
4742         struct ieee80211_sta *sta = NULL;
4743         struct ieee80211_vif *vif = tx_info->control.vif;
4744         struct device *dev = &priv->udev->dev;
4745         u32 queue, rate;
4746         u16 pktlen = skb->len;
4747         u16 seq_number;
4748         u16 rate_flag = tx_info->control.rates[0].flags;
4749         int ret;
4750
4751         if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4752                 dev_warn(dev,
4753                          "%s: Not enough headroom (%i) for tx descriptor\n",
4754                          __func__, skb_headroom(skb));
4755                 goto error;
4756         }
4757
4758         if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4759                 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4760                          __func__, skb->len);
4761                 goto error;
4762         }
4763
4764         tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4765         if (!tx_urb) {
4766                 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4767                 goto error;
4768         }
4769
4770         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4771                 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4772                          __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4773
4774         if (ieee80211_is_action(hdr->frame_control))
4775                 rtl8xxxu_dump_action(dev, hdr);
4776
4777         tx_info->rate_driver_data[0] = hw;
4778
4779         if (control && control->sta)
4780                 sta = control->sta;
4781
4782         tx_desc = (struct rtl8xxxu_tx_desc *)
4783                 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4784
4785         memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4786         tx_desc->pkt_size = cpu_to_le16(pktlen);
4787         tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4788
4789         tx_desc->txdw0 =
4790                 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4791         if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4792             is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4793                 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4794
4795         queue = rtl8xxxu_queue_select(hw, skb);
4796         tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4797
4798         if (tx_info->control.hw_key) {
4799                 switch (tx_info->control.hw_key->cipher) {
4800                 case WLAN_CIPHER_SUITE_WEP40:
4801                 case WLAN_CIPHER_SUITE_WEP104:
4802                 case WLAN_CIPHER_SUITE_TKIP:
4803                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4804                         break;
4805                 case WLAN_CIPHER_SUITE_CCMP:
4806                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4807                         break;
4808                 default:
4809                         break;
4810                 }
4811         }
4812
4813         seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4814         tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4815
4816         if (rate_flag & IEEE80211_TX_RC_MCS)
4817                 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4818         else
4819                 rate = tx_rate->hw_value;
4820         tx_desc->txdw5 = cpu_to_le32(rate);
4821
4822         if (ieee80211_is_data(hdr->frame_control))
4823                 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4824
4825         /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4826         if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4827                 if (sta->ht_cap.ht_supported) {
4828                         u32 ampdu, val32;
4829
4830                         ampdu = (u32)sta->ht_cap.ampdu_density;
4831                         val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4832                         tx_desc->txdw2 |= cpu_to_le32(val32);
4833                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4834                 } else
4835                         tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4836         } else
4837                 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4838
4839         if (ieee80211_is_data_qos(hdr->frame_control))
4840                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4841         if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4842             (sta && vif && vif->bss_conf.use_short_preamble))
4843                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4844         if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4845             (ieee80211_is_data_qos(hdr->frame_control) &&
4846              sta && sta->ht_cap.cap &
4847              (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4848                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4849         }
4850         if (ieee80211_is_mgmt(hdr->frame_control)) {
4851                 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4852                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4853                 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4854                 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4855         }
4856
4857         if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4858                 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4859                 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4860                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4861                 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4862         }
4863
4864         rtl8xxxu_calc_tx_desc_csum(tx_desc);
4865
4866         usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
4867                           skb->data, skb->len, rtl8xxxu_tx_complete, skb);
4868
4869         usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
4870         ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
4871         if (ret) {
4872                 usb_unanchor_urb(&tx_urb->urb);
4873                 rtl8xxxu_free_tx_urb(priv, tx_urb);
4874                 goto error;
4875         }
4876         return;
4877 error:
4878         dev_kfree_skb(skb);
4879 }
4880
4881 static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
4882                                        struct ieee80211_rx_status *rx_status,
4883                                        struct rtl8xxxu_rx_desc *rx_desc,
4884                                        struct rtl8723au_phy_stats *phy_stats)
4885 {
4886         if (phy_stats->sgi_en)
4887                 rx_status->flag |= RX_FLAG_SHORT_GI;
4888
4889         if (rx_desc->rxmcs < DESC_RATE_6M) {
4890                 /*
4891                  * Handle PHY stats for CCK rates
4892                  */
4893                 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
4894
4895                 switch (cck_agc_rpt & 0xc0) {
4896                 case 0xc0:
4897                         rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
4898                         break;
4899                 case 0x80:
4900                         rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
4901                         break;
4902                 case 0x40:
4903                         rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
4904                         break;
4905                 case 0x00:
4906                         rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
4907                         break;
4908                 }
4909         } else {
4910                 rx_status->signal =
4911                         (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
4912         }
4913 }
4914
4915 static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
4916 {
4917         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4918         unsigned long flags;
4919
4920         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4921
4922         list_for_each_entry_safe(rx_urb, tmp,
4923                                  &priv->rx_urb_pending_list, list) {
4924                 list_del(&rx_urb->list);
4925                 priv->rx_urb_pending_count--;
4926                 usb_free_urb(&rx_urb->urb);
4927         }
4928
4929         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4930 }
4931
4932 static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
4933                                   struct rtl8xxxu_rx_urb *rx_urb)
4934 {
4935         struct sk_buff *skb;
4936         unsigned long flags;
4937         int pending = 0;
4938
4939         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4940
4941         if (!priv->shutdown) {
4942                 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
4943                 priv->rx_urb_pending_count++;
4944                 pending = priv->rx_urb_pending_count;
4945         } else {
4946                 skb = (struct sk_buff *)rx_urb->urb.context;
4947                 dev_kfree_skb(skb);
4948                 usb_free_urb(&rx_urb->urb);
4949         }
4950
4951         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4952
4953         if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
4954                 schedule_work(&priv->rx_urb_wq);
4955 }
4956
4957 static void rtl8xxxu_rx_urb_work(struct work_struct *work)
4958 {
4959         struct rtl8xxxu_priv *priv;
4960         struct rtl8xxxu_rx_urb *rx_urb, *tmp;
4961         struct list_head local;
4962         struct sk_buff *skb;
4963         unsigned long flags;
4964         int ret;
4965
4966         priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
4967         INIT_LIST_HEAD(&local);
4968
4969         spin_lock_irqsave(&priv->rx_urb_lock, flags);
4970
4971         list_splice_init(&priv->rx_urb_pending_list, &local);
4972         priv->rx_urb_pending_count = 0;
4973
4974         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
4975
4976         list_for_each_entry_safe(rx_urb, tmp, &local, list) {
4977                 list_del_init(&rx_urb->list);
4978                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
4979                 /*
4980                  * If out of memory or temporary error, put it back on the
4981                  * queue and try again. Otherwise the device is dead/gone
4982                  * and we should drop it.
4983                  */
4984                 switch (ret) {
4985                 case 0:
4986                         break;
4987                 case -ENOMEM:
4988                 case -EAGAIN:
4989                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
4990                         break;
4991                 default:
4992                         pr_info("failed to requeue urb %i\n", ret);
4993                         skb = (struct sk_buff *)rx_urb->urb.context;
4994                         dev_kfree_skb(skb);
4995                         usb_free_urb(&rx_urb->urb);
4996                 }
4997         }
4998 }
4999
5000 static void rtl8xxxu_rx_complete(struct urb *urb)
5001 {
5002         struct rtl8xxxu_rx_urb *rx_urb =
5003                 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5004         struct ieee80211_hw *hw = rx_urb->hw;
5005         struct rtl8xxxu_priv *priv = hw->priv;
5006         struct sk_buff *skb = (struct sk_buff *)urb->context;
5007         struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5008         struct rtl8723au_phy_stats *phy_stats;
5009         struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5010         struct ieee80211_mgmt *mgmt;
5011         struct device *dev = &priv->udev->dev;
5012         __le32 *_rx_desc_le = (__le32 *)skb->data;
5013         u32 *_rx_desc = (u32 *)skb->data;
5014         int cnt, len, drvinfo_sz, desc_shift, i;
5015
5016         for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5017                 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5018
5019         cnt = rx_desc->frag;
5020         len = rx_desc->pktlen;
5021         drvinfo_sz = rx_desc->drvinfo_sz * 8;
5022         desc_shift = rx_desc->shift;
5023         skb_put(skb, urb->actual_length);
5024
5025         if (urb->status == 0) {
5026                 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5027                 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5028
5029                 skb_pull(skb, drvinfo_sz + desc_shift);
5030
5031                 mgmt = (struct ieee80211_mgmt *)skb->data;
5032
5033                 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5034
5035                 if (rx_desc->phy_stats)
5036                         rtl8xxxu_rx_parse_phystats(priv, rx_status,
5037                                                    rx_desc, phy_stats);
5038
5039                 rx_status->freq = hw->conf.chandef.chan->center_freq;
5040                 rx_status->band = hw->conf.chandef.chan->band;
5041
5042                 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5043                 rx_status->flag |= RX_FLAG_MACTIME_START;
5044
5045                 if (!rx_desc->swdec)
5046                         rx_status->flag |= RX_FLAG_DECRYPTED;
5047                 if (rx_desc->crc32)
5048                         rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5049                 if (rx_desc->bw)
5050                         rx_status->flag |= RX_FLAG_40MHZ;
5051
5052                 if (rx_desc->rxht) {
5053                         rx_status->flag |= RX_FLAG_HT;
5054                         rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5055                 } else {
5056                         rx_status->rate_idx = rx_desc->rxmcs;
5057                 }
5058
5059                 ieee80211_rx_irqsafe(hw, skb);
5060                 skb = NULL;
5061                 rx_urb->urb.context = NULL;
5062                 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5063         } else {
5064                 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5065                 goto cleanup;
5066         }
5067         return;
5068
5069 cleanup:
5070         usb_free_urb(urb);
5071         dev_kfree_skb(skb);
5072         return;
5073 }
5074
5075 static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5076                                   struct rtl8xxxu_rx_urb *rx_urb)
5077 {
5078         struct sk_buff *skb;
5079         int skb_size;
5080         int ret;
5081
5082         skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5083         skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5084         if (!skb)
5085                 return -ENOMEM;
5086
5087         memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5088         usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5089                           skb_size, rtl8xxxu_rx_complete, skb);
5090         usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5091         ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5092         if (ret)
5093                 usb_unanchor_urb(&rx_urb->urb);
5094         return ret;
5095 }
5096
5097 static void rtl8xxxu_int_complete(struct urb *urb)
5098 {
5099         struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5100         struct device *dev = &priv->udev->dev;
5101         int ret;
5102
5103         dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5104         if (urb->status == 0) {
5105                 usb_anchor_urb(urb, &priv->int_anchor);
5106                 ret = usb_submit_urb(urb, GFP_ATOMIC);
5107                 if (ret)
5108                         usb_unanchor_urb(urb);
5109         } else {
5110                 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5111         }
5112 }
5113
5114
5115 static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5116 {
5117         struct rtl8xxxu_priv *priv = hw->priv;
5118         struct urb *urb;
5119         u32 val32;
5120         int ret;
5121
5122         urb = usb_alloc_urb(0, GFP_KERNEL);
5123         if (!urb)
5124                 return -ENOMEM;
5125
5126         usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5127                          priv->int_buf, USB_INTR_CONTENT_LENGTH,
5128                          rtl8xxxu_int_complete, priv, 1);
5129         usb_anchor_urb(urb, &priv->int_anchor);
5130         ret = usb_submit_urb(urb, GFP_KERNEL);
5131         if (ret) {
5132                 usb_unanchor_urb(urb);
5133                 goto error;
5134         }
5135
5136         val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5137         val32 |= USB_HIMR_CPWM;
5138         rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5139
5140 error:
5141         usb_free_urb(urb);
5142         return ret;
5143 }
5144
5145 static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5146                                   struct ieee80211_vif *vif)
5147 {
5148         struct rtl8xxxu_priv *priv = hw->priv;
5149         int ret;
5150         u8 val8;
5151
5152         switch (vif->type) {
5153         case NL80211_IFTYPE_STATION:
5154                 rtl8723a_stop_tx_beacon(priv);
5155
5156                 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5157                 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5158                         BEACON_DISABLE_TSF_UPDATE;
5159                 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5160                 ret = 0;
5161                 break;
5162         default:
5163                 ret = -EOPNOTSUPP;
5164         }
5165
5166         rtl8xxxu_set_linktype(priv, vif->type);
5167
5168         return ret;
5169 }
5170
5171 static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5172                                       struct ieee80211_vif *vif)
5173 {
5174         struct rtl8xxxu_priv *priv = hw->priv;
5175
5176         dev_dbg(&priv->udev->dev, "%s\n", __func__);
5177 }
5178
5179 static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5180 {
5181         struct rtl8xxxu_priv *priv = hw->priv;
5182         struct device *dev = &priv->udev->dev;
5183         u16 val16;
5184         int ret = 0, channel;
5185         bool ht40;
5186
5187         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5188                 dev_info(dev,
5189                          "%s: channel: %i (changed %08x chandef.width %02x)\n",
5190                          __func__, hw->conf.chandef.chan->hw_value,
5191                          changed, hw->conf.chandef.width);
5192
5193         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5194                 val16 = ((hw->conf.long_frame_max_tx_count <<
5195                           RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5196                         ((hw->conf.short_frame_max_tx_count <<
5197                           RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5198                 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5199         }
5200
5201         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5202                 switch (hw->conf.chandef.width) {
5203                 case NL80211_CHAN_WIDTH_20_NOHT:
5204                 case NL80211_CHAN_WIDTH_20:
5205                         ht40 = false;
5206                         break;
5207                 case NL80211_CHAN_WIDTH_40:
5208                         ht40 = true;
5209                         break;
5210                 default:
5211                         ret = -ENOTSUPP;
5212                         goto exit;
5213                 }
5214
5215                 channel = hw->conf.chandef.chan->hw_value;
5216
5217                 rtl8723a_set_tx_power(priv, channel, ht40);
5218
5219                 rtl8723au_config_channel(hw);
5220         }
5221
5222 exit:
5223         return ret;
5224 }
5225
5226 static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5227                             struct ieee80211_vif *vif, u16 queue,
5228                             const struct ieee80211_tx_queue_params *param)
5229 {
5230         struct rtl8xxxu_priv *priv = hw->priv;
5231         struct device *dev = &priv->udev->dev;
5232         u32 val32;
5233         u8 aifs, acm_ctrl, acm_bit;
5234
5235         aifs = param->aifs;
5236
5237         val32 = aifs |
5238                 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5239                 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5240                 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5241
5242         acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5243         dev_dbg(dev,
5244                 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5245                 __func__, queue, val32, param->acm, acm_ctrl);
5246
5247         switch (queue) {
5248         case IEEE80211_AC_VO:
5249                 acm_bit = ACM_HW_CTRL_VO;
5250                 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5251                 break;
5252         case IEEE80211_AC_VI:
5253                 acm_bit = ACM_HW_CTRL_VI;
5254                 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5255                 break;
5256         case IEEE80211_AC_BE:
5257                 acm_bit = ACM_HW_CTRL_BE;
5258                 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5259                 break;
5260         case IEEE80211_AC_BK:
5261                 acm_bit = ACM_HW_CTRL_BK;
5262                 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5263                 break;
5264         default:
5265                 acm_bit = 0;
5266                 break;
5267         }
5268
5269         if (param->acm)
5270                 acm_ctrl |= acm_bit;
5271         else
5272                 acm_ctrl &= ~acm_bit;
5273         rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5274
5275         return 0;
5276 }
5277
5278 static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5279                                       unsigned int changed_flags,
5280                                       unsigned int *total_flags, u64 multicast)
5281 {
5282         struct rtl8xxxu_priv *priv = hw->priv;
5283
5284         dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5285                 __func__, changed_flags, *total_flags);
5286
5287         *total_flags &= (FIF_ALLMULTI | FIF_CONTROL | FIF_BCN_PRBRESP_PROMISC);
5288 }
5289
5290 static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5291 {
5292         if (rts > 2347)
5293                 return -EINVAL;
5294
5295         return 0;
5296 }
5297
5298 static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5299                             struct ieee80211_vif *vif,
5300                             struct ieee80211_sta *sta,
5301                             struct ieee80211_key_conf *key)
5302 {
5303         struct rtl8xxxu_priv *priv = hw->priv;
5304         struct device *dev = &priv->udev->dev;
5305         u8 mac_addr[ETH_ALEN];
5306         u8 val8;
5307         u16 val16;
5308         u32 val32;
5309         int retval = -EOPNOTSUPP;
5310
5311         dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5312                 __func__, cmd, key->cipher, key->keyidx);
5313
5314         if (vif->type != NL80211_IFTYPE_STATION)
5315                 return -EOPNOTSUPP;
5316
5317         if (key->keyidx > 3)
5318                 return -EOPNOTSUPP;
5319
5320         switch (key->cipher) {
5321         case WLAN_CIPHER_SUITE_WEP40:
5322         case WLAN_CIPHER_SUITE_WEP104:
5323
5324                 break;
5325         case WLAN_CIPHER_SUITE_CCMP:
5326                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5327                 break;
5328         case WLAN_CIPHER_SUITE_TKIP:
5329                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5330                 break;
5331         default:
5332                 return -EOPNOTSUPP;
5333         }
5334
5335         if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5336                 dev_dbg(dev, "%s: pairwise key\n", __func__);
5337                 ether_addr_copy(mac_addr, sta->addr);
5338         } else {
5339                 dev_dbg(dev, "%s: group key\n", __func__);
5340                 eth_broadcast_addr(mac_addr);
5341         }
5342
5343         val16 = rtl8xxxu_read16(priv, REG_CR);
5344         val16 |= CR_SECURITY_ENABLE;
5345         rtl8xxxu_write16(priv, REG_CR, val16);
5346
5347         val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5348                 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5349         val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5350         rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5351
5352         switch (cmd) {
5353         case SET_KEY:
5354                 key->hw_key_idx = key->keyidx;
5355                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5356                 rtl8xxxu_cam_write(priv, key, mac_addr);
5357                 retval = 0;
5358                 break;
5359         case DISABLE_KEY:
5360                 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5361                 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5362                         key->keyidx << CAM_CMD_KEY_SHIFT;
5363                 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5364                 retval = 0;
5365                 break;
5366         default:
5367                 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5368         }
5369
5370         return retval;
5371 }
5372
5373 static int
5374 rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5375                       struct ieee80211_ampdu_params *params)
5376 {
5377         struct rtl8xxxu_priv *priv = hw->priv;
5378         struct device *dev = &priv->udev->dev;
5379         u8 ampdu_factor, ampdu_density;
5380         struct ieee80211_sta *sta = params->sta;
5381         enum ieee80211_ampdu_mlme_action action = params->action;
5382
5383         switch (action) {
5384         case IEEE80211_AMPDU_TX_START:
5385                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5386                 ampdu_factor = sta->ht_cap.ampdu_factor;
5387                 ampdu_density = sta->ht_cap.ampdu_density;
5388                 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5389                 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5390                 dev_dbg(dev,
5391                         "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5392                         ampdu_factor, ampdu_density);
5393                 break;
5394         case IEEE80211_AMPDU_TX_STOP_FLUSH:
5395                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5396                 rtl8xxxu_set_ampdu_factor(priv, 0);
5397                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5398                 break;
5399         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5400                 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5401                          __func__);
5402                 rtl8xxxu_set_ampdu_factor(priv, 0);
5403                 rtl8xxxu_set_ampdu_min_space(priv, 0);
5404                 break;
5405         case IEEE80211_AMPDU_RX_START:
5406                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5407                 break;
5408         case IEEE80211_AMPDU_RX_STOP:
5409                 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5410                 break;
5411         default:
5412                 break;
5413         }
5414         return 0;
5415 }
5416
5417 static int rtl8xxxu_start(struct ieee80211_hw *hw)
5418 {
5419         struct rtl8xxxu_priv *priv = hw->priv;
5420         struct rtl8xxxu_rx_urb *rx_urb;
5421         struct rtl8xxxu_tx_urb *tx_urb;
5422         struct sk_buff *skb;
5423         unsigned long flags;
5424         int ret, i;
5425
5426         ret = 0;
5427
5428         init_usb_anchor(&priv->rx_anchor);
5429         init_usb_anchor(&priv->tx_anchor);
5430         init_usb_anchor(&priv->int_anchor);
5431
5432         rtl8723a_enable_rf(priv);
5433         ret = rtl8xxxu_submit_int_urb(hw);
5434         if (ret)
5435                 goto exit;
5436
5437         for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5438                 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5439                 if (!tx_urb) {
5440                         if (!i)
5441                                 ret = -ENOMEM;
5442
5443                         goto error_out;
5444                 }
5445                 usb_init_urb(&tx_urb->urb);
5446                 INIT_LIST_HEAD(&tx_urb->list);
5447                 tx_urb->hw = hw;
5448                 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5449                 priv->tx_urb_free_count++;
5450         }
5451
5452         priv->tx_stopped = false;
5453
5454         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5455         priv->shutdown = false;
5456         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5457
5458         for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5459                 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5460                 if (!rx_urb) {
5461                         if (!i)
5462                                 ret = -ENOMEM;
5463
5464                         goto error_out;
5465                 }
5466                 usb_init_urb(&rx_urb->urb);
5467                 INIT_LIST_HEAD(&rx_urb->list);
5468                 rx_urb->hw = hw;
5469
5470                 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5471                 if (ret) {
5472                         if (ret != -ENOMEM) {
5473                                 skb = (struct sk_buff *)rx_urb->urb.context;
5474                                 dev_kfree_skb(skb);
5475                         }
5476                         rtl8xxxu_queue_rx_urb(priv, rx_urb);
5477                 }
5478         }
5479 exit:
5480         /*
5481          * Disable all data frames
5482          */
5483         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5484         /*
5485          * Accept all mgmt frames
5486          */
5487         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5488
5489         rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5490
5491         return ret;
5492
5493 error_out:
5494         rtl8xxxu_free_tx_resources(priv);
5495         /*
5496          * Disable all data and mgmt frames
5497          */
5498         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5499         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5500
5501         return ret;
5502 }
5503
5504 static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5505 {
5506         struct rtl8xxxu_priv *priv = hw->priv;
5507         unsigned long flags;
5508
5509         rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5510
5511         rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5512         rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5513
5514         spin_lock_irqsave(&priv->rx_urb_lock, flags);
5515         priv->shutdown = true;
5516         spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5517
5518         usb_kill_anchored_urbs(&priv->rx_anchor);
5519         usb_kill_anchored_urbs(&priv->tx_anchor);
5520         usb_kill_anchored_urbs(&priv->int_anchor);
5521
5522         rtl8723a_disable_rf(priv);
5523
5524         /*
5525          * Disable interrupts
5526          */
5527         rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5528
5529         rtl8xxxu_free_rx_resources(priv);
5530         rtl8xxxu_free_tx_resources(priv);
5531 }
5532
5533 static const struct ieee80211_ops rtl8xxxu_ops = {
5534         .tx = rtl8xxxu_tx,
5535         .add_interface = rtl8xxxu_add_interface,
5536         .remove_interface = rtl8xxxu_remove_interface,
5537         .config = rtl8xxxu_config,
5538         .conf_tx = rtl8xxxu_conf_tx,
5539         .bss_info_changed = rtl8xxxu_bss_info_changed,
5540         .configure_filter = rtl8xxxu_configure_filter,
5541         .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5542         .start = rtl8xxxu_start,
5543         .stop = rtl8xxxu_stop,
5544         .sw_scan_start = rtl8xxxu_sw_scan_start,
5545         .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5546         .set_key = rtl8xxxu_set_key,
5547         .ampdu_action = rtl8xxxu_ampdu_action,
5548 };
5549
5550 static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5551                               struct usb_interface *interface)
5552 {
5553         struct usb_interface_descriptor *interface_desc;
5554         struct usb_host_interface *host_interface;
5555         struct usb_endpoint_descriptor *endpoint;
5556         struct device *dev = &priv->udev->dev;
5557         int i, j = 0, endpoints;
5558         u8 dir, xtype, num;
5559         int ret = 0;
5560
5561         host_interface = interface->cur_altsetting;
5562         interface_desc = &host_interface->desc;
5563         endpoints = interface_desc->bNumEndpoints;
5564
5565         for (i = 0; i < endpoints; i++) {
5566                 endpoint = &host_interface->endpoint[i].desc;
5567
5568                 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5569                 num = usb_endpoint_num(endpoint);
5570                 xtype = usb_endpoint_type(endpoint);
5571                 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5572                         dev_dbg(dev,
5573                                 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5574                                 __func__, dir, num, xtype);
5575                 if (usb_endpoint_dir_in(endpoint) &&
5576                     usb_endpoint_xfer_bulk(endpoint)) {
5577                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5578                                 dev_dbg(dev, "%s: in endpoint num %i\n",
5579                                         __func__, num);
5580
5581                         if (priv->pipe_in) {
5582                                 dev_warn(dev,
5583                                          "%s: Too many IN pipes\n", __func__);
5584                                 ret = -EINVAL;
5585                                 goto exit;
5586                         }
5587
5588                         priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5589                 }
5590
5591                 if (usb_endpoint_dir_in(endpoint) &&
5592                     usb_endpoint_xfer_int(endpoint)) {
5593                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5594                                 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5595                                         __func__, num);
5596
5597                         if (priv->pipe_interrupt) {
5598                                 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5599                                          __func__);
5600                                 ret = -EINVAL;
5601                                 goto exit;
5602                         }
5603
5604                         priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5605                 }
5606
5607                 if (usb_endpoint_dir_out(endpoint) &&
5608                     usb_endpoint_xfer_bulk(endpoint)) {
5609                         if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5610                                 dev_dbg(dev, "%s: out endpoint num %i\n",
5611                                         __func__, num);
5612                         if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5613                                 dev_warn(dev,
5614                                          "%s: Too many OUT pipes\n", __func__);
5615                                 ret = -EINVAL;
5616                                 goto exit;
5617                         }
5618                         priv->out_ep[j++] = num;
5619                 }
5620         }
5621 exit:
5622         priv->nr_out_eps = j;
5623         return ret;
5624 }
5625
5626 static int rtl8xxxu_probe(struct usb_interface *interface,
5627                           const struct usb_device_id *id)
5628 {
5629         struct rtl8xxxu_priv *priv;
5630         struct ieee80211_hw *hw;
5631         struct usb_device *udev;
5632         struct ieee80211_supported_band *sband;
5633         int ret = 0;
5634         int untested = 1;
5635
5636         udev = usb_get_dev(interface_to_usbdev(interface));
5637
5638         switch (id->idVendor) {
5639         case USB_VENDOR_ID_REALTEK:
5640                 switch(id->idProduct) {
5641                 case 0x1724:
5642                 case 0x8176:
5643                 case 0x8178:
5644                 case 0x817f:
5645                         untested = 0;
5646                         break;
5647                 }
5648                 break;
5649         case 0x7392:
5650                 if (id->idProduct == 0x7811)
5651                         untested = 0;
5652                 break;
5653         default:
5654                 break;
5655         }
5656
5657         if (untested) {
5658                 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5659                 dev_info(&udev->dev,
5660                          "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5661                          id->idVendor, id->idProduct);
5662                 dev_info(&udev->dev,
5663                          "Please report results to Jes.Sorensen@gmail.com\n");
5664         }
5665
5666         hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5667         if (!hw) {
5668                 ret = -ENOMEM;
5669                 goto exit;
5670         }
5671
5672         priv = hw->priv;
5673         priv->hw = hw;
5674         priv->udev = udev;
5675         priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5676         mutex_init(&priv->usb_buf_mutex);
5677         mutex_init(&priv->h2c_mutex);
5678         INIT_LIST_HEAD(&priv->tx_urb_free_list);
5679         spin_lock_init(&priv->tx_urb_lock);
5680         INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5681         spin_lock_init(&priv->rx_urb_lock);
5682         INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5683
5684         usb_set_intfdata(interface, hw);
5685
5686         ret = rtl8xxxu_parse_usb(priv, interface);
5687         if (ret)
5688                 goto exit;
5689
5690         ret = rtl8xxxu_identify_chip(priv);
5691         if (ret) {
5692                 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5693                 goto exit;
5694         }
5695
5696         ret = rtl8xxxu_read_efuse(priv);
5697         if (ret) {
5698                 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5699                 goto exit;
5700         }
5701
5702         ret = priv->fops->parse_efuse(priv);
5703         if (ret) {
5704                 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5705                 goto exit;
5706         }
5707
5708         rtl8xxxu_print_chipinfo(priv);
5709
5710         ret = priv->fops->load_firmware(priv);
5711         if (ret) {
5712                 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5713                 goto exit;
5714         }
5715
5716         ret = rtl8xxxu_init_device(hw);
5717
5718         hw->wiphy->max_scan_ssids = 1;
5719         hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5720         hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5721         hw->queues = 4;
5722
5723         sband = &rtl8xxxu_supported_band;
5724         sband->ht_cap.ht_supported = true;
5725         sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5726         sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5727         sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5728         memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5729         sband->ht_cap.mcs.rx_mask[0] = 0xff;
5730         sband->ht_cap.mcs.rx_mask[4] = 0x01;
5731         if (priv->rf_paths > 1) {
5732                 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5733                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5734         }
5735         sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5736         /*
5737          * Some APs will negotiate HT20_40 in a noisy environment leading
5738          * to miserable performance. Rather than defaulting to this, only
5739          * enable it if explicitly requested at module load time.
5740          */
5741         if (rtl8xxxu_ht40_2g) {
5742                 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5743                 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5744         }
5745         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5746
5747         hw->wiphy->rts_threshold = 2347;
5748
5749         SET_IEEE80211_DEV(priv->hw, &interface->dev);
5750         SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5751
5752         hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5753         ieee80211_hw_set(hw, SIGNAL_DBM);
5754         /*
5755          * The firmware handles rate control
5756          */
5757         ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5758         ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5759
5760         ret = ieee80211_register_hw(priv->hw);
5761         if (ret) {
5762                 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5763                         __func__, ret);
5764                 goto exit;
5765         }
5766
5767 exit:
5768         if (ret < 0)
5769                 usb_put_dev(udev);
5770         return ret;
5771 }
5772
5773 static void rtl8xxxu_disconnect(struct usb_interface *interface)
5774 {
5775         struct rtl8xxxu_priv *priv;
5776         struct ieee80211_hw *hw;
5777
5778         hw = usb_get_intfdata(interface);
5779         priv = hw->priv;
5780
5781         rtl8xxxu_disable_device(hw);
5782         usb_set_intfdata(interface, NULL);
5783
5784         dev_info(&priv->udev->dev, "disconnecting\n");
5785
5786         ieee80211_unregister_hw(hw);
5787
5788         kfree(priv->fw_data);
5789         mutex_destroy(&priv->usb_buf_mutex);
5790         mutex_destroy(&priv->h2c_mutex);
5791
5792         usb_put_dev(priv->udev);
5793         ieee80211_free_hw(hw);
5794 }
5795
5796 static struct rtl8xxxu_fileops rtl8723au_fops = {
5797         .parse_efuse = rtl8723au_parse_efuse,
5798         .load_firmware = rtl8723au_load_firmware,
5799         .power_on = rtl8723au_power_on,
5800         .writeN_block_size = 1024,
5801 };
5802
5803 #ifdef CONFIG_RTL8XXXU_UNTESTED
5804
5805 static struct rtl8xxxu_fileops rtl8192cu_fops = {
5806         .parse_efuse = rtl8192cu_parse_efuse,
5807         .load_firmware = rtl8192cu_load_firmware,
5808         .power_on = rtl8192cu_power_on,
5809         .writeN_block_size = 128,
5810 };
5811
5812 #endif
5813
5814 static struct usb_device_id dev_table[] = {
5815 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5816         .driver_info = (unsigned long)&rtl8723au_fops},
5817 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5818         .driver_info = (unsigned long)&rtl8723au_fops},
5819 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5820         .driver_info = (unsigned long)&rtl8723au_fops},
5821 #ifdef CONFIG_RTL8XXXU_UNTESTED
5822 /* Still supported by rtlwifi */
5823 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5824         .driver_info = (unsigned long)&rtl8192cu_fops},
5825 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5826         .driver_info = (unsigned long)&rtl8192cu_fops},
5827 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5828         .driver_info = (unsigned long)&rtl8192cu_fops},
5829 /* Tested by Larry Finger */
5830 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
5831         .driver_info = (unsigned long)&rtl8192cu_fops},
5832 /* Currently untested 8188 series devices */
5833 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
5834         .driver_info = (unsigned long)&rtl8192cu_fops},
5835 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
5836         .driver_info = (unsigned long)&rtl8192cu_fops},
5837 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
5838         .driver_info = (unsigned long)&rtl8192cu_fops},
5839 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
5840         .driver_info = (unsigned long)&rtl8192cu_fops},
5841 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
5842         .driver_info = (unsigned long)&rtl8192cu_fops},
5843 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
5844         .driver_info = (unsigned long)&rtl8192cu_fops},
5845 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
5846         .driver_info = (unsigned long)&rtl8192cu_fops},
5847 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
5848         .driver_info = (unsigned long)&rtl8192cu_fops},
5849 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5850         .driver_info = (unsigned long)&rtl8192cu_fops},
5851 {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
5852         .driver_info = (unsigned long)&rtl8192cu_fops},
5853 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
5854         .driver_info = (unsigned long)&rtl8192cu_fops},
5855 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
5856         .driver_info = (unsigned long)&rtl8192cu_fops},
5857 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
5858         .driver_info = (unsigned long)&rtl8192cu_fops},
5859 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
5860         .driver_info = (unsigned long)&rtl8192cu_fops},
5861 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
5862         .driver_info = (unsigned long)&rtl8192cu_fops},
5863 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
5864         .driver_info = (unsigned long)&rtl8192cu_fops},
5865 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
5866         .driver_info = (unsigned long)&rtl8192cu_fops},
5867 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
5868         .driver_info = (unsigned long)&rtl8192cu_fops},
5869 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
5870         .driver_info = (unsigned long)&rtl8192cu_fops},
5871 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
5872         .driver_info = (unsigned long)&rtl8192cu_fops},
5873 {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
5874         .driver_info = (unsigned long)&rtl8192cu_fops},
5875 {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
5876         .driver_info = (unsigned long)&rtl8192cu_fops},
5877 {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
5878         .driver_info = (unsigned long)&rtl8192cu_fops},
5879 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
5880         .driver_info = (unsigned long)&rtl8192cu_fops},
5881 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
5882         .driver_info = (unsigned long)&rtl8192cu_fops},
5883 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
5884         .driver_info = (unsigned long)&rtl8192cu_fops},
5885 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
5886         .driver_info = (unsigned long)&rtl8192cu_fops},
5887 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
5888         .driver_info = (unsigned long)&rtl8192cu_fops},
5889 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
5890         .driver_info = (unsigned long)&rtl8192cu_fops},
5891 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
5892         .driver_info = (unsigned long)&rtl8192cu_fops},
5893 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
5894         .driver_info = (unsigned long)&rtl8192cu_fops},
5895 {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
5896         .driver_info = (unsigned long)&rtl8192cu_fops},
5897 {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
5898         .driver_info = (unsigned long)&rtl8192cu_fops},
5899 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
5900         .driver_info = (unsigned long)&rtl8192cu_fops}, /* Netcore 8188RU */
5901 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
5902         .driver_info = (unsigned long)&rtl8192cu_fops},
5903 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
5904         .driver_info = (unsigned long)&rtl8192cu_fops},
5905 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
5906         .driver_info = (unsigned long)&rtl8192cu_fops},
5907 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
5908         .driver_info = (unsigned long)&rtl8192cu_fops},
5909 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
5910         .driver_info = (unsigned long)&rtl8192cu_fops},
5911 {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
5912         .driver_info = (unsigned long)&rtl8192cu_fops},
5913 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
5914         .driver_info = (unsigned long)&rtl8192cu_fops},
5915 /* Currently untested 8192 series devices */
5916 {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
5917         .driver_info = (unsigned long)&rtl8192cu_fops},
5918 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
5919         .driver_info = (unsigned long)&rtl8192cu_fops},
5920 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
5921         .driver_info = (unsigned long)&rtl8192cu_fops},
5922 {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
5923         .driver_info = (unsigned long)&rtl8192cu_fops},
5924 {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
5925         .driver_info = (unsigned long)&rtl8192cu_fops},
5926 {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
5927         .driver_info = (unsigned long)&rtl8192cu_fops},
5928 {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
5929         .driver_info = (unsigned long)&rtl8192cu_fops},
5930 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
5931         .driver_info = (unsigned long)&rtl8192cu_fops},
5932 {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
5933         .driver_info = (unsigned long)&rtl8192cu_fops},
5934 {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
5935         .driver_info = (unsigned long)&rtl8192cu_fops},
5936 {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
5937         .driver_info = (unsigned long)&rtl8192cu_fops},
5938 {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
5939         .driver_info = (unsigned long)&rtl8192cu_fops},
5940 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
5941         .driver_info = (unsigned long)&rtl8192cu_fops},
5942 {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
5943         .driver_info = (unsigned long)&rtl8192cu_fops},
5944 {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
5945         .driver_info = (unsigned long)&rtl8192cu_fops},
5946 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
5947         .driver_info = (unsigned long)&rtl8192cu_fops},
5948 {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
5949         .driver_info = (unsigned long)&rtl8192cu_fops},
5950 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
5951         .driver_info = (unsigned long)&rtl8192cu_fops},
5952 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
5953         .driver_info = (unsigned long)&rtl8192cu_fops},
5954 {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
5955         .driver_info = (unsigned long)&rtl8192cu_fops},
5956 {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
5957         .driver_info = (unsigned long)&rtl8192cu_fops},
5958 {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
5959         .driver_info = (unsigned long)&rtl8192cu_fops},
5960 {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
5961         .driver_info = (unsigned long)&rtl8192cu_fops},
5962 {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
5963         .driver_info = (unsigned long)&rtl8192cu_fops},
5964 {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
5965         .driver_info = (unsigned long)&rtl8192cu_fops},
5966 #endif
5967 { }
5968 };
5969
5970 static struct usb_driver rtl8xxxu_driver = {
5971         .name = DRIVER_NAME,
5972         .probe = rtl8xxxu_probe,
5973         .disconnect = rtl8xxxu_disconnect,
5974         .id_table = dev_table,
5975         .disable_hub_initiated_lpm = 1,
5976 };
5977
5978 static int __init rtl8xxxu_module_init(void)
5979 {
5980         int res;
5981
5982         res = usb_register(&rtl8xxxu_driver);
5983         if (res < 0)
5984                 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
5985
5986         return res;
5987 }
5988
5989 static void __exit rtl8xxxu_module_exit(void)
5990 {
5991         usb_deregister(&rtl8xxxu_driver);
5992 }
5993
5994
5995 MODULE_DEVICE_TABLE(usb, dev_table);
5996
5997 module_init(rtl8xxxu_module_init);
5998 module_exit(rtl8xxxu_module_exit);