2 /* Linux device driver for RTL8180 / RTL8185 / RTL8187SE
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007,2014 Andrea Merello <andrea.merello@gmail.com>
7 * Based on the r8180 driver, which is:
8 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 * Thanks to Realtek for their support!
12 ************************************************************************
14 * The driver was extended to the RTL8187SE in 2014 by
15 * Andrea Merello <andrea.merello@gmail.com>
18 * - portions of rtl8187se Linux staging driver, Copyright Realtek corp.
19 * (available in drivers/staging/rtl8187se directory of Linux 3.14)
20 * - other GPL, unpublished (until now), Linux driver code,
21 * Copyright Larry Finger <Larry.Finger@lwfinger.net>
23 * A huge thanks goes to Sara V. Nari who forgives me when I'm
24 * sitting in front of my laptop at evening, week-end, night...
26 * A special thanks goes to Antonio Cuni, who helped me with
27 * some python userspace stuff I used to debug RTL8187SE code, and who
28 * bought a laptop with an unsupported Wi-Fi card some years ago...
30 * Thanks to Larry Finger for writing some code for rtl8187se and for
33 * Thanks to Dan Carpenter for reviewing my initial patch and for his
36 * Thanks to Bernhard Schiffner for his help in testing and for his
39 ************************************************************************
41 * This program is free software; you can redistribute it and/or modify
42 * it under the terms of the GNU General Public License version 2 as
43 * published by the Free Software Foundation.
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/slab.h>
49 #include <linux/delay.h>
50 #include <linux/etherdevice.h>
51 #include <linux/eeprom_93cx6.h>
52 #include <linux/module.h>
53 #include <net/mac80211.h>
60 #include "rtl8225se.h"
62 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
63 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
64 MODULE_DESCRIPTION("RTL8180 / RTL8185 / RTL8187SE PCI wireless driver");
65 MODULE_LICENSE("GPL");
67 static const struct pci_device_id rtl8180_table[] = {
70 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8199) },
73 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
74 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
75 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
78 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
79 { PCI_DEVICE(0x1799, 0x6001) },
80 { PCI_DEVICE(0x1799, 0x6020) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
82 { PCI_DEVICE(0x1186, 0x3301) },
83 { PCI_DEVICE(0x1432, 0x7106) },
87 MODULE_DEVICE_TABLE(pci, rtl8180_table);
89 static const struct ieee80211_rate rtl818x_rates[] = {
90 { .bitrate = 10, .hw_value = 0, },
91 { .bitrate = 20, .hw_value = 1, },
92 { .bitrate = 55, .hw_value = 2, },
93 { .bitrate = 110, .hw_value = 3, },
94 { .bitrate = 60, .hw_value = 4, },
95 { .bitrate = 90, .hw_value = 5, },
96 { .bitrate = 120, .hw_value = 6, },
97 { .bitrate = 180, .hw_value = 7, },
98 { .bitrate = 240, .hw_value = 8, },
99 { .bitrate = 360, .hw_value = 9, },
100 { .bitrate = 480, .hw_value = 10, },
101 { .bitrate = 540, .hw_value = 11, },
104 static const struct ieee80211_channel rtl818x_channels[] = {
105 { .center_freq = 2412 },
106 { .center_freq = 2417 },
107 { .center_freq = 2422 },
108 { .center_freq = 2427 },
109 { .center_freq = 2432 },
110 { .center_freq = 2437 },
111 { .center_freq = 2442 },
112 { .center_freq = 2447 },
113 { .center_freq = 2452 },
114 { .center_freq = 2457 },
115 { .center_freq = 2462 },
116 { .center_freq = 2467 },
117 { .center_freq = 2472 },
118 { .center_freq = 2484 },
121 /* Queues for rtl8187se card
132 * The complete map for DMA kick reg using use all queue is:
133 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
134 * {1, 6, 5, 4, 3, 2, 7};
136 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
139 * BC | 7 | 4 <- currently not used yet
140 * MG | 1 | x <- Not used
141 * HI | 6 | x <- Not used
147 * Beacon queue could be used, but this is not finished yet.
149 * I thougth about using the other two queues but I decided not to do this:
151 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
154 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
155 * queue but since mac80211 will do not know about it, I will probably gain
156 * some HW priority whenever the VO queue is not empty, but this gain is
157 * limited by the fact that I had to stop the mac80211 queue whenever one of
158 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
161 * - I don't know how to set in the HW the contention window params for MGMT
162 * and HI-prio queues.
165 static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
167 /* Queues for rtl8180/rtl8185 cards
175 * The complete map for DMA kick reg using all queue is:
176 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
178 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
179 * otherwise QoS can't be done, we use just one.
180 * Beacon queue could be used, but this is not finished yet.
184 * BC | 7 | 1 <- currently not used yet.
185 * HI | 6 | x <- not used
186 * NO | 5 | x <- not used
190 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
192 /* LNA gain table for rtl8187se */
193 static const u8 rtl8187se_lna_gain[4] = {02, 17, 29, 39};
195 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
197 struct rtl8180_priv *priv = dev->priv;
201 buf = (data << 8) | addr;
203 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
205 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
206 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
211 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
213 struct rtl8180_priv *priv = dev->priv;
214 struct rtl818x_rx_cmd_desc *cmd_desc;
215 unsigned int count = 32;
221 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
222 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
223 u32 flags, flags2, flags3 = 0;
226 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
227 struct rtl8187se_rx_desc *desc = entry;
229 flags = le32_to_cpu(desc->flags);
230 /* if ownership flag is set, then we can trust the
231 * HW has written other fields. We must not trust
232 * other descriptor data read before we checked (read)
236 flags3 = le32_to_cpu(desc->flags3);
237 flags2 = le32_to_cpu(desc->flags2);
238 tsft = le64_to_cpu(desc->tsft);
240 struct rtl8180_rx_desc *desc = entry;
242 flags = le32_to_cpu(desc->flags);
245 flags2 = le32_to_cpu(desc->flags2);
246 tsft = le64_to_cpu(desc->tsft);
249 if (flags & RTL818X_RX_DESC_FLAG_OWN)
252 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
253 RTL818X_RX_DESC_FLAG_FOF |
254 RTL818X_RX_DESC_FLAG_RX_ERR)))
257 struct ieee80211_rx_status rx_status = {0};
258 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
260 if (unlikely(!new_skb))
263 mapping = pci_map_single(priv->pdev,
264 skb_tail_pointer(new_skb),
265 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
267 if (pci_dma_mapping_error(priv->pdev, mapping)) {
269 dev_err(&priv->pdev->dev, "RX DMA map error\n");
274 pci_unmap_single(priv->pdev,
275 *((dma_addr_t *)skb->cb),
276 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
277 skb_put(skb, flags & 0xFFF);
279 rx_status.antenna = (flags2 >> 15) & 1;
280 rx_status.rate_idx = (flags >> 20) & 0xF;
281 agc = (flags2 >> 17) & 0x7F;
283 switch (priv->chip_family) {
284 case RTL818X_CHIP_FAMILY_RTL8185:
285 if (rx_status.rate_idx > 3)
286 signal = -clamp_t(u8, agc, 25, 90) - 9;
288 signal = -clamp_t(u8, agc, 30, 95);
290 case RTL818X_CHIP_FAMILY_RTL8180:
292 signal = priv->rf->calc_rssi(agc, sq);
294 case RTL818X_CHIP_FAMILY_RTL8187SE:
295 /* OFDM measure reported by HW is signed,
296 * in 0.5dBm unit, with zero centered @ -41dBm
299 if (rx_status.rate_idx > 3) {
300 signal = (s8)((flags3 >> 16) & 0xff);
301 signal = signal / 2 - 41;
305 idx = (agc & 0x60) >> 5;
306 bb = (agc & 0x1F) * 2;
307 /* bias + BB gain + LNA gain */
308 signal = 4 - bb - rtl8187se_lna_gain[idx];
312 rx_status.signal = signal;
313 rx_status.freq = dev->conf.chandef.chan->center_freq;
314 rx_status.band = dev->conf.chandef.chan->band;
315 rx_status.mactime = tsft;
316 rx_status.flag |= RX_FLAG_MACTIME_START;
317 if (flags & RTL818X_RX_DESC_FLAG_SPLCP)
318 rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE;
319 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
320 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
322 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
323 ieee80211_rx_irqsafe(dev, skb);
326 priv->rx_buf[priv->rx_idx] = skb;
327 *((dma_addr_t *) skb->cb) = mapping;
332 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
333 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
335 if (priv->rx_idx == 31)
337 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
338 priv->rx_idx = (priv->rx_idx + 1) % 32;
342 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
344 struct rtl8180_priv *priv = dev->priv;
345 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
347 while (skb_queue_len(&ring->queue)) {
348 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
350 struct ieee80211_tx_info *info;
351 u32 flags = le32_to_cpu(entry->flags);
353 if (flags & RTL818X_TX_DESC_FLAG_OWN)
356 ring->idx = (ring->idx + 1) % ring->entries;
357 skb = __skb_dequeue(&ring->queue);
358 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
359 skb->len, PCI_DMA_TODEVICE);
361 info = IEEE80211_SKB_CB(skb);
362 ieee80211_tx_info_clear_status(info);
364 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
365 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
366 info->flags |= IEEE80211_TX_STAT_ACK;
368 info->status.rates[0].count = (flags & 0xFF) + 1;
370 ieee80211_tx_status_irqsafe(dev, skb);
371 if (ring->entries - skb_queue_len(&ring->queue) == 2)
372 ieee80211_wake_queue(dev, prio);
376 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
378 struct ieee80211_hw *dev = dev_id;
379 struct rtl8180_priv *priv = dev->priv;
384 spin_lock_irqsave(&priv->lock, flags);
385 /* Note: 32-bit interrupt status */
386 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
387 if (unlikely(reg == 0xFFFFFFFF)) {
388 spin_unlock_irqrestore(&priv->lock, flags);
392 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
394 if (reg & IMR_TIMEOUT1)
395 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
397 if (reg & (IMR_TBDOK | IMR_TBDER))
398 rtl8180_handle_tx(dev, 4);
400 if (reg & (IMR_TVODOK | IMR_TVODER))
401 rtl8180_handle_tx(dev, 0);
403 if (reg & (IMR_TVIDOK | IMR_TVIDER))
404 rtl8180_handle_tx(dev, 1);
406 if (reg & (IMR_TBEDOK | IMR_TBEDER))
407 rtl8180_handle_tx(dev, 2);
409 if (reg & (IMR_TBKDOK | IMR_TBKDER))
410 rtl8180_handle_tx(dev, 3);
412 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
413 rtl8180_handle_rx(dev);
414 /* The interface sometimes generates several RX DMA descriptor errors
415 * at startup. Do not report these.
417 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
419 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
421 spin_unlock_irqrestore(&priv->lock, flags);
425 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
427 struct ieee80211_hw *dev = dev_id;
428 struct rtl8180_priv *priv = dev->priv;
431 spin_lock(&priv->lock);
432 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
433 if (unlikely(reg == 0xFFFF)) {
434 spin_unlock(&priv->lock);
438 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
440 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
441 rtl8180_handle_tx(dev, 1);
443 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
444 rtl8180_handle_tx(dev, 0);
446 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
447 rtl8180_handle_rx(dev);
449 spin_unlock(&priv->lock);
454 static void rtl8180_tx(struct ieee80211_hw *dev,
455 struct ieee80211_tx_control *control,
458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
459 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
460 struct rtl8180_priv *priv = dev->priv;
461 struct rtl8180_tx_ring *ring;
462 struct rtl8180_tx_desc *entry;
463 unsigned int prio = 0;
465 unsigned int idx, hw_prio;
471 __le16 rts_duration = 0;
472 /* do arithmetic and then convert to le16 */
473 u16 frame_duration = 0;
475 /* rtl8180/rtl8185 only has one useable tx queue */
476 if (dev->queues > IEEE80211_AC_BK)
477 prio = skb_get_queue_mapping(skb);
478 ring = &priv->tx_ring[prio];
480 mapping = pci_map_single(priv->pdev, skb->data,
481 skb->len, PCI_DMA_TODEVICE);
483 if (pci_dma_mapping_error(priv->pdev, mapping)) {
485 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
489 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
490 RTL818X_TX_DESC_FLAG_LS |
491 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
494 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
495 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
496 RTL818X_TX_DESC_FLAG_NO_ENC;
498 rc_flags = info->control.rates[0].flags;
500 /* HW will perform RTS-CTS when only RTS flags is set.
501 * HW will perform CTS-to-self when both RTS and CTS flags are set.
502 * RTS rate and RTS duration will be used also for CTS-to-self.
504 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
505 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
506 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
507 rts_duration = ieee80211_rts_duration(dev, priv->vif,
509 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
510 tx_flags |= RTL818X_TX_DESC_FLAG_RTS | RTL818X_TX_DESC_FLAG_CTS;
511 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
512 rts_duration = ieee80211_ctstoself_duration(dev, priv->vif,
516 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
517 unsigned int remainder;
519 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
520 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
521 remainder = (16 * (skb->len + 4)) %
522 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
527 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
529 /* SIFS time (required by HW) is already included by
530 * ieee80211_generic_frame_duration
532 duration = ieee80211_generic_frame_duration(dev, priv->vif,
533 NL80211_BAND_2GHZ, skb->len,
534 ieee80211_get_tx_rate(dev, info));
536 frame_duration = priv->ack_time + le16_to_cpu(duration);
539 spin_lock_irqsave(&priv->lock, flags);
541 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
542 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
544 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
545 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
548 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
549 entry = &ring->desc[idx];
551 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
552 entry->frame_duration = cpu_to_le16(frame_duration);
553 entry->frame_len_se = cpu_to_le16(skb->len);
556 entry->flags3 = cpu_to_le16(1<<4);
558 entry->frame_len = cpu_to_le32(skb->len);
560 entry->rts_duration = rts_duration;
561 entry->plcp_len = cpu_to_le16(plcp_len);
562 entry->tx_buf = cpu_to_le32(mapping);
564 entry->retry_limit = info->control.rates[0].count - 1;
566 /* We must be sure that tx_flags is written last because the HW
567 * looks at it to check if the rest of data is valid or not
570 entry->flags = cpu_to_le32(tx_flags);
571 /* We must be sure this has been written before followings HW
572 * register write, because this write will made the HW attempts
573 * to DMA the just-written data
577 __skb_queue_tail(&ring->queue, skb);
578 if (ring->entries - skb_queue_len(&ring->queue) < 2)
579 ieee80211_stop_queue(dev, prio);
581 spin_unlock_irqrestore(&priv->lock, flags);
583 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
584 /* just poll: rings are stopped with TPPollStop reg */
585 hw_prio = rtl8187se_queues_map[prio];
586 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
589 hw_prio = rtl8180_queues_map[prio];
590 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
591 (1 << hw_prio) | /* ring to poll */
592 (1<<1) | (1<<2));/* stopped rings */
596 static void rtl8180_set_anaparam3(struct rtl8180_priv *priv, u16 anaparam3)
600 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
601 RTL818X_EEPROM_CMD_CONFIG);
603 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
604 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
605 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
607 rtl818x_iowrite16(priv, &priv->map->ANAPARAM3, anaparam3);
609 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
610 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
612 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
613 RTL818X_EEPROM_CMD_NORMAL);
616 void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2)
620 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
621 RTL818X_EEPROM_CMD_CONFIG);
623 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
624 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
625 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
627 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
629 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
630 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
632 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
633 RTL818X_EEPROM_CMD_NORMAL);
636 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
640 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
641 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
642 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
643 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
644 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
645 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
646 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
647 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
650 static void rtl8187se_mac_config(struct ieee80211_hw *dev)
652 struct rtl8180_priv *priv = dev->priv;
655 rtl818x_iowrite32(priv, REG_ADDR4(0x1F0), 0);
656 rtl818x_ioread32(priv, REG_ADDR4(0x1F0));
657 rtl818x_iowrite32(priv, REG_ADDR4(0x1F4), 0);
658 rtl818x_ioread32(priv, REG_ADDR4(0x1F4));
659 rtl818x_iowrite8(priv, REG_ADDR1(0x1F8), 0);
660 rtl818x_ioread8(priv, REG_ADDR1(0x1F8));
661 /* Enable DA10 TX power saving */
662 reg = rtl818x_ioread8(priv, &priv->map->PHY_PR);
663 rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04);
665 rtl818x_iowrite16(priv, PI_DATA_REG, 0x1000);
666 rtl818x_iowrite16(priv, SI_DATA_REG, 0x1000);
667 /* AFE - default to power ON */
668 rtl818x_iowrite16(priv, REG_ADDR2(0x370), 0x0560);
669 rtl818x_iowrite16(priv, REG_ADDR2(0x372), 0x0560);
670 rtl818x_iowrite16(priv, REG_ADDR2(0x374), 0x0DA4);
671 rtl818x_iowrite16(priv, REG_ADDR2(0x376), 0x0DA4);
672 rtl818x_iowrite16(priv, REG_ADDR2(0x378), 0x0560);
673 rtl818x_iowrite16(priv, REG_ADDR2(0x37A), 0x0560);
674 rtl818x_iowrite16(priv, REG_ADDR2(0x37C), 0x00EC);
675 rtl818x_iowrite16(priv, REG_ADDR2(0x37E), 0x00EC);
676 rtl818x_iowrite8(priv, REG_ADDR1(0x24E), 0x01);
677 /* unknown, needed for suspend to RAM resume */
678 rtl818x_iowrite8(priv, REG_ADDR1(0x0A), 0x72);
681 static void rtl8187se_set_antenna_config(struct ieee80211_hw *dev, u8 def_ant,
684 struct rtl8180_priv *priv = dev->priv;
686 rtl8225_write_phy_cck(dev, 0x0C, 0x09);
689 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
690 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
691 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
692 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
693 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
694 } else { /* main antenna */
695 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
696 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
697 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
698 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
699 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
701 } else { /* disable antenna diversity */
703 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
704 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
705 rtl8225_write_phy_cck(dev, 0x01, 0x47);
706 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
707 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
708 } else { /* main antenna */
709 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
710 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
711 rtl8225_write_phy_cck(dev, 0x01, 0x47);
712 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
713 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
716 /* priv->curr_ant = def_ant; */
719 static void rtl8180_int_enable(struct ieee80211_hw *dev)
721 struct rtl8180_priv *priv = dev->priv;
723 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
724 rtl818x_iowrite32(priv, &priv->map->IMR,
725 IMR_TBDER | IMR_TBDOK |
726 IMR_TVODER | IMR_TVODOK |
727 IMR_TVIDER | IMR_TVIDOK |
728 IMR_TBEDER | IMR_TBEDOK |
729 IMR_TBKDER | IMR_TBKDOK |
731 IMR_ROK | IMR_RQOSOK);
733 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
737 static void rtl8180_int_disable(struct ieee80211_hw *dev)
739 struct rtl8180_priv *priv = dev->priv;
741 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
742 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
744 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
748 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
751 struct rtl8180_priv *priv = dev->priv;
755 u8 resp_max, resp_min;
757 resp_mask = basic_mask;
758 /* IEEE80211 says the response rate should be equal to the highest basic
759 * rate that is not faster than received frame. But it says also that if
760 * the basic rate set does not contains any rate for the current
761 * modulation class then mandatory rate set must be used for that
762 * modulation class. Eventually add OFDM mandatory rates..
764 if ((resp_mask & 0xf) == resp_mask)
765 resp_mask |= 0x150; /* 6, 12, 24Mbps */
767 switch (priv->chip_family) {
769 case RTL818X_CHIP_FAMILY_RTL8180:
770 /* in 8180 this is NOT a BITMAP */
771 basic_max = fls(basic_mask) - 1;
772 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
775 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
778 case RTL818X_CHIP_FAMILY_RTL8185:
779 resp_max = fls(resp_mask) - 1;
780 resp_min = ffs(resp_mask) - 1;
781 /* in 8185 this is a BITMAP */
782 rtl818x_iowrite16(priv, &priv->map->BRSR, basic_mask);
783 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (resp_max << 4) |
787 case RTL818X_CHIP_FAMILY_RTL8187SE:
788 /* in 8187se this is a BITMAP. BRSR reg actually sets
791 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, resp_mask);
796 static void rtl8180_config_cardbus(struct ieee80211_hw *dev)
798 struct rtl8180_priv *priv = dev->priv;
802 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3);
804 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8);
806 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
807 rtl818x_iowrite16(priv, FEMR_SE, 0xffff);
809 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR);
810 reg16 |= (1 << 15) | (1 << 14) | (1 << 4);
811 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16);
816 static int rtl8180_init_hw(struct ieee80211_hw *dev)
818 struct rtl8180_priv *priv = dev->priv;
822 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
823 rtl818x_ioread8(priv, &priv->map->CMD);
827 rtl8180_int_disable(dev);
828 rtl818x_ioread8(priv, &priv->map->CMD);
830 reg = rtl818x_ioread8(priv, &priv->map->CMD);
832 reg |= RTL818X_CMD_RESET;
833 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
834 rtl818x_ioread8(priv, &priv->map->CMD);
837 /* check success of reset */
838 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
839 wiphy_err(dev->wiphy, "reset timeout!\n");
843 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
844 rtl818x_ioread8(priv, &priv->map->CMD);
847 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
848 rtl8180_config_cardbus(dev);
851 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
852 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
854 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
856 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
857 rtl8180_set_anaparam(priv, priv->anaparam);
859 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
860 /* mac80211 queue have higher prio for lower index. The last queue
861 * (that mac80211 is not aware of) is reserved for beacons (and have
862 * the highest priority on the NIC)
864 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
865 rtl818x_iowrite32(priv, &priv->map->TBDA,
866 priv->tx_ring[1].dma);
867 rtl818x_iowrite32(priv, &priv->map->TLPDA,
868 priv->tx_ring[0].dma);
870 rtl818x_iowrite32(priv, &priv->map->TBDA,
871 priv->tx_ring[4].dma);
872 rtl818x_iowrite32(priv, &priv->map->TVODA,
873 priv->tx_ring[0].dma);
874 rtl818x_iowrite32(priv, &priv->map->TVIDA,
875 priv->tx_ring[1].dma);
876 rtl818x_iowrite32(priv, &priv->map->TBEDA,
877 priv->tx_ring[2].dma);
878 rtl818x_iowrite32(priv, &priv->map->TBKDA,
879 priv->tx_ring[3].dma);
882 /* TODO: necessary? specs indicate not */
883 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
884 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
885 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
886 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
887 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
888 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
890 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
892 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
894 /* TODO: turn off hw wep on rtl8180 */
896 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
898 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
899 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
900 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
902 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
904 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
905 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
908 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
909 /* TODO: set ClkRun enable? necessary? */
910 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
911 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
912 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
913 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
914 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
915 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
916 /* fix eccessive IFS after CTS-to-self */
920 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT);
921 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
922 rtl818x_iowrite8(priv, REG_ADDR1(0xff), 0x35);
923 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
925 rtl818x_iowrite8(priv, REG_ADDR1(0x1ff), 0x35);
928 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
930 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
931 rtl818x_iowrite16(priv, ARFR, 0xFFF);
932 rtl818x_ioread16(priv, ARFR);
934 /* stop unused queus (no dma alloc) */
935 rtl818x_iowrite8(priv, &priv->map->TPPOLL_STOP,
936 RTL818x_TPPOLL_STOP_MG | RTL818x_TPPOLL_STOP_HI);
938 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0x00);
939 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
941 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
943 /* some black magic here.. */
944 rtl8187se_mac_config(dev);
946 rtl818x_iowrite16(priv, RFSW_CTRL, 0x569A);
947 rtl818x_ioread16(priv, RFSW_CTRL);
949 rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_ON);
950 rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_ON);
951 rtl8180_set_anaparam3(priv, RTL8225SE_ANAPARAM3);
954 rtl818x_iowrite8(priv, &priv->map->CONFIG5,
955 rtl818x_ioread8(priv, &priv->map->CONFIG5) & 0x7F);
957 /*probably this switch led on */
958 rtl818x_iowrite8(priv, &priv->map->PGSELECT,
959 rtl818x_ioread8(priv, &priv->map->PGSELECT) | 0x08);
961 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
962 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1BFF);
963 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
965 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x4003);
967 /* the reference code mac hardcode table write
968 * this reg by doing byte-wide accesses.
969 * It does it just for lowest and highest byte..
971 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA);
974 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32);
976 /* stop unused queus (no dma alloc) */
977 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
982 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
983 * otherwise. bitmask 0x3 and 0x01f3 respectively.
984 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
985 * this after rf init.
986 * TODO: try to find out whether RF code really needs to do this..
988 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
989 rtl8180_conf_basic_rates(dev, 0x3);
991 rtl8180_conf_basic_rates(dev, 0x1f3);
993 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
994 rtl8187se_set_antenna_config(dev,
995 priv->antenna_diversity_default,
996 priv->antenna_diversity_en);
1000 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
1002 struct rtl8180_priv *priv = dev->priv;
1003 struct rtl818x_rx_cmd_desc *entry;
1006 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1007 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
1009 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
1011 priv->rx_ring = pci_zalloc_consistent(priv->pdev, priv->rx_ring_sz * 32,
1012 &priv->rx_ring_dma);
1013 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
1014 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
1020 for (i = 0; i < 32; i++) {
1021 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
1022 dma_addr_t *mapping;
1023 entry = priv->rx_ring + priv->rx_ring_sz*i;
1025 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
1026 priv->rx_ring, priv->rx_ring_dma);
1027 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
1030 priv->rx_buf[i] = skb;
1031 mapping = (dma_addr_t *)skb->cb;
1032 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
1033 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
1035 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
1037 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
1038 priv->rx_ring, priv->rx_ring_dma);
1039 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
1043 entry->rx_buf = cpu_to_le32(*mapping);
1044 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
1047 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
1051 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
1053 struct rtl8180_priv *priv = dev->priv;
1056 for (i = 0; i < 32; i++) {
1057 struct sk_buff *skb = priv->rx_buf[i];
1061 pci_unmap_single(priv->pdev,
1062 *((dma_addr_t *)skb->cb),
1063 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
1067 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
1068 priv->rx_ring, priv->rx_ring_dma);
1069 priv->rx_ring = NULL;
1072 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
1073 unsigned int prio, unsigned int entries)
1075 struct rtl8180_priv *priv = dev->priv;
1076 struct rtl8180_tx_desc *ring;
1080 ring = pci_zalloc_consistent(priv->pdev, sizeof(*ring) * entries,
1082 if (!ring || (unsigned long)ring & 0xFF) {
1083 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
1088 priv->tx_ring[prio].desc = ring;
1089 priv->tx_ring[prio].dma = dma;
1090 priv->tx_ring[prio].idx = 0;
1091 priv->tx_ring[prio].entries = entries;
1092 skb_queue_head_init(&priv->tx_ring[prio].queue);
1094 for (i = 0; i < entries; i++)
1095 ring[i].next_tx_desc =
1096 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
1101 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
1103 struct rtl8180_priv *priv = dev->priv;
1104 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
1106 while (skb_queue_len(&ring->queue)) {
1107 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
1108 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1110 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
1111 skb->len, PCI_DMA_TODEVICE);
1113 ring->idx = (ring->idx + 1) % ring->entries;
1116 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
1117 ring->desc, ring->dma);
1121 static int rtl8180_start(struct ieee80211_hw *dev)
1123 struct rtl8180_priv *priv = dev->priv;
1127 ret = rtl8180_init_rx_ring(dev);
1131 for (i = 0; i < (dev->queues + 1); i++)
1132 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
1133 goto err_free_rings;
1135 ret = rtl8180_init_hw(dev);
1137 goto err_free_rings;
1139 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1140 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
1141 IRQF_SHARED, KBUILD_MODNAME, dev);
1143 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
1144 IRQF_SHARED, KBUILD_MODNAME, dev);
1148 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1149 goto err_free_rings;
1152 rtl8180_int_enable(dev);
1154 /* in rtl8187se at MAR regs offset there is the management
1155 * TX descriptor DMA addres..
1157 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
1158 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
1159 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
1162 reg = RTL818X_RX_CONF_ONLYERLPKT |
1163 RTL818X_RX_CONF_RX_AUTORESETPHY |
1164 RTL818X_RX_CONF_MGMT |
1165 RTL818X_RX_CONF_DATA |
1166 (7 << 8 /* MAX RX DMA */) |
1167 RTL818X_RX_CONF_BROADCAST |
1168 RTL818X_RX_CONF_NICMAC;
1170 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
1171 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
1172 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1173 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
1174 ? RTL818X_RX_CONF_CSDM1 : 0;
1175 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
1176 ? RTL818X_RX_CONF_CSDM2 : 0;
1178 reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2);
1181 priv->rx_conf = reg;
1182 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
1184 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1185 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
1187 /* CW is not on per-packet basis.
1188 * in rtl8185 the CW_VALUE reg is used.
1189 * in rtl8187se the AC param regs are used.
1191 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
1192 /* retry limit IS on per-packet basis.
1193 * the short and long retry limit in TX_CONF
1196 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
1197 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
1199 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
1200 /* TX antenna and TX gain are not on per-packet basis.
1201 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1202 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1204 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
1205 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
1206 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
1207 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
1209 /* disable early TX */
1210 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
1213 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1214 reg |= (6 << 21 /* MAX TX DMA */) |
1215 RTL818X_TX_CONF_NO_ICV;
1217 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1218 reg |= 1<<30; /* "duration procedure mode" */
1220 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
1221 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
1223 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
1225 reg &= ~RTL818X_TX_CONF_DISCW;
1227 /* different meaning, same value on both rtl8185 and rtl8180 */
1228 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
1230 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1232 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1233 reg |= RTL818X_CMD_RX_ENABLE;
1234 reg |= RTL818X_CMD_TX_ENABLE;
1235 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1240 rtl8180_free_rx_ring(dev);
1241 for (i = 0; i < (dev->queues + 1); i++)
1242 if (priv->tx_ring[i].desc)
1243 rtl8180_free_tx_ring(dev, i);
1248 static void rtl8180_stop(struct ieee80211_hw *dev)
1250 struct rtl8180_priv *priv = dev->priv;
1254 rtl8180_int_disable(dev);
1256 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1257 reg &= ~RTL818X_CMD_TX_ENABLE;
1258 reg &= ~RTL818X_CMD_RX_ENABLE;
1259 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1261 priv->rf->stop(dev);
1263 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1264 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1265 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1266 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1268 free_irq(priv->pdev->irq, dev);
1270 rtl8180_free_rx_ring(dev);
1271 for (i = 0; i < (dev->queues + 1); i++)
1272 rtl8180_free_tx_ring(dev, i);
1275 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
1276 struct ieee80211_vif *vif)
1278 struct rtl8180_priv *priv = dev->priv;
1280 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1281 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1284 static void rtl8180_beacon_work(struct work_struct *work)
1286 struct rtl8180_vif *vif_priv =
1287 container_of(work, struct rtl8180_vif, beacon_work.work);
1288 struct ieee80211_vif *vif =
1289 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1290 struct ieee80211_hw *dev = vif_priv->dev;
1291 struct ieee80211_mgmt *mgmt;
1292 struct sk_buff *skb;
1294 /* don't overflow the tx ring */
1295 if (ieee80211_queue_stopped(dev, 0))
1298 /* grab a fresh beacon */
1299 skb = ieee80211_beacon_get(dev, vif);
1304 * update beacon timestamp w/ TSF value
1305 * TODO: make hardware update beacon timestamp
1307 mgmt = (struct ieee80211_mgmt *)skb->data;
1308 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
1310 /* TODO: use actual beacon queue */
1311 skb_set_queue_mapping(skb, 0);
1313 rtl8180_tx(dev, NULL, skb);
1317 * schedule next beacon
1318 * TODO: use hardware support for beacon timing
1320 schedule_delayed_work(&vif_priv->beacon_work,
1321 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1324 static int rtl8180_add_interface(struct ieee80211_hw *dev,
1325 struct ieee80211_vif *vif)
1327 struct rtl8180_priv *priv = dev->priv;
1328 struct rtl8180_vif *vif_priv;
1331 * We only support one active interface at a time.
1336 switch (vif->type) {
1337 case NL80211_IFTYPE_STATION:
1338 case NL80211_IFTYPE_ADHOC:
1346 /* Initialize driver private area */
1347 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1348 vif_priv->dev = dev;
1349 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1350 vif_priv->enable_beacon = false;
1352 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1353 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1354 le32_to_cpu(*(__le32 *)vif->addr));
1355 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1356 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1357 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1362 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1363 struct ieee80211_vif *vif)
1365 struct rtl8180_priv *priv = dev->priv;
1369 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
1371 struct rtl8180_priv *priv = dev->priv;
1372 struct ieee80211_conf *conf = &dev->conf;
1374 priv->rf->set_chan(dev, conf);
1379 static void rtl8187se_conf_ac_parm(struct ieee80211_hw *dev, u8 queue)
1381 const struct ieee80211_tx_queue_params *params;
1382 struct rtl8180_priv *priv = dev->priv;
1391 params = &priv->queue_param[queue];
1393 cw_min = fls(params->cw_min);
1394 cw_max = fls(params->cw_max);
1396 aifs = 10 + params->aifs * priv->slot_time;
1398 /* TODO: check if txop HW is in us (mult by 32) */
1399 txop = params->txop;
1401 ac_param = txop << AC_PARAM_TXOP_LIMIT_SHIFT |
1402 cw_max << AC_PARAM_ECW_MAX_SHIFT |
1403 cw_min << AC_PARAM_ECW_MIN_SHIFT |
1404 aifs << AC_PARAM_AIFS_SHIFT;
1407 case IEEE80211_AC_BK:
1408 rtl818x_iowrite32(priv, &priv->map->AC_BK_PARAM, ac_param);
1410 case IEEE80211_AC_BE:
1411 rtl818x_iowrite32(priv, &priv->map->AC_BE_PARAM, ac_param);
1413 case IEEE80211_AC_VI:
1414 rtl818x_iowrite32(priv, &priv->map->AC_VI_PARAM, ac_param);
1416 case IEEE80211_AC_VO:
1417 rtl818x_iowrite32(priv, &priv->map->AC_VO_PARAM, ac_param);
1422 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1423 struct ieee80211_vif *vif, u16 queue,
1424 const struct ieee80211_tx_queue_params *params)
1426 struct rtl8180_priv *priv = dev->priv;
1429 /* nothing to do ? */
1430 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1433 cw_min = fls(params->cw_min);
1434 cw_max = fls(params->cw_max);
1436 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1437 priv->queue_param[queue] = *params;
1438 rtl8187se_conf_ac_parm(dev, queue);
1440 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1441 (cw_max << 4) | cw_min);
1445 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1446 struct ieee80211_bss_conf *info)
1448 struct rtl8180_priv *priv = dev->priv;
1453 /* TODO: should we do something ? */
1454 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1457 /* I _hope_ this means 10uS for the HW.
1458 * In reference code it is 0x22 for
1459 * both rtl8187L and rtl8187SE
1463 if (info->use_short_slot)
1464 priv->slot_time = 9;
1466 priv->slot_time = 20;
1468 /* 10 is SIFS time in uS */
1469 difs = 10 + 2 * priv->slot_time;
1470 eifs = 10 + difs + priv->ack_time;
1472 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1473 hw_eifs = DIV_ROUND_UP(eifs, 4);
1476 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1477 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1478 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1480 /* from reference code. set ack timeout reg = eifs reg */
1481 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1483 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1484 rtl818x_iowrite8(priv, &priv->map->EIFS_8187SE, hw_eifs);
1485 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
1486 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1487 * the HW still wait for DIFS.
1488 * HW uses 4uS units for EIFS.
1490 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1492 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1496 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1497 struct ieee80211_vif *vif,
1498 struct ieee80211_bss_conf *info,
1501 struct rtl8180_priv *priv = dev->priv;
1502 struct rtl8180_vif *vif_priv;
1506 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1508 if (changed & BSS_CHANGED_BSSID) {
1509 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->BSSID[0],
1510 le16_to_cpu(*(__le16 *)info->bssid));
1511 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->BSSID[2],
1512 le32_to_cpu(*(__le32 *)(info->bssid + 2)));
1514 if (is_valid_ether_addr(info->bssid)) {
1515 if (vif->type == NL80211_IFTYPE_ADHOC)
1516 reg = RTL818X_MSR_ADHOC;
1518 reg = RTL818X_MSR_INFRA;
1520 reg = RTL818X_MSR_NO_LINK;
1522 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1523 reg |= RTL818X_MSR_ENEDCA;
1525 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1528 if (changed & BSS_CHANGED_BASIC_RATES)
1529 rtl8180_conf_basic_rates(dev, info->basic_rates);
1531 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1533 /* when preamble changes, acktime duration changes, and erp must
1534 * be recalculated. ACK time is calculated at lowest rate.
1535 * Since mac80211 include SIFS time we remove it (-10)
1538 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1540 NL80211_BAND_2GHZ, 10,
1541 &priv->rates[0])) - 10;
1543 rtl8180_conf_erp(dev, info);
1545 /* mac80211 supplies aifs_n to driver and calls
1546 * conf_tx callback whether aifs_n changes, NOT
1547 * when aifs changes.
1548 * Aifs should be recalculated if slot changes.
1550 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1551 for (i = 0; i < 4; i++)
1552 rtl8187se_conf_ac_parm(dev, i);
1556 if (changed & BSS_CHANGED_BEACON_ENABLED)
1557 vif_priv->enable_beacon = info->enable_beacon;
1559 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1560 cancel_delayed_work_sync(&vif_priv->beacon_work);
1561 if (vif_priv->enable_beacon)
1562 schedule_work(&vif_priv->beacon_work.work);
1566 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1567 struct netdev_hw_addr_list *mc_list)
1569 return netdev_hw_addr_list_count(mc_list);
1572 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1573 unsigned int changed_flags,
1574 unsigned int *total_flags,
1577 struct rtl8180_priv *priv = dev->priv;
1579 if (changed_flags & FIF_FCSFAIL)
1580 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1581 if (changed_flags & FIF_CONTROL)
1582 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1583 if (changed_flags & FIF_OTHER_BSS)
1584 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1585 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1586 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1588 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1592 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1593 *total_flags |= FIF_FCSFAIL;
1594 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1595 *total_flags |= FIF_CONTROL;
1596 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1597 *total_flags |= FIF_OTHER_BSS;
1598 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1599 *total_flags |= FIF_ALLMULTI;
1601 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1604 static const struct ieee80211_ops rtl8180_ops = {
1606 .start = rtl8180_start,
1607 .stop = rtl8180_stop,
1608 .add_interface = rtl8180_add_interface,
1609 .remove_interface = rtl8180_remove_interface,
1610 .config = rtl8180_config,
1611 .bss_info_changed = rtl8180_bss_info_changed,
1612 .conf_tx = rtl8180_conf_tx,
1613 .prepare_multicast = rtl8180_prepare_multicast,
1614 .configure_filter = rtl8180_configure_filter,
1615 .get_tsf = rtl8180_get_tsf,
1618 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1620 struct rtl8180_priv *priv = eeprom->data;
1621 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1623 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1624 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1625 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1626 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1629 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1631 struct rtl8180_priv *priv = eeprom->data;
1634 if (eeprom->reg_data_in)
1635 reg |= RTL818X_EEPROM_CMD_WRITE;
1636 if (eeprom->reg_data_out)
1637 reg |= RTL818X_EEPROM_CMD_READ;
1638 if (eeprom->reg_data_clock)
1639 reg |= RTL818X_EEPROM_CMD_CK;
1640 if (eeprom->reg_chip_select)
1641 reg |= RTL818X_EEPROM_CMD_CS;
1643 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1644 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1648 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1650 struct eeprom_93cx6 eeprom;
1651 int eeprom_cck_table_adr;
1656 eeprom.register_read = rtl8180_eeprom_register_read;
1657 eeprom.register_write = rtl8180_eeprom_register_write;
1658 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1659 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1661 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1663 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1664 RTL818X_EEPROM_CMD_PROGRAM);
1665 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1668 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1670 priv->rf_type = eeprom_val;
1672 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1673 priv->csthreshold = eeprom_val >> 8;
1675 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1677 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1678 eeprom_cck_table_adr = 0x30;
1680 eeprom_cck_table_adr = 0x10;
1683 for (i = 0; i < 14; i += 2) {
1685 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1687 priv->channels[i].hw_value = txpwr & 0xFF;
1688 priv->channels[i + 1].hw_value = txpwr >> 8;
1692 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1693 for (i = 0; i < 14; i += 2) {
1695 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1696 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1697 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1701 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1703 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1704 priv->anaparam = le32_to_cpu(anaparam);
1705 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1708 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1709 eeprom_93cx6_read(&eeprom, 0x3F, &eeprom_val);
1710 priv->antenna_diversity_en = !!(eeprom_val & 0x100);
1711 priv->antenna_diversity_default = (eeprom_val & 0xC00) == 0x400;
1713 eeprom_93cx6_read(&eeprom, 0x7C, &eeprom_val);
1714 priv->xtal_out = eeprom_val & 0xF;
1715 priv->xtal_in = (eeprom_val & 0xF0) >> 4;
1716 priv->xtal_cal = !!(eeprom_val & 0x1000);
1717 priv->thermal_meter_val = (eeprom_val & 0xF00) >> 8;
1718 priv->thermal_meter_en = !!(eeprom_val & 0x2000);
1721 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1722 RTL818X_EEPROM_CMD_NORMAL);
1725 static int rtl8180_probe(struct pci_dev *pdev,
1726 const struct pci_device_id *id)
1728 struct ieee80211_hw *dev;
1729 struct rtl8180_priv *priv;
1730 unsigned long mem_addr, mem_len;
1731 unsigned int io_addr, io_len;
1733 const char *chip_name, *rf_name = NULL;
1736 err = pci_enable_device(pdev);
1738 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1743 err = pci_request_regions(pdev, KBUILD_MODNAME);
1745 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1747 goto err_disable_dev;
1750 io_addr = pci_resource_start(pdev, 0);
1751 io_len = pci_resource_len(pdev, 0);
1752 mem_addr = pci_resource_start(pdev, 1);
1753 mem_len = pci_resource_len(pdev, 1);
1755 if (mem_len < sizeof(struct rtl818x_csr) ||
1756 io_len < sizeof(struct rtl818x_csr)) {
1757 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1763 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1764 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1765 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1770 pci_set_master(pdev);
1772 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1774 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1784 SET_IEEE80211_DEV(dev, &pdev->dev);
1785 pci_set_drvdata(pdev, dev);
1787 priv->map_pio = false;
1788 priv->map = pci_iomap(pdev, 1, mem_len);
1790 priv->map = pci_iomap(pdev, 0, io_len);
1791 priv->map_pio = true;
1795 dev_err(&pdev->dev, "Cannot map device memory/PIO\n");
1800 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1801 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1803 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1804 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1806 priv->band.band = NL80211_BAND_2GHZ;
1807 priv->band.channels = priv->channels;
1808 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1809 priv->band.bitrates = priv->rates;
1810 priv->band.n_bitrates = 4;
1811 dev->wiphy->bands[NL80211_BAND_2GHZ] = &priv->band;
1813 ieee80211_hw_set(dev, HOST_BROADCAST_PS_BUFFERING);
1814 ieee80211_hw_set(dev, RX_INCLUDES_FCS);
1816 dev->vif_data_size = sizeof(struct rtl8180_vif);
1817 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1818 BIT(NL80211_IFTYPE_ADHOC);
1819 dev->max_signal = 65;
1821 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1822 reg &= RTL818X_TX_CONF_HWVER_MASK;
1824 case RTL818X_TX_CONF_R8180_ABCD:
1825 chip_name = "RTL8180";
1826 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1829 case RTL818X_TX_CONF_R8180_F:
1830 chip_name = "RTL8180vF";
1831 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1834 case RTL818X_TX_CONF_R8185_ABC:
1835 chip_name = "RTL8185";
1836 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1839 case RTL818X_TX_CONF_R8185_D:
1840 chip_name = "RTL8185vD";
1841 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1844 case RTL818X_TX_CONF_RTL8187SE:
1845 chip_name = "RTL8187SE";
1846 if (priv->map_pio) {
1848 "MMIO failed. PIO not supported on RTL8187SE\n");
1852 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8187SE;
1856 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1857 pci_name(pdev), reg >> 25);
1862 /* we declare to MAC80211 all the queues except for beacon queue
1863 * that will be eventually handled by DRV.
1864 * TX rings are arranged in such a way that lower is the IDX,
1865 * higher is the priority, in order to achieve direct mapping
1866 * with mac80211, however the beacon queue is an exception and it
1867 * is mapped on the highst tx ring IDX.
1869 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1870 dev->queues = RTL8187SE_NR_TX_QUEUES - 1;
1872 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1874 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1875 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1876 pci_try_set_mwi(pdev);
1879 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
1880 ieee80211_hw_set(dev, SIGNAL_DBM);
1882 ieee80211_hw_set(dev, SIGNAL_UNSPEC);
1884 wiphy_ext_feature_set(dev->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1886 rtl8180_eeprom_read(priv);
1888 switch (priv->rf_type) {
1889 case 1: rf_name = "Intersil";
1891 case 2: rf_name = "RFMD";
1893 case 3: priv->rf = &sa2400_rf_ops;
1895 case 4: priv->rf = &max2820_rf_ops;
1897 case 5: priv->rf = &grf5101_rf_ops;
1900 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1901 priv->rf = rtl8187se_detect_rf(dev);
1903 priv->rf = rtl8180_detect_rf(dev);
1906 rf_name = "RTL8255";
1909 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1910 pci_name(pdev), priv->rf_type);
1916 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1917 pci_name(pdev), rf_name);
1922 if (!is_valid_ether_addr(priv->mac_addr)) {
1923 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1924 " randomly generated MAC addr\n", pci_name(pdev));
1925 eth_random_addr(priv->mac_addr);
1927 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1929 spin_lock_init(&priv->lock);
1931 err = ieee80211_register_hw(dev);
1933 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1938 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1939 priv->mac_addr, chip_name, priv->rf->name);
1944 pci_iounmap(pdev, priv->map);
1947 ieee80211_free_hw(dev);
1950 pci_release_regions(pdev);
1953 pci_disable_device(pdev);
1957 static void rtl8180_remove(struct pci_dev *pdev)
1959 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1960 struct rtl8180_priv *priv;
1965 ieee80211_unregister_hw(dev);
1969 pci_iounmap(pdev, priv->map);
1970 pci_release_regions(pdev);
1971 pci_disable_device(pdev);
1972 ieee80211_free_hw(dev);
1976 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1978 pci_save_state(pdev);
1979 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1983 static int rtl8180_resume(struct pci_dev *pdev)
1985 pci_set_power_state(pdev, PCI_D0);
1986 pci_restore_state(pdev);
1990 #endif /* CONFIG_PM */
1992 static struct pci_driver rtl8180_driver = {
1993 .name = KBUILD_MODNAME,
1994 .id_table = rtl8180_table,
1995 .probe = rtl8180_probe,
1996 .remove = rtl8180_remove,
1998 .suspend = rtl8180_suspend,
1999 .resume = rtl8180_resume,
2000 #endif /* CONFIG_PM */
2003 module_pci_driver(rtl8180_driver);