drivers/net/wireless/ralink/rt2x00/rt2800lib.c

   1 /*
   2         Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
   3         Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
   4         Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
   5         Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
   6
   7         Based on the original rt2800pci.c and rt2800usb.c.
   8           Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
   9           Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
  10           Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
  11           Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
  12           Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
  13           Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
  14           <http://rt2x00.serialmonkey.com>
  15
  16         This program is free software; you can redistribute it and/or modify
  17         it under the terms of the GNU General Public License as published by
  18         the Free Software Foundation; either version 2 of the License, or
  19         (at your option) any later version.
  20
  21         This program is distributed in the hope that it will be useful,
  22         but WITHOUT ANY WARRANTY; without even the implied warranty of
  23         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  24         GNU General Public License for more details.
  25
  26         You should have received a copy of the GNU General Public License
  27         along with this program; if not, see <http://www.gnu.org/licenses/>.
  28  */
  29
  30 /*
  31         Module: rt2800lib
  32         Abstract: rt2800 generic device routines.
  33  */
  34
  35 #include <linux/crc-ccitt.h>
  36 #include <linux/kernel.h>
  37 #include <linux/module.h>
  38 #include <linux/slab.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2800lib.h"
  42 #include "rt2800.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2800_register_read and rt2800_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  * The _lock versions must be used if you already hold the csr_mutex
  57  */
  58 #define WAIT_FOR_BBP(__dev, __reg) \
  59         rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
  60 #define WAIT_FOR_RFCSR(__dev, __reg) \
  61         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
  62 #define WAIT_FOR_RFCSR_MT7620(__dev, __reg) \
  63         rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY_MT7620, \
  64                             (__reg))
  65 #define WAIT_FOR_RF(__dev, __reg) \
  66         rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
  67 #define WAIT_FOR_MCU(__dev, __reg) \
  68         rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
  69                             H2M_MAILBOX_CSR_OWNER, (__reg))
  70
  71 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
  72 {
  73         /* check for rt2872 on SoC */
  74         if (!rt2x00_is_soc(rt2x00dev) ||
  75             !rt2x00_rt(rt2x00dev, RT2872))
  76                 return false;
  77
  78         /* we know for sure that these rf chipsets are used on rt305x boards */
  79         if (rt2x00_rf(rt2x00dev, RF3020) ||
  80             rt2x00_rf(rt2x00dev, RF3021) ||
  81             rt2x00_rf(rt2x00dev, RF3022))
  82                 return true;
  83
  84         rt2x00_warn(rt2x00dev, "Unknown RF chipset on rt305x\n");
  85         return false;
  86 }
  87
  88 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
  89                              const unsigned int word, const u8 value)
  90 {
  91         u32 reg;
  92
  93         mutex_lock(&rt2x00dev->csr_mutex);
  94
  95         /*
  96          * Wait until the BBP becomes available, afterwards we
  97          * can safely write the new data into the register.
  98          */
  99         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 100                 reg = 0;
 101                 rt2x00_set_field32(&reg, BBP_CSR_CFG_VALUE, value);
 102                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 103                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 104                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 0);
 105                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 106
 107                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 108         }
 109
 110         mutex_unlock(&rt2x00dev->csr_mutex);
 111 }
 112
 113 static u8 rt2800_bbp_read(struct rt2x00_dev *rt2x00dev, const unsigned int word)
 114 {
 115         u32 reg;
 116         u8 value;
 117
 118         mutex_lock(&rt2x00dev->csr_mutex);
 119
 120         /*
 121          * Wait until the BBP becomes available, afterwards we
 122          * can safely write the read request into the register.
 123          * After the data has been written, we wait until hardware
 124          * returns the correct value, if at any time the register
 125          * doesn't become available in time, reg will be 0xffffffff
 126          * which means we return 0xff to the caller.
 127          */
 128         if (WAIT_FOR_BBP(rt2x00dev, &reg)) {
 129                 reg = 0;
 130                 rt2x00_set_field32(&reg, BBP_CSR_CFG_REGNUM, word);
 131                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BUSY, 1);
 132                 rt2x00_set_field32(&reg, BBP_CSR_CFG_READ_CONTROL, 1);
 133                 rt2x00_set_field32(&reg, BBP_CSR_CFG_BBP_RW_MODE, 1);
 134
 135                 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
 136
 137                 WAIT_FOR_BBP(rt2x00dev, &reg);
 138         }
 139
 140         value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
 141
 142         mutex_unlock(&rt2x00dev->csr_mutex);
 143
 144         return value;
 145 }
 146
 147 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
 148                                const unsigned int word, const u8 value)
 149 {
 150         u32 reg;
 151
 152         mutex_lock(&rt2x00dev->csr_mutex);
 153
 154         /*
 155          * Wait until the RFCSR becomes available, afterwards we
 156          * can safely write the new data into the register.
 157          */
 158         switch (rt2x00dev->chip.rt) {
 159         case RT6352:
 160                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 161                         reg = 0;
 162                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA_MT7620, value);
 163                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 164                                            word);
 165                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 1);
 166                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 167
 168                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 169                 }
 170                 break;
 171
 172         default:
 173                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 174                         reg = 0;
 175                         rt2x00_set_field32(&reg, RF_CSR_CFG_DATA, value);
 176                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 177                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 1);
 178                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 179
 180                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 181                 }
 182                 break;
 183         }
 184
 185         mutex_unlock(&rt2x00dev->csr_mutex);
 186 }
 187
 188 static void rt2800_rfcsr_write_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 189                                     const unsigned int reg, const u8 value)
 190 {
 191         rt2800_rfcsr_write(rt2x00dev, (reg | (bank << 6)), value);
 192 }
 193
 194 static void rt2800_rfcsr_write_chanreg(struct rt2x00_dev *rt2x00dev,
 195                                        const unsigned int reg, const u8 value)
 196 {
 197         rt2800_rfcsr_write_bank(rt2x00dev, 4, reg, value);
 198         rt2800_rfcsr_write_bank(rt2x00dev, 6, reg, value);
 199 }
 200
 201 static void rt2800_rfcsr_write_dccal(struct rt2x00_dev *rt2x00dev,
 202                                      const unsigned int reg, const u8 value)
 203 {
 204         rt2800_rfcsr_write_bank(rt2x00dev, 5, reg, value);
 205         rt2800_rfcsr_write_bank(rt2x00dev, 7, reg, value);
 206 }
 207
 208 static u8 rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
 209                             const unsigned int word)
 210 {
 211         u32 reg;
 212         u8 value;
 213
 214         mutex_lock(&rt2x00dev->csr_mutex);
 215
 216         /*
 217          * Wait until the RFCSR becomes available, afterwards we
 218          * can safely write the read request into the register.
 219          * After the data has been written, we wait until hardware
 220          * returns the correct value, if at any time the register
 221          * doesn't become available in time, reg will be 0xffffffff
 222          * which means we return 0xff to the caller.
 223          */
 224         switch (rt2x00dev->chip.rt) {
 225         case RT6352:
 226                 if (WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg)) {
 227                         reg = 0;
 228                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM_MT7620,
 229                                            word);
 230                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE_MT7620, 0);
 231                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY_MT7620, 1);
 232
 233                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 234
 235                         WAIT_FOR_RFCSR_MT7620(rt2x00dev, &reg);
 236                 }
 237
 238                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA_MT7620);
 239                 break;
 240
 241         default:
 242                 if (WAIT_FOR_RFCSR(rt2x00dev, &reg)) {
 243                         reg = 0;
 244                         rt2x00_set_field32(&reg, RF_CSR_CFG_REGNUM, word);
 245                         rt2x00_set_field32(&reg, RF_CSR_CFG_WRITE, 0);
 246                         rt2x00_set_field32(&reg, RF_CSR_CFG_BUSY, 1);
 247
 248                         rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
 249
 250                         WAIT_FOR_RFCSR(rt2x00dev, &reg);
 251                 }
 252
 253                 value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
 254                 break;
 255         }
 256
 257         mutex_unlock(&rt2x00dev->csr_mutex);
 258
 259         return value;
 260 }
 261
 262 static u8 rt2800_rfcsr_read_bank(struct rt2x00_dev *rt2x00dev, const u8 bank,
 263                                  const unsigned int reg)
 264 {
 265         return rt2800_rfcsr_read(rt2x00dev, (reg | (bank << 6)));
 266 }
 267
 268 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
 269                             const unsigned int word, const u32 value)
 270 {
 271         u32 reg;
 272
 273         mutex_lock(&rt2x00dev->csr_mutex);
 274
 275         /*
 276          * Wait until the RF becomes available, afterwards we
 277          * can safely write the new data into the register.
 278          */
 279         if (WAIT_FOR_RF(rt2x00dev, &reg)) {
 280                 reg = 0;
 281                 rt2x00_set_field32(&reg, RF_CSR_CFG0_REG_VALUE_BW, value);
 282                 rt2x00_set_field32(&reg, RF_CSR_CFG0_STANDBYMODE, 0);
 283                 rt2x00_set_field32(&reg, RF_CSR_CFG0_SEL, 0);
 284                 rt2x00_set_field32(&reg, RF_CSR_CFG0_BUSY, 1);
 285
 286                 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
 287                 rt2x00_rf_write(rt2x00dev, word, value);
 288         }
 289
 290         mutex_unlock(&rt2x00dev->csr_mutex);
 291 }
 292
 293 static const unsigned int rt2800_eeprom_map[EEPROM_WORD_COUNT] = {
 294         [EEPROM_CHIP_ID]                = 0x0000,
 295         [EEPROM_VERSION]                = 0x0001,
 296         [EEPROM_MAC_ADDR_0]             = 0x0002,
 297         [EEPROM_MAC_ADDR_1]             = 0x0003,
 298         [EEPROM_MAC_ADDR_2]             = 0x0004,
 299         [EEPROM_NIC_CONF0]              = 0x001a,
 300         [EEPROM_NIC_CONF1]              = 0x001b,
 301         [EEPROM_FREQ]                   = 0x001d,
 302         [EEPROM_LED_AG_CONF]            = 0x001e,
 303         [EEPROM_LED_ACT_CONF]           = 0x001f,
 304         [EEPROM_LED_POLARITY]           = 0x0020,
 305         [EEPROM_NIC_CONF2]              = 0x0021,
 306         [EEPROM_LNA]                    = 0x0022,
 307         [EEPROM_RSSI_BG]                = 0x0023,
 308         [EEPROM_RSSI_BG2]               = 0x0024,
 309         [EEPROM_TXMIXER_GAIN_BG]        = 0x0024, /* overlaps with RSSI_BG2 */
 310         [EEPROM_RSSI_A]                 = 0x0025,
 311         [EEPROM_RSSI_A2]                = 0x0026,
 312         [EEPROM_TXMIXER_GAIN_A]         = 0x0026, /* overlaps with RSSI_A2 */
 313         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0027,
 314         [EEPROM_TXPOWER_DELTA]          = 0x0028,
 315         [EEPROM_TXPOWER_BG1]            = 0x0029,
 316         [EEPROM_TXPOWER_BG2]            = 0x0030,
 317         [EEPROM_TSSI_BOUND_BG1]         = 0x0037,
 318         [EEPROM_TSSI_BOUND_BG2]         = 0x0038,
 319         [EEPROM_TSSI_BOUND_BG3]         = 0x0039,
 320         [EEPROM_TSSI_BOUND_BG4]         = 0x003a,
 321         [EEPROM_TSSI_BOUND_BG5]         = 0x003b,
 322         [EEPROM_TXPOWER_A1]             = 0x003c,
 323         [EEPROM_TXPOWER_A2]             = 0x0053,
 324         [EEPROM_TXPOWER_INIT]           = 0x0068,
 325         [EEPROM_TSSI_BOUND_A1]          = 0x006a,
 326         [EEPROM_TSSI_BOUND_A2]          = 0x006b,
 327         [EEPROM_TSSI_BOUND_A3]          = 0x006c,
 328         [EEPROM_TSSI_BOUND_A4]          = 0x006d,
 329         [EEPROM_TSSI_BOUND_A5]          = 0x006e,
 330         [EEPROM_TXPOWER_BYRATE]         = 0x006f,
 331         [EEPROM_BBP_START]              = 0x0078,
 332 };
 333
 334 static const unsigned int rt2800_eeprom_map_ext[EEPROM_WORD_COUNT] = {
 335         [EEPROM_CHIP_ID]                = 0x0000,
 336         [EEPROM_VERSION]                = 0x0001,
 337         [EEPROM_MAC_ADDR_0]             = 0x0002,
 338         [EEPROM_MAC_ADDR_1]             = 0x0003,
 339         [EEPROM_MAC_ADDR_2]             = 0x0004,
 340         [EEPROM_NIC_CONF0]              = 0x001a,
 341         [EEPROM_NIC_CONF1]              = 0x001b,
 342         [EEPROM_NIC_CONF2]              = 0x001c,
 343         [EEPROM_EIRP_MAX_TX_POWER]      = 0x0020,
 344         [EEPROM_FREQ]                   = 0x0022,
 345         [EEPROM_LED_AG_CONF]            = 0x0023,
 346         [EEPROM_LED_ACT_CONF]           = 0x0024,
 347         [EEPROM_LED_POLARITY]           = 0x0025,
 348         [EEPROM_LNA]                    = 0x0026,
 349         [EEPROM_EXT_LNA2]               = 0x0027,
 350         [EEPROM_RSSI_BG]                = 0x0028,
 351         [EEPROM_RSSI_BG2]               = 0x0029,
 352         [EEPROM_RSSI_A]                 = 0x002a,
 353         [EEPROM_RSSI_A2]                = 0x002b,
 354         [EEPROM_TXPOWER_BG1]            = 0x0030,
 355         [EEPROM_TXPOWER_BG2]            = 0x0037,
 356         [EEPROM_EXT_TXPOWER_BG3]        = 0x003e,
 357         [EEPROM_TSSI_BOUND_BG1]         = 0x0045,
 358         [EEPROM_TSSI_BOUND_BG2]         = 0x0046,
 359         [EEPROM_TSSI_BOUND_BG3]         = 0x0047,
 360         [EEPROM_TSSI_BOUND_BG4]         = 0x0048,
 361         [EEPROM_TSSI_BOUND_BG5]         = 0x0049,
 362         [EEPROM_TXPOWER_A1]             = 0x004b,
 363         [EEPROM_TXPOWER_A2]             = 0x0065,
 364         [EEPROM_EXT_TXPOWER_A3]         = 0x007f,
 365         [EEPROM_TSSI_BOUND_A1]          = 0x009a,
 366         [EEPROM_TSSI_BOUND_A2]          = 0x009b,
 367         [EEPROM_TSSI_BOUND_A3]          = 0x009c,
 368         [EEPROM_TSSI_BOUND_A4]          = 0x009d,
 369         [EEPROM_TSSI_BOUND_A5]          = 0x009e,
 370         [EEPROM_TXPOWER_BYRATE]         = 0x00a0,
 371 };
 372
 373 static unsigned int rt2800_eeprom_word_index(struct rt2x00_dev *rt2x00dev,
 374                                              const enum rt2800_eeprom_word word)
 375 {
 376         const unsigned int *map;
 377         unsigned int index;
 378
 379         if (WARN_ONCE(word >= EEPROM_WORD_COUNT,
 380                       "%s: invalid EEPROM word %d\n",
 381                       wiphy_name(rt2x00dev->hw->wiphy), word))
 382                 return 0;
 383
 384         if (rt2x00_rt(rt2x00dev, RT3593))
 385                 map = rt2800_eeprom_map_ext;
 386         else
 387                 map = rt2800_eeprom_map;
 388
 389         index = map[word];
 390
 391         /* Index 0 is valid only for EEPROM_CHIP_ID.
 392          * Otherwise it means that the offset of the
 393          * given word is not initialized in the map,
 394          * or that the field is not usable on the
 395          * actual chipset.
 396          */
 397         WARN_ONCE(word != EEPROM_CHIP_ID && index == 0,
 398                   "%s: invalid access of EEPROM word %d\n",
 399                   wiphy_name(rt2x00dev->hw->wiphy), word);
 400
 401         return index;
 402 }
 403
 404 static void *rt2800_eeprom_addr(struct rt2x00_dev *rt2x00dev,
 405                                 const enum rt2800_eeprom_word word)
 406 {
 407         unsigned int index;
 408
 409         index = rt2800_eeprom_word_index(rt2x00dev, word);
 410         return rt2x00_eeprom_addr(rt2x00dev, index);
 411 }
 412
 413 static u16 rt2800_eeprom_read(struct rt2x00_dev *rt2x00dev,
 414                               const enum rt2800_eeprom_word word)
 415 {
 416         unsigned int index;
 417
 418         index = rt2800_eeprom_word_index(rt2x00dev, word);
 419         return rt2x00_eeprom_read(rt2x00dev, index);
 420 }
 421
 422 static void rt2800_eeprom_write(struct rt2x00_dev *rt2x00dev,
 423                                 const enum rt2800_eeprom_word word, u16 data)
 424 {
 425         unsigned int index;
 426
 427         index = rt2800_eeprom_word_index(rt2x00dev, word);
 428         rt2x00_eeprom_write(rt2x00dev, index, data);
 429 }
 430
 431 static u16 rt2800_eeprom_read_from_array(struct rt2x00_dev *rt2x00dev,
 432                                          const enum rt2800_eeprom_word array,
 433                                          unsigned int offset)
 434 {
 435         unsigned int index;
 436
 437         index = rt2800_eeprom_word_index(rt2x00dev, array);
 438         return rt2x00_eeprom_read(rt2x00dev, index + offset);
 439 }
 440
 441 static int rt2800_enable_wlan_rt3290(struct rt2x00_dev *rt2x00dev)
 442 {
 443         u32 reg;
 444         int i, count;
 445
 446         reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 447         rt2x00_set_field32(&reg, WLAN_GPIO_OUT_OE_BIT_ALL, 0xff);
 448         rt2x00_set_field32(&reg, FRC_WL_ANT_SET, 1);
 449         rt2x00_set_field32(&reg, WLAN_CLK_EN, 0);
 450         rt2x00_set_field32(&reg, WLAN_EN, 1);
 451         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 452
 453         udelay(REGISTER_BUSY_DELAY);
 454
 455         count = 0;
 456         do {
 457                 /*
 458                  * Check PLL_LD & XTAL_RDY.
 459                  */
 460                 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 461                         reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
 462                         if (rt2x00_get_field32(reg, PLL_LD) &&
 463                             rt2x00_get_field32(reg, XTAL_RDY))
 464                                 break;
 465                         udelay(REGISTER_BUSY_DELAY);
 466                 }
 467
 468                 if (i >= REGISTER_BUSY_COUNT) {
 469
 470                         if (count >= 10)
 471                                 return -EIO;
 472
 473                         rt2800_register_write(rt2x00dev, 0x58, 0x018);
 474                         udelay(REGISTER_BUSY_DELAY);
 475                         rt2800_register_write(rt2x00dev, 0x58, 0x418);
 476                         udelay(REGISTER_BUSY_DELAY);
 477                         rt2800_register_write(rt2x00dev, 0x58, 0x618);
 478                         udelay(REGISTER_BUSY_DELAY);
 479                         count++;
 480                 } else {
 481                         count = 0;
 482                 }
 483
 484                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
 485                 rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 0);
 486                 rt2x00_set_field32(&reg, WLAN_CLK_EN, 1);
 487                 rt2x00_set_field32(&reg, WLAN_RESET, 1);
 488                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 489                 udelay(10);
 490                 rt2x00_set_field32(&reg, WLAN_RESET, 0);
 491                 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
 492                 udelay(10);
 493                 rt2800_register_write(rt2x00dev, INT_SOURCE_CSR, 0x7fffffff);
 494         } while (count != 0);
 495
 496         return 0;
 497 }
 498
 499 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
 500                         const u8 command, const u8 token,
 501                         const u8 arg0, const u8 arg1)
 502 {
 503         u32 reg;
 504
 505         /*
 506          * SOC devices don't support MCU requests.
 507          */
 508         if (rt2x00_is_soc(rt2x00dev))
 509                 return;
 510
 511         mutex_lock(&rt2x00dev->csr_mutex);
 512
 513         /*
 514          * Wait until the MCU becomes available, afterwards we
 515          * can safely write the new data into the register.
 516          */
 517         if (WAIT_FOR_MCU(rt2x00dev, &reg)) {
 518                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_OWNER, 1);
 519                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_CMD_TOKEN, token);
 520                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG0, arg0);
 521                 rt2x00_set_field32(&reg, H2M_MAILBOX_CSR_ARG1, arg1);
 522                 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
 523
 524                 reg = 0;
 525                 rt2x00_set_field32(&reg, HOST_CMD_CSR_HOST_COMMAND, command);
 526                 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
 527         }
 528
 529         mutex_unlock(&rt2x00dev->csr_mutex);
 530 }
 531 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
 532
 533 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
 534 {
 535         unsigned int i = 0;
 536         u32 reg;
 537
 538         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 539                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
 540                 if (reg && reg != ~0)
 541                         return 0;
 542                 msleep(1);
 543         }
 544
 545         rt2x00_err(rt2x00dev, "Unstable hardware\n");
 546         return -EBUSY;
 547 }
 548 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
 549
 550 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
 551 {
 552         unsigned int i;
 553         u32 reg;
 554
 555         /*
 556          * Some devices are really slow to respond here. Wait a whole second
 557          * before timing out.
 558          */
 559         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 560                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 561                 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
 562                     !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
 563                         return 0;
 564
 565                 msleep(10);
 566         }
 567
 568         rt2x00_err(rt2x00dev, "WPDMA TX/RX busy [0x%08x]\n", reg);
 569         return -EACCES;
 570 }
 571 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
 572
 573 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
 574 {
 575         u32 reg;
 576
 577         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
 578         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
 579         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
 580         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
 581         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
 582         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
 583         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
 584 }
 585 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
 586
 587 void rt2800_get_txwi_rxwi_size(struct rt2x00_dev *rt2x00dev,
 588                                unsigned short *txwi_size,
 589                                unsigned short *rxwi_size)
 590 {
 591         switch (rt2x00dev->chip.rt) {
 592         case RT3593:
 593                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 594                 *rxwi_size = RXWI_DESC_SIZE_5WORDS;
 595                 break;
 596
 597         case RT5592:
 598         case RT6352:
 599                 *txwi_size = TXWI_DESC_SIZE_5WORDS;
 600                 *rxwi_size = RXWI_DESC_SIZE_6WORDS;
 601                 break;
 602
 603         default:
 604                 *txwi_size = TXWI_DESC_SIZE_4WORDS;
 605                 *rxwi_size = RXWI_DESC_SIZE_4WORDS;
 606                 break;
 607         }
 608 }
 609 EXPORT_SYMBOL_GPL(rt2800_get_txwi_rxwi_size);
 610
 611 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
 612 {
 613         u16 fw_crc;
 614         u16 crc;
 615
 616         /*
 617          * The last 2 bytes in the firmware array are the crc checksum itself,
 618          * this means that we should never pass those 2 bytes to the crc
 619          * algorithm.
 620          */
 621         fw_crc = (data[len - 2] << 8 | data[len - 1]);
 622
 623         /*
 624          * Use the crc ccitt algorithm.
 625          * This will return the same value as the legacy driver which
 626          * used bit ordering reversion on the both the firmware bytes
 627          * before input input as well as on the final output.
 628          * Obviously using crc ccitt directly is much more efficient.
 629          */
 630         crc = crc_ccitt(~0, data, len - 2);
 631
 632         /*
 633          * There is a small difference between the crc-itu-t + bitrev and
 634          * the crc-ccitt crc calculation. In the latter method the 2 bytes
 635          * will be swapped, use swab16 to convert the crc to the correct
 636          * value.
 637          */
 638         crc = swab16(crc);
 639
 640         return fw_crc == crc;
 641 }
 642
 643 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
 644                           const u8 *data, const size_t len)
 645 {
 646         size_t offset = 0;
 647         size_t fw_len;
 648         bool multiple;
 649
 650         /*
 651          * PCI(e) & SOC devices require firmware with a length
 652          * of 8kb. USB devices require firmware files with a length
 653          * of 4kb. Certain USB chipsets however require different firmware,
 654          * which Ralink only provides attached to the original firmware
 655          * file. Thus for USB devices, firmware files have a length
 656          * which is a multiple of 4kb. The firmware for rt3290 chip also
 657          * have a length which is a multiple of 4kb.
 658          */
 659         if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
 660                 fw_len = 4096;
 661         else
 662                 fw_len = 8192;
 663
 664         multiple = true;
 665         /*
 666          * Validate the firmware length
 667          */
 668         if (len != fw_len && (!multiple || (len % fw_len) != 0))
 669                 return FW_BAD_LENGTH;
 670
 671         /*
 672          * Check if the chipset requires one of the upper parts
 673          * of the firmware.
 674          */
 675         if (rt2x00_is_usb(rt2x00dev) &&
 676             !rt2x00_rt(rt2x00dev, RT2860) &&
 677             !rt2x00_rt(rt2x00dev, RT2872) &&
 678             !rt2x00_rt(rt2x00dev, RT3070) &&
 679             ((len / fw_len) == 1))
 680                 return FW_BAD_VERSION;
 681
 682         /*
 683          * 8kb firmware files must be checked as if it were
 684          * 2 separate firmware files.
 685          */
 686         while (offset < len) {
 687                 if (!rt2800_check_firmware_crc(data + offset, fw_len))
 688                         return FW_BAD_CRC;
 689
 690                 offset += fw_len;
 691         }
 692
 693         return FW_OK;
 694 }
 695 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
 696
 697 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
 698                          const u8 *data, const size_t len)
 699 {
 700         unsigned int i;
 701         u32 reg;
 702         int retval;
 703
 704         if (rt2x00_rt(rt2x00dev, RT3290)) {
 705                 retval = rt2800_enable_wlan_rt3290(rt2x00dev);
 706                 if (retval)
 707                         return -EBUSY;
 708         }
 709
 710         /*
 711          * If driver doesn't wake up firmware here,
 712          * rt2800_load_firmware will hang forever when interface is up again.
 713          */
 714         rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
 715
 716         /*
 717          * Wait for stable hardware.
 718          */
 719         if (rt2800_wait_csr_ready(rt2x00dev))
 720                 return -EBUSY;
 721
 722         if (rt2x00_is_pci(rt2x00dev)) {
 723                 if (rt2x00_rt(rt2x00dev, RT3290) ||
 724                     rt2x00_rt(rt2x00dev, RT3572) ||
 725                     rt2x00_rt(rt2x00dev, RT5390) ||
 726                     rt2x00_rt(rt2x00dev, RT5392)) {
 727                         reg = rt2800_register_read(rt2x00dev, AUX_CTRL);
 728                         rt2x00_set_field32(&reg, AUX_CTRL_FORCE_PCIE_CLK, 1);
 729                         rt2x00_set_field32(&reg, AUX_CTRL_WAKE_PCIE_EN, 1);
 730                         rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
 731                 }
 732                 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
 733         }
 734
 735         rt2800_disable_wpdma(rt2x00dev);
 736
 737         /*
 738          * Write firmware to the device.
 739          */
 740         rt2800_drv_write_firmware(rt2x00dev, data, len);
 741
 742         /*
 743          * Wait for device to stabilize.
 744          */
 745         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 746                 reg = rt2800_register_read(rt2x00dev, PBF_SYS_CTRL);
 747                 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
 748                         break;
 749                 msleep(1);
 750         }
 751
 752         if (i == REGISTER_BUSY_COUNT) {
 753                 rt2x00_err(rt2x00dev, "PBF system register not ready\n");
 754                 return -EBUSY;
 755         }
 756
 757         /*
 758          * Disable DMA, will be reenabled later when enabling
 759          * the radio.
 760          */
 761         rt2800_disable_wpdma(rt2x00dev);
 762
 763         /*
 764          * Initialize firmware.
 765          */
 766         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
 767         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
 768         if (rt2x00_is_usb(rt2x00dev)) {
 769                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
 770                 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
 771         }
 772         msleep(1);
 773
 774         return 0;
 775 }
 776 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
 777
 778 void rt2800_write_tx_data(struct queue_entry *entry,
 779                           struct txentry_desc *txdesc)
 780 {
 781         __le32 *txwi = rt2800_drv_get_txwi(entry);
 782         u32 word;
 783         int i;
 784
 785         /*
 786          * Initialize TX Info descriptor
 787          */
 788         word = rt2x00_desc_read(txwi, 0);
 789         rt2x00_set_field32(&word, TXWI_W0_FRAG,
 790                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
 791         rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
 792                            test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
 793         rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
 794         rt2x00_set_field32(&word, TXWI_W0_TS,
 795                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
 796         rt2x00_set_field32(&word, TXWI_W0_AMPDU,
 797                            test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
 798         rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
 799                            txdesc->u.ht.mpdu_density);
 800         rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
 801         rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
 802         rt2x00_set_field32(&word, TXWI_W0_BW,
 803                            test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
 804         rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
 805                            test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
 806         rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
 807         rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
 808         rt2x00_desc_write(txwi, 0, word);
 809
 810         word = rt2x00_desc_read(txwi, 1);
 811         rt2x00_set_field32(&word, TXWI_W1_ACK,
 812                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
 813         rt2x00_set_field32(&word, TXWI_W1_NSEQ,
 814                            test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
 815         rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
 816         rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
 817                            test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
 818                            txdesc->key_idx : txdesc->u.ht.wcid);
 819         rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
 820                            txdesc->length);
 821         rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
 822         rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
 823         rt2x00_desc_write(txwi, 1, word);
 824
 825         /*
 826          * Always write 0 to IV/EIV fields (word 2 and 3), hardware will insert
 827          * the IV from the IVEIV register when TXD_W3_WIV is set to 0.
 828          * When TXD_W3_WIV is set to 1 it will use the IV data
 829          * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
 830          * crypto entry in the registers should be used to encrypt the frame.
 831          *
 832          * Nulify all remaining words as well, we don't know how to program them.
 833          */
 834         for (i = 2; i < entry->queue->winfo_size / sizeof(__le32); i++)
 835                 _rt2x00_desc_write(txwi, i, 0);
 836 }
 837 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
 838
 839 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
 840 {
 841         s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
 842         s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
 843         s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
 844         u16 eeprom;
 845         u8 offset0;
 846         u8 offset1;
 847         u8 offset2;
 848
 849         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
 850                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
 851                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
 852                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
 853                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
 854                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
 855         } else {
 856                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
 857                 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
 858                 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
 859                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
 860                 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
 861         }
 862
 863         /*
 864          * Convert the value from the descriptor into the RSSI value
 865          * If the value in the descriptor is 0, it is considered invalid
 866          * and the default (extremely low) rssi value is assumed
 867          */
 868         rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
 869         rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
 870         rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
 871
 872         /*
 873          * mac80211 only accepts a single RSSI value. Calculating the
 874          * average doesn't deliver a fair answer either since -60:-60 would
 875          * be considered equally good as -50:-70 while the second is the one
 876          * which gives less energy...
 877          */
 878         rssi0 = max(rssi0, rssi1);
 879         return (int)max(rssi0, rssi2);
 880 }
 881
 882 void rt2800_process_rxwi(struct queue_entry *entry,
 883                          struct rxdone_entry_desc *rxdesc)
 884 {
 885         __le32 *rxwi = (__le32 *) entry->skb->data;
 886         u32 word;
 887
 888         word = rt2x00_desc_read(rxwi, 0);
 889
 890         rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
 891         rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
 892
 893         word = rt2x00_desc_read(rxwi, 1);
 894
 895         if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
 896                 rxdesc->enc_flags |= RX_ENC_FLAG_SHORT_GI;
 897
 898         if (rt2x00_get_field32(word, RXWI_W1_BW))
 899                 rxdesc->bw = RATE_INFO_BW_40;
 900
 901         /*
 902          * Detect RX rate, always use MCS as signal type.
 903          */
 904         rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
 905         rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
 906         rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
 907
 908         /*
 909          * Mask of 0x8 bit to remove the short preamble flag.
 910          */
 911         if (rxdesc->rate_mode == RATE_MODE_CCK)
 912                 rxdesc->signal &= ~0x8;
 913
 914         word = rt2x00_desc_read(rxwi, 2);
 915
 916         /*
 917          * Convert descriptor AGC value to RSSI value.
 918          */
 919         rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
 920         /*
 921          * Remove RXWI descriptor from start of the buffer.
 922          */
 923         skb_pull(entry->skb, entry->queue->winfo_size);
 924 }
 925 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
 926
 927 static void rt2800_rate_from_status(struct skb_frame_desc *skbdesc,
 928                                     u32 status, enum nl80211_band band)
 929 {
 930         u8 flags = 0;
 931         u8 idx = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 932
 933         switch (rt2x00_get_field32(status, TX_STA_FIFO_PHYMODE)) {
 934         case RATE_MODE_HT_GREENFIELD:
 935                 flags |= IEEE80211_TX_RC_GREEN_FIELD;
 936                 /* fall through */
 937         case RATE_MODE_HT_MIX:
 938                 flags |= IEEE80211_TX_RC_MCS;
 939                 break;
 940         case RATE_MODE_OFDM:
 941                 if (band == NL80211_BAND_2GHZ)
 942                         idx += 4;
 943                 break;
 944         case RATE_MODE_CCK:
 945                 if (idx >= 8)
 946                         idx -= 8;
 947                 break;
 948         }
 949
 950         if (rt2x00_get_field32(status, TX_STA_FIFO_BW))
 951                 flags |= IEEE80211_TX_RC_40_MHZ_WIDTH;
 952
 953         if (rt2x00_get_field32(status, TX_STA_FIFO_SGI))
 954                 flags |= IEEE80211_TX_RC_SHORT_GI;
 955
 956         skbdesc->tx_rate_idx = idx;
 957         skbdesc->tx_rate_flags = flags;
 958 }
 959
 960 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi,
 961                          bool match)
 962 {
 963         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
 964         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
 965         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
 966         struct txdone_entry_desc txdesc;
 967         u32 word;
 968         u16 mcs, real_mcs;
 969         int aggr, ampdu, wcid, ack_req;
 970
 971         /*
 972          * Obtain the status about this packet.
 973          */
 974         txdesc.flags = 0;
 975         word = rt2x00_desc_read(txwi, 0);
 976
 977         mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
 978         ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
 979
 980         real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
 981         aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
 982         wcid = rt2x00_get_field32(status, TX_STA_FIFO_WCID);
 983         ack_req = rt2x00_get_field32(status, TX_STA_FIFO_TX_ACK_REQUIRED);
 984
 985         /*
 986          * If a frame was meant to be sent as a single non-aggregated MPDU
 987          * but ended up in an aggregate the used tx rate doesn't correlate
 988          * with the one specified in the TXWI as the whole aggregate is sent
 989          * with the same rate.
 990          *
 991          * For example: two frames are sent to rt2x00, the first one sets
 992          * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
 993          * and requests MCS15. If the hw aggregates both frames into one
 994          * AMDPU the tx status for both frames will contain MCS7 although
 995          * the frame was sent successfully.
 996          *
 997          * Hence, replace the requested rate with the real tx rate to not
 998          * confuse the rate control algortihm by providing clearly wrong
 999          * data.
1000          *
1001          * FIXME: if we do not find matching entry, we tell that frame was
1002          * posted without any retries. We need to find a way to fix that
1003          * and provide retry count.
1004          */
1005         if (unlikely((aggr == 1 && ampdu == 0 && real_mcs != mcs)) || !match) {
1006                 rt2800_rate_from_status(skbdesc, status, rt2x00dev->curr_band);
1007                 mcs = real_mcs;
1008         }
1009
1010         if (aggr == 1 || ampdu == 1)
1011                 __set_bit(TXDONE_AMPDU, &txdesc.flags);
1012
1013         if (!ack_req)
1014                 __set_bit(TXDONE_NO_ACK_REQ, &txdesc.flags);
1015
1016         /*
1017          * Ralink has a retry mechanism using a global fallback
1018          * table. We setup this fallback table to try the immediate
1019          * lower rate for all rates. In the TX_STA_FIFO, the MCS field
1020          * always contains the MCS used for the last transmission, be
1021          * it successful or not.
1022          */
1023         if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
1024                 /*
1025                  * Transmission succeeded. The number of retries is
1026                  * mcs - real_mcs
1027                  */
1028                 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1029                 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
1030         } else {
1031                 /*
1032                  * Transmission failed. The number of retries is
1033                  * always 7 in this case (for a total number of 8
1034                  * frames sent).
1035                  */
1036                 __set_bit(TXDONE_FAILURE, &txdesc.flags);
1037                 txdesc.retry = rt2x00dev->long_retry;
1038         }
1039
1040         /*
1041          * the frame was retried at least once
1042          * -> hw used fallback rates
1043          */
1044         if (txdesc.retry)
1045                 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
1046
1047         if (!match) {
1048                 /* RCU assures non-null sta will not be freed by mac80211. */
1049                 rcu_read_lock();
1050                 if (likely(wcid >= WCID_START && wcid <= WCID_END))
1051                         skbdesc->sta = drv_data->wcid_to_sta[wcid - WCID_START];
1052                 else
1053                         skbdesc->sta = NULL;
1054                 rt2x00lib_txdone_nomatch(entry, &txdesc);
1055                 rcu_read_unlock();
1056         } else {
1057                 rt2x00lib_txdone(entry, &txdesc);
1058         }
1059 }
1060 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
1061
1062 static unsigned int rt2800_hw_beacon_base(struct rt2x00_dev *rt2x00dev,
1063                                           unsigned int index)
1064 {
1065         return HW_BEACON_BASE(index);
1066 }
1067
1068 static inline u8 rt2800_get_beacon_offset(struct rt2x00_dev *rt2x00dev,
1069                                           unsigned int index)
1070 {
1071         return BEACON_BASE_TO_OFFSET(rt2800_hw_beacon_base(rt2x00dev, index));
1072 }
1073
1074 static void rt2800_update_beacons_setup(struct rt2x00_dev *rt2x00dev)
1075 {
1076         struct data_queue *queue = rt2x00dev->bcn;
1077         struct queue_entry *entry;
1078         int i, bcn_num = 0;
1079         u64 off, reg = 0;
1080         u32 bssid_dw1;
1081
1082         /*
1083          * Setup offsets of all active beacons in BCN_OFFSET{0,1} registers.
1084          */
1085         for (i = 0; i < queue->limit; i++) {
1086                 entry = &queue->entries[i];
1087                 if (!test_bit(ENTRY_BCN_ENABLED, &entry->flags))
1088                         continue;
1089                 off = rt2800_get_beacon_offset(rt2x00dev, entry->entry_idx);
1090                 reg |= off << (8 * bcn_num);
1091                 bcn_num++;
1092         }
1093
1094         rt2800_register_write(rt2x00dev, BCN_OFFSET0, (u32) reg);
1095         rt2800_register_write(rt2x00dev, BCN_OFFSET1, (u32) (reg >> 32));
1096
1097         /*
1098          * H/W sends up to MAC_BSSID_DW1_BSS_BCN_NUM + 1 consecutive beacons.
1099          */
1100         bssid_dw1 = rt2800_register_read(rt2x00dev, MAC_BSSID_DW1);
1101         rt2x00_set_field32(&bssid_dw1, MAC_BSSID_DW1_BSS_BCN_NUM,
1102                            bcn_num > 0 ? bcn_num - 1 : 0);
1103         rt2800_register_write(rt2x00dev, MAC_BSSID_DW1, bssid_dw1);
1104 }
1105
1106 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
1107 {
1108         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1109         struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
1110         unsigned int beacon_base;
1111         unsigned int padding_len;
1112         u32 orig_reg, reg;
1113         const int txwi_desc_size = entry->queue->winfo_size;
1114
1115         /*
1116          * Disable beaconing while we are reloading the beacon data,
1117          * otherwise we might be sending out invalid data.
1118          */
1119         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1120         orig_reg = reg;
1121         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1122         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1123
1124         /*
1125          * Add space for the TXWI in front of the skb.
1126          */
1127         memset(skb_push(entry->skb, txwi_desc_size), 0, txwi_desc_size);
1128
1129         /*
1130          * Register descriptor details in skb frame descriptor.
1131          */
1132         skbdesc->flags |= SKBDESC_DESC_IN_SKB;
1133         skbdesc->desc = entry->skb->data;
1134         skbdesc->desc_len = txwi_desc_size;
1135
1136         /*
1137          * Add the TXWI for the beacon to the skb.
1138          */
1139         rt2800_write_tx_data(entry, txdesc);
1140
1141         /*
1142          * Dump beacon to userspace through debugfs.
1143          */
1144         rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry);
1145
1146         /*
1147          * Write entire beacon with TXWI and padding to register.
1148          */
1149         padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
1150         if (padding_len && skb_pad(entry->skb, padding_len)) {
1151                 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n");
1152                 /* skb freed by skb_pad() on failure */
1153                 entry->skb = NULL;
1154                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1155                 return;
1156         }
1157
1158         beacon_base = rt2800_hw_beacon_base(rt2x00dev, entry->entry_idx);
1159
1160         rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
1161                                    entry->skb->len + padding_len);
1162         __set_bit(ENTRY_BCN_ENABLED, &entry->flags);
1163
1164         /*
1165          * Change global beacons settings.
1166          */
1167         rt2800_update_beacons_setup(rt2x00dev);
1168
1169         /*
1170          * Restore beaconing state.
1171          */
1172         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1173
1174         /*
1175          * Clean up beacon skb.
1176          */
1177         dev_kfree_skb_any(entry->skb);
1178         entry->skb = NULL;
1179 }
1180 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
1181
1182 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
1183                                                 unsigned int index)
1184 {
1185         int i;
1186         const int txwi_desc_size = rt2x00dev->bcn->winfo_size;
1187         unsigned int beacon_base;
1188
1189         beacon_base = rt2800_hw_beacon_base(rt2x00dev, index);
1190
1191         /*
1192          * For the Beacon base registers we only need to clear
1193          * the whole TXWI which (when set to 0) will invalidate
1194          * the entire beacon.
1195          */
1196         for (i = 0; i < txwi_desc_size; i += sizeof(__le32))
1197                 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
1198 }
1199
1200 void rt2800_clear_beacon(struct queue_entry *entry)
1201 {
1202         struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
1203         u32 orig_reg, reg;
1204
1205         /*
1206          * Disable beaconing while we are reloading the beacon data,
1207          * otherwise we might be sending out invalid data.
1208          */
1209         orig_reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1210         reg = orig_reg;
1211         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
1212         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1213
1214         /*
1215          * Clear beacon.
1216          */
1217         rt2800_clear_beacon_register(rt2x00dev, entry->entry_idx);
1218         __clear_bit(ENTRY_BCN_ENABLED, &entry->flags);
1219
1220         /*
1221          * Change global beacons settings.
1222          */
1223         rt2800_update_beacons_setup(rt2x00dev);
1224         /*
1225          * Restore beaconing state.
1226          */
1227         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
1228 }
1229 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
1230
1231 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1232 const struct rt2x00debug rt2800_rt2x00debug = {
1233         .owner  = THIS_MODULE,
1234         .csr    = {
1235                 .read           = rt2800_register_read,
1236                 .write          = rt2800_register_write,
1237                 .flags          = RT2X00DEBUGFS_OFFSET,
1238                 .word_base      = CSR_REG_BASE,
1239                 .word_size      = sizeof(u32),
1240                 .word_count     = CSR_REG_SIZE / sizeof(u32),
1241         },
1242         .eeprom = {
1243                 /* NOTE: The local EEPROM access functions can't
1244                  * be used here, use the generic versions instead.
1245                  */
1246                 .read           = rt2x00_eeprom_read,
1247                 .write          = rt2x00_eeprom_write,
1248                 .word_base      = EEPROM_BASE,
1249                 .word_size      = sizeof(u16),
1250                 .word_count     = EEPROM_SIZE / sizeof(u16),
1251         },
1252         .bbp    = {
1253                 .read           = rt2800_bbp_read,
1254                 .write          = rt2800_bbp_write,
1255                 .word_base      = BBP_BASE,
1256                 .word_size      = sizeof(u8),
1257                 .word_count     = BBP_SIZE / sizeof(u8),
1258         },
1259         .rf     = {
1260                 .read           = rt2x00_rf_read,
1261                 .write          = rt2800_rf_write,
1262                 .word_base      = RF_BASE,
1263                 .word_size      = sizeof(u32),
1264                 .word_count     = RF_SIZE / sizeof(u32),
1265         },
1266         .rfcsr  = {
1267                 .read           = rt2800_rfcsr_read,
1268                 .write          = rt2800_rfcsr_write,
1269                 .word_base      = RFCSR_BASE,
1270                 .word_size      = sizeof(u8),
1271                 .word_count     = RFCSR_SIZE / sizeof(u8),
1272         },
1273 };
1274 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
1275 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1276
1277 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
1278 {
1279         u32 reg;
1280
1281         if (rt2x00_rt(rt2x00dev, RT3290)) {
1282                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
1283                 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
1284         } else {
1285                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1286                 return rt2x00_get_field32(reg, GPIO_CTRL_VAL2);
1287         }
1288 }
1289 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
1290
1291 #ifdef CONFIG_RT2X00_LIB_LEDS
1292 static void rt2800_brightness_set(struct led_classdev *led_cdev,
1293                                   enum led_brightness brightness)
1294 {
1295         struct rt2x00_led *led =
1296             container_of(led_cdev, struct rt2x00_led, led_dev);
1297         unsigned int enabled = brightness != LED_OFF;
1298         unsigned int bg_mode =
1299             (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ);
1300         unsigned int polarity =
1301                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1302                                    EEPROM_FREQ_LED_POLARITY);
1303         unsigned int ledmode =
1304                 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
1305                                    EEPROM_FREQ_LED_MODE);
1306         u32 reg;
1307
1308         /* Check for SoC (SOC devices don't support MCU requests) */
1309         if (rt2x00_is_soc(led->rt2x00dev)) {
1310                 reg = rt2800_register_read(led->rt2x00dev, LED_CFG);
1311
1312                 /* Set LED Polarity */
1313                 rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, polarity);
1314
1315                 /* Set LED Mode */
1316                 if (led->type == LED_TYPE_RADIO) {
1317                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE,
1318                                            enabled ? 3 : 0);
1319                 } else if (led->type == LED_TYPE_ASSOC) {
1320                         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE,
1321                                            enabled ? 3 : 0);
1322                 } else if (led->type == LED_TYPE_QUALITY) {
1323                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE,
1324                                            enabled ? 3 : 0);
1325                 }
1326
1327                 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
1328
1329         } else {
1330                 if (led->type == LED_TYPE_RADIO) {
1331                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1332                                               enabled ? 0x20 : 0);
1333                 } else if (led->type == LED_TYPE_ASSOC) {
1334                         rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
1335                                               enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
1336                 } else if (led->type == LED_TYPE_QUALITY) {
1337                         /*
1338                          * The brightness is divided into 6 levels (0 - 5),
1339                          * The specs tell us the following levels:
1340                          *      0, 1 ,3, 7, 15, 31
1341                          * to determine the level in a simple way we can simply
1342                          * work with bitshifting:
1343                          *      (1 << level) - 1
1344                          */
1345                         rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
1346                                               (1 << brightness / (LED_FULL / 6)) - 1,
1347                                               polarity);
1348                 }
1349         }
1350 }
1351
1352 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
1353                      struct rt2x00_led *led, enum led_type type)
1354 {
1355         led->rt2x00dev = rt2x00dev;
1356         led->type = type;
1357         led->led_dev.brightness_set = rt2800_brightness_set;
1358         led->flags = LED_INITIALIZED;
1359 }
1360 #endif /* CONFIG_RT2X00_LIB_LEDS */
1361
1362 /*
1363  * Configuration handlers.
1364  */
1365 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
1366                                const u8 *address,
1367                                int wcid)
1368 {
1369         struct mac_wcid_entry wcid_entry;
1370         u32 offset;
1371
1372         offset = MAC_WCID_ENTRY(wcid);
1373
1374         memset(&wcid_entry, 0xff, sizeof(wcid_entry));
1375         if (address)
1376                 memcpy(wcid_entry.mac, address, ETH_ALEN);
1377
1378         rt2800_register_multiwrite(rt2x00dev, offset,
1379                                       &wcid_entry, sizeof(wcid_entry));
1380 }
1381
1382 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
1383 {
1384         u32 offset;
1385         offset = MAC_WCID_ATTR_ENTRY(wcid);
1386         rt2800_register_write(rt2x00dev, offset, 0);
1387 }
1388
1389 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
1390                                            int wcid, u32 bssidx)
1391 {
1392         u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
1393         u32 reg;
1394
1395         /*
1396          * The BSS Idx numbers is split in a main value of 3 bits,
1397          * and a extended field for adding one additional bit to the value.
1398          */
1399         reg = rt2800_register_read(rt2x00dev, offset);
1400         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
1401         rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
1402                            (bssidx & 0x8) >> 3);
1403         rt2800_register_write(rt2x00dev, offset, reg);
1404 }
1405
1406 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
1407                                            struct rt2x00lib_crypto *crypto,
1408                                            struct ieee80211_key_conf *key)
1409 {
1410         struct mac_iveiv_entry iveiv_entry;
1411         u32 offset;
1412         u32 reg;
1413
1414         offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
1415
1416         if (crypto->cmd == SET_KEY) {
1417                 reg = rt2800_register_read(rt2x00dev, offset);
1418                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB,
1419                                    !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
1420                 /*
1421                  * Both the cipher as the BSS Idx numbers are split in a main
1422                  * value of 3 bits, and a extended field for adding one additional
1423                  * bit to the value.
1424                  */
1425                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER,
1426                                    (crypto->cipher & 0x7));
1427                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1428                                    (crypto->cipher & 0x8) >> 3);
1429                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1430                 rt2800_register_write(rt2x00dev, offset, reg);
1431         } else {
1432                 /* Delete the cipher without touching the bssidx */
1433                 reg = rt2800_register_read(rt2x00dev, offset);
1434                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1435                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1436                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1437                 rt2x00_set_field32(&reg, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1438                 rt2800_register_write(rt2x00dev, offset, reg);
1439         }
1440
1441         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1442
1443         memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1444         if ((crypto->cipher == CIPHER_TKIP) ||
1445             (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1446             (crypto->cipher == CIPHER_AES))
1447                 iveiv_entry.iv[3] |= 0x20;
1448         iveiv_entry.iv[3] |= key->keyidx << 6;
1449         rt2800_register_multiwrite(rt2x00dev, offset,
1450                                       &iveiv_entry, sizeof(iveiv_entry));
1451 }
1452
1453 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1454                              struct rt2x00lib_crypto *crypto,
1455                              struct ieee80211_key_conf *key)
1456 {
1457         struct hw_key_entry key_entry;
1458         struct rt2x00_field32 field;
1459         u32 offset;
1460         u32 reg;
1461
1462         if (crypto->cmd == SET_KEY) {
1463                 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1464
1465                 memcpy(key_entry.key, crypto->key,
1466                        sizeof(key_entry.key));
1467                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1468                        sizeof(key_entry.tx_mic));
1469                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1470                        sizeof(key_entry.rx_mic));
1471
1472                 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1473                 rt2800_register_multiwrite(rt2x00dev, offset,
1474                                               &key_entry, sizeof(key_entry));
1475         }
1476
1477         /*
1478          * The cipher types are stored over multiple registers
1479          * starting with SHARED_KEY_MODE_BASE each word will have
1480          * 32 bits and contains the cipher types for 2 bssidx each.
1481          * Using the correct defines correctly will cause overhead,
1482          * so just calculate the correct offset.
1483          */
1484         field.bit_offset = 4 * (key->hw_key_idx % 8);
1485         field.bit_mask = 0x7 << field.bit_offset;
1486
1487         offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1488
1489         reg = rt2800_register_read(rt2x00dev, offset);
1490         rt2x00_set_field32(&reg, field,
1491                            (crypto->cmd == SET_KEY) * crypto->cipher);
1492         rt2800_register_write(rt2x00dev, offset, reg);
1493
1494         /*
1495          * Update WCID information
1496          */
1497         rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1498         rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1499                                        crypto->bssidx);
1500         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1501
1502         return 0;
1503 }
1504 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1505
1506 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1507                                struct rt2x00lib_crypto *crypto,
1508                                struct ieee80211_key_conf *key)
1509 {
1510         struct hw_key_entry key_entry;
1511         u32 offset;
1512
1513         if (crypto->cmd == SET_KEY) {
1514                 /*
1515                  * Allow key configuration only for STAs that are
1516                  * known by the hw.
1517                  */
1518                 if (crypto->wcid > WCID_END)
1519                         return -ENOSPC;
1520                 key->hw_key_idx = crypto->wcid;
1521
1522                 memcpy(key_entry.key, crypto->key,
1523                        sizeof(key_entry.key));
1524                 memcpy(key_entry.tx_mic, crypto->tx_mic,
1525                        sizeof(key_entry.tx_mic));
1526                 memcpy(key_entry.rx_mic, crypto->rx_mic,
1527                        sizeof(key_entry.rx_mic));
1528
1529                 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1530                 rt2800_register_multiwrite(rt2x00dev, offset,
1531                                               &key_entry, sizeof(key_entry));
1532         }
1533
1534         /*
1535          * Update WCID information
1536          */
1537         rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1538
1539         return 0;
1540 }
1541 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1542
1543 static void rt2800_set_max_psdu_len(struct rt2x00_dev *rt2x00dev)
1544 {
1545         u8 i, max_psdu;
1546         u32 reg;
1547         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1548
1549         for (i = 0; i < 3; i++)
1550                 if (drv_data->ampdu_factor_cnt[i] > 0)
1551                         break;
1552
1553         max_psdu = min(drv_data->max_psdu, i);
1554
1555         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
1556         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, max_psdu);
1557         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
1558 }
1559
1560 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1561                    struct ieee80211_sta *sta)
1562 {
1563         int wcid;
1564         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1565         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1566
1567         /*
1568          * Limit global maximum TX AMPDU length to smallest value of all
1569          * connected stations. In AP mode this can be suboptimal, but we
1570          * do not have a choice if some connected STA is not capable to
1571          * receive the same amount of data like the others.
1572          */
1573         if (sta->ht_cap.ht_supported) {
1574                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]++;
1575                 rt2800_set_max_psdu_len(rt2x00dev);
1576         }
1577
1578         /*
1579          * Search for the first free WCID entry and return the corresponding
1580          * index.
1581          */
1582         wcid = find_first_zero_bit(drv_data->sta_ids, STA_IDS_SIZE) + WCID_START;
1583
1584         /*
1585          * Store selected wcid even if it is invalid so that we can
1586          * later decide if the STA is uploaded into the hw.
1587          */
1588         sta_priv->wcid = wcid;
1589
1590         /*
1591          * No space left in the device, however, we can still communicate
1592          * with the STA -> No error.
1593          */
1594         if (wcid > WCID_END)
1595                 return 0;
1596
1597         __set_bit(wcid - WCID_START, drv_data->sta_ids);
1598         drv_data->wcid_to_sta[wcid - WCID_START] = sta;
1599
1600         /*
1601          * Clean up WCID attributes and write STA address to the device.
1602          */
1603         rt2800_delete_wcid_attr(rt2x00dev, wcid);
1604         rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1605         rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1606                                        rt2x00lib_get_bssidx(rt2x00dev, vif));
1607         return 0;
1608 }
1609 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1610
1611 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, struct ieee80211_sta *sta)
1612 {
1613         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1614         struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1615         int wcid = sta_priv->wcid;
1616
1617         if (sta->ht_cap.ht_supported) {
1618                 drv_data->ampdu_factor_cnt[sta->ht_cap.ampdu_factor & 3]--;
1619                 rt2800_set_max_psdu_len(rt2x00dev);
1620         }
1621
1622         if (wcid > WCID_END)
1623                 return 0;
1624         /*
1625          * Remove WCID entry, no need to clean the attributes as they will
1626          * get renewed when the WCID is reused.
1627          */
1628         rt2800_config_wcid(rt2x00dev, NULL, wcid);
1629         drv_data->wcid_to_sta[wcid - WCID_START] = NULL;
1630         __clear_bit(wcid - WCID_START, drv_data->sta_ids);
1631
1632         return 0;
1633 }
1634 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1635
1636 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1637                           const unsigned int filter_flags)
1638 {
1639         u32 reg;
1640
1641         /*
1642          * Start configuration steps.
1643          * Note that the version error will always be dropped
1644          * and broadcast frames will always be accepted since
1645          * there is no filter for it at this time.
1646          */
1647         reg = rt2800_register_read(rt2x00dev, RX_FILTER_CFG);
1648         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CRC_ERROR,
1649                            !(filter_flags & FIF_FCSFAIL));
1650         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PHY_ERROR,
1651                            !(filter_flags & FIF_PLCPFAIL));
1652         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_TO_ME,
1653                            !test_bit(CONFIG_MONITORING, &rt2x00dev->flags));
1654         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1655         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1656         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_MULTICAST,
1657                            !(filter_flags & FIF_ALLMULTI));
1658         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BROADCAST, 0);
1659         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1660         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END_ACK,
1661                            !(filter_flags & FIF_CONTROL));
1662         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CF_END,
1663                            !(filter_flags & FIF_CONTROL));
1664         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_ACK,
1665                            !(filter_flags & FIF_CONTROL));
1666         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CTS,
1667                            !(filter_flags & FIF_CONTROL));
1668         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_RTS,
1669                            !(filter_flags & FIF_CONTROL));
1670         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_PSPOLL,
1671                            !(filter_flags & FIF_PSPOLL));
1672         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BA, 0);
1673         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_BAR,
1674                            !(filter_flags & FIF_CONTROL));
1675         rt2x00_set_field32(&reg, RX_FILTER_CFG_DROP_CNTL,
1676                            !(filter_flags & FIF_CONTROL));
1677         rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1678 }
1679 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1680
1681 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1682                         struct rt2x00intf_conf *conf, const unsigned int flags)
1683 {
1684         u32 reg;
1685         bool update_bssid = false;
1686
1687         if (flags & CONFIG_UPDATE_TYPE) {
1688                 /*
1689                  * Enable synchronisation.
1690                  */
1691                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1692                 rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1693                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1694
1695                 if (conf->sync == TSF_SYNC_AP_NONE) {
1696                         /*
1697                          * Tune beacon queue transmit parameters for AP mode
1698                          */
1699                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1700                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1701                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1702                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1703                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1704                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1705                 } else {
1706                         reg = rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG);
1707                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1708                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1709                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1710                         rt2x00_set_field32(&reg, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1711                         rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1712                 }
1713         }
1714
1715         if (flags & CONFIG_UPDATE_MAC) {
1716                 if (flags & CONFIG_UPDATE_TYPE &&
1717                     conf->sync == TSF_SYNC_AP_NONE) {
1718                         /*
1719                          * The BSSID register has to be set to our own mac
1720                          * address in AP mode.
1721                          */
1722                         memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1723                         update_bssid = true;
1724                 }
1725
1726                 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1727                         reg = le32_to_cpu(conf->mac[1]);
1728                         rt2x00_set_field32(&reg, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1729                         conf->mac[1] = cpu_to_le32(reg);
1730                 }
1731
1732                 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1733                                               conf->mac, sizeof(conf->mac));
1734         }
1735
1736         if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1737                 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1738                         reg = le32_to_cpu(conf->bssid[1]);
1739                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1740                         rt2x00_set_field32(&reg, MAC_BSSID_DW1_BSS_BCN_NUM, 0);
1741                         conf->bssid[1] = cpu_to_le32(reg);
1742                 }
1743
1744                 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1745                                               conf->bssid, sizeof(conf->bssid));
1746         }
1747 }
1748 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1749
1750 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1751                                     struct rt2x00lib_erp *erp)
1752 {
1753         bool any_sta_nongf = !!(erp->ht_opmode &
1754                                 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1755         u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1756         u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1757         u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1758         u32 reg;
1759
1760         /* default protection rate for HT20: OFDM 24M */
1761         mm20_rate = gf20_rate = 0x4004;
1762
1763         /* default protection rate for HT40: duplicate OFDM 24M */
1764         mm40_rate = gf40_rate = 0x4084;
1765
1766         switch (protection) {
1767         case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1768                 /*
1769                  * All STAs in this BSS are HT20/40 but there might be
1770                  * STAs not supporting greenfield mode.
1771                  * => Disable protection for HT transmissions.
1772                  */
1773                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1774
1775                 break;
1776         case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1777                 /*
1778                  * All STAs in this BSS are HT20 or HT20/40 but there
1779                  * might be STAs not supporting greenfield mode.
1780                  * => Protect all HT40 transmissions.
1781                  */
1782                 mm20_mode = gf20_mode = 0;
1783                 mm40_mode = gf40_mode = 1;
1784
1785                 break;
1786         case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1787                 /*
1788                  * Nonmember protection:
1789                  * According to 802.11n we _should_ protect all
1790                  * HT transmissions (but we don't have to).
1791                  *
1792                  * But if cts_protection is enabled we _shall_ protect
1793                  * all HT transmissions using a CCK rate.
1794                  *
1795                  * And if any station is non GF we _shall_ protect
1796                  * GF transmissions.
1797                  *
1798                  * We decide to protect everything
1799                  * -> fall through to mixed mode.
1800                  */
1801         case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1802                 /*
1803                  * Legacy STAs are present
1804                  * => Protect all HT transmissions.
1805                  */
1806                 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 1;
1807
1808                 /*
1809                  * If erp protection is needed we have to protect HT
1810                  * transmissions with CCK 11M long preamble.
1811                  */
1812                 if (erp->cts_protection) {
1813                         /* don't duplicate RTS/CTS in CCK mode */
1814                         mm20_rate = mm40_rate = 0x0003;
1815                         gf20_rate = gf40_rate = 0x0003;
1816                 }
1817                 break;
1818         }
1819
1820         /* check for STAs not supporting greenfield mode */
1821         if (any_sta_nongf)
1822                 gf20_mode = gf40_mode = 1;
1823
1824         /* Update HT protection config */
1825         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
1826         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1827         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1828         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1829
1830         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
1831         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1832         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1833         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1834
1835         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
1836         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1837         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1838         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1839
1840         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
1841         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1842         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1843         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1844 }
1845
1846 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1847                        u32 changed)
1848 {
1849         u32 reg;
1850
1851         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1852                 reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
1853                 rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE,
1854                                    !!erp->short_preamble);
1855                 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1856         }
1857
1858         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1859                 reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
1860                 rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL,
1861                                    erp->cts_protection ? 2 : 0);
1862                 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1863         }
1864
1865         if (changed & BSS_CHANGED_BASIC_RATES) {
1866                 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1867                                       0xff0 | erp->basic_rates);
1868                 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1869         }
1870
1871         if (changed & BSS_CHANGED_ERP_SLOT) {
1872                 reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
1873                 rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME,
1874                                    erp->slot_time);
1875                 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1876
1877                 reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
1878                 rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, erp->eifs);
1879                 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1880         }
1881
1882         if (changed & BSS_CHANGED_BEACON_INT) {
1883                 reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
1884                 rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL,
1885                                    erp->beacon_int * 16);
1886                 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1887         }
1888
1889         if (changed & BSS_CHANGED_HT)
1890                 rt2800_config_ht_opmode(rt2x00dev, erp);
1891 }
1892 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1893
1894 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1895 {
1896         u32 reg;
1897         u16 eeprom;
1898         u8 led_ctrl, led_g_mode, led_r_mode;
1899
1900         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
1901         if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) {
1902                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 1);
1903                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 1);
1904         } else {
1905                 rt2x00_set_field32(&reg, GPIO_SWITCH_0, 0);
1906                 rt2x00_set_field32(&reg, GPIO_SWITCH_1, 0);
1907         }
1908         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1909
1910         reg = rt2800_register_read(rt2x00dev, LED_CFG);
1911         led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1912         led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1913         if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1914             led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1915                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
1916                 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1917                 if (led_ctrl == 0 || led_ctrl > 0x40) {
1918                         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, led_g_mode);
1919                         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, led_r_mode);
1920                         rt2800_register_write(rt2x00dev, LED_CFG, reg);
1921                 } else {
1922                         rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1923                                            (led_g_mode << 2) | led_r_mode, 1);
1924                 }
1925         }
1926 }
1927
1928 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1929                                      enum antenna ant)
1930 {
1931         u32 reg;
1932         u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1933         u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1934
1935         if (rt2x00_is_pci(rt2x00dev)) {
1936                 reg = rt2800_register_read(rt2x00dev, E2PROM_CSR);
1937                 rt2x00_set_field32(&reg, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1938                 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1939         } else if (rt2x00_is_usb(rt2x00dev))
1940                 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1941                                    eesk_pin, 0);
1942
1943         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
1944         rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
1945         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, gpio_bit3);
1946         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
1947 }
1948
1949 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1950 {
1951         u8 r1;
1952         u8 r3;
1953         u16 eeprom;
1954
1955         r1 = rt2800_bbp_read(rt2x00dev, 1);
1956         r3 = rt2800_bbp_read(rt2x00dev, 3);
1957
1958         if (rt2x00_rt(rt2x00dev, RT3572) &&
1959             rt2x00_has_cap_bt_coexist(rt2x00dev))
1960                 rt2800_config_3572bt_ant(rt2x00dev);
1961
1962         /*
1963          * Configure the TX antenna.
1964          */
1965         switch (ant->tx_chain_num) {
1966         case 1:
1967                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1968                 break;
1969         case 2:
1970                 if (rt2x00_rt(rt2x00dev, RT3572) &&
1971                     rt2x00_has_cap_bt_coexist(rt2x00dev))
1972                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1973                 else
1974                         rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1975                 break;
1976         case 3:
1977                 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1978                 break;
1979         }
1980
1981         /*
1982          * Configure the RX antenna.
1983          */
1984         switch (ant->rx_chain_num) {
1985         case 1:
1986                 if (rt2x00_rt(rt2x00dev, RT3070) ||
1987                     rt2x00_rt(rt2x00dev, RT3090) ||
1988                     rt2x00_rt(rt2x00dev, RT3352) ||
1989                     rt2x00_rt(rt2x00dev, RT3390)) {
1990                         eeprom = rt2800_eeprom_read(rt2x00dev,
1991                                                     EEPROM_NIC_CONF1);
1992                         if (rt2x00_get_field16(eeprom,
1993                                                 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1994                                 rt2800_set_ant_diversity(rt2x00dev,
1995                                                 rt2x00dev->default_ant.rx);
1996                 }
1997                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1998                 break;
1999         case 2:
2000                 if (rt2x00_rt(rt2x00dev, RT3572) &&
2001                     rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2002                         rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
2003                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
2004                                 rt2x00dev->curr_band == NL80211_BAND_5GHZ);
2005                         rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
2006                 } else {
2007                         rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
2008                 }
2009                 break;
2010         case 3:
2011                 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
2012                 break;
2013         }
2014
2015         rt2800_bbp_write(rt2x00dev, 3, r3);
2016         rt2800_bbp_write(rt2x00dev, 1, r1);
2017
2018         if (rt2x00_rt(rt2x00dev, RT3593)) {
2019                 if (ant->rx_chain_num == 1)
2020                         rt2800_bbp_write(rt2x00dev, 86, 0x00);
2021                 else
2022                         rt2800_bbp_write(rt2x00dev, 86, 0x46);
2023         }
2024 }
2025 EXPORT_SYMBOL_GPL(rt2800_config_ant);
2026
2027 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
2028                                    struct rt2x00lib_conf *libconf)
2029 {
2030         u16 eeprom;
2031         short lna_gain;
2032
2033         if (libconf->rf.channel <= 14) {
2034                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2035                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
2036         } else if (libconf->rf.channel <= 64) {
2037                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
2038                 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
2039         } else if (libconf->rf.channel <= 128) {
2040                 if (rt2x00_rt(rt2x00dev, RT3593)) {
2041                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2042                         lna_gain = rt2x00_get_field16(eeprom,
2043                                                       EEPROM_EXT_LNA2_A1);
2044                 } else {
2045                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
2046                         lna_gain = rt2x00_get_field16(eeprom,
2047                                                       EEPROM_RSSI_BG2_LNA_A1);
2048                 }
2049         } else {
2050                 if (rt2x00_rt(rt2x00dev, RT3593)) {
2051                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
2052                         lna_gain = rt2x00_get_field16(eeprom,
2053                                                       EEPROM_EXT_LNA2_A2);
2054                 } else {
2055                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
2056                         lna_gain = rt2x00_get_field16(eeprom,
2057                                                       EEPROM_RSSI_A2_LNA_A2);
2058                 }
2059         }
2060
2061         rt2x00dev->lna_gain = lna_gain;
2062 }
2063
2064 static inline bool rt2800_clk_is_20mhz(struct rt2x00_dev *rt2x00dev)
2065 {
2066         return clk_get_rate(rt2x00dev->clk) == 20000000;
2067 }
2068
2069 #define FREQ_OFFSET_BOUND       0x5f
2070
2071 static void rt2800_freq_cal_mode1(struct rt2x00_dev *rt2x00dev)
2072 {
2073         u8 freq_offset, prev_freq_offset;
2074         u8 rfcsr, prev_rfcsr;
2075
2076         freq_offset = rt2x00_get_field8(rt2x00dev->freq_offset, RFCSR17_CODE);
2077         freq_offset = min_t(u8, freq_offset, FREQ_OFFSET_BOUND);
2078
2079         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
2080         prev_rfcsr = rfcsr;
2081
2082         rt2x00_set_field8(&rfcsr, RFCSR17_CODE, freq_offset);
2083         if (rfcsr == prev_rfcsr)
2084                 return;
2085
2086         if (rt2x00_is_usb(rt2x00dev)) {
2087                 rt2800_mcu_request(rt2x00dev, MCU_FREQ_OFFSET, 0xff,
2088                                    freq_offset, prev_rfcsr);
2089                 return;
2090         }
2091
2092         prev_freq_offset = rt2x00_get_field8(prev_rfcsr, RFCSR17_CODE);
2093         while (prev_freq_offset != freq_offset) {
2094                 if (prev_freq_offset < freq_offset)
2095                         prev_freq_offset++;
2096                 else
2097                         prev_freq_offset--;
2098
2099                 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, prev_freq_offset);
2100                 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2101
2102                 usleep_range(1000, 1500);
2103         }
2104 }
2105
2106 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
2107                                          struct ieee80211_conf *conf,
2108                                          struct rf_channel *rf,
2109                                          struct channel_info *info)
2110 {
2111         rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
2112
2113         if (rt2x00dev->default_ant.tx_chain_num == 1)
2114                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
2115
2116         if (rt2x00dev->default_ant.rx_chain_num == 1) {
2117                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
2118                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2119         } else if (rt2x00dev->default_ant.rx_chain_num == 2)
2120                 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
2121
2122         if (rf->channel > 14) {
2123                 /*
2124                  * When TX power is below 0, we should increase it by 7 to
2125                  * make it a positive value (Minimum value is -7).
2126                  * However this means that values between 0 and 7 have
2127                  * double meaning, and we should set a 7DBm boost flag.
2128                  */
2129                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
2130                                    (info->default_power1 >= 0));
2131
2132                 if (info->default_power1 < 0)
2133                         info->default_power1 += 7;
2134
2135                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
2136
2137                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
2138                                    (info->default_power2 >= 0));
2139
2140                 if (info->default_power2 < 0)
2141                         info->default_power2 += 7;
2142
2143                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
2144         } else {
2145                 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
2146                 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
2147         }
2148
2149         rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
2150
2151         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2152         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2153         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2154         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2155
2156         udelay(200);
2157
2158         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2159         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2160         rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
2161         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2162
2163         udelay(200);
2164
2165         rt2800_rf_write(rt2x00dev, 1, rf->rf1);
2166         rt2800_rf_write(rt2x00dev, 2, rf->rf2);
2167         rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
2168         rt2800_rf_write(rt2x00dev, 4, rf->rf4);
2169 }
2170
2171 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
2172                                          struct ieee80211_conf *conf,
2173                                          struct rf_channel *rf,
2174                                          struct channel_info *info)
2175 {
2176         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2177         u8 rfcsr, calib_tx, calib_rx;
2178
2179         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2180
2181         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2182         rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
2183         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2184
2185         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2186         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2187         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2188
2189         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2190         rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
2191         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2192
2193         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2194         rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
2195         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2196
2197         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2198         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2199         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
2200                           rt2x00dev->default_ant.rx_chain_num <= 1);
2201         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD,
2202                           rt2x00dev->default_ant.rx_chain_num <= 2);
2203         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2204         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
2205                           rt2x00dev->default_ant.tx_chain_num <= 1);
2206         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD,
2207                           rt2x00dev->default_ant.tx_chain_num <= 2);
2208         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2209
2210         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2211         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2212         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2213
2214         if (rt2x00_rt(rt2x00dev, RT3390)) {
2215                 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
2216                 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
2217         } else {
2218                 if (conf_is_ht40(conf)) {
2219                         calib_tx = drv_data->calibration_bw40;
2220                         calib_rx = drv_data->calibration_bw40;
2221                 } else {
2222                         calib_tx = drv_data->calibration_bw20;
2223                         calib_rx = drv_data->calibration_bw20;
2224                 }
2225         }
2226
2227         rfcsr = rt2800_rfcsr_read(rt2x00dev, 24);
2228         rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
2229         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
2230
2231         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
2232         rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
2233         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2234
2235         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2236         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2237         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2238
2239         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2240         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2241         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2242
2243         usleep_range(1000, 1500);
2244
2245         rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
2246         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2247 }
2248
2249 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
2250                                          struct ieee80211_conf *conf,
2251                                          struct rf_channel *rf,
2252                                          struct channel_info *info)
2253 {
2254         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2255         u8 rfcsr;
2256         u32 reg;
2257
2258         if (rf->channel <= 14) {
2259                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2260                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2261         } else {
2262                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2263                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2264         }
2265
2266         rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
2267         rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
2268
2269         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2270         rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
2271         if (rf->channel <= 14)
2272                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
2273         else
2274                 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
2275         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2276
2277         rfcsr = rt2800_rfcsr_read(rt2x00dev, 5);
2278         if (rf->channel <= 14)
2279                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
2280         else
2281                 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
2282         rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
2283
2284         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2285         if (rf->channel <= 14) {
2286                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
2287                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2288                                   info->default_power1);
2289         } else {
2290                 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
2291                 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
2292                                 (info->default_power1 & 0x3) |
2293                                 ((info->default_power1 & 0xC) << 1));
2294         }
2295         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2296
2297         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
2298         if (rf->channel <= 14) {
2299                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
2300                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2301                                   info->default_power2);
2302         } else {
2303                 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
2304                 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
2305                                 (info->default_power2 & 0x3) |
2306                                 ((info->default_power2 & 0xC) << 1));
2307         }
2308         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
2309
2310         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2311         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2312         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2313         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2314         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2315         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2316         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2317         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2318                 if (rf->channel <= 14) {
2319                         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2320                         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2321                 }
2322                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2323                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2324         } else {
2325                 switch (rt2x00dev->default_ant.tx_chain_num) {
2326                 case 1:
2327                         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2328                 case 2:
2329                         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2330                         break;
2331                 }
2332
2333                 switch (rt2x00dev->default_ant.rx_chain_num) {
2334                 case 1:
2335                         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2336                 case 2:
2337                         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2338                         break;
2339                 }
2340         }
2341         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2342
2343         rfcsr = rt2800_rfcsr_read(rt2x00dev, 23);
2344         rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
2345         rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2346
2347         if (conf_is_ht40(conf)) {
2348                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
2349                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
2350         } else {
2351                 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
2352                 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
2353         }
2354
2355         if (rf->channel <= 14) {
2356                 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
2357                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
2358                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2359                 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
2360                 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
2361                 rfcsr = 0x4c;
2362                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2363                                   drv_data->txmixer_gain_24g);
2364                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2365                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2366                 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
2367                 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
2368                 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
2369                 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
2370                 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
2371                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
2372         } else {
2373                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2374                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
2375                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
2376                 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
2377                 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
2378                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2379                 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
2380                 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
2381                 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
2382                 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
2383                 rfcsr = 0x7a;
2384                 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
2385                                   drv_data->txmixer_gain_5g);
2386                 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
2387                 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
2388                 if (rf->channel <= 64) {
2389                         rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
2390                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
2391                         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
2392                 } else if (rf->channel <= 128) {
2393                         rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
2394                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
2395                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2396                 } else {
2397                         rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
2398                         rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
2399                         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
2400                 }
2401                 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
2402                 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
2403                 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
2404         }
2405
2406         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
2407         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
2408         if (rf->channel <= 14)
2409                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
2410         else
2411                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 0);
2412         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
2413
2414         rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
2415         rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2416         rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2417 }
2418
2419 static void rt2800_config_channel_rf3053(struct rt2x00_dev *rt2x00dev,
2420                                          struct ieee80211_conf *conf,
2421                                          struct rf_channel *rf,
2422                                          struct channel_info *info)
2423 {
2424         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
2425         u8 txrx_agc_fc;
2426         u8 txrx_h20m;
2427         u8 rfcsr;
2428         u8 bbp;
2429         const bool txbf_enabled = false; /* TODO */
2430
2431         /* TODO: use TX{0,1,2}FinePowerControl values from EEPROM */
2432         bbp = rt2800_bbp_read(rt2x00dev, 109);
2433         rt2x00_set_field8(&bbp, BBP109_TX0_POWER, 0);
2434         rt2x00_set_field8(&bbp, BBP109_TX1_POWER, 0);
2435         rt2800_bbp_write(rt2x00dev, 109, bbp);
2436
2437         bbp = rt2800_bbp_read(rt2x00dev, 110);
2438         rt2x00_set_field8(&bbp, BBP110_TX2_POWER, 0);
2439         rt2800_bbp_write(rt2x00dev, 110, bbp);
2440
2441         if (rf->channel <= 14) {
2442                 /* Restore BBP 25 & 26 for 2.4 GHz */
2443                 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
2444                 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
2445         } else {
2446                 /* Hard code BBP 25 & 26 for 5GHz */
2447
2448                 /* Enable IQ Phase correction */
2449                 rt2800_bbp_write(rt2x00dev, 25, 0x09);
2450                 /* Setup IQ Phase correction value */
2451                 rt2800_bbp_write(rt2x00dev, 26, 0xff);
2452         }
2453
2454         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2455         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3 & 0xf);
2456
2457         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2458         rt2x00_set_field8(&rfcsr, RFCSR11_R, (rf->rf2 & 0x3));
2459         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2460
2461         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2462         rt2x00_set_field8(&rfcsr, RFCSR11_PLL_IDOH, 1);
2463         if (rf->channel <= 14)
2464                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 1);
2465         else
2466                 rt2x00_set_field8(&rfcsr, RFCSR11_PLL_MOD, 2);
2467         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2468
2469         rfcsr = rt2800_rfcsr_read(rt2x00dev, 53);
2470         if (rf->channel <= 14) {
2471                 rfcsr = 0;
2472                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2473                                   info->default_power1 & 0x1f);
2474         } else {
2475                 if (rt2x00_is_usb(rt2x00dev))
2476                         rfcsr = 0x40;
2477
2478                 rt2x00_set_field8(&rfcsr, RFCSR53_TX_POWER,
2479                                   ((info->default_power1 & 0x18) << 1) |
2480                                   (info->default_power1 & 7));
2481         }
2482         rt2800_rfcsr_write(rt2x00dev, 53, rfcsr);
2483
2484         rfcsr = rt2800_rfcsr_read(rt2x00dev, 55);
2485         if (rf->channel <= 14) {
2486                 rfcsr = 0;
2487                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2488                                   info->default_power2 & 0x1f);
2489         } else {
2490                 if (rt2x00_is_usb(rt2x00dev))
2491                         rfcsr = 0x40;
2492
2493                 rt2x00_set_field8(&rfcsr, RFCSR55_TX_POWER,
2494                                   ((info->default_power2 & 0x18) << 1) |
2495                                   (info->default_power2 & 7));
2496         }
2497         rt2800_rfcsr_write(rt2x00dev, 55, rfcsr);
2498
2499         rfcsr = rt2800_rfcsr_read(rt2x00dev, 54);
2500         if (rf->channel <= 14) {
2501                 rfcsr = 0;
2502                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2503                                   info->default_power3 & 0x1f);
2504         } else {
2505                 if (rt2x00_is_usb(rt2x00dev))
2506                         rfcsr = 0x40;
2507
2508                 rt2x00_set_field8(&rfcsr, RFCSR54_TX_POWER,
2509                                   ((info->default_power3 & 0x18) << 1) |
2510                                   (info->default_power3 & 7));
2511         }
2512         rt2800_rfcsr_write(rt2x00dev, 54, rfcsr);
2513
2514         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2515         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
2516         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
2517         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2518         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2519         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2520         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2521         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2522         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2523
2524         switch (rt2x00dev->default_ant.tx_chain_num) {
2525         case 3:
2526                 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
2527                 /* fallthrough */
2528         case 2:
2529                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2530                 /* fallthrough */
2531         case 1:
2532                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2533                 break;
2534         }
2535
2536         switch (rt2x00dev->default_ant.rx_chain_num) {
2537         case 3:
2538                 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
2539                 /* fallthrough */
2540         case 2:
2541                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2542                 /* fallthrough */
2543         case 1:
2544                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2545                 break;
2546         }
2547         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2548
2549         rt2800_freq_cal_mode1(rt2x00dev);
2550
2551         if (conf_is_ht40(conf)) {
2552                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw40,
2553                                                 RFCSR24_TX_AGC_FC);
2554                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw40,
2555                                               RFCSR24_TX_H20M);
2556         } else {
2557                 txrx_agc_fc = rt2x00_get_field8(drv_data->calibration_bw20,
2558                                                 RFCSR24_TX_AGC_FC);
2559                 txrx_h20m = rt2x00_get_field8(drv_data->calibration_bw20,
2560                                               RFCSR24_TX_H20M);
2561         }
2562
2563         /* NOTE: the reference driver does not writes the new value
2564          * back to RFCSR 32
2565          */
2566         rfcsr = rt2800_rfcsr_read(rt2x00dev, 32);
2567         rt2x00_set_field8(&rfcsr, RFCSR32_TX_AGC_FC, txrx_agc_fc);
2568
2569         if (rf->channel <= 14)
2570                 rfcsr = 0xa0;
2571         else
2572                 rfcsr = 0x80;
2573         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
2574
2575         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2576         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, txrx_h20m);
2577         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, txrx_h20m);
2578         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2579
2580         /* Band selection */
2581         rfcsr = rt2800_rfcsr_read(rt2x00dev, 36);
2582         if (rf->channel <= 14)
2583                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 1);
2584         else
2585                 rt2x00_set_field8(&rfcsr, RFCSR36_RF_BS, 0);
2586         rt2800_rfcsr_write(rt2x00dev, 36, rfcsr);
2587
2588         rfcsr = rt2800_rfcsr_read(rt2x00dev, 34);
2589         if (rf->channel <= 14)
2590                 rfcsr = 0x3c;
2591         else
2592                 rfcsr = 0x20;
2593         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
2594
2595         rfcsr = rt2800_rfcsr_read(rt2x00dev, 12);
2596         if (rf->channel <= 14)
2597                 rfcsr = 0x1a;
2598         else
2599                 rfcsr = 0x12;
2600         rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
2601
2602         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
2603         if (rf->channel >= 1 && rf->channel <= 14)
2604                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2605         else if (rf->channel >= 36 && rf->channel <= 64)
2606                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2607         else if (rf->channel >= 100 && rf->channel <= 128)
2608                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 2);
2609         else
2610                 rt2x00_set_field8(&rfcsr, RFCSR6_VCO_IC, 1);
2611         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
2612
2613         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
2614         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
2615         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2616
2617         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
2618
2619         if (rf->channel <= 14) {
2620                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
2621                 rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
2622         } else {
2623                 rt2800_rfcsr_write(rt2x00dev, 10, 0xd8);
2624                 rt2800_rfcsr_write(rt2x00dev, 13, 0x23);
2625         }
2626
2627         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2628         rt2x00_set_field8(&rfcsr, RFCSR51_BITS01, 1);
2629         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2630
2631         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
2632         if (rf->channel <= 14) {
2633                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 5);
2634                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 3);
2635         } else {
2636                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, 4);
2637                 rt2x00_set_field8(&rfcsr, RFCSR51_BITS57, 2);
2638         }
2639         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
2640
2641         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2642         if (rf->channel <= 14)
2643                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 3);
2644         else
2645                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_LO1_IC, 2);
2646
2647         if (txbf_enabled)
2648                 rt2x00_set_field8(&rfcsr, RFCSR49_TX_DIV, 1);
2649
2650         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2651
2652         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2653         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO1_EN, 0);
2654         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2655
2656         rfcsr = rt2800_rfcsr_read(rt2x00dev, 57);
2657         if (rf->channel <= 14)
2658                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x1b);
2659         else
2660                 rt2x00_set_field8(&rfcsr, RFCSR57_DRV_CC, 0x0f);
2661         rt2800_rfcsr_write(rt2x00dev, 57, rfcsr);
2662
2663         if (rf->channel <= 14) {
2664                 rt2800_rfcsr_write(rt2x00dev, 44, 0x93);
2665                 rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
2666         } else {
2667                 rt2800_rfcsr_write(rt2x00dev, 44, 0x9b);
2668                 rt2800_rfcsr_write(rt2x00dev, 52, 0x05);
2669         }
2670
2671         /* Initiate VCO calibration */
2672         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
2673         if (rf->channel <= 14) {
2674                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2675         } else {
2676                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT1, 1);
2677                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT2, 1);
2678                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT3, 1);
2679                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT4, 1);
2680                 rt2x00_set_field8(&rfcsr, RFCSR3_BIT5, 1);
2681                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
2682         }
2683         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2684
2685         if (rf->channel >= 1 && rf->channel <= 14) {
2686                 rfcsr = 0x23;
2687                 if (txbf_enabled)
2688                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2689                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2690
2691                 rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
2692         } else if (rf->channel >= 36 && rf->channel <= 64) {
2693                 rfcsr = 0x36;
2694                 if (txbf_enabled)
2695                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2696                 rt2800_rfcsr_write(rt2x00dev, 39, 0x36);
2697
2698                 rt2800_rfcsr_write(rt2x00dev, 45, 0xeb);
2699         } else if (rf->channel >= 100 && rf->channel <= 128) {
2700                 rfcsr = 0x32;
2701                 if (txbf_enabled)
2702                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2703                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2704
2705                 rt2800_rfcsr_write(rt2x00dev, 45, 0xb3);
2706         } else {
2707                 rfcsr = 0x30;
2708                 if (txbf_enabled)
2709                         rt2x00_set_field8(&rfcsr, RFCSR39_RX_DIV, 1);
2710                 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
2711
2712                 rt2800_rfcsr_write(rt2x00dev, 45, 0x9b);
2713         }
2714 }
2715
2716 #define POWER_BOUND             0x27
2717 #define POWER_BOUND_5G          0x2b
2718
2719 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
2720                                          struct ieee80211_conf *conf,
2721                                          struct rf_channel *rf,
2722                                          struct channel_info *info)
2723 {
2724         u8 rfcsr;
2725
2726         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2727         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2728         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2729         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2730         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2731
2732         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2733         if (info->default_power1 > POWER_BOUND)
2734                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2735         else
2736                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2737         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2738
2739         rt2800_freq_cal_mode1(rt2x00dev);
2740
2741         if (rf->channel <= 14) {
2742                 if (rf->channel == 6)
2743                         rt2800_bbp_write(rt2x00dev, 68, 0x0c);
2744                 else
2745                         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
2746
2747                 if (rf->channel >= 1 && rf->channel <= 6)
2748                         rt2800_bbp_write(rt2x00dev, 59, 0x0f);
2749                 else if (rf->channel >= 7 && rf->channel <= 11)
2750                         rt2800_bbp_write(rt2x00dev, 59, 0x0e);
2751                 else if (rf->channel >= 12 && rf->channel <= 14)
2752                         rt2800_bbp_write(rt2x00dev, 59, 0x0d);
2753         }
2754 }
2755
2756 static void rt2800_config_channel_rf3322(struct rt2x00_dev *rt2x00dev,
2757                                          struct ieee80211_conf *conf,
2758                                          struct rf_channel *rf,
2759                                          struct channel_info *info)
2760 {
2761         u8 rfcsr;
2762
2763         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2764         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2765
2766         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
2767         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
2768         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
2769
2770         if (info->default_power1 > POWER_BOUND)
2771                 rt2800_rfcsr_write(rt2x00dev, 47, POWER_BOUND);
2772         else
2773                 rt2800_rfcsr_write(rt2x00dev, 47, info->default_power1);
2774
2775         if (info->default_power2 > POWER_BOUND)
2776                 rt2800_rfcsr_write(rt2x00dev, 48, POWER_BOUND);
2777         else
2778                 rt2800_rfcsr_write(rt2x00dev, 48, info->default_power2);
2779
2780         rt2800_freq_cal_mode1(rt2x00dev);
2781
2782         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2783         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2784         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2785
2786         if ( rt2x00dev->default_ant.tx_chain_num == 2 )
2787                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2788         else
2789                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
2790
2791         if ( rt2x00dev->default_ant.rx_chain_num == 2 )
2792                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2793         else
2794                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
2795
2796         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
2797         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
2798
2799         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2800
2801         rt2800_rfcsr_write(rt2x00dev, 31, 80);
2802 }
2803
2804 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
2805                                          struct ieee80211_conf *conf,
2806                                          struct rf_channel *rf,
2807                                          struct channel_info *info)
2808 {
2809         u8 rfcsr;
2810
2811         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
2812         rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
2813         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2814         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
2815         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2816
2817         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
2818         if (info->default_power1 > POWER_BOUND)
2819                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2820         else
2821                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2822         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2823
2824         if (rt2x00_rt(rt2x00dev, RT5392)) {
2825                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
2826                 if (info->default_power2 > POWER_BOUND)
2827                         rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2828                 else
2829                         rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2830                                           info->default_power2);
2831                 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2832         }
2833
2834         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
2835         if (rt2x00_rt(rt2x00dev, RT5392)) {
2836                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2837                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2838         }
2839         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2840         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2841         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2842         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2843         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2844
2845         rt2800_freq_cal_mode1(rt2x00dev);
2846
2847         if (rf->channel <= 14) {
2848                 int idx = rf->channel-1;
2849
2850                 if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
2851                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2852                                 /* r55/r59 value array of channel 1~14 */
2853                                 static const char r55_bt_rev[] = {0x83, 0x83,
2854                                         0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2855                                         0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2856                                 static const char r59_bt_rev[] = {0x0e, 0x0e,
2857                                         0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2858                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2859
2860                                 rt2800_rfcsr_write(rt2x00dev, 55,
2861                                                    r55_bt_rev[idx]);
2862                                 rt2800_rfcsr_write(rt2x00dev, 59,
2863                                                    r59_bt_rev[idx]);
2864                         } else {
2865                                 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2866                                         0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2867                                         0x88, 0x88, 0x86, 0x85, 0x84};
2868
2869                                 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2870                         }
2871                 } else {
2872                         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2873                                 static const char r55_nonbt_rev[] = {0x23, 0x23,
2874                                         0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2875                                         0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2876                                 static const char r59_nonbt_rev[] = {0x07, 0x07,
2877                                         0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2878                                         0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2879
2880                                 rt2800_rfcsr_write(rt2x00dev, 55,
2881                                                    r55_nonbt_rev[idx]);
2882                                 rt2800_rfcsr_write(rt2x00dev, 59,
2883                                                    r59_nonbt_rev[idx]);
2884                         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2885                                    rt2x00_rt(rt2x00dev, RT5392) ||
2886                                    rt2x00_rt(rt2x00dev, RT6352)) {
2887                                 static const char r59_non_bt[] = {0x8f, 0x8f,
2888                                         0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2889                                         0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2890
2891                                 rt2800_rfcsr_write(rt2x00dev, 59,
2892                                                    r59_non_bt[idx]);
2893                         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
2894                                 static const char r59_non_bt[] = {0x0b, 0x0b,
2895                                         0x0b, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a,
2896                                         0x0a, 0x09, 0x08, 0x07, 0x07, 0x06};
2897
2898                                 rt2800_rfcsr_write(rt2x00dev, 59,
2899                                                    r59_non_bt[idx]);
2900                         }
2901                 }
2902         }
2903 }
2904
2905 static void rt2800_config_channel_rf55xx(struct rt2x00_dev *rt2x00dev,
2906                                          struct ieee80211_conf *conf,
2907                                          struct rf_channel *rf,
2908                                          struct channel_info *info)
2909 {
2910         u8 rfcsr, ep_reg;
2911         u32 reg;
2912         int power_bound;
2913
2914         /* TODO */
2915         const bool is_11b = false;
2916         const bool is_type_ep = false;
2917
2918         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
2919         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL,
2920                            (rf->channel > 14 || conf_is_ht40(conf)) ? 5 : 0);
2921         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
2922
2923         /* Order of values on rf_channel entry: N, K, mod, R */
2924         rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1 & 0xff);
2925
2926         rfcsr = rt2800_rfcsr_read(rt2x00dev,  9);
2927         rt2x00_set_field8(&rfcsr, RFCSR9_K, rf->rf2 & 0xf);
2928         rt2x00_set_field8(&rfcsr, RFCSR9_N, (rf->rf1 & 0x100) >> 8);
2929         rt2x00_set_field8(&rfcsr, RFCSR9_MOD, ((rf->rf3 - 8) & 0x4) >> 2);
2930         rt2800_rfcsr_write(rt2x00dev, 9, rfcsr);
2931
2932         rfcsr = rt2800_rfcsr_read(rt2x00dev, 11);
2933         rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf4 - 1);
2934         rt2x00_set_field8(&rfcsr, RFCSR11_MOD, (rf->rf3 - 8) & 0x3);
2935         rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2936
2937         if (rf->channel <= 14) {
2938                 rt2800_rfcsr_write(rt2x00dev, 10, 0x90);
2939                 /* FIXME: RF11 owerwrite ? */
2940                 rt2800_rfcsr_write(rt2x00dev, 11, 0x4A);
2941                 rt2800_rfcsr_write(rt2x00dev, 12, 0x52);
2942                 rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
2943                 rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
2944                 rt2800_rfcsr_write(rt2x00dev, 24, 0x4A);
2945                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
2946                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2947                 rt2800_rfcsr_write(rt2x00dev, 36, 0x80);
2948                 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
2949                 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
2950                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1B);
2951                 rt2800_rfcsr_write(rt2x00dev, 40, 0x0D);
2952                 rt2800_rfcsr_write(rt2x00dev, 41, 0x9B);
2953                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD5);
2954                 rt2800_rfcsr_write(rt2x00dev, 43, 0x72);
2955                 rt2800_rfcsr_write(rt2x00dev, 44, 0x0E);
2956                 rt2800_rfcsr_write(rt2x00dev, 45, 0xA2);
2957                 rt2800_rfcsr_write(rt2x00dev, 46, 0x6B);
2958                 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
2959                 rt2800_rfcsr_write(rt2x00dev, 51, 0x3E);
2960                 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
2961                 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
2962                 rt2800_rfcsr_write(rt2x00dev, 56, 0xA1);
2963                 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
2964                 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
2965                 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
2966                 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
2967                 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
2968
2969                 /* TODO RF27 <- tssi */
2970
2971                 rfcsr = rf->channel <= 10 ? 0x07 : 0x06;
2972                 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
2973                 rt2800_rfcsr_write(rt2x00dev, 59, rfcsr);
2974
2975                 if (is_11b) {
2976                         /* CCK */
2977                         rt2800_rfcsr_write(rt2x00dev, 31, 0xF8);
2978                         rt2800_rfcsr_write(rt2x00dev, 32, 0xC0);
2979                         if (is_type_ep)
2980                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06);
2981                         else
2982                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x47);
2983                 } else {
2984                         /* OFDM */
2985                         if (is_type_ep)
2986                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x03);
2987                         else
2988                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
2989                 }
2990
2991                 power_bound = POWER_BOUND;
2992                 ep_reg = 0x2;
2993         } else {
2994                 rt2800_rfcsr_write(rt2x00dev, 10, 0x97);
2995                 /* FIMXE: RF11 overwrite */
2996                 rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
2997                 rt2800_rfcsr_write(rt2x00dev, 25, 0xBF);
2998                 rt2800_rfcsr_write(rt2x00dev, 27, 0x42);
2999                 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3000                 rt2800_rfcsr_write(rt2x00dev, 37, 0x04);
3001                 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3002                 rt2800_rfcsr_write(rt2x00dev, 40, 0x42);
3003                 rt2800_rfcsr_write(rt2x00dev, 41, 0xBB);
3004                 rt2800_rfcsr_write(rt2x00dev, 42, 0xD7);
3005                 rt2800_rfcsr_write(rt2x00dev, 45, 0x41);
3006                 rt2800_rfcsr_write(rt2x00dev, 48, 0x00);
3007                 rt2800_rfcsr_write(rt2x00dev, 57, 0x77);
3008                 rt2800_rfcsr_write(rt2x00dev, 60, 0x05);
3009                 rt2800_rfcsr_write(rt2x00dev, 61, 0x01);
3010
3011                 /* TODO RF27 <- tssi */
3012
3013                 if (rf->channel >= 36 && rf->channel <= 64) {
3014
3015                         rt2800_rfcsr_write(rt2x00dev, 12, 0x2E);
3016                         rt2800_rfcsr_write(rt2x00dev, 13, 0x22);
3017                         rt2800_rfcsr_write(rt2x00dev, 22, 0x60);
3018                         rt2800_rfcsr_write(rt2x00dev, 23, 0x7F);
3019                         if (rf->channel <= 50)
3020                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x09);
3021                         else if (rf->channel >= 52)
3022                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x07);
3023                         rt2800_rfcsr_write(rt2x00dev, 39, 0x1C);
3024                         rt2800_rfcsr_write(rt2x00dev, 43, 0x5B);
3025                         rt2800_rfcsr_write(rt2x00dev, 44, 0X40);
3026                         rt2800_rfcsr_write(rt2x00dev, 46, 0X00);
3027                         rt2800_rfcsr_write(rt2x00dev, 51, 0xFE);
3028                         rt2800_rfcsr_write(rt2x00dev, 52, 0x0C);
3029                         rt2800_rfcsr_write(rt2x00dev, 54, 0xF8);
3030                         if (rf->channel <= 50) {
3031                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x06),
3032                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xD3);
3033                         } else if (rf->channel >= 52) {
3034                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x04);
3035                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3036                         }
3037
3038                         rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3039                         rt2800_rfcsr_write(rt2x00dev, 59, 0x7F);
3040                         rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3041
3042                 } else if (rf->channel >= 100 && rf->channel <= 165) {
3043
3044                         rt2800_rfcsr_write(rt2x00dev, 12, 0x0E);
3045                         rt2800_rfcsr_write(rt2x00dev, 13, 0x42);
3046                         rt2800_rfcsr_write(rt2x00dev, 22, 0x40);
3047                         if (rf->channel <= 153) {
3048                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x3C);
3049                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x06);
3050                         } else if (rf->channel >= 155) {
3051                                 rt2800_rfcsr_write(rt2x00dev, 23, 0x38);
3052                                 rt2800_rfcsr_write(rt2x00dev, 24, 0x05);
3053                         }
3054                         if (rf->channel <= 138) {
3055                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x1A);
3056                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x3B);
3057                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x20);
3058                                 rt2800_rfcsr_write(rt2x00dev, 46, 0x18);
3059                         } else if (rf->channel >= 140) {
3060                                 rt2800_rfcsr_write(rt2x00dev, 39, 0x18);
3061                                 rt2800_rfcsr_write(rt2x00dev, 43, 0x1B);
3062                                 rt2800_rfcsr_write(rt2x00dev, 44, 0x10);
3063                                 rt2800_rfcsr_write(rt2x00dev, 46, 0X08);
3064                         }
3065                         if (rf->channel <= 124)
3066                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xFC);
3067                         else if (rf->channel >= 126)
3068                                 rt2800_rfcsr_write(rt2x00dev, 51, 0xEC);
3069                         if (rf->channel <= 138)
3070                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3071                         else if (rf->channel >= 140)
3072                                 rt2800_rfcsr_write(rt2x00dev, 52, 0x06);
3073                         rt2800_rfcsr_write(rt2x00dev, 54, 0xEB);
3074                         if (rf->channel <= 138)
3075                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x01);
3076                         else if (rf->channel >= 140)
3077                                 rt2800_rfcsr_write(rt2x00dev, 55, 0x00);
3078                         if (rf->channel <= 128)
3079                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xBB);
3080                         else if (rf->channel >= 130)
3081                                 rt2800_rfcsr_write(rt2x00dev, 56, 0xAB);
3082                         if (rf->channel <= 116)
3083                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x1D);
3084                         else if (rf->channel >= 118)
3085                                 rt2800_rfcsr_write(rt2x00dev, 58, 0x15);
3086                         if (rf->channel <= 138)
3087                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x3F);
3088                         else if (rf->channel >= 140)
3089                                 rt2800_rfcsr_write(rt2x00dev, 59, 0x7C);
3090                         if (rf->channel <= 116)
3091                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x1D);
3092                         else if (rf->channel >= 118)
3093                                 rt2800_rfcsr_write(rt2x00dev, 62, 0x15);
3094                 }
3095
3096                 power_bound = POWER_BOUND_5G;
3097                 ep_reg = 0x3;
3098         }
3099
3100         rfcsr = rt2800_rfcsr_read(rt2x00dev, 49);
3101         if (info->default_power1 > power_bound)
3102                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, power_bound);
3103         else
3104                 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
3105         if (is_type_ep)
3106                 rt2x00_set_field8(&rfcsr, RFCSR49_EP, ep_reg);
3107         rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
3108
3109         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
3110         if (info->default_power2 > power_bound)
3111                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, power_bound);
3112         else
3113                 rt2x00_set_field8(&rfcsr, RFCSR50_TX, info->default_power2);
3114         if (is_type_ep)
3115                 rt2x00_set_field8(&rfcsr, RFCSR50_EP, ep_reg);
3116         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
3117
3118         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3119         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
3120         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
3121
3122         rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD,
3123                           rt2x00dev->default_ant.tx_chain_num >= 1);
3124         rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
3125                           rt2x00dev->default_ant.tx_chain_num == 2);
3126         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
3127
3128         rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD,
3129                           rt2x00dev->default_ant.rx_chain_num >= 1);
3130         rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
3131                           rt2x00dev->default_ant.rx_chain_num == 2);
3132         rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
3133
3134         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3135         rt2800_rfcsr_write(rt2x00dev, 6, 0xe4);
3136
3137         if (conf_is_ht40(conf))
3138                 rt2800_rfcsr_write(rt2x00dev, 30, 0x16);
3139         else
3140                 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3141
3142         if (!is_11b) {
3143                 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3144                 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3145         }
3146
3147         /* TODO proper frequency adjustment */
3148         rt2800_freq_cal_mode1(rt2x00dev);
3149
3150         /* TODO merge with others */
3151         rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3152         rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3153         rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3154
3155         /* BBP settings */
3156         rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3157         rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3158         rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3159
3160         rt2800_bbp_write(rt2x00dev, 79, (rf->channel <= 14) ? 0x1C : 0x18);
3161         rt2800_bbp_write(rt2x00dev, 80, (rf->channel <= 14) ? 0x0E : 0x08);
3162         rt2800_bbp_write(rt2x00dev, 81, (rf->channel <= 14) ? 0x3A : 0x38);
3163         rt2800_bbp_write(rt2x00dev, 82, (rf->channel <= 14) ? 0x62 : 0x92);
3164
3165         /* GLRT band configuration */
3166         rt2800_bbp_write(rt2x00dev, 195, 128);
3167         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0xE0 : 0xF0);
3168         rt2800_bbp_write(rt2x00dev, 195, 129);
3169         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x1F : 0x1E);
3170         rt2800_bbp_write(rt2x00dev, 195, 130);
3171         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x38 : 0x28);
3172         rt2800_bbp_write(rt2x00dev, 195, 131);
3173         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x32 : 0x20);
3174         rt2800_bbp_write(rt2x00dev, 195, 133);
3175         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x28 : 0x7F);
3176         rt2800_bbp_write(rt2x00dev, 195, 124);
3177         rt2800_bbp_write(rt2x00dev, 196, (rf->channel <= 14) ? 0x19 : 0x7F);
3178 }
3179
3180 static void rt2800_config_channel_rf7620(struct rt2x00_dev *rt2x00dev,
3181                                          struct ieee80211_conf *conf,
3182                                          struct rf_channel *rf,
3183                                          struct channel_info *info)
3184 {
3185         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3186         u8 rx_agc_fc, tx_agc_fc;
3187         u8 rfcsr;
3188
3189         /* Frequeny plan setting */
3190         /* Rdiv setting (set 0x03 if Xtal==20)
3191          * R13[1:0]
3192          */
3193         rfcsr = rt2800_rfcsr_read(rt2x00dev, 13);
3194         rt2x00_set_field8(&rfcsr, RFCSR13_RDIV_MT7620,
3195                           rt2800_clk_is_20mhz(rt2x00dev) ? 3 : 0);
3196         rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
3197
3198         /* N setting
3199          * R20[7:0] in rf->rf1
3200          * R21[0] always 0
3201          */
3202         rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
3203         rfcsr = (rf->rf1 & 0x00ff);
3204         rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
3205
3206         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3207         rt2x00_set_field8(&rfcsr, RFCSR21_BIT1, 0);
3208         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3209
3210         /* K setting (always 0)
3211          * R16[3:0] (RF PLL freq selection)
3212          */
3213         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3214         rt2x00_set_field8(&rfcsr, RFCSR16_RF_PLL_FREQ_SEL_MT7620, 0);
3215         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3216
3217         /* D setting (always 0)
3218          * R22[2:0] (D=15, R22[2:0]=<111>)
3219          */
3220         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
3221         rt2x00_set_field8(&rfcsr, RFCSR22_FREQPLAN_D_MT7620, 0);
3222         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3223
3224         /* Ksd setting
3225          * Ksd: R17<7:0> in rf->rf2
3226          *      R18<7:0> in rf->rf3
3227          *      R19<1:0> in rf->rf4
3228          */
3229         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
3230         rfcsr = rf->rf2;
3231         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
3232
3233         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
3234         rfcsr = rf->rf3;
3235         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
3236
3237         rfcsr = rt2800_rfcsr_read(rt2x00dev, 19);
3238         rt2x00_set_field8(&rfcsr, RFCSR19_K, rf->rf4);
3239         rt2800_rfcsr_write(rt2x00dev, 19, rfcsr);
3240
3241         /* Default: XO=20MHz , SDM mode */
3242         rfcsr = rt2800_rfcsr_read(rt2x00dev, 16);
3243         rt2x00_set_field8(&rfcsr, RFCSR16_SDM_MODE_MT7620, 0x80);
3244         rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
3245
3246         rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
3247         rt2x00_set_field8(&rfcsr, RFCSR21_BIT8, 1);
3248         rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
3249
3250         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
3251         rt2x00_set_field8(&rfcsr, RFCSR1_TX2_EN_MT7620,
3252                           rt2x00dev->default_ant.tx_chain_num != 1);
3253         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
3254
3255         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
3256         rt2x00_set_field8(&rfcsr, RFCSR2_TX2_EN_MT7620,
3257                           rt2x00dev->default_ant.tx_chain_num != 1);
3258         rt2x00_set_field8(&rfcsr, RFCSR2_RX2_EN_MT7620,
3259                           rt2x00dev->default_ant.rx_chain_num != 1);
3260         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3261
3262         rfcsr = rt2800_rfcsr_read(rt2x00dev, 42);
3263         rt2x00_set_field8(&rfcsr, RFCSR42_TX2_EN_MT7620,
3264                           rt2x00dev->default_ant.tx_chain_num != 1);
3265         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
3266
3267         /* RF for DC Cal BW */
3268         if (conf_is_ht40(conf)) {
3269                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
3270                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
3271                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
3272                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
3273                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
3274         } else {
3275                 rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x20);
3276                 rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x20);
3277                 rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x00);
3278                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x20);
3279                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x20);
3280         }
3281
3282         if (conf_is_ht40(conf)) {
3283                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x08);
3284                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x08);
3285         } else {
3286                 rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x28);
3287                 rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x28);
3288         }
3289
3290         rfcsr = rt2800_rfcsr_read(rt2x00dev, 28);
3291         rt2x00_set_field8(&rfcsr, RFCSR28_CH11_HT40,
3292                           conf_is_ht40(conf) && (rf->channel == 11));
3293         rt2800_rfcsr_write(rt2x00dev, 28, rfcsr);
3294
3295         if (!test_bit(DEVICE_STATE_SCANNING, &rt2x00dev->flags)) {
3296                 if (conf_is_ht40(conf)) {
3297                         rx_agc_fc = drv_data->rx_calibration_bw40;
3298                         tx_agc_fc = drv_data->tx_calibration_bw40;
3299                 } else {
3300                         rx_agc_fc = drv_data->rx_calibration_bw20;
3301                         tx_agc_fc = drv_data->tx_calibration_bw20;
3302                 }
3303                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
3304                 rfcsr &= (~0x3F);
3305                 rfcsr |= rx_agc_fc;
3306                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rfcsr);
3307                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
3308                 rfcsr &= (~0x3F);
3309                 rfcsr |= rx_agc_fc;
3310                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rfcsr);
3311                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 6);
3312                 rfcsr &= (~0x3F);
3313                 rfcsr |= rx_agc_fc;
3314                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 6, rfcsr);
3315                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 7);
3316                 rfcsr &= (~0x3F);
3317                 rfcsr |= rx_agc_fc;
3318                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 7, rfcsr);
3319
3320                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
3321                 rfcsr &= (~0x3F);
3322                 rfcsr |= tx_agc_fc;
3323                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rfcsr);
3324                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
3325                 rfcsr &= (~0x3F);
3326                 rfcsr |= tx_agc_fc;
3327                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rfcsr);
3328                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 58);
3329                 rfcsr &= (~0x3F);
3330                 rfcsr |= tx_agc_fc;
3331                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 58, rfcsr);
3332                 rfcsr = rt2800_rfcsr_read_bank(rt2x00dev, 7, 59);
3333                 rfcsr &= (~0x3F);
3334                 rfcsr |= tx_agc_fc;
3335                 rt2800_rfcsr_write_bank(rt2x00dev, 7, 59, rfcsr);
3336         }
3337 }
3338
3339 static void rt2800_config_alc(struct rt2x00_dev *rt2x00dev,
3340                               struct ieee80211_channel *chan,
3341                               int power_level) {
3342         u16 eeprom, target_power, max_power;
3343         u32 mac_sys_ctrl, mac_status;
3344         u32 reg;
3345         u8 bbp;
3346         int i;
3347
3348         /* hardware unit is 0.5dBm, limited to 23.5dBm */
3349         power_level *= 2;
3350         if (power_level > 0x2f)
3351                 power_level = 0x2f;
3352
3353         max_power = chan->max_power * 2;
3354         if (max_power > 0x2f)
3355                 max_power = 0x2f;
3356
3357         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_0);
3358         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, power_level);
3359         rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, power_level);
3360         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_0, max_power);
3361         rt2x00_set_field32(&reg, TX_ALC_CFG_0_LIMIT_1, max_power);
3362
3363         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3364         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_INTERNAL_TX_ALC)) {
3365                 /* init base power by eeprom target power */
3366                 target_power = rt2800_eeprom_read(rt2x00dev,
3367                                                   EEPROM_TXPOWER_INIT);
3368                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_0, target_power);
3369                 rt2x00_set_field32(&reg, TX_ALC_CFG_0_CH_INIT_1, target_power);
3370         }
3371         rt2800_register_write(rt2x00dev, TX_ALC_CFG_0, reg);
3372
3373         reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
3374         rt2x00_set_field32(&reg, TX_ALC_CFG_1_TX_TEMP_COMP, 0);
3375         rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
3376
3377         /* Save MAC SYS CTRL registers */
3378         mac_sys_ctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
3379         /* Disable Tx/Rx */
3380         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0);
3381         /* Check MAC Tx/Rx idle */
3382         for (i = 0; i < 10000; i++) {
3383                 mac_status = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
3384                 if (mac_status & 0x3)
3385                         usleep_range(50, 200);
3386                 else
3387                         break;
3388         }
3389
3390         if (i == 10000)
3391                 rt2x00_warn(rt2x00dev, "Wait MAC Status to MAX !!!\n");
3392
3393         if (chan->center_freq > 2457) {
3394                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3395                 bbp = 0x40;
3396                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3397                 rt2800_rfcsr_write(rt2x00dev, 39, 0);
3398                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3399                         rt2800_rfcsr_write(rt2x00dev, 42, 0xfb);
3400                 else
3401                         rt2800_rfcsr_write(rt2x00dev, 42, 0x7b);
3402         } else {
3403                 bbp = rt2800_bbp_read(rt2x00dev, 30);
3404                 bbp = 0x1f;
3405                 rt2800_bbp_write(rt2x00dev, 30, bbp);
3406                 rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
3407                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev))
3408                         rt2800_rfcsr_write(rt2x00dev, 42, 0xdb);
3409                 else
3410                         rt2800_rfcsr_write(rt2x00dev, 42, 0x5b);
3411         }
3412         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, mac_sys_ctrl);
3413
3414         rt2800_vco_calibration(rt2x00dev);
3415 }
3416
3417 static void rt2800_bbp_write_with_rx_chain(struct rt2x00_dev *rt2x00dev,
3418                                            const unsigned int word,
3419                                            const u8 value)
3420 {
3421         u8 chain, reg;
3422
3423         for (chain = 0; chain < rt2x00dev->default_ant.rx_chain_num; chain++) {
3424                 reg = rt2800_bbp_read(rt2x00dev, 27);
3425                 rt2x00_set_field8(&reg,  BBP27_RX_CHAIN_SEL, chain);
3426                 rt2800_bbp_write(rt2x00dev, 27, reg);
3427
3428                 rt2800_bbp_write(rt2x00dev, word, value);
3429         }
3430 }
3431
3432 static void rt2800_iq_calibrate(struct rt2x00_dev *rt2x00dev, int channel)
3433 {
3434         u8 cal;
3435
3436         /* TX0 IQ Gain */
3437         rt2800_bbp_write(rt2x00dev, 158, 0x2c);
3438         if (channel <= 14)
3439                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX0_2G);
3440         else if (channel >= 36 && channel <= 64)
3441                 cal = rt2x00_eeprom_byte(rt2x00dev,
3442                                          EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G);
3443         else if (channel >= 100 && channel <= 138)
3444                 cal = rt2x00_eeprom_byte(rt2x00dev,
3445                                          EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G);
3446         else if (channel >= 140 && channel <= 165)
3447                 cal = rt2x00_eeprom_byte(rt2x00dev,
3448                                          EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G);
3449         else
3450                 cal = 0;
3451         rt2800_bbp_write(rt2x00dev, 159, cal);
3452
3453         /* TX0 IQ Phase */
3454         rt2800_bbp_write(rt2x00dev, 158, 0x2d);
3455         if (channel <= 14)
3456                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX0_2G);
3457         else if (channel >= 36 && channel <= 64)
3458                 cal = rt2x00_eeprom_byte(rt2x00dev,
3459                                          EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G);
3460         else if (channel >= 100 && channel <= 138)
3461                 cal = rt2x00_eeprom_byte(rt2x00dev,
3462                                          EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G);
3463         else if (channel >= 140 && channel <= 165)
3464                 cal = rt2x00_eeprom_byte(rt2x00dev,
3465                                          EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G);
3466         else
3467                 cal = 0;
3468         rt2800_bbp_write(rt2x00dev, 159, cal);
3469
3470         /* TX1 IQ Gain */
3471         rt2800_bbp_write(rt2x00dev, 158, 0x4a);
3472         if (channel <= 14)
3473                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_GAIN_CAL_TX1_2G);
3474         else if (channel >= 36 && channel <= 64)
3475                 cal = rt2x00_eeprom_byte(rt2x00dev,
3476                                          EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G);
3477         else if (channel >= 100 && channel <= 138)
3478                 cal = rt2x00_eeprom_byte(rt2x00dev,
3479                                          EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G);
3480         else if (channel >= 140 && channel <= 165)
3481                 cal = rt2x00_eeprom_byte(rt2x00dev,
3482                                          EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G);
3483         else
3484                 cal = 0;
3485         rt2800_bbp_write(rt2x00dev, 159, cal);
3486
3487         /* TX1 IQ Phase */
3488         rt2800_bbp_write(rt2x00dev, 158, 0x4b);
3489         if (channel <= 14)
3490                 cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_IQ_PHASE_CAL_TX1_2G);
3491         else if (channel >= 36 && channel <= 64)
3492                 cal = rt2x00_eeprom_byte(rt2x00dev,
3493                                          EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G);
3494         else if (channel >= 100 && channel <= 138)
3495                 cal = rt2x00_eeprom_byte(rt2x00dev,
3496                                          EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G);
3497         else if (channel >= 140 && channel <= 165)
3498                 cal = rt2x00_eeprom_byte(rt2x00dev,
3499                                          EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G);
3500         else
3501                 cal = 0;
3502         rt2800_bbp_write(rt2x00dev, 159, cal);
3503
3504         /* FIXME: possible RX0, RX1 callibration ? */
3505
3506         /* RF IQ compensation control */
3507         rt2800_bbp_write(rt2x00dev, 158, 0x04);
3508         cal = rt2x00_eeprom_byte(rt2x00dev, EEPROM_RF_IQ_COMPENSATION_CONTROL);
3509         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3510
3511         /* RF IQ imbalance compensation control */
3512         rt2800_bbp_write(rt2x00dev, 158, 0x03);
3513         cal = rt2x00_eeprom_byte(rt2x00dev,
3514                                  EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL);
3515         rt2800_bbp_write(rt2x00dev, 159, cal != 0xff ? cal : 0);
3516 }
3517
3518 static char rt2800_txpower_to_dev(struct rt2x00_dev *rt2x00dev,
3519                                   unsigned int channel,
3520                                   char txpower)
3521 {
3522         if (rt2x00_rt(rt2x00dev, RT3593))
3523                 txpower = rt2x00_get_field8(txpower, EEPROM_TXPOWER_ALC);
3524
3525         if (channel <= 14)
3526                 return clamp_t(char, txpower, MIN_G_TXPOWER, MAX_G_TXPOWER);
3527
3528         if (rt2x00_rt(rt2x00dev, RT3593))
3529                 return clamp_t(char, txpower, MIN_A_TXPOWER_3593,
3530                                MAX_A_TXPOWER_3593);
3531         else
3532                 return clamp_t(char, txpower, MIN_A_TXPOWER, MAX_A_TXPOWER);
3533 }
3534
3535 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
3536                                   struct ieee80211_conf *conf,
3537                                   struct rf_channel *rf,
3538                                   struct channel_info *info)
3539 {
3540         u32 reg;
3541         u32 tx_pin;
3542         u8 bbp, rfcsr;
3543
3544         info->default_power1 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3545                                                      info->default_power1);
3546         info->default_power2 = rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3547                                                      info->default_power2);
3548         if (rt2x00dev->default_ant.tx_chain_num > 2)
3549                 info->default_power3 =
3550                         rt2800_txpower_to_dev(rt2x00dev, rf->channel,
3551                                               info->default_power3);
3552
3553         switch (rt2x00dev->chip.rf) {
3554         case RF2020:
3555         case RF3020:
3556         case RF3021:
3557         case RF3022:
3558         case RF3320:
3559                 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
3560                 break;
3561         case RF3052:
3562                 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
3563                 break;
3564         case RF3053:
3565                 rt2800_config_channel_rf3053(rt2x00dev, conf, rf, info);
3566                 break;
3567         case RF3290:
3568                 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
3569                 break;
3570         case RF3322:
3571                 rt2800_config_channel_rf3322(rt2x00dev, conf, rf, info);
3572                 break;
3573         case RF3070:
3574         case RF5350:
3575         case RF5360:
3576         case RF5362:
3577         case RF5370:
3578         case RF5372:
3579         case RF5390:
3580         case RF5392:
3581                 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
3582                 break;
3583         case RF5592:
3584                 rt2800_config_channel_rf55xx(rt2x00dev, conf, rf, info);
3585                 break;
3586         case RF7620:
3587                 rt2800_config_channel_rf7620(rt2x00dev, conf, rf, info);
3588                 break;
3589         default:
3590                 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
3591         }
3592
3593         if (rt2x00_rf(rt2x00dev, RF3070) ||
3594             rt2x00_rf(rt2x00dev, RF3290) ||
3595             rt2x00_rf(rt2x00dev, RF3322) ||
3596             rt2x00_rf(rt2x00dev, RF5350) ||
3597             rt2x00_rf(rt2x00dev, RF5360) ||
3598             rt2x00_rf(rt2x00dev, RF5362) ||
3599             rt2x00_rf(rt2x00dev, RF5370) ||
3600             rt2x00_rf(rt2x00dev, RF5372) ||
3601             rt2x00_rf(rt2x00dev, RF5390) ||
3602             rt2x00_rf(rt2x00dev, RF5392)) {
3603                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
3604                 if (rt2x00_rf(rt2x00dev, RF3322)) {
3605                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_TX_H20M,
3606                                           conf_is_ht40(conf));
3607                         rt2x00_set_field8(&rfcsr, RF3322_RFCSR30_RX_H20M,
3608                                           conf_is_ht40(conf));
3609                 } else {
3610                         rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M,
3611                                           conf_is_ht40(conf));
3612                         rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M,
3613                                           conf_is_ht40(conf));
3614                 }
3615                 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3616
3617                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
3618                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
3619                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
3620         }
3621
3622         /*
3623          * Change BBP settings
3624          */
3625
3626         if (rt2x00_rt(rt2x00dev, RT3352)) {
3627                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3628                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3629                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3630
3631                 rt2800_bbp_write(rt2x00dev, 27, 0x0);
3632                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3633                 rt2800_bbp_write(rt2x00dev, 27, 0x20);
3634                 rt2800_bbp_write(rt2x00dev, 66, 0x26 + rt2x00dev->lna_gain);
3635                 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3636                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3637         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
3638                 if (rf->channel > 14) {
3639                         /* Disable CCK Packet detection on 5GHz */
3640                         rt2800_bbp_write(rt2x00dev, 70, 0x00);
3641                 } else {
3642                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3643                 }
3644
3645                 if (conf_is_ht40(conf))
3646                         rt2800_bbp_write(rt2x00dev, 105, 0x04);
3647                 else
3648                         rt2800_bbp_write(rt2x00dev, 105, 0x34);
3649
3650                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3651                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3652                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3653                 rt2800_bbp_write(rt2x00dev, 77, 0x98);
3654         } else {
3655                 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
3656                 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
3657                 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
3658                 if (rt2x00_rt(rt2x00dev, RT6352))
3659                         rt2800_bbp_write(rt2x00dev, 86, 0x38);
3660                 else
3661                         rt2800_bbp_write(rt2x00dev, 86, 0);
3662         }
3663
3664         if (rf->channel <= 14) {
3665                 if (!rt2x00_rt(rt2x00dev, RT5390) &&
3666                     !rt2x00_rt(rt2x00dev, RT5392) &&
3667                     !rt2x00_rt(rt2x00dev, RT6352)) {
3668                         if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3669                                 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3670                                 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3671                         } else {
3672                                 if (rt2x00_rt(rt2x00dev, RT3593))
3673                                         rt2800_bbp_write(rt2x00dev, 82, 0x62);
3674                                 else
3675                                         rt2800_bbp_write(rt2x00dev, 82, 0x84);
3676                                 rt2800_bbp_write(rt2x00dev, 75, 0x50);
3677                         }
3678                         if (rt2x00_rt(rt2x00dev, RT3593))
3679                                 rt2800_bbp_write(rt2x00dev, 83, 0x8a);
3680                 }
3681
3682         } else {
3683                 if (rt2x00_rt(rt2x00dev, RT3572))
3684                         rt2800_bbp_write(rt2x00dev, 82, 0x94);
3685                 else if (rt2x00_rt(rt2x00dev, RT3593))
3686                         rt2800_bbp_write(rt2x00dev, 82, 0x82);
3687                 else if (!rt2x00_rt(rt2x00dev, RT6352))
3688                         rt2800_bbp_write(rt2x00dev, 82, 0xf2);
3689
3690                 if (rt2x00_rt(rt2x00dev, RT3593))
3691                         rt2800_bbp_write(rt2x00dev, 83, 0x9a);
3692
3693                 if (rt2x00_has_cap_external_lna_a(rt2x00dev))
3694                         rt2800_bbp_write(rt2x00dev, 75, 0x46);
3695                 else
3696                         rt2800_bbp_write(rt2x00dev, 75, 0x50);
3697         }
3698
3699         reg = rt2800_register_read(rt2x00dev, TX_BAND_CFG);
3700         rt2x00_set_field32(&reg, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
3701         rt2x00_set_field32(&reg, TX_BAND_CFG_A, rf->channel > 14);
3702         rt2x00_set_field32(&reg, TX_BAND_CFG_BG, rf->channel <= 14);
3703         rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
3704
3705         if (rt2x00_rt(rt2x00dev, RT3572))
3706                 rt2800_rfcsr_write(rt2x00dev, 8, 0);
3707
3708         if (rt2x00_rt(rt2x00dev, RT6352))
3709                 tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
3710         else
3711                 tx_pin = 0;
3712
3713         switch (rt2x00dev->default_ant.tx_chain_num) {
3714         case 3:
3715                 /* Turn on tertiary PAs */
3716                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN,
3717                                    rf->channel > 14);
3718                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN,
3719                                    rf->channel <= 14);
3720                 /* fall-through */
3721         case 2:
3722                 /* Turn on secondary PAs */
3723                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
3724                                    rf->channel > 14);
3725                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
3726                                    rf->channel <= 14);
3727                 /* fall-through */
3728         case 1:
3729                 /* Turn on primary PAs */
3730                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN,
3731                                    rf->channel > 14);
3732                 if (rt2x00_has_cap_bt_coexist(rt2x00dev))
3733                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
3734                 else
3735                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
3736                                            rf->channel <= 14);
3737                 break;
3738         }
3739
3740         switch (rt2x00dev->default_ant.rx_chain_num) {
3741         case 3:
3742                 /* Turn on tertiary LNAs */
3743                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A2_EN, 1);
3744                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G2_EN, 1);
3745                 /* fall-through */
3746         case 2:
3747                 /* Turn on secondary LNAs */
3748                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
3749                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
3750                 /* fall-through */
3751         case 1:
3752                 /* Turn on primary LNAs */
3753                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
3754                 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
3755                 break;
3756         }
3757
3758         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
3759         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
3760         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFRX_EN, 1); /* mt7620 */
3761
3762         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
3763
3764         if (rt2x00_rt(rt2x00dev, RT3572)) {
3765                 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
3766
3767                 /* AGC init */
3768                 if (rf->channel <= 14)
3769                         reg = 0x1c + (2 * rt2x00dev->lna_gain);
3770                 else
3771                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3772
3773                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3774         }
3775
3776         if (rt2x00_rt(rt2x00dev, RT3593)) {
3777                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
3778
3779                 /* Band selection */
3780                 if (rt2x00_is_usb(rt2x00dev) ||
3781                     rt2x00_is_pcie(rt2x00dev)) {
3782                         /* GPIO #8 controls all paths */
3783                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR8, 0);
3784                         if (rf->channel <= 14)
3785                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 1);
3786                         else
3787                                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL8, 0);
3788                 }
3789
3790                 /* LNA PE control. */
3791                 if (rt2x00_is_usb(rt2x00dev)) {
3792                         /* GPIO #4 controls PE0 and PE1,
3793                          * GPIO #7 controls PE2
3794                          */
3795                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3796                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR7, 0);
3797
3798                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3799                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL7, 1);
3800                 } else if (rt2x00_is_pcie(rt2x00dev)) {
3801                         /* GPIO #4 controls PE0, PE1 and PE2 */
3802                         rt2x00_set_field32(&reg, GPIO_CTRL_DIR4, 0);
3803                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL4, 1);
3804                 }
3805
3806                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
3807
3808                 /* AGC init */
3809                 if (rf->channel <= 14)
3810                         reg = 0x1c + 2 * rt2x00dev->lna_gain;
3811                 else
3812                         reg = 0x22 + ((rt2x00dev->lna_gain * 5) / 3);
3813
3814                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3815
3816                 usleep_range(1000, 1500);
3817         }
3818
3819         if (rt2x00_rt(rt2x00dev, RT5592) || rt2x00_rt(rt2x00dev, RT6352)) {
3820                 reg = 0x10;
3821                 if (!conf_is_ht40(conf)) {
3822                         if (rt2x00_rt(rt2x00dev, RT6352) &&
3823                             rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
3824                                 reg |= 0x5;
3825                         } else {
3826                                 reg |= 0xa;
3827                         }
3828                 }
3829                 rt2800_bbp_write(rt2x00dev, 195, 141);
3830                 rt2800_bbp_write(rt2x00dev, 196, reg);
3831
3832                 /* AGC init */
3833                 if (rt2x00_rt(rt2x00dev, RT6352))
3834                         reg = 0x04;
3835                 else
3836                         reg = rf->channel <= 14 ? 0x1c : 0x24;
3837
3838                 reg += 2 * rt2x00dev->lna_gain;
3839                 rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, reg);
3840
3841                 if (rt2x00_rt(rt2x00dev, RT5592))
3842                         rt2800_iq_calibrate(rt2x00dev, rf->channel);
3843         }
3844
3845         bbp = rt2800_bbp_read(rt2x00dev, 4);
3846         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
3847         rt2800_bbp_write(rt2x00dev, 4, bbp);
3848
3849         bbp = rt2800_bbp_read(rt2x00dev, 3);
3850         rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
3851         rt2800_bbp_write(rt2x00dev, 3, bbp);
3852
3853         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3854                 if (conf_is_ht40(conf)) {
3855                         rt2800_bbp_write(rt2x00dev, 69, 0x1a);
3856                         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3857                         rt2800_bbp_write(rt2x00dev, 73, 0x16);
3858                 } else {
3859                         rt2800_bbp_write(rt2x00dev, 69, 0x16);
3860                         rt2800_bbp_write(rt2x00dev, 70, 0x08);
3861                         rt2800_bbp_write(rt2x00dev, 73, 0x11);
3862                 }
3863         }
3864
3865         usleep_range(1000, 1500);
3866
3867         /*
3868          * Clear channel statistic counters
3869          */
3870         reg = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
3871         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
3872         reg = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
3873
3874         /*
3875          * Clear update flag
3876          */
3877         if (rt2x00_rt(rt2x00dev, RT3352) ||
3878             rt2x00_rt(rt2x00dev, RT5350)) {
3879                 bbp = rt2800_bbp_read(rt2x00dev, 49);
3880                 rt2x00_set_field8(&bbp, BBP49_UPDATE_FLAG, 0);
3881                 rt2800_bbp_write(rt2x00dev, 49, bbp);
3882         }
3883 }
3884
3885 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
3886 {
3887         u8 tssi_bounds[9];
3888         u8 current_tssi;
3889         u16 eeprom;
3890         u8 step;
3891         int i;
3892
3893         /*
3894          * First check if temperature compensation is supported.
3895          */
3896         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
3897         if (!rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC))
3898                 return 0;
3899
3900         /*
3901          * Read TSSI boundaries for temperature compensation from
3902          * the EEPROM.
3903          *
3904          * Array idx               0    1    2    3    4    5    6    7    8
3905          * Matching Delta value   -4   -3   -2   -1    0   +1   +2   +3   +4
3906          * Example TSSI bounds  0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
3907          */
3908         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
3909                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1);
3910                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3911                                         EEPROM_TSSI_BOUND_BG1_MINUS4);
3912                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3913                                         EEPROM_TSSI_BOUND_BG1_MINUS3);
3914
3915                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2);
3916                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3917                                         EEPROM_TSSI_BOUND_BG2_MINUS2);
3918                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3919                                         EEPROM_TSSI_BOUND_BG2_MINUS1);
3920
3921                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3);
3922                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3923                                         EEPROM_TSSI_BOUND_BG3_REF);
3924                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3925                                         EEPROM_TSSI_BOUND_BG3_PLUS1);
3926
3927                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4);
3928                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3929                                         EEPROM_TSSI_BOUND_BG4_PLUS2);
3930                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3931                                         EEPROM_TSSI_BOUND_BG4_PLUS3);
3932
3933                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5);
3934                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3935                                         EEPROM_TSSI_BOUND_BG5_PLUS4);
3936
3937                 step = rt2x00_get_field16(eeprom,
3938                                           EEPROM_TSSI_BOUND_BG5_AGC_STEP);
3939         } else {
3940                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1);
3941                 tssi_bounds[0] = rt2x00_get_field16(eeprom,
3942                                         EEPROM_TSSI_BOUND_A1_MINUS4);
3943                 tssi_bounds[1] = rt2x00_get_field16(eeprom,
3944                                         EEPROM_TSSI_BOUND_A1_MINUS3);
3945
3946                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2);
3947                 tssi_bounds[2] = rt2x00_get_field16(eeprom,
3948                                         EEPROM_TSSI_BOUND_A2_MINUS2);
3949                 tssi_bounds[3] = rt2x00_get_field16(eeprom,
3950                                         EEPROM_TSSI_BOUND_A2_MINUS1);
3951
3952                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3);
3953                 tssi_bounds[4] = rt2x00_get_field16(eeprom,
3954                                         EEPROM_TSSI_BOUND_A3_REF);
3955                 tssi_bounds[5] = rt2x00_get_field16(eeprom,
3956                                         EEPROM_TSSI_BOUND_A3_PLUS1);
3957
3958                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4);
3959                 tssi_bounds[6] = rt2x00_get_field16(eeprom,
3960                                         EEPROM_TSSI_BOUND_A4_PLUS2);
3961                 tssi_bounds[7] = rt2x00_get_field16(eeprom,
3962                                         EEPROM_TSSI_BOUND_A4_PLUS3);
3963
3964                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5);
3965                 tssi_bounds[8] = rt2x00_get_field16(eeprom,
3966                                         EEPROM_TSSI_BOUND_A5_PLUS4);
3967
3968                 step = rt2x00_get_field16(eeprom,
3969                                           EEPROM_TSSI_BOUND_A5_AGC_STEP);
3970         }
3971
3972         /*
3973          * Check if temperature compensation is supported.
3974          */
3975         if (tssi_bounds[4] == 0xff || step == 0xff)
3976                 return 0;
3977
3978         /*
3979          * Read current TSSI (BBP 49).
3980          */
3981         current_tssi = rt2800_bbp_read(rt2x00dev, 49);
3982
3983         /*
3984          * Compare TSSI value (BBP49) with the compensation boundaries
3985          * from the EEPROM and increase or decrease tx power.
3986          */
3987         for (i = 0; i <= 3; i++) {
3988                 if (current_tssi > tssi_bounds[i])
3989                         break;
3990         }
3991
3992         if (i == 4) {
3993                 for (i = 8; i >= 5; i--) {
3994                         if (current_tssi < tssi_bounds[i])
3995                                 break;
3996                 }
3997         }
3998
3999         return (i - 4) * step;
4000 }
4001
4002 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
4003                                       enum nl80211_band band)
4004 {
4005         u16 eeprom;
4006         u8 comp_en;
4007         u8 comp_type;
4008         int comp_value = 0;
4009
4010         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA);
4011
4012         /*
4013          * HT40 compensation not required.
4014          */
4015         if (eeprom == 0xffff ||
4016             !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4017                 return 0;
4018
4019         if (band == NL80211_BAND_2GHZ) {
4020                 comp_en = rt2x00_get_field16(eeprom,
4021                                  EEPROM_TXPOWER_DELTA_ENABLE_2G);
4022                 if (comp_en) {
4023                         comp_type = rt2x00_get_field16(eeprom,
4024                                            EEPROM_TXPOWER_DELTA_TYPE_2G);
4025                         comp_value = rt2x00_get_field16(eeprom,
4026                                             EEPROM_TXPOWER_DELTA_VALUE_2G);
4027                         if (!comp_type)
4028                                 comp_value = -comp_value;
4029                 }
4030         } else {
4031                 comp_en = rt2x00_get_field16(eeprom,
4032                                  EEPROM_TXPOWER_DELTA_ENABLE_5G);
4033                 if (comp_en) {
4034                         comp_type = rt2x00_get_field16(eeprom,
4035                                            EEPROM_TXPOWER_DELTA_TYPE_5G);
4036                         comp_value = rt2x00_get_field16(eeprom,
4037                                             EEPROM_TXPOWER_DELTA_VALUE_5G);
4038                         if (!comp_type)
4039                                 comp_value = -comp_value;
4040                 }
4041         }
4042
4043         return comp_value;
4044 }
4045
4046 static int rt2800_get_txpower_reg_delta(struct rt2x00_dev *rt2x00dev,
4047                                         int power_level, int max_power)
4048 {
4049         int delta;
4050
4051         if (rt2x00_has_cap_power_limit(rt2x00dev))
4052                 return 0;
4053
4054         /*
4055          * XXX: We don't know the maximum transmit power of our hardware since
4056          * the EEPROM doesn't expose it. We only know that we are calibrated
4057          * to 100% tx power.
4058          *
4059          * Hence, we assume the regulatory limit that cfg80211 calulated for
4060          * the current channel is our maximum and if we are requested to lower
4061          * the value we just reduce our tx power accordingly.
4062          */
4063         delta = power_level - max_power;
4064         return min(delta, 0);
4065 }
4066
4067 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
4068                                    enum nl80211_band band, int power_level,
4069                                    u8 txpower, int delta)
4070 {
4071         u16 eeprom;
4072         u8 criterion;
4073         u8 eirp_txpower;
4074         u8 eirp_txpower_criterion;
4075         u8 reg_limit;
4076
4077         if (rt2x00_rt(rt2x00dev, RT3593))
4078                 return min_t(u8, txpower, 0xc);
4079
4080         if (rt2x00_has_cap_power_limit(rt2x00dev)) {
4081                 /*
4082                  * Check if eirp txpower exceed txpower_limit.
4083                  * We use OFDM 6M as criterion and its eirp txpower
4084                  * is stored at EEPROM_EIRP_MAX_TX_POWER.
4085                  * .11b data rate need add additional 4dbm
4086                  * when calculating eirp txpower.
4087                  */
4088                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4089                                                        EEPROM_TXPOWER_BYRATE,
4090                                                        1);
4091                 criterion = rt2x00_get_field16(eeprom,
4092                                                EEPROM_TXPOWER_BYRATE_RATE0);
4093
4094                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
4095
4096                 if (band == NL80211_BAND_2GHZ)
4097                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4098                                                  EEPROM_EIRP_MAX_TX_POWER_2GHZ);
4099                 else
4100                         eirp_txpower_criterion = rt2x00_get_field16(eeprom,
4101                                                  EEPROM_EIRP_MAX_TX_POWER_5GHZ);
4102
4103                 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
4104                                (is_rate_b ? 4 : 0) + delta;
4105
4106                 reg_limit = (eirp_txpower > power_level) ?
4107                                         (eirp_txpower - power_level) : 0;
4108         } else
4109                 reg_limit = 0;
4110
4111         txpower = max(0, txpower + delta - reg_limit);
4112         return min_t(u8, txpower, 0xc);
4113 }
4114
4115
4116 enum {
4117         TX_PWR_CFG_0_IDX,
4118         TX_PWR_CFG_1_IDX,
4119         TX_PWR_CFG_2_IDX,
4120         TX_PWR_CFG_3_IDX,
4121         TX_PWR_CFG_4_IDX,
4122         TX_PWR_CFG_5_IDX,
4123         TX_PWR_CFG_6_IDX,
4124         TX_PWR_CFG_7_IDX,
4125         TX_PWR_CFG_8_IDX,
4126         TX_PWR_CFG_9_IDX,
4127         TX_PWR_CFG_0_EXT_IDX,
4128         TX_PWR_CFG_1_EXT_IDX,
4129         TX_PWR_CFG_2_EXT_IDX,
4130         TX_PWR_CFG_3_EXT_IDX,
4131         TX_PWR_CFG_4_EXT_IDX,
4132         TX_PWR_CFG_IDX_COUNT,
4133 };
4134
4135 static void rt2800_config_txpower_rt3593(struct rt2x00_dev *rt2x00dev,
4136                                          struct ieee80211_channel *chan,
4137                                          int power_level)
4138 {
4139         u8 txpower;
4140         u16 eeprom;
4141         u32 regs[TX_PWR_CFG_IDX_COUNT];
4142         unsigned int offset;
4143         enum nl80211_band band = chan->band;
4144         int delta;
4145         int i;
4146
4147         memset(regs, '\0', sizeof(regs));
4148
4149         /* TODO: adapt TX power reduction from the rt28xx code */
4150
4151         /* calculate temperature compensation delta */
4152         delta = rt2800_get_gain_calibration_delta(rt2x00dev);
4153
4154         if (band == NL80211_BAND_5GHZ)
4155                 offset = 16;
4156         else
4157                 offset = 0;
4158
4159         if (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
4160                 offset += 8;
4161
4162         /* read the next four txpower values */
4163         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4164                                                offset);
4165
4166         /* CCK 1MBS,2MBS */
4167         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4168         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4169                                             txpower, delta);
4170         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4171                            TX_PWR_CFG_0_CCK1_CH0, txpower);
4172         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4173                            TX_PWR_CFG_0_CCK1_CH1, txpower);
4174         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4175                            TX_PWR_CFG_0_EXT_CCK1_CH2, txpower);
4176
4177         /* CCK 5.5MBS,11MBS */
4178         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4179         txpower = rt2800_compensate_txpower(rt2x00dev, 1, band, power_level,
4180                                             txpower, delta);
4181         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4182                            TX_PWR_CFG_0_CCK5_CH0, txpower);
4183         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4184                            TX_PWR_CFG_0_CCK5_CH1, txpower);
4185         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4186                            TX_PWR_CFG_0_EXT_CCK5_CH2, txpower);
4187
4188         /* OFDM 6MBS,9MBS */
4189         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4190         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4191                                             txpower, delta);
4192         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4193                            TX_PWR_CFG_0_OFDM6_CH0, txpower);
4194         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4195                            TX_PWR_CFG_0_OFDM6_CH1, txpower);
4196         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4197                            TX_PWR_CFG_0_EXT_OFDM6_CH2, txpower);
4198
4199         /* OFDM 12MBS,18MBS */
4200         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4201         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4202                                             txpower, delta);
4203         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4204                            TX_PWR_CFG_0_OFDM12_CH0, txpower);
4205         rt2x00_set_field32(&regs[TX_PWR_CFG_0_IDX],
4206                            TX_PWR_CFG_0_OFDM12_CH1, txpower);
4207         rt2x00_set_field32(&regs[TX_PWR_CFG_0_EXT_IDX],
4208                            TX_PWR_CFG_0_EXT_OFDM12_CH2, txpower);
4209
4210         /* read the next four txpower values */
4211         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4212                                                offset + 1);
4213
4214         /* OFDM 24MBS,36MBS */
4215         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4216         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4217                                             txpower, delta);
4218         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4219                            TX_PWR_CFG_1_OFDM24_CH0, txpower);
4220         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4221                            TX_PWR_CFG_1_OFDM24_CH1, txpower);
4222         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4223                            TX_PWR_CFG_1_EXT_OFDM24_CH2, txpower);
4224
4225         /* OFDM 48MBS */
4226         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4227         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4228                                             txpower, delta);
4229         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4230                            TX_PWR_CFG_1_OFDM48_CH0, txpower);
4231         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4232                            TX_PWR_CFG_1_OFDM48_CH1, txpower);
4233         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4234                            TX_PWR_CFG_1_EXT_OFDM48_CH2, txpower);
4235
4236         /* OFDM 54MBS */
4237         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4238         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4239                                             txpower, delta);
4240         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4241                            TX_PWR_CFG_7_OFDM54_CH0, txpower);
4242         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4243                            TX_PWR_CFG_7_OFDM54_CH1, txpower);
4244         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4245                            TX_PWR_CFG_7_OFDM54_CH2, txpower);
4246
4247         /* read the next four txpower values */
4248         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4249                                                offset + 2);
4250
4251         /* MCS 0,1 */
4252         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4253         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4254                                             txpower, delta);
4255         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4256                            TX_PWR_CFG_1_MCS0_CH0, txpower);
4257         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4258                            TX_PWR_CFG_1_MCS0_CH1, txpower);
4259         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4260                            TX_PWR_CFG_1_EXT_MCS0_CH2, txpower);
4261
4262         /* MCS 2,3 */
4263         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4264         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4265                                             txpower, delta);
4266         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4267                            TX_PWR_CFG_1_MCS2_CH0, txpower);
4268         rt2x00_set_field32(&regs[TX_PWR_CFG_1_IDX],
4269                            TX_PWR_CFG_1_MCS2_CH1, txpower);
4270         rt2x00_set_field32(&regs[TX_PWR_CFG_1_EXT_IDX],
4271                            TX_PWR_CFG_1_EXT_MCS2_CH2, txpower);
4272
4273         /* MCS 4,5 */
4274         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4275         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4276                                             txpower, delta);
4277         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4278                            TX_PWR_CFG_2_MCS4_CH0, txpower);
4279         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4280                            TX_PWR_CFG_2_MCS4_CH1, txpower);
4281         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4282                            TX_PWR_CFG_2_EXT_MCS4_CH2, txpower);
4283
4284         /* MCS 6 */
4285         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4286         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4287                                             txpower, delta);
4288         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4289                            TX_PWR_CFG_2_MCS6_CH0, txpower);
4290         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4291                            TX_PWR_CFG_2_MCS6_CH1, txpower);
4292         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4293                            TX_PWR_CFG_2_EXT_MCS6_CH2, txpower);
4294
4295         /* read the next four txpower values */
4296         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4297                                                offset + 3);
4298
4299         /* MCS 7 */
4300         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4301         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4302                                             txpower, delta);
4303         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4304                            TX_PWR_CFG_7_MCS7_CH0, txpower);
4305         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4306                            TX_PWR_CFG_7_MCS7_CH1, txpower);
4307         rt2x00_set_field32(&regs[TX_PWR_CFG_7_IDX],
4308                            TX_PWR_CFG_7_MCS7_CH2, txpower);
4309
4310         /* MCS 8,9 */
4311         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4312         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4313                                             txpower, delta);
4314         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4315                            TX_PWR_CFG_2_MCS8_CH0, txpower);
4316         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4317                            TX_PWR_CFG_2_MCS8_CH1, txpower);
4318         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4319                            TX_PWR_CFG_2_EXT_MCS8_CH2, txpower);
4320
4321         /* MCS 10,11 */
4322         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4323         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4324                                             txpower, delta);
4325         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4326                            TX_PWR_CFG_2_MCS10_CH0, txpower);
4327         rt2x00_set_field32(&regs[TX_PWR_CFG_2_IDX],
4328                            TX_PWR_CFG_2_MCS10_CH1, txpower);
4329         rt2x00_set_field32(&regs[TX_PWR_CFG_2_EXT_IDX],
4330                            TX_PWR_CFG_2_EXT_MCS10_CH2, txpower);
4331
4332         /* MCS 12,13 */
4333         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4334         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4335                                             txpower, delta);
4336         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4337                            TX_PWR_CFG_3_MCS12_CH0, txpower);
4338         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4339                            TX_PWR_CFG_3_MCS12_CH1, txpower);
4340         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4341                            TX_PWR_CFG_3_EXT_MCS12_CH2, txpower);
4342
4343         /* read the next four txpower values */
4344         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4345                                                offset + 4);
4346
4347         /* MCS 14 */
4348         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4349         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4350                                             txpower, delta);
4351         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4352                            TX_PWR_CFG_3_MCS14_CH0, txpower);
4353         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4354                            TX_PWR_CFG_3_MCS14_CH1, txpower);
4355         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4356                            TX_PWR_CFG_3_EXT_MCS14_CH2, txpower);
4357
4358         /* MCS 15 */
4359         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4360         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4361                                             txpower, delta);
4362         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4363                            TX_PWR_CFG_8_MCS15_CH0, txpower);
4364         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4365                            TX_PWR_CFG_8_MCS15_CH1, txpower);
4366         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4367                            TX_PWR_CFG_8_MCS15_CH2, txpower);
4368
4369         /* MCS 16,17 */
4370         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4371         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4372                                             txpower, delta);
4373         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4374                            TX_PWR_CFG_5_MCS16_CH0, txpower);
4375         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4376                            TX_PWR_CFG_5_MCS16_CH1, txpower);
4377         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4378                            TX_PWR_CFG_5_MCS16_CH2, txpower);
4379
4380         /* MCS 18,19 */
4381         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4382         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4383                                             txpower, delta);
4384         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4385                            TX_PWR_CFG_5_MCS18_CH0, txpower);
4386         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4387                            TX_PWR_CFG_5_MCS18_CH1, txpower);
4388         rt2x00_set_field32(&regs[TX_PWR_CFG_5_IDX],
4389                            TX_PWR_CFG_5_MCS18_CH2, txpower);
4390
4391         /* read the next four txpower values */
4392         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4393                                                offset + 5);
4394
4395         /* MCS 20,21 */
4396         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4397         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4398                                             txpower, delta);
4399         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4400                            TX_PWR_CFG_6_MCS20_CH0, txpower);
4401         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4402                            TX_PWR_CFG_6_MCS20_CH1, txpower);
4403         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4404                            TX_PWR_CFG_6_MCS20_CH2, txpower);
4405
4406         /* MCS 22 */
4407         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4408         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4409                                             txpower, delta);
4410         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4411                            TX_PWR_CFG_6_MCS22_CH0, txpower);
4412         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4413                            TX_PWR_CFG_6_MCS22_CH1, txpower);
4414         rt2x00_set_field32(&regs[TX_PWR_CFG_6_IDX],
4415                            TX_PWR_CFG_6_MCS22_CH2, txpower);
4416
4417         /* MCS 23 */
4418         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4419         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4420                                             txpower, delta);
4421         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4422                            TX_PWR_CFG_8_MCS23_CH0, txpower);
4423         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4424                            TX_PWR_CFG_8_MCS23_CH1, txpower);
4425         rt2x00_set_field32(&regs[TX_PWR_CFG_8_IDX],
4426                            TX_PWR_CFG_8_MCS23_CH2, txpower);
4427
4428         /* read the next four txpower values */
4429         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4430                                                offset + 6);
4431
4432         /* STBC, MCS 0,1 */
4433         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4434         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4435                                             txpower, delta);
4436         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4437                            TX_PWR_CFG_3_STBC0_CH0, txpower);
4438         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4439                            TX_PWR_CFG_3_STBC0_CH1, txpower);
4440         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4441                            TX_PWR_CFG_3_EXT_STBC0_CH2, txpower);
4442
4443         /* STBC, MCS 2,3 */
4444         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE1);
4445         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4446                                             txpower, delta);
4447         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4448                            TX_PWR_CFG_3_STBC2_CH0, txpower);
4449         rt2x00_set_field32(&regs[TX_PWR_CFG_3_IDX],
4450                            TX_PWR_CFG_3_STBC2_CH1, txpower);
4451         rt2x00_set_field32(&regs[TX_PWR_CFG_3_EXT_IDX],
4452                            TX_PWR_CFG_3_EXT_STBC2_CH2, txpower);
4453
4454         /* STBC, MCS 4,5 */
4455         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE2);
4456         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4457                                             txpower, delta);
4458         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE0, txpower);
4459         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE1, txpower);
4460         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE0,
4461                            txpower);
4462
4463         /* STBC, MCS 6 */
4464         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE3);
4465         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4466                                             txpower, delta);
4467         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE2, txpower);
4468         rt2x00_set_field32(&regs[TX_PWR_CFG_4_IDX], TX_PWR_CFG_RATE3, txpower);
4469         rt2x00_set_field32(&regs[TX_PWR_CFG_4_EXT_IDX], TX_PWR_CFG_RATE2,
4470                            txpower);
4471
4472         /* read the next four txpower values */
4473         eeprom = rt2800_eeprom_read_from_array(rt2x00dev, EEPROM_TXPOWER_BYRATE,
4474                                                offset + 7);
4475
4476         /* STBC, MCS 7 */
4477         txpower = rt2x00_get_field16(eeprom, EEPROM_TXPOWER_BYRATE_RATE0);
4478         txpower = rt2800_compensate_txpower(rt2x00dev, 0, band, power_level,
4479                                             txpower, delta);
4480         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4481                            TX_PWR_CFG_9_STBC7_CH0, txpower);
4482         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4483                            TX_PWR_CFG_9_STBC7_CH1, txpower);
4484         rt2x00_set_field32(&regs[TX_PWR_CFG_9_IDX],
4485                            TX_PWR_CFG_9_STBC7_CH2, txpower);
4486
4487         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0, regs[TX_PWR_CFG_0_IDX]);
4488         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1, regs[TX_PWR_CFG_1_IDX]);
4489         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2, regs[TX_PWR_CFG_2_IDX]);
4490         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3, regs[TX_PWR_CFG_3_IDX]);
4491         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4, regs[TX_PWR_CFG_4_IDX]);
4492         rt2800_register_write(rt2x00dev, TX_PWR_CFG_5, regs[TX_PWR_CFG_5_IDX]);
4493         rt2800_register_write(rt2x00dev, TX_PWR_CFG_6, regs[TX_PWR_CFG_6_IDX]);
4494         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, regs[TX_PWR_CFG_7_IDX]);
4495         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, regs[TX_PWR_CFG_8_IDX]);
4496         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, regs[TX_PWR_CFG_9_IDX]);
4497
4498         rt2800_register_write(rt2x00dev, TX_PWR_CFG_0_EXT,
4499                               regs[TX_PWR_CFG_0_EXT_IDX]);
4500         rt2800_register_write(rt2x00dev, TX_PWR_CFG_1_EXT,
4501                               regs[TX_PWR_CFG_1_EXT_IDX]);
4502         rt2800_register_write(rt2x00dev, TX_PWR_CFG_2_EXT,
4503                               regs[TX_PWR_CFG_2_EXT_IDX]);
4504         rt2800_register_write(rt2x00dev, TX_PWR_CFG_3_EXT,
4505                               regs[TX_PWR_CFG_3_EXT_IDX]);
4506         rt2800_register_write(rt2x00dev, TX_PWR_CFG_4_EXT,
4507                               regs[TX_PWR_CFG_4_EXT_IDX]);
4508
4509         for (i = 0; i < TX_PWR_CFG_IDX_COUNT; i++)
4510                 rt2x00_dbg(rt2x00dev,
4511                            "band:%cGHz, BW:%c0MHz, TX_PWR_CFG_%d%s = %08lx\n",
4512                            (band == NL80211_BAND_5GHZ) ? '5' : '2',
4513                            (test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) ?
4514                                                                 '4' : '2',
4515                            (i > TX_PWR_CFG_9_IDX) ?
4516                                         (i - TX_PWR_CFG_9_IDX - 1) : i,
4517                            (i > TX_PWR_CFG_9_IDX) ? "_EXT" : "",
4518                            (unsigned long) regs[i]);
4519 }
4520
4521 static void rt2800_config_txpower_rt6352(struct rt2x00_dev *rt2x00dev,
4522                                          struct ieee80211_channel *chan,
4523                                          int power_level)
4524 {
4525         u32 reg, pwreg;
4526         u16 eeprom;
4527         u32 data, gdata;
4528         u8 t, i;
4529         enum nl80211_band band = chan->band;
4530         int delta;
4531
4532         /* Warn user if bw_comp is set in EEPROM */
4533         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4534
4535         if (delta)
4536                 rt2x00_warn(rt2x00dev, "ignoring EEPROM HT40 power delta: %d\n",
4537                             delta);
4538
4539         /* populate TX_PWR_CFG_0 up to TX_PWR_CFG_4 from EEPROM for HT20, limit
4540          * value to 0x3f and replace 0x20 by 0x21 as this is what the vendor
4541          * driver does as well, though it looks kinda wrong.
4542          * Maybe some misunderstanding of what a signed 8-bit value is? Maybe
4543          * the hardware has a problem handling 0x20, and as the code initially
4544          * used a fixed offset between HT20 and HT40 rates they had to work-
4545          * around that issue and most likely just forgot about it later on.
4546          * Maybe we should use rt2800_get_txpower_bw_comp() here as well,
4547          * however, the corresponding EEPROM value is not respected by the
4548          * vendor driver, so maybe this is rather being taken care of the
4549          * TXALC and the driver doesn't need to handle it...?
4550          * Though this is all very awkward, just do as they did, as that's what
4551          * board vendors expected when they populated the EEPROM...
4552          */
4553         for (i = 0; i < 5; i++) {
4554                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4555                                                        EEPROM_TXPOWER_BYRATE,
4556                                                        i * 2);
4557
4558                 data = eeprom;
4559
4560                 t = eeprom & 0x3f;
4561                 if (t == 32)
4562                         t++;
4563
4564                 gdata = t;
4565
4566                 t = (eeprom & 0x3f00) >> 8;
4567                 if (t == 32)
4568                         t++;
4569
4570                 gdata |= (t << 8);
4571
4572                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4573                                                        EEPROM_TXPOWER_BYRATE,
4574                                                        (i * 2) + 1);
4575
4576                 t = eeprom & 0x3f;
4577                 if (t == 32)
4578                         t++;
4579
4580                 gdata |= (t << 16);
4581
4582                 t = (eeprom & 0x3f00) >> 8;
4583                 if (t == 32)
4584                         t++;
4585
4586                 gdata |= (t << 24);
4587                 data |= (eeprom << 16);
4588
4589                 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags)) {
4590                         /* HT20 */
4591                         if (data != 0xffffffff)
4592                                 rt2800_register_write(rt2x00dev,
4593                                                       TX_PWR_CFG_0 + (i * 4),
4594                                                       data);
4595                 } else {
4596                         /* HT40 */
4597                         if (gdata != 0xffffffff)
4598                                 rt2800_register_write(rt2x00dev,
4599                                                       TX_PWR_CFG_0 + (i * 4),
4600                                                       gdata);
4601                 }
4602         }
4603
4604         /* Aparently Ralink ran out of space in the BYRATE calibration section
4605          * of the EERPOM which is copied to the corresponding TX_PWR_CFG_x
4606          * registers. As recent 2T chips use 8-bit instead of 4-bit values for
4607          * power-offsets more space would be needed. Ralink decided to keep the
4608          * EEPROM layout untouched and rather have some shared values covering
4609          * multiple bitrates.
4610          * Populate the registers not covered by the EEPROM in the same way the
4611          * vendor driver does.
4612          */
4613
4614         /* For OFDM 54MBS use value from OFDM 48MBS */
4615         pwreg = 0;
4616         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_1);
4617         t = rt2x00_get_field32(reg, TX_PWR_CFG_1B_48MBS);
4618         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_54MBS, t);
4619
4620         /* For MCS 7 use value from MCS 6 */
4621         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_2);
4622         t = rt2x00_get_field32(reg, TX_PWR_CFG_2B_MCS6_MCS7);
4623         rt2x00_set_field32(&pwreg, TX_PWR_CFG_7B_MCS7, t);
4624         rt2800_register_write(rt2x00dev, TX_PWR_CFG_7, pwreg);
4625
4626         /* For MCS 15 use value from MCS 14 */
4627         pwreg = 0;
4628         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_3);
4629         t = rt2x00_get_field32(reg, TX_PWR_CFG_3B_MCS14);
4630         rt2x00_set_field32(&pwreg, TX_PWR_CFG_8B_MCS15, t);
4631         rt2800_register_write(rt2x00dev, TX_PWR_CFG_8, pwreg);
4632
4633         /* For STBC MCS 7 use value from STBC MCS 6 */
4634         pwreg = 0;
4635         reg = rt2800_register_read(rt2x00dev, TX_PWR_CFG_4);
4636         t = rt2x00_get_field32(reg, TX_PWR_CFG_4B_STBC_MCS6);
4637         rt2x00_set_field32(&pwreg, TX_PWR_CFG_9B_STBC_MCS7, t);
4638         rt2800_register_write(rt2x00dev, TX_PWR_CFG_9, pwreg);
4639
4640         rt2800_config_alc(rt2x00dev, chan, power_level);
4641
4642         /* TODO: temperature compensation code! */
4643 }
4644
4645 /*
4646  * We configure transmit power using MAC TX_PWR_CFG_{0,...,N} registers and
4647  * BBP R1 register. TX_PWR_CFG_X allow to configure per rate TX power values,
4648  * 4 bits for each rate (tune from 0 to 15 dBm). BBP_R1 controls transmit power
4649  * for all rates, but allow to set only 4 discrete values: -12, -6, 0 and 6 dBm.
4650  * Reference per rate transmit power values are located in the EEPROM at
4651  * EEPROM_TXPOWER_BYRATE offset. We adjust them and BBP R1 settings according to
4652  * current conditions (i.e. band, bandwidth, temperature, user settings).
4653  */
4654 static void rt2800_config_txpower_rt28xx(struct rt2x00_dev *rt2x00dev,
4655                                          struct ieee80211_channel *chan,
4656                                          int power_level)
4657 {
4658         u8 txpower, r1;
4659         u16 eeprom;
4660         u32 reg, offset;
4661         int i, is_rate_b, delta, power_ctrl;
4662         enum nl80211_band band = chan->band;
4663
4664         /*
4665          * Calculate HT40 compensation. For 40MHz we need to add or subtract
4666          * value read from EEPROM (different for 2GHz and for 5GHz).
4667          */
4668         delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
4669
4670         /*
4671          * Calculate temperature compensation. Depends on measurement of current
4672          * TSSI (Transmitter Signal Strength Indication) we know TX power (due
4673          * to temperature or maybe other factors) is smaller or bigger than
4674          * expected. We adjust it, based on TSSI reference and boundaries values
4675          * provided in EEPROM.
4676          */
4677         switch (rt2x00dev->chip.rt) {
4678         case RT2860:
4679         case RT2872:
4680         case RT2883:
4681         case RT3070:
4682         case RT3071:
4683         case RT3090:
4684         case RT3572:
4685                 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
4686                 break;
4687         default:
4688                 /* TODO: temperature compensation code for other chips. */
4689                 break;
4690         }
4691
4692         /*
4693          * Decrease power according to user settings, on devices with unknown
4694          * maximum tx power. For other devices we take user power_level into
4695          * consideration on rt2800_compensate_txpower().
4696          */
4697         delta += rt2800_get_txpower_reg_delta(rt2x00dev, power_level,
4698                                               chan->max_power);
4699
4700         /*
4701          * BBP_R1 controls TX power for all rates, it allow to set the following
4702          * gains -12, -6, 0, +6 dBm by setting values 2, 1, 0, 3 respectively.
4703          *
4704          * TODO: we do not use +6 dBm option to do not increase power beyond
4705          * regulatory limit, however this could be utilized for devices with
4706          * CAPABILITY_POWER_LIMIT.
4707          */
4708         if (delta <= -12) {
4709                 power_ctrl = 2;
4710                 delta += 12;
4711         } else if (delta <= -6) {
4712                 power_ctrl = 1;
4713                 delta += 6;
4714         } else {
4715                 power_ctrl = 0;
4716         }
4717         r1 = rt2800_bbp_read(rt2x00dev, 1);
4718         rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, power_ctrl);
4719         rt2800_bbp_write(rt2x00dev, 1, r1);
4720
4721         offset = TX_PWR_CFG_0;
4722
4723         for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
4724                 /* just to be safe */
4725                 if (offset > TX_PWR_CFG_4)
4726                         break;
4727
4728                 reg = rt2800_register_read(rt2x00dev, offset);
4729
4730                 /* read the next four txpower values */
4731                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4732                                                        EEPROM_TXPOWER_BYRATE,
4733                                                        i);
4734
4735                 is_rate_b = i ? 0 : 1;
4736                 /*
4737                  * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
4738                  * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
4739                  * TX_PWR_CFG_4: unknown
4740                  */
4741                 txpower = rt2x00_get_field16(eeprom,
4742                                              EEPROM_TXPOWER_BYRATE_RATE0);
4743                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4744                                              power_level, txpower, delta);
4745                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE0, txpower);
4746
4747                 /*
4748                  * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
4749                  * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
4750                  * TX_PWR_CFG_4: unknown
4751                  */
4752                 txpower = rt2x00_get_field16(eeprom,
4753                                              EEPROM_TXPOWER_BYRATE_RATE1);
4754                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4755                                              power_level, txpower, delta);
4756                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE1, txpower);
4757
4758                 /*
4759                  * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
4760                  * TX_PWR_CFG_2: MCS6,  TX_PWR_CFG_3: MCS14,
4761                  * TX_PWR_CFG_4: unknown
4762                  */
4763                 txpower = rt2x00_get_field16(eeprom,
4764                                              EEPROM_TXPOWER_BYRATE_RATE2);
4765                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4766                                              power_level, txpower, delta);
4767                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE2, txpower);
4768
4769                 /*
4770                  * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
4771                  * TX_PWR_CFG_2: MCS7,  TX_PWR_CFG_3: MCS15,
4772                  * TX_PWR_CFG_4: unknown
4773                  */
4774                 txpower = rt2x00_get_field16(eeprom,
4775                                              EEPROM_TXPOWER_BYRATE_RATE3);
4776                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4777                                              power_level, txpower, delta);
4778                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE3, txpower);
4779
4780                 /* read the next four txpower values */
4781                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
4782                                                        EEPROM_TXPOWER_BYRATE,
4783                                                        i + 1);
4784
4785                 is_rate_b = 0;
4786                 /*
4787                  * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
4788                  * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
4789                  * TX_PWR_CFG_4: unknown
4790                  */
4791                 txpower = rt2x00_get_field16(eeprom,
4792                                              EEPROM_TXPOWER_BYRATE_RATE0);
4793                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4794                                              power_level, txpower, delta);
4795                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE4, txpower);
4796
4797                 /*
4798                  * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
4799                  * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
4800                  * TX_PWR_CFG_4: unknown
4801                  */
4802                 txpower = rt2x00_get_field16(eeprom,
4803                                              EEPROM_TXPOWER_BYRATE_RATE1);
4804                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4805                                              power_level, txpower, delta);
4806                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE5, txpower);
4807
4808                 /*
4809                  * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
4810                  * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
4811                  * TX_PWR_CFG_4: unknown
4812                  */
4813                 txpower = rt2x00_get_field16(eeprom,
4814                                              EEPROM_TXPOWER_BYRATE_RATE2);
4815                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4816                                              power_level, txpower, delta);
4817                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE6, txpower);
4818
4819                 /*
4820                  * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
4821                  * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
4822                  * TX_PWR_CFG_4: unknown
4823                  */
4824                 txpower = rt2x00_get_field16(eeprom,
4825                                              EEPROM_TXPOWER_BYRATE_RATE3);
4826                 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
4827                                              power_level, txpower, delta);
4828                 rt2x00_set_field32(&reg, TX_PWR_CFG_RATE7, txpower);
4829
4830                 rt2800_register_write(rt2x00dev, offset, reg);
4831
4832                 /* next TX_PWR_CFG register */
4833                 offset += 4;
4834         }
4835 }
4836
4837 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
4838                                   struct ieee80211_channel *chan,
4839                                   int power_level)
4840 {
4841         if (rt2x00_rt(rt2x00dev, RT3593))
4842                 rt2800_config_txpower_rt3593(rt2x00dev, chan, power_level);
4843         else if (rt2x00_rt(rt2x00dev, RT6352))
4844                 rt2800_config_txpower_rt6352(rt2x00dev, chan, power_level);
4845         else
4846                 rt2800_config_txpower_rt28xx(rt2x00dev, chan, power_level);
4847 }
4848
4849 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
4850 {
4851         rt2800_config_txpower(rt2x00dev, rt2x00dev->hw->conf.chandef.chan,
4852                               rt2x00dev->tx_power);
4853 }
4854 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
4855
4856 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
4857 {
4858         u32     tx_pin;
4859         u8      rfcsr;
4860         unsigned long min_sleep = 0;
4861
4862         /*
4863          * A voltage-controlled oscillator(VCO) is an electronic oscillator
4864          * designed to be controlled in oscillation frequency by a voltage
4865          * input. Maybe the temperature will affect the frequency of
4866          * oscillation to be shifted. The VCO calibration will be called
4867          * periodically to adjust the frequency to be precision.
4868         */
4869
4870         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4871         tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
4872         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4873
4874         switch (rt2x00dev->chip.rf) {
4875         case RF2020:
4876         case RF3020:
4877         case RF3021:
4878         case RF3022:
4879         case RF3320:
4880         case RF3052:
4881                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 7);
4882                 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
4883                 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
4884                 break;
4885         case RF3053:
4886         case RF3070:
4887         case RF3290:
4888         case RF5350:
4889         case RF5360:
4890         case RF5362:
4891         case RF5370:
4892         case RF5372:
4893         case RF5390:
4894         case RF5392:
4895         case RF5592:
4896                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 3);
4897                 rt2x00_set_field8(&rfcsr, RFCSR3_VCOCAL_EN, 1);
4898                 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
4899                 min_sleep = 1000;
4900                 break;
4901         case RF7620:
4902                 rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
4903                 rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
4904                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 4);
4905                 rt2x00_set_field8(&rfcsr, RFCSR4_VCOCAL_EN, 1);
4906                 rt2800_rfcsr_write(rt2x00dev, 4, rfcsr);
4907                 min_sleep = 2000;
4908                 break;
4909         default:
4910                 WARN_ONCE(1, "Not supported RF chipet %x for VCO recalibration",
4911                           rt2x00dev->chip.rf);
4912                 return;
4913         }
4914
4915         if (min_sleep > 0)
4916                 usleep_range(min_sleep, min_sleep * 2);
4917
4918         tx_pin = rt2800_register_read(rt2x00dev, TX_PIN_CFG);
4919         if (rt2x00dev->rf_channel <= 14) {
4920                 switch (rt2x00dev->default_ant.tx_chain_num) {
4921                 case 3:
4922                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
4923                         /* fall through */
4924                 case 2:
4925                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
4926                         /* fall through */
4927                 case 1:
4928                 default:
4929                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
4930                         break;
4931                 }
4932         } else {
4933                 switch (rt2x00dev->default_ant.tx_chain_num) {
4934                 case 3:
4935                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
4936                         /* fall through */
4937                 case 2:
4938                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
4939                         /* fall through */
4940                 case 1:
4941                 default:
4942                         rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
4943                         break;
4944                 }
4945         }
4946         rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
4947
4948         if (rt2x00_rt(rt2x00dev, RT6352)) {
4949                 if (rt2x00dev->default_ant.rx_chain_num == 1) {
4950                         rt2800_bbp_write(rt2x00dev, 91, 0x07);
4951                         rt2800_bbp_write(rt2x00dev, 95, 0x1A);
4952                         rt2800_bbp_write(rt2x00dev, 195, 128);
4953                         rt2800_bbp_write(rt2x00dev, 196, 0xA0);
4954                         rt2800_bbp_write(rt2x00dev, 195, 170);
4955                         rt2800_bbp_write(rt2x00dev, 196, 0x12);
4956                         rt2800_bbp_write(rt2x00dev, 195, 171);
4957                         rt2800_bbp_write(rt2x00dev, 196, 0x10);
4958                 } else {
4959                         rt2800_bbp_write(rt2x00dev, 91, 0x06);
4960                         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
4961                         rt2800_bbp_write(rt2x00dev, 195, 128);
4962                         rt2800_bbp_write(rt2x00dev, 196, 0xE0);
4963                         rt2800_bbp_write(rt2x00dev, 195, 170);
4964                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
4965                         rt2800_bbp_write(rt2x00dev, 195, 171);
4966                         rt2800_bbp_write(rt2x00dev, 196, 0x30);
4967                 }
4968
4969                 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) {
4970                         rt2800_bbp_write(rt2x00dev, 75, 0x68);
4971                         rt2800_bbp_write(rt2x00dev, 76, 0x4C);
4972                         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
4973                         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
4974                         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
4975                 }
4976
4977                 /* On 11A, We should delay and wait RF/BBP to be stable
4978                  * and the appropriate time should be 1000 micro seconds
4979                  * 2005/06/05 - On 11G, we also need this delay time.
4980                  * Otherwise it's difficult to pass the WHQL.
4981                  */
4982                 usleep_range(1000, 1500);
4983         }
4984 }
4985 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
4986
4987 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
4988                                       struct rt2x00lib_conf *libconf)
4989 {
4990         u32 reg;
4991
4992         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
4993         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT,
4994                            libconf->conf->short_frame_max_tx_count);
4995         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT,
4996                            libconf->conf->long_frame_max_tx_count);
4997         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
4998 }
4999
5000 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
5001                              struct rt2x00lib_conf *libconf)
5002 {
5003         enum dev_state state =
5004             (libconf->conf->flags & IEEE80211_CONF_PS) ?
5005                 STATE_SLEEP : STATE_AWAKE;
5006         u32 reg;
5007
5008         if (state == STATE_SLEEP) {
5009                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
5010
5011                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5012                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
5013                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
5014                                    libconf->conf->listen_interval - 1);
5015                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 1);
5016                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5017
5018                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5019         } else {
5020                 reg = rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG);
5021                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
5022                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
5023                 rt2x00_set_field32(&reg, AUTOWAKEUP_CFG_AUTOWAKE, 0);
5024                 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
5025
5026                 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
5027         }
5028 }
5029
5030 void rt2800_config(struct rt2x00_dev *rt2x00dev,
5031                    struct rt2x00lib_conf *libconf,
5032                    const unsigned int flags)
5033 {
5034         /* Always recalculate LNA gain before changing configuration */
5035         rt2800_config_lna_gain(rt2x00dev, libconf);
5036
5037         if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
5038                 rt2800_config_channel(rt2x00dev, libconf->conf,
5039                                       &libconf->rf, &libconf->channel);
5040                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5041                                       libconf->conf->power_level);
5042         }
5043         if (flags & IEEE80211_CONF_CHANGE_POWER)
5044                 rt2800_config_txpower(rt2x00dev, libconf->conf->chandef.chan,
5045                                       libconf->conf->power_level);
5046         if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
5047                 rt2800_config_retry_limit(rt2x00dev, libconf);
5048         if (flags & IEEE80211_CONF_CHANGE_PS)
5049                 rt2800_config_ps(rt2x00dev, libconf);
5050 }
5051 EXPORT_SYMBOL_GPL(rt2800_config);
5052
5053 /*
5054  * Link tuning
5055  */
5056 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5057 {
5058         u32 reg;
5059
5060         /*
5061          * Update FCS error count from register.
5062          */
5063         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5064         qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
5065 }
5066 EXPORT_SYMBOL_GPL(rt2800_link_stats);
5067
5068 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
5069 {
5070         u8 vgc;
5071
5072         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ) {
5073                 if (rt2x00_rt(rt2x00dev, RT3070) ||
5074                     rt2x00_rt(rt2x00dev, RT3071) ||
5075                     rt2x00_rt(rt2x00dev, RT3090) ||
5076                     rt2x00_rt(rt2x00dev, RT3290) ||
5077                     rt2x00_rt(rt2x00dev, RT3390) ||
5078                     rt2x00_rt(rt2x00dev, RT3572) ||
5079                     rt2x00_rt(rt2x00dev, RT3593) ||
5080                     rt2x00_rt(rt2x00dev, RT5390) ||
5081                     rt2x00_rt(rt2x00dev, RT5392) ||
5082                     rt2x00_rt(rt2x00dev, RT5592) ||
5083                     rt2x00_rt(rt2x00dev, RT6352))
5084                         vgc = 0x1c + (2 * rt2x00dev->lna_gain);
5085                 else
5086                         vgc = 0x2e + rt2x00dev->lna_gain;
5087         } else { /* 5GHZ band */
5088                 if (rt2x00_rt(rt2x00dev, RT3593))
5089                         vgc = 0x20 + (rt2x00dev->lna_gain * 5) / 3;
5090                 else if (rt2x00_rt(rt2x00dev, RT5592))
5091                         vgc = 0x24 + (2 * rt2x00dev->lna_gain);
5092                 else {
5093                         if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
5094                                 vgc = 0x32 + (rt2x00dev->lna_gain * 5) / 3;
5095                         else
5096                                 vgc = 0x3a + (rt2x00dev->lna_gain * 5) / 3;
5097                 }
5098         }
5099
5100         return vgc;
5101 }
5102
5103 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
5104                                   struct link_qual *qual, u8 vgc_level)
5105 {
5106         if (qual->vgc_level != vgc_level) {
5107                 if (rt2x00_rt(rt2x00dev, RT3572) ||
5108                     rt2x00_rt(rt2x00dev, RT3593)) {
5109                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66,
5110                                                        vgc_level);
5111                 } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5112                         rt2800_bbp_write(rt2x00dev, 83, qual->rssi > -65 ? 0x4a : 0x7a);
5113                         rt2800_bbp_write_with_rx_chain(rt2x00dev, 66, vgc_level);
5114                 } else {
5115                         rt2800_bbp_write(rt2x00dev, 66, vgc_level);
5116                 }
5117
5118                 qual->vgc_level = vgc_level;
5119                 qual->vgc_level_reg = vgc_level;
5120         }
5121 }
5122
5123 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
5124 {
5125         rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
5126 }
5127 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
5128
5129 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
5130                        const u32 count)
5131 {
5132         u8 vgc;
5133
5134         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
5135                 return;
5136
5137         /* When RSSI is better than a certain threshold, increase VGC
5138          * with a chip specific value in order to improve the balance
5139          * between sensibility and noise isolation.
5140          */
5141
5142         vgc = rt2800_get_default_vgc(rt2x00dev);
5143
5144         switch (rt2x00dev->chip.rt) {
5145         case RT3572:
5146         case RT3593:
5147                 if (qual->rssi > -65) {
5148                         if (rt2x00dev->curr_band == NL80211_BAND_2GHZ)
5149                                 vgc += 0x20;
5150                         else
5151                                 vgc += 0x10;
5152                 }
5153                 break;
5154
5155         case RT5592:
5156                 if (qual->rssi > -65)
5157                         vgc += 0x20;
5158                 break;
5159
5160         default:
5161                 if (qual->rssi > -80)
5162                         vgc += 0x10;
5163                 break;
5164         }
5165
5166         rt2800_set_vgc(rt2x00dev, qual, vgc);
5167 }
5168 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
5169
5170 /*
5171  * Initialization functions.
5172  */
5173 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
5174 {
5175         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
5176         u32 reg;
5177         u16 eeprom;
5178         unsigned int i;
5179         int ret;
5180
5181         rt2800_disable_wpdma(rt2x00dev);
5182
5183         ret = rt2800_drv_init_registers(rt2x00dev);
5184         if (ret)
5185                 return ret;
5186
5187         rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
5188         rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
5189
5190         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
5191
5192         reg = rt2800_register_read(rt2x00dev, BCN_TIME_CFG);
5193         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
5194         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_TICKING, 0);
5195         rt2x00_set_field32(&reg, BCN_TIME_CFG_TSF_SYNC, 0);
5196         rt2x00_set_field32(&reg, BCN_TIME_CFG_TBTT_ENABLE, 0);
5197         rt2x00_set_field32(&reg, BCN_TIME_CFG_BEACON_GEN, 0);
5198         rt2x00_set_field32(&reg, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
5199         rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
5200
5201         rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
5202
5203         reg = rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG);
5204         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_SLOT_TIME, 9);
5205         rt2x00_set_field32(&reg, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
5206         rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
5207
5208         if (rt2x00_rt(rt2x00dev, RT3290)) {
5209                 reg = rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL);
5210                 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
5211                         rt2x00_set_field32(&reg, PCIE_APP0_CLK_REQ, 1);
5212                         rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
5213                 }
5214
5215                 reg = rt2800_register_read(rt2x00dev, CMB_CTRL);
5216                 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
5217                         rt2x00_set_field32(&reg, LDO0_EN, 1);
5218                         rt2x00_set_field32(&reg, LDO_BGSEL, 3);
5219                         rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
5220                 }
5221
5222                 reg = rt2800_register_read(rt2x00dev, OSC_CTRL);
5223                 rt2x00_set_field32(&reg, OSC_ROSC_EN, 1);
5224                 rt2x00_set_field32(&reg, OSC_CAL_REQ, 1);
5225                 rt2x00_set_field32(&reg, OSC_REF_CYCLE, 0x27);
5226                 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
5227
5228                 reg = rt2800_register_read(rt2x00dev, COEX_CFG0);
5229                 rt2x00_set_field32(&reg, COEX_CFG_ANT, 0x5e);
5230                 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
5231
5232                 reg = rt2800_register_read(rt2x00dev, COEX_CFG2);
5233                 rt2x00_set_field32(&reg, BT_COEX_CFG1, 0x00);
5234                 rt2x00_set_field32(&reg, BT_COEX_CFG0, 0x17);
5235                 rt2x00_set_field32(&reg, WL_COEX_CFG1, 0x93);
5236                 rt2x00_set_field32(&reg, WL_COEX_CFG0, 0x7f);
5237                 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
5238
5239                 reg = rt2800_register_read(rt2x00dev, PLL_CTRL);
5240                 rt2x00_set_field32(&reg, PLL_CONTROL, 1);
5241                 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
5242         }
5243
5244         if (rt2x00_rt(rt2x00dev, RT3071) ||
5245             rt2x00_rt(rt2x00dev, RT3090) ||
5246             rt2x00_rt(rt2x00dev, RT3290) ||
5247             rt2x00_rt(rt2x00dev, RT3390)) {
5248
5249                 if (rt2x00_rt(rt2x00dev, RT3290))
5250                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5251                                               0x00000404);
5252                 else
5253                         rt2800_register_write(rt2x00dev, TX_SW_CFG0,
5254                                               0x00000400);
5255
5256                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5257                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
5258                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
5259                     rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
5260                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5261                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
5262                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5263                                                       0x0000002c);
5264                         else
5265                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5266                                                       0x0000000f);
5267                 } else {
5268                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5269                 }
5270         } else if (rt2x00_rt(rt2x00dev, RT3070)) {
5271                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5272
5273                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
5274                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5275                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
5276                 } else {
5277                         rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5278                         rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5279                 }
5280         } else if (rt2800_is_305x_soc(rt2x00dev)) {
5281                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5282                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5283                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
5284         } else if (rt2x00_rt(rt2x00dev, RT3352)) {
5285                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5286                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5287                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5288         } else if (rt2x00_rt(rt2x00dev, RT3572)) {
5289                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
5290                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5291         } else if (rt2x00_rt(rt2x00dev, RT3593)) {
5292                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000402);
5293                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5294                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3593, REV_RT3593E)) {
5295                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
5296                         if (rt2x00_get_field16(eeprom,
5297                                                EEPROM_NIC_CONF1_DAC_TEST))
5298                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5299                                                       0x0000001f);
5300                         else
5301                                 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5302                                                       0x0000000f);
5303                 } else {
5304                         rt2800_register_write(rt2x00dev, TX_SW_CFG2,
5305                                               0x00000000);
5306                 }
5307         } else if (rt2x00_rt(rt2x00dev, RT5390) ||
5308                    rt2x00_rt(rt2x00dev, RT5392) ||
5309                    rt2x00_rt(rt2x00dev, RT6352)) {
5310                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5311                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5312                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5313         } else if (rt2x00_rt(rt2x00dev, RT5592)) {
5314                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5315                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
5316                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5317         } else if (rt2x00_rt(rt2x00dev, RT5350)) {
5318                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
5319         } else if (rt2x00_rt(rt2x00dev, RT6352)) {
5320                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000401);
5321                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x000C0001);
5322                 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
5323                 rt2800_register_write(rt2x00dev, MIMO_PS_CFG, 0x00000002);
5324                 rt2800_register_write(rt2x00dev, TX_PIN_CFG, 0x00150F0F);
5325                 rt2800_register_write(rt2x00dev, TX_ALC_VGA3, 0x06060606);
5326                 rt2800_register_write(rt2x00dev, TX0_BB_GAIN_ATTEN, 0x0);
5327                 rt2800_register_write(rt2x00dev, TX1_BB_GAIN_ATTEN, 0x0);
5328                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_ATTEN, 0x6C6C666C);
5329                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_ATTEN, 0x6C6C666C);
5330                 rt2800_register_write(rt2x00dev, TX0_RF_GAIN_CORRECT,
5331                                       0x3630363A);
5332                 rt2800_register_write(rt2x00dev, TX1_RF_GAIN_CORRECT,
5333                                       0x3630363A);
5334                 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
5335                 rt2x00_set_field32(&reg, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
5336                 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
5337         } else {
5338                 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
5339                 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
5340         }
5341
5342         reg = rt2800_register_read(rt2x00dev, TX_LINK_CFG);
5343         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
5344         rt2x00_set_field32(&reg, TX_LINK_CFG_MFB_ENABLE, 0);
5345         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
5346         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_MRQ_EN, 0);
5347         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_RDG_EN, 0);
5348         rt2x00_set_field32(&reg, TX_LINK_CFG_TX_CF_ACK_EN, 1);
5349         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFB, 0);
5350         rt2x00_set_field32(&reg, TX_LINK_CFG_REMOTE_MFS, 0);
5351         rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
5352
5353         reg = rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG);
5354         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
5355         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
5356         rt2x00_set_field32(&reg, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
5357         rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
5358
5359         reg = rt2800_register_read(rt2x00dev, MAX_LEN_CFG);
5360         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
5361         if (rt2x00_is_usb(rt2x00dev)) {
5362                 drv_data->max_psdu = 3;
5363         } else if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
5364                    rt2x00_rt(rt2x00dev, RT2883) ||
5365                    rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E)) {
5366                 drv_data->max_psdu = 2;
5367         } else {
5368                 drv_data->max_psdu = 1;
5369         }
5370         rt2x00_set_field32(&reg, MAX_LEN_CFG_MAX_PSDU, drv_data->max_psdu);
5371         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_PSDU, 10);
5372         rt2x00_set_field32(&reg, MAX_LEN_CFG_MIN_MPDU, 10);
5373         rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
5374
5375         reg = rt2800_register_read(rt2x00dev, LED_CFG);
5376         rt2x00_set_field32(&reg, LED_CFG_ON_PERIOD, 70);
5377         rt2x00_set_field32(&reg, LED_CFG_OFF_PERIOD, 30);
5378         rt2x00_set_field32(&reg, LED_CFG_SLOW_BLINK_PERIOD, 3);
5379         rt2x00_set_field32(&reg, LED_CFG_R_LED_MODE, 3);
5380         rt2x00_set_field32(&reg, LED_CFG_G_LED_MODE, 3);
5381         rt2x00_set_field32(&reg, LED_CFG_Y_LED_MODE, 3);
5382         rt2x00_set_field32(&reg, LED_CFG_LED_POLAR, 1);
5383         rt2800_register_write(rt2x00dev, LED_CFG, reg);
5384
5385         rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
5386
5387         reg = rt2800_register_read(rt2x00dev, TX_RTY_CFG);
5388         rt2x00_set_field32(&reg, TX_RTY_CFG_SHORT_RTY_LIMIT, 2);
5389         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_LIMIT, 2);
5390         rt2x00_set_field32(&reg, TX_RTY_CFG_LONG_RTY_THRE, 2000);
5391         rt2x00_set_field32(&reg, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
5392         rt2x00_set_field32(&reg, TX_RTY_CFG_AGG_RTY_MODE, 0);
5393         rt2x00_set_field32(&reg, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
5394         rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
5395
5396         reg = rt2800_register_read(rt2x00dev, AUTO_RSP_CFG);
5397         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AUTORESPONDER, 1);
5398         rt2x00_set_field32(&reg, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
5399         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MMODE, 1);
5400         rt2x00_set_field32(&reg, AUTO_RSP_CFG_CTS_40_MREF, 0);
5401         rt2x00_set_field32(&reg, AUTO_RSP_CFG_AR_PREAMBLE, 0);
5402         rt2x00_set_field32(&reg, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
5403         rt2x00_set_field32(&reg, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
5404         rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
5405
5406         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
5407         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_RATE, 3);
5408         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_CTRL, 0);
5409         rt2x00_set_field32(&reg, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
5410         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5411         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5412         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5413         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5414         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5415         rt2x00_set_field32(&reg, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5416         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, 1);
5417         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
5418
5419         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
5420         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_RATE, 3);
5421         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_CTRL, 0);
5422         rt2x00_set_field32(&reg, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
5423         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
5424         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5425         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5426         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5427         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5428         rt2x00_set_field32(&reg, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5429         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, 1);
5430         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
5431
5432         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
5433         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
5434         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_CTRL, 1);
5435         rt2x00_set_field32(&reg, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5436         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5437         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5438         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5439         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5440         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5441         rt2x00_set_field32(&reg, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5442         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, 0);
5443         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
5444
5445         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
5446         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
5447         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_CTRL, 1);
5448         rt2x00_set_field32(&reg, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5449         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5450         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5451         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5452         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5453         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5454         rt2x00_set_field32(&reg, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5455         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, 0);
5456         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
5457
5458         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
5459         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
5460         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_CTRL, 1);
5461         rt2x00_set_field32(&reg, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
5462         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5463         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5464         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5465         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
5466         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5467         rt2x00_set_field32(&reg, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
5468         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, 0);
5469         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
5470
5471         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
5472         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
5473         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_CTRL, 1);
5474         rt2x00_set_field32(&reg, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
5475         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 0);
5476         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
5477         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
5478         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
5479         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
5480         rt2x00_set_field32(&reg, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
5481         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, 0);
5482         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
5483
5484         if (rt2x00_is_usb(rt2x00dev)) {
5485                 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
5486
5487                 reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
5488                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
5489                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
5490                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
5491                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
5492                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
5493                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
5494                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
5495                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
5496                 rt2x00_set_field32(&reg, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
5497                 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
5498         }
5499
5500         /*
5501          * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
5502          * although it is reserved.
5503          */
5504         reg = rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG);
5505         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
5506         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
5507         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
5508         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
5509         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
5510         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
5511         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
5512         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
5513         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
5514         rt2x00_set_field32(&reg, TXOP_CTRL_CFG_EXT_CWMIN, 0);
5515         rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
5516
5517         reg = rt2x00_rt(rt2x00dev, RT5592) ? 0x00000082 : 0x00000002;
5518         rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, reg);
5519
5520         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
5521         rt2x00_set_field32(&reg, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 7);
5522         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES,
5523                            IEEE80211_MAX_RTS_THRESHOLD);
5524         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_FBK_EN, 1);
5525         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
5526
5527         rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
5528
5529         /*
5530          * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
5531          * time should be set to 16. However, the original Ralink driver uses
5532          * 16 for both and indeed using a value of 10 for CCK SIFS results in
5533          * connection problems with 11g + CTS protection. Hence, use the same
5534          * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
5535          */
5536         reg = rt2800_register_read(rt2x00dev, XIFS_TIME_CFG);
5537         rt2x00_set_field32(&reg, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
5538         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
5539         rt2x00_set_field32(&reg, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
5540         rt2x00_set_field32(&reg, XIFS_TIME_CFG_EIFS, 314);
5541         rt2x00_set_field32(&reg, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
5542         rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
5543
5544         rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
5545
5546         /*
5547          * ASIC will keep garbage value after boot, clear encryption keys.
5548          */
5549         for (i = 0; i < 4; i++)
5550                 rt2800_register_write(rt2x00dev,
5551                                          SHARED_KEY_MODE_ENTRY(i), 0);
5552
5553         for (i = 0; i < 256; i++) {
5554                 rt2800_config_wcid(rt2x00dev, NULL, i);
5555                 rt2800_delete_wcid_attr(rt2x00dev, i);
5556                 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
5557         }
5558
5559         /*
5560          * Clear all beacons
5561          */
5562         for (i = 0; i < 8; i++)
5563                 rt2800_clear_beacon_register(rt2x00dev, i);
5564
5565         if (rt2x00_is_usb(rt2x00dev)) {
5566                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5567                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 30);
5568                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5569         } else if (rt2x00_is_pcie(rt2x00dev)) {
5570                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5571                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
5572                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5573         } else if (rt2x00_is_soc(rt2x00dev)) {
5574                 struct clk *clk = clk_get_sys("bus", NULL);
5575                 int rate;
5576
5577                 if (IS_ERR(clk)) {
5578                         clk = clk_get_sys("cpu", NULL);
5579
5580                         if (IS_ERR(clk)) {
5581                                 rate = 125;
5582                         } else {
5583                                 rate = clk_get_rate(clk) / 3000000;
5584                                 clk_put(clk);
5585                         }
5586                 } else {
5587                         rate = clk_get_rate(clk) / 1000000;
5588                         clk_put(clk);
5589                 }
5590
5591                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
5592                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
5593                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
5594         }
5595
5596         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);
5597         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS0FBK, 0);
5598         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS1FBK, 0);
5599         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS2FBK, 1);
5600         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS3FBK, 2);
5601         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS4FBK, 3);
5602         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS5FBK, 4);
5603         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS6FBK, 5);
5604         rt2x00_set_field32(&reg, HT_FBK_CFG0_HTMCS7FBK, 6);
5605         rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
5606
5607         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG1);
5608         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS8FBK, 8);
5609         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS9FBK, 8);
5610         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS10FBK, 9);
5611         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS11FBK, 10);
5612         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS12FBK, 11);
5613         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS13FBK, 12);
5614         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS14FBK, 13);
5615         rt2x00_set_field32(&reg, HT_FBK_CFG1_HTMCS15FBK, 14);
5616         rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
5617
5618         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG0);
5619         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS0FBK, 8);
5620         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS1FBK, 8);
5621         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS2FBK, 9);
5622         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS3FBK, 10);
5623         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS4FBK, 11);
5624         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS5FBK, 12);
5625         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS6FBK, 13);
5626         rt2x00_set_field32(&reg, LG_FBK_CFG0_OFDMMCS7FBK, 14);
5627         rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
5628
5629         reg = rt2800_register_read(rt2x00dev, LG_FBK_CFG1);
5630         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS0FBK, 0);
5631         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS1FBK, 0);
5632         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS2FBK, 1);
5633         rt2x00_set_field32(&reg, LG_FBK_CFG0_CCKMCS3FBK, 2);
5634         rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
5635
5636         /*
5637          * Do not force the BA window size, we use the TXWI to set it
5638          */
5639         reg = rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE);
5640         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
5641         rt2x00_set_field32(&reg, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
5642         rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
5643
5644         /*
5645          * We must clear the error counters.
5646          * These registers are cleared on read,
5647          * so we may pass a useless variable to store the value.
5648          */
5649         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT0);
5650         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT1);
5651         reg = rt2800_register_read(rt2x00dev, RX_STA_CNT2);
5652         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT0);
5653         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT1);
5654         reg = rt2800_register_read(rt2x00dev, TX_STA_CNT2);
5655
5656         /*
5657          * Setup leadtime for pre tbtt interrupt to 6ms
5658          */
5659         reg = rt2800_register_read(rt2x00dev, INT_TIMER_CFG);
5660         rt2x00_set_field32(&reg, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
5661         rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
5662
5663         /*
5664          * Set up channel statistics timer
5665          */
5666         reg = rt2800_register_read(rt2x00dev, CH_TIME_CFG);
5667         rt2x00_set_field32(&reg, CH_TIME_CFG_EIFS_BUSY, 1);
5668         rt2x00_set_field32(&reg, CH_TIME_CFG_NAV_BUSY, 1);
5669         rt2x00_set_field32(&reg, CH_TIME_CFG_RX_BUSY, 1);
5670         rt2x00_set_field32(&reg, CH_TIME_CFG_TX_BUSY, 1);
5671         rt2x00_set_field32(&reg, CH_TIME_CFG_TMR_EN, 1);
5672         rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
5673
5674         return 0;
5675 }
5676
5677 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
5678 {
5679         unsigned int i;
5680         u32 reg;
5681
5682         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5683                 reg = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
5684                 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
5685                         return 0;
5686
5687                 udelay(REGISTER_BUSY_DELAY);
5688         }
5689
5690         rt2x00_err(rt2x00dev, "BBP/RF register access failed, aborting\n");
5691         return -EACCES;
5692 }
5693
5694 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
5695 {
5696         unsigned int i;
5697         u8 value;
5698
5699         /*
5700          * BBP was enabled after firmware was loaded,
5701          * but we need to reactivate it now.
5702          */
5703         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
5704         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
5705         msleep(1);
5706
5707         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
5708                 value = rt2800_bbp_read(rt2x00dev, 0);
5709                 if ((value != 0xff) && (value != 0x00))
5710                         return 0;
5711                 udelay(REGISTER_BUSY_DELAY);
5712         }
5713
5714         rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n");
5715         return -EACCES;
5716 }
5717
5718 static void rt2800_bbp4_mac_if_ctrl(struct rt2x00_dev *rt2x00dev)
5719 {
5720         u8 value;
5721
5722         value = rt2800_bbp_read(rt2x00dev, 4);
5723         rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
5724         rt2800_bbp_write(rt2x00dev, 4, value);
5725 }
5726
5727 static void rt2800_init_freq_calibration(struct rt2x00_dev *rt2x00dev)
5728 {
5729         rt2800_bbp_write(rt2x00dev, 142, 1);
5730         rt2800_bbp_write(rt2x00dev, 143, 57);
5731 }
5732
5733 static void rt2800_init_bbp_5592_glrt(struct rt2x00_dev *rt2x00dev)
5734 {
5735         static const u8 glrt_table[] = {
5736                 0xE0, 0x1F, 0X38, 0x32, 0x08, 0x28, 0x19, 0x0A, 0xFF, 0x00, /* 128 ~ 137 */
5737                 0x16, 0x10, 0x10, 0x0B, 0x36, 0x2C, 0x26, 0x24, 0x42, 0x36, /* 138 ~ 147 */
5738                 0x30, 0x2D, 0x4C, 0x46, 0x3D, 0x40, 0x3E, 0x42, 0x3D, 0x40, /* 148 ~ 157 */
5739                 0X3C, 0x34, 0x2C, 0x2F, 0x3C, 0x35, 0x2E, 0x2A, 0x49, 0x41, /* 158 ~ 167 */
5740                 0x36, 0x31, 0x30, 0x30, 0x0E, 0x0D, 0x28, 0x21, 0x1C, 0x16, /* 168 ~ 177 */
5741                 0x50, 0x4A, 0x43, 0x40, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, /* 178 ~ 187 */
5742                 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 188 ~ 197 */
5743                 0x00, 0x00, 0x7D, 0x14, 0x32, 0x2C, 0x36, 0x4C, 0x43, 0x2C, /* 198 ~ 207 */
5744                 0x2E, 0x36, 0x30, 0x6E,                                     /* 208 ~ 211 */
5745         };
5746         int i;
5747
5748         for (i = 0; i < ARRAY_SIZE(glrt_table); i++) {
5749                 rt2800_bbp_write(rt2x00dev, 195, 128 + i);
5750                 rt2800_bbp_write(rt2x00dev, 196, glrt_table[i]);
5751         }
5752 };
5753
5754 static void rt2800_init_bbp_early(struct rt2x00_dev *rt2x00dev)
5755 {
5756         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
5757         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5758         rt2800_bbp_write(rt2x00dev, 68, 0x0B);
5759         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5760         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5761         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5762         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5763         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5764         rt2800_bbp_write(rt2x00dev, 83, 0x6A);
5765         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5766         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5767         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5768         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5769         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5770         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5771         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5772 }
5773
5774 static void rt2800_disable_unused_dac_adc(struct rt2x00_dev *rt2x00dev)
5775 {
5776         u16 eeprom;
5777         u8 value;
5778
5779         value = rt2800_bbp_read(rt2x00dev, 138);
5780         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
5781         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
5782                 value |= 0x20;
5783         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
5784                 value &= ~0x02;
5785         rt2800_bbp_write(rt2x00dev, 138, value);
5786 }
5787
5788 static void rt2800_init_bbp_305x_soc(struct rt2x00_dev *rt2x00dev)
5789 {
5790         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5791
5792         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5793         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5794
5795         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5796         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5797
5798         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5799
5800         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5801         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5802
5803         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5804
5805         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5806
5807         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5808
5809         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5810
5811         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5812
5813         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5814
5815         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5816
5817         rt2800_bbp_write(rt2x00dev, 105, 0x01);
5818
5819         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5820 }
5821
5822 static void rt2800_init_bbp_28xx(struct rt2x00_dev *rt2x00dev)
5823 {
5824         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5825         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5826
5827         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
5828                 rt2800_bbp_write(rt2x00dev, 69, 0x16);
5829                 rt2800_bbp_write(rt2x00dev, 73, 0x12);
5830         } else {
5831                 rt2800_bbp_write(rt2x00dev, 69, 0x12);
5832                 rt2800_bbp_write(rt2x00dev, 73, 0x10);
5833         }
5834
5835         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5836
5837         rt2800_bbp_write(rt2x00dev, 81, 0x37);
5838
5839         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5840
5841         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5842
5843         if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
5844                 rt2800_bbp_write(rt2x00dev, 84, 0x19);
5845         else
5846                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
5847
5848         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5849
5850         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5851
5852         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5853
5854         rt2800_bbp_write(rt2x00dev, 103, 0x00);
5855
5856         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5857
5858         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5859 }
5860
5861 static void rt2800_init_bbp_30xx(struct rt2x00_dev *rt2x00dev)
5862 {
5863         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5864         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5865
5866         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5867         rt2800_bbp_write(rt2x00dev, 73, 0x10);
5868
5869         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5870
5871         rt2800_bbp_write(rt2x00dev, 79, 0x13);
5872         rt2800_bbp_write(rt2x00dev, 80, 0x05);
5873         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5874
5875         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5876
5877         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
5878
5879         rt2800_bbp_write(rt2x00dev, 84, 0x99);
5880
5881         rt2800_bbp_write(rt2x00dev, 86, 0x00);
5882
5883         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5884
5885         rt2800_bbp_write(rt2x00dev, 92, 0x00);
5886
5887         if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
5888             rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
5889             rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E))
5890                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5891         else
5892                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
5893
5894         rt2800_bbp_write(rt2x00dev, 105, 0x05);
5895
5896         rt2800_bbp_write(rt2x00dev, 106, 0x35);
5897
5898         if (rt2x00_rt(rt2x00dev, RT3071) ||
5899             rt2x00_rt(rt2x00dev, RT3090))
5900                 rt2800_disable_unused_dac_adc(rt2x00dev);
5901 }
5902
5903 static void rt2800_init_bbp_3290(struct rt2x00_dev *rt2x00dev)
5904 {
5905         u8 value;
5906
5907         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
5908
5909         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5910
5911         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5912         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5913
5914         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5915
5916         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5917         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5918         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5919         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5920
5921         rt2800_bbp_write(rt2x00dev, 77, 0x58);
5922
5923         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5924
5925         rt2800_bbp_write(rt2x00dev, 74, 0x0b);
5926         rt2800_bbp_write(rt2x00dev, 79, 0x18);
5927         rt2800_bbp_write(rt2x00dev, 80, 0x09);
5928         rt2800_bbp_write(rt2x00dev, 81, 0x33);
5929
5930         rt2800_bbp_write(rt2x00dev, 82, 0x62);
5931
5932         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
5933
5934         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
5935
5936         rt2800_bbp_write(rt2x00dev, 86, 0x38);
5937
5938         rt2800_bbp_write(rt2x00dev, 91, 0x04);
5939
5940         rt2800_bbp_write(rt2x00dev, 92, 0x02);
5941
5942         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
5943
5944         rt2800_bbp_write(rt2x00dev, 104, 0x92);
5945
5946         rt2800_bbp_write(rt2x00dev, 105, 0x1c);
5947
5948         rt2800_bbp_write(rt2x00dev, 106, 0x03);
5949
5950         rt2800_bbp_write(rt2x00dev, 128, 0x12);
5951
5952         rt2800_bbp_write(rt2x00dev, 67, 0x24);
5953         rt2800_bbp_write(rt2x00dev, 143, 0x04);
5954         rt2800_bbp_write(rt2x00dev, 142, 0x99);
5955         rt2800_bbp_write(rt2x00dev, 150, 0x30);
5956         rt2800_bbp_write(rt2x00dev, 151, 0x2e);
5957         rt2800_bbp_write(rt2x00dev, 152, 0x20);
5958         rt2800_bbp_write(rt2x00dev, 153, 0x34);
5959         rt2800_bbp_write(rt2x00dev, 154, 0x40);
5960         rt2800_bbp_write(rt2x00dev, 155, 0x3b);
5961         rt2800_bbp_write(rt2x00dev, 253, 0x04);
5962
5963         value = rt2800_bbp_read(rt2x00dev, 47);
5964         rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
5965         rt2800_bbp_write(rt2x00dev, 47, value);
5966
5967         /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
5968         value = rt2800_bbp_read(rt2x00dev, 3);
5969         rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
5970         rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
5971         rt2800_bbp_write(rt2x00dev, 3, value);
5972 }
5973
5974 static void rt2800_init_bbp_3352(struct rt2x00_dev *rt2x00dev)
5975 {
5976         rt2800_bbp_write(rt2x00dev, 3, 0x00);
5977         rt2800_bbp_write(rt2x00dev, 4, 0x50);
5978
5979         rt2800_bbp_write(rt2x00dev, 31, 0x08);
5980
5981         rt2800_bbp_write(rt2x00dev, 47, 0x48);
5982
5983         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
5984         rt2800_bbp_write(rt2x00dev, 66, 0x38);
5985
5986         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
5987
5988         rt2800_bbp_write(rt2x00dev, 69, 0x12);
5989         rt2800_bbp_write(rt2x00dev, 73, 0x13);
5990         rt2800_bbp_write(rt2x00dev, 75, 0x46);
5991         rt2800_bbp_write(rt2x00dev, 76, 0x28);
5992
5993         rt2800_bbp_write(rt2x00dev, 77, 0x59);
5994
5995         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
5996
5997         rt2800_bbp_write(rt2x00dev, 78, 0x0e);
5998         rt2800_bbp_write(rt2x00dev, 80, 0x08);
5999         rt2800_bbp_write(rt2x00dev, 81, 0x37);
6000
6001         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6002
6003         if (rt2x00_rt(rt2x00dev, RT5350)) {
6004                 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6005                 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6006         } else {
6007                 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6008                 rt2800_bbp_write(rt2x00dev, 84, 0x99);
6009         }
6010
6011         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6012
6013         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6014
6015         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6016
6017         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6018
6019         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6020
6021         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6022
6023         if (rt2x00_rt(rt2x00dev, RT5350)) {
6024                 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6025                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6026         } else {
6027                 rt2800_bbp_write(rt2x00dev, 105, 0x34);
6028                 rt2800_bbp_write(rt2x00dev, 106, 0x05);
6029         }
6030
6031         rt2800_bbp_write(rt2x00dev, 120, 0x50);
6032
6033         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6034
6035         rt2800_bbp_write(rt2x00dev, 163, 0xbd);
6036         /* Set ITxBF timeout to 0x9c40=1000msec */
6037         rt2800_bbp_write(rt2x00dev, 179, 0x02);
6038         rt2800_bbp_write(rt2x00dev, 180, 0x00);
6039         rt2800_bbp_write(rt2x00dev, 182, 0x40);
6040         rt2800_bbp_write(rt2x00dev, 180, 0x01);
6041         rt2800_bbp_write(rt2x00dev, 182, 0x9c);
6042         rt2800_bbp_write(rt2x00dev, 179, 0x00);
6043         /* Reprogram the inband interface to put right values in RXWI */
6044         rt2800_bbp_write(rt2x00dev, 142, 0x04);
6045         rt2800_bbp_write(rt2x00dev, 143, 0x3b);
6046         rt2800_bbp_write(rt2x00dev, 142, 0x06);
6047         rt2800_bbp_write(rt2x00dev, 143, 0xa0);
6048         rt2800_bbp_write(rt2x00dev, 142, 0x07);
6049         rt2800_bbp_write(rt2x00dev, 143, 0xa1);
6050         rt2800_bbp_write(rt2x00dev, 142, 0x08);
6051         rt2800_bbp_write(rt2x00dev, 143, 0xa2);
6052
6053         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
6054
6055         if (rt2x00_rt(rt2x00dev, RT5350)) {
6056                 /* Antenna Software OFDM */
6057                 rt2800_bbp_write(rt2x00dev, 150, 0x40);
6058                 /* Antenna Software CCK */
6059                 rt2800_bbp_write(rt2x00dev, 151, 0x30);
6060                 rt2800_bbp_write(rt2x00dev, 152, 0xa3);
6061                 /* Clear previously selected antenna */
6062                 rt2800_bbp_write(rt2x00dev, 154, 0);
6063         }
6064 }
6065
6066 static void rt2800_init_bbp_3390(struct rt2x00_dev *rt2x00dev)
6067 {
6068         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6069         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6070
6071         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6072         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6073
6074         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6075
6076         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6077         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6078         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6079
6080         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6081
6082         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6083
6084         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6085
6086         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6087
6088         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6089
6090         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6091
6092         if (rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E))
6093                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6094         else
6095                 rt2800_bbp_write(rt2x00dev, 103, 0x00);
6096
6097         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6098
6099         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6100
6101         rt2800_disable_unused_dac_adc(rt2x00dev);
6102 }
6103
6104 static void rt2800_init_bbp_3572(struct rt2x00_dev *rt2x00dev)
6105 {
6106         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6107
6108         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6109         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6110
6111         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6112         rt2800_bbp_write(rt2x00dev, 73, 0x10);
6113
6114         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6115
6116         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6117         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6118         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6119
6120         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6121
6122         rt2800_bbp_write(rt2x00dev, 83, 0x6a);
6123
6124         rt2800_bbp_write(rt2x00dev, 84, 0x99);
6125
6126         rt2800_bbp_write(rt2x00dev, 86, 0x00);
6127
6128         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6129
6130         rt2800_bbp_write(rt2x00dev, 92, 0x00);
6131
6132         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6133
6134         rt2800_bbp_write(rt2x00dev, 105, 0x05);
6135
6136         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6137
6138         rt2800_disable_unused_dac_adc(rt2x00dev);
6139 }
6140
6141 static void rt2800_init_bbp_3593(struct rt2x00_dev *rt2x00dev)
6142 {
6143         rt2800_init_bbp_early(rt2x00dev);
6144
6145         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6146         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6147         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6148         rt2800_bbp_write(rt2x00dev, 137, 0x0f);
6149
6150         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6151
6152         /* Enable DC filter */
6153         if (rt2x00_rt_rev_gte(rt2x00dev, RT3593, REV_RT3593E))
6154                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6155 }
6156
6157 static void rt2800_init_bbp_53xx(struct rt2x00_dev *rt2x00dev)
6158 {
6159         int ant, div_mode;
6160         u16 eeprom;
6161         u8 value;
6162
6163         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6164
6165         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6166
6167         rt2800_bbp_write(rt2x00dev, 65, 0x2c);
6168         rt2800_bbp_write(rt2x00dev, 66, 0x38);
6169
6170         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
6171
6172         rt2800_bbp_write(rt2x00dev, 69, 0x12);
6173         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6174         rt2800_bbp_write(rt2x00dev, 75, 0x46);
6175         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6176
6177         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6178
6179         rt2800_bbp_write(rt2x00dev, 70, 0x0a);
6180
6181         rt2800_bbp_write(rt2x00dev, 79, 0x13);
6182         rt2800_bbp_write(rt2x00dev, 80, 0x05);
6183         rt2800_bbp_write(rt2x00dev, 81, 0x33);
6184
6185         rt2800_bbp_write(rt2x00dev, 82, 0x62);
6186
6187         rt2800_bbp_write(rt2x00dev, 83, 0x7a);
6188
6189         rt2800_bbp_write(rt2x00dev, 84, 0x9a);
6190
6191         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6192
6193         if (rt2x00_rt(rt2x00dev, RT5392))
6194                 rt2800_bbp_write(rt2x00dev, 88, 0x90);
6195
6196         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6197
6198         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6199
6200         if (rt2x00_rt(rt2x00dev, RT5392)) {
6201                 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6202                 rt2800_bbp_write(rt2x00dev, 98, 0x12);
6203         }
6204
6205         rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6206
6207         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6208
6209         rt2800_bbp_write(rt2x00dev, 105, 0x3c);
6210
6211         if (rt2x00_rt(rt2x00dev, RT5390))
6212                 rt2800_bbp_write(rt2x00dev, 106, 0x03);
6213         else if (rt2x00_rt(rt2x00dev, RT5392))
6214                 rt2800_bbp_write(rt2x00dev, 106, 0x12);
6215         else
6216                 WARN_ON(1);
6217
6218         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6219
6220         if (rt2x00_rt(rt2x00dev, RT5392)) {
6221                 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
6222                 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
6223         }
6224
6225         rt2800_disable_unused_dac_adc(rt2x00dev);
6226
6227         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6228         div_mode = rt2x00_get_field16(eeprom,
6229                                       EEPROM_NIC_CONF1_ANT_DIVERSITY);
6230         ant = (div_mode == 3) ? 1 : 0;
6231
6232         /* check if this is a Bluetooth combo card */
6233         if (rt2x00_has_cap_bt_coexist(rt2x00dev)) {
6234                 u32 reg;
6235
6236                 reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
6237                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR3, 0);
6238                 rt2x00_set_field32(&reg, GPIO_CTRL_DIR6, 0);
6239                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 0);
6240                 rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 0);
6241                 if (ant == 0)
6242                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL3, 1);
6243                 else if (ant == 1)
6244                         rt2x00_set_field32(&reg, GPIO_CTRL_VAL6, 1);
6245                 rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
6246         }
6247
6248         /* This chip has hardware antenna diversity*/
6249         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
6250                 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
6251                 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
6252                 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
6253         }
6254
6255         value = rt2800_bbp_read(rt2x00dev, 152);
6256         if (ant == 0)
6257                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6258         else
6259                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6260         rt2800_bbp_write(rt2x00dev, 152, value);
6261
6262         rt2800_init_freq_calibration(rt2x00dev);
6263 }
6264
6265 static void rt2800_init_bbp_5592(struct rt2x00_dev *rt2x00dev)
6266 {
6267         int ant, div_mode;
6268         u16 eeprom;
6269         u8 value;
6270
6271         rt2800_init_bbp_early(rt2x00dev);
6272
6273         value = rt2800_bbp_read(rt2x00dev, 105);
6274         rt2x00_set_field8(&value, BBP105_MLD,
6275                           rt2x00dev->default_ant.rx_chain_num == 2);
6276         rt2800_bbp_write(rt2x00dev, 105, value);
6277
6278         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6279
6280         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6281         rt2800_bbp_write(rt2x00dev, 31, 0x08);
6282         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6283         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6284         rt2800_bbp_write(rt2x00dev, 69, 0x1A);
6285         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6286         rt2800_bbp_write(rt2x00dev, 73, 0x13);
6287         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6288         rt2800_bbp_write(rt2x00dev, 75, 0x4F);
6289         rt2800_bbp_write(rt2x00dev, 76, 0x28);
6290         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6291         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6292         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6293         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6294         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6295         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6296         rt2800_bbp_write(rt2x00dev, 95, 0x9a);
6297         rt2800_bbp_write(rt2x00dev, 98, 0x12);
6298         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6299         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6300         /* FIXME BBP105 owerwrite */
6301         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6302         rt2800_bbp_write(rt2x00dev, 106, 0x35);
6303         rt2800_bbp_write(rt2x00dev, 128, 0x12);
6304         rt2800_bbp_write(rt2x00dev, 134, 0xD0);
6305         rt2800_bbp_write(rt2x00dev, 135, 0xF6);
6306         rt2800_bbp_write(rt2x00dev, 137, 0x0F);
6307
6308         /* Initialize GLRT (Generalized Likehood Radio Test) */
6309         rt2800_init_bbp_5592_glrt(rt2x00dev);
6310
6311         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6312
6313         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6314         div_mode = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_ANT_DIVERSITY);
6315         ant = (div_mode == 3) ? 1 : 0;
6316         value = rt2800_bbp_read(rt2x00dev, 152);
6317         if (ant == 0) {
6318                 /* Main antenna */
6319                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
6320         } else {
6321                 /* Auxiliary antenna */
6322                 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
6323         }
6324         rt2800_bbp_write(rt2x00dev, 152, value);
6325
6326         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C)) {
6327                 value = rt2800_bbp_read(rt2x00dev, 254);
6328                 rt2x00_set_field8(&value, BBP254_BIT7, 1);
6329                 rt2800_bbp_write(rt2x00dev, 254, value);
6330         }
6331
6332         rt2800_init_freq_calibration(rt2x00dev);
6333
6334         rt2800_bbp_write(rt2x00dev, 84, 0x19);
6335         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
6336                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
6337 }
6338
6339 static void rt2800_bbp_glrt_write(struct rt2x00_dev *rt2x00dev,
6340                                   const u8 reg, const u8 value)
6341 {
6342         rt2800_bbp_write(rt2x00dev, 195, reg);
6343         rt2800_bbp_write(rt2x00dev, 196, value);
6344 }
6345
6346 static void rt2800_bbp_dcoc_write(struct rt2x00_dev *rt2x00dev,
6347                                   const u8 reg, const u8 value)
6348 {
6349         rt2800_bbp_write(rt2x00dev, 158, reg);
6350         rt2800_bbp_write(rt2x00dev, 159, value);
6351 }
6352
6353 static u8 rt2800_bbp_dcoc_read(struct rt2x00_dev *rt2x00dev, const u8 reg)
6354 {
6355         rt2800_bbp_write(rt2x00dev, 158, reg);
6356         return rt2800_bbp_read(rt2x00dev, 159);
6357 }
6358
6359 static void rt2800_init_bbp_6352(struct rt2x00_dev *rt2x00dev)
6360 {
6361         u8 bbp;
6362
6363         /* Apply Maximum Likelihood Detection (MLD) for 2 stream case */
6364         bbp = rt2800_bbp_read(rt2x00dev, 105);
6365         rt2x00_set_field8(&bbp, BBP105_MLD,
6366                           rt2x00dev->default_ant.rx_chain_num == 2);
6367         rt2800_bbp_write(rt2x00dev, 105, bbp);
6368
6369         /* Avoid data loss and CRC errors */
6370         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6371
6372         /* Fix I/Q swap issue */
6373         bbp = rt2800_bbp_read(rt2x00dev, 1);
6374         bbp |= 0x04;
6375         rt2800_bbp_write(rt2x00dev, 1, bbp);
6376
6377         /* BBP for G band */
6378         rt2800_bbp_write(rt2x00dev, 3, 0x08);
6379         rt2800_bbp_write(rt2x00dev, 4, 0x00); /* rt2800_bbp4_mac_if_ctrl? */
6380         rt2800_bbp_write(rt2x00dev, 6, 0x08);
6381         rt2800_bbp_write(rt2x00dev, 14, 0x09);
6382         rt2800_bbp_write(rt2x00dev, 15, 0xFF);
6383         rt2800_bbp_write(rt2x00dev, 16, 0x01);
6384         rt2800_bbp_write(rt2x00dev, 20, 0x06);
6385         rt2800_bbp_write(rt2x00dev, 21, 0x00);
6386         rt2800_bbp_write(rt2x00dev, 22, 0x00);
6387         rt2800_bbp_write(rt2x00dev, 27, 0x00);
6388         rt2800_bbp_write(rt2x00dev, 28, 0x00);
6389         rt2800_bbp_write(rt2x00dev, 30, 0x00);
6390         rt2800_bbp_write(rt2x00dev, 31, 0x48);
6391         rt2800_bbp_write(rt2x00dev, 47, 0x40);
6392         rt2800_bbp_write(rt2x00dev, 62, 0x00);
6393         rt2800_bbp_write(rt2x00dev, 63, 0x00);
6394         rt2800_bbp_write(rt2x00dev, 64, 0x00);
6395         rt2800_bbp_write(rt2x00dev, 65, 0x2C);
6396         rt2800_bbp_write(rt2x00dev, 66, 0x1C);
6397         rt2800_bbp_write(rt2x00dev, 67, 0x20);
6398         rt2800_bbp_write(rt2x00dev, 68, 0xDD);
6399         rt2800_bbp_write(rt2x00dev, 69, 0x10);
6400         rt2800_bbp_write(rt2x00dev, 70, 0x05);
6401         rt2800_bbp_write(rt2x00dev, 73, 0x18);
6402         rt2800_bbp_write(rt2x00dev, 74, 0x0F);
6403         rt2800_bbp_write(rt2x00dev, 75, 0x60);
6404         rt2800_bbp_write(rt2x00dev, 76, 0x44);
6405         rt2800_bbp_write(rt2x00dev, 77, 0x59);
6406         rt2800_bbp_write(rt2x00dev, 78, 0x1E);
6407         rt2800_bbp_write(rt2x00dev, 79, 0x1C);
6408         rt2800_bbp_write(rt2x00dev, 80, 0x0C);
6409         rt2800_bbp_write(rt2x00dev, 81, 0x3A);
6410         rt2800_bbp_write(rt2x00dev, 82, 0xB6);
6411         rt2800_bbp_write(rt2x00dev, 83, 0x9A);
6412         rt2800_bbp_write(rt2x00dev, 84, 0x9A);
6413         rt2800_bbp_write(rt2x00dev, 86, 0x38);
6414         rt2800_bbp_write(rt2x00dev, 88, 0x90);
6415         rt2800_bbp_write(rt2x00dev, 91, 0x04);
6416         rt2800_bbp_write(rt2x00dev, 92, 0x02);
6417         rt2800_bbp_write(rt2x00dev, 95, 0x9A);
6418         rt2800_bbp_write(rt2x00dev, 96, 0x00);
6419         rt2800_bbp_write(rt2x00dev, 103, 0xC0);
6420         rt2800_bbp_write(rt2x00dev, 104, 0x92);
6421         /* FIXME BBP105 owerwrite */
6422         rt2800_bbp_write(rt2x00dev, 105, 0x3C);
6423         rt2800_bbp_write(rt2x00dev, 106, 0x12);
6424         rt2800_bbp_write(rt2x00dev, 109, 0x00);
6425         rt2800_bbp_write(rt2x00dev, 134, 0x10);
6426         rt2800_bbp_write(rt2x00dev, 135, 0xA6);
6427         rt2800_bbp_write(rt2x00dev, 137, 0x04);
6428         rt2800_bbp_write(rt2x00dev, 142, 0x30);
6429         rt2800_bbp_write(rt2x00dev, 143, 0xF7);
6430         rt2800_bbp_write(rt2x00dev, 160, 0xEC);
6431         rt2800_bbp_write(rt2x00dev, 161, 0xC4);
6432         rt2800_bbp_write(rt2x00dev, 162, 0x77);
6433         rt2800_bbp_write(rt2x00dev, 163, 0xF9);
6434         rt2800_bbp_write(rt2x00dev, 164, 0x00);
6435         rt2800_bbp_write(rt2x00dev, 165, 0x00);
6436         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6437         rt2800_bbp_write(rt2x00dev, 187, 0x00);
6438         rt2800_bbp_write(rt2x00dev, 188, 0x00);
6439         rt2800_bbp_write(rt2x00dev, 186, 0x00);
6440         rt2800_bbp_write(rt2x00dev, 187, 0x01);
6441         rt2800_bbp_write(rt2x00dev, 188, 0x00);
6442         rt2800_bbp_write(rt2x00dev, 189, 0x00);
6443
6444         rt2800_bbp_write(rt2x00dev, 91, 0x06);
6445         rt2800_bbp_write(rt2x00dev, 92, 0x04);
6446         rt2800_bbp_write(rt2x00dev, 93, 0x54);
6447         rt2800_bbp_write(rt2x00dev, 99, 0x50);
6448         rt2800_bbp_write(rt2x00dev, 148, 0x84);
6449         rt2800_bbp_write(rt2x00dev, 167, 0x80);
6450         rt2800_bbp_write(rt2x00dev, 178, 0xFF);
6451         rt2800_bbp_write(rt2x00dev, 106, 0x13);
6452
6453         /* BBP for G band GLRT function (BBP_128 ~ BBP_221) */
6454         rt2800_bbp_glrt_write(rt2x00dev, 0, 0x00);
6455         rt2800_bbp_glrt_write(rt2x00dev, 1, 0x14);
6456         rt2800_bbp_glrt_write(rt2x00dev, 2, 0x20);
6457         rt2800_bbp_glrt_write(rt2x00dev, 3, 0x0A);
6458         rt2800_bbp_glrt_write(rt2x00dev, 10, 0x16);
6459         rt2800_bbp_glrt_write(rt2x00dev, 11, 0x06);
6460         rt2800_bbp_glrt_write(rt2x00dev, 12, 0x02);
6461         rt2800_bbp_glrt_write(rt2x00dev, 13, 0x07);
6462         rt2800_bbp_glrt_write(rt2x00dev, 14, 0x05);
6463         rt2800_bbp_glrt_write(rt2x00dev, 15, 0x09);
6464         rt2800_bbp_glrt_write(rt2x00dev, 16, 0x20);
6465         rt2800_bbp_glrt_write(rt2x00dev, 17, 0x08);
6466         rt2800_bbp_glrt_write(rt2x00dev, 18, 0x4A);
6467         rt2800_bbp_glrt_write(rt2x00dev, 19, 0x00);
6468         rt2800_bbp_glrt_write(rt2x00dev, 20, 0x00);
6469         rt2800_bbp_glrt_write(rt2x00dev, 128, 0xE0);
6470         rt2800_bbp_glrt_write(rt2x00dev, 129, 0x1F);
6471         rt2800_bbp_glrt_write(rt2x00dev, 130, 0x4F);
6472         rt2800_bbp_glrt_write(rt2x00dev, 131, 0x32);
6473         rt2800_bbp_glrt_write(rt2x00dev, 132, 0x08);
6474         rt2800_bbp_glrt_write(rt2x00dev, 133, 0x28);
6475         rt2800_bbp_glrt_write(rt2x00dev, 134, 0x19);
6476         rt2800_bbp_glrt_write(rt2x00dev, 135, 0x0A);
6477         rt2800_bbp_glrt_write(rt2x00dev, 138, 0x16);
6478         rt2800_bbp_glrt_write(rt2x00dev, 139, 0x10);
6479         rt2800_bbp_glrt_write(rt2x00dev, 140, 0x10);
6480         rt2800_bbp_glrt_write(rt2x00dev, 141, 0x1A);
6481         rt2800_bbp_glrt_write(rt2x00dev, 142, 0x36);
6482         rt2800_bbp_glrt_write(rt2x00dev, 143, 0x2C);
6483         rt2800_bbp_glrt_write(rt2x00dev, 144, 0x26);
6484         rt2800_bbp_glrt_write(rt2x00dev, 145, 0x24);
6485         rt2800_bbp_glrt_write(rt2x00dev, 146, 0x42);
6486         rt2800_bbp_glrt_write(rt2x00dev, 147, 0x40);
6487         rt2800_bbp_glrt_write(rt2x00dev, 148, 0x30);
6488         rt2800_bbp_glrt_write(rt2x00dev, 149, 0x29);
6489         rt2800_bbp_glrt_write(rt2x00dev, 150, 0x4C);
6490         rt2800_bbp_glrt_write(rt2x00dev, 151, 0x46);
6491         rt2800_bbp_glrt_write(rt2x00dev, 152, 0x3D);
6492         rt2800_bbp_glrt_write(rt2x00dev, 153, 0x40);
6493         rt2800_bbp_glrt_write(rt2x00dev, 154, 0x3E);
6494         rt2800_bbp_glrt_write(rt2x00dev, 155, 0x38);
6495         rt2800_bbp_glrt_write(rt2x00dev, 156, 0x3D);
6496         rt2800_bbp_glrt_write(rt2x00dev, 157, 0x2F);
6497         rt2800_bbp_glrt_write(rt2x00dev, 158, 0x3C);
6498         rt2800_bbp_glrt_write(rt2x00dev, 159, 0x34);
6499         rt2800_bbp_glrt_write(rt2x00dev, 160, 0x2C);
6500         rt2800_bbp_glrt_write(rt2x00dev, 161, 0x2F);
6501         rt2800_bbp_glrt_write(rt2x00dev, 162, 0x3C);
6502         rt2800_bbp_glrt_write(rt2x00dev, 163, 0x35);
6503         rt2800_bbp_glrt_write(rt2x00dev, 164, 0x2E);
6504         rt2800_bbp_glrt_write(rt2x00dev, 165, 0x2F);
6505         rt2800_bbp_glrt_write(rt2x00dev, 166, 0x49);
6506         rt2800_bbp_glrt_write(rt2x00dev, 167, 0x41);
6507         rt2800_bbp_glrt_write(rt2x00dev, 168, 0x36);
6508         rt2800_bbp_glrt_write(rt2x00dev, 169, 0x39);
6509         rt2800_bbp_glrt_write(rt2x00dev, 170, 0x30);
6510         rt2800_bbp_glrt_write(rt2x00dev, 171, 0x30);
6511         rt2800_bbp_glrt_write(rt2x00dev, 172, 0x0E);
6512         rt2800_bbp_glrt_write(rt2x00dev, 173, 0x0D);
6513         rt2800_bbp_glrt_write(rt2x00dev, 174, 0x28);
6514         rt2800_bbp_glrt_write(rt2x00dev, 175, 0x21);
6515         rt2800_bbp_glrt_write(rt2x00dev, 176, 0x1C);
6516         rt2800_bbp_glrt_write(rt2x00dev, 177, 0x16);
6517         rt2800_bbp_glrt_write(rt2x00dev, 178, 0x50);
6518         rt2800_bbp_glrt_write(rt2x00dev, 179, 0x4A);
6519         rt2800_bbp_glrt_write(rt2x00dev, 180, 0x43);
6520         rt2800_bbp_glrt_write(rt2x00dev, 181, 0x50);
6521         rt2800_bbp_glrt_write(rt2x00dev, 182, 0x10);
6522         rt2800_bbp_glrt_write(rt2x00dev, 183, 0x10);
6523         rt2800_bbp_glrt_write(rt2x00dev, 184, 0x10);
6524         rt2800_bbp_glrt_write(rt2x00dev, 185, 0x10);
6525         rt2800_bbp_glrt_write(rt2x00dev, 200, 0x7D);
6526         rt2800_bbp_glrt_write(rt2x00dev, 201, 0x14);
6527         rt2800_bbp_glrt_write(rt2x00dev, 202, 0x32);
6528         rt2800_bbp_glrt_write(rt2x00dev, 203, 0x2C);
6529         rt2800_bbp_glrt_write(rt2x00dev, 204, 0x36);
6530         rt2800_bbp_glrt_write(rt2x00dev, 205, 0x4C);
6531         rt2800_bbp_glrt_write(rt2x00dev, 206, 0x43);
6532         rt2800_bbp_glrt_write(rt2x00dev, 207, 0x2C);
6533         rt2800_bbp_glrt_write(rt2x00dev, 208, 0x2E);
6534         rt2800_bbp_glrt_write(rt2x00dev, 209, 0x36);
6535         rt2800_bbp_glrt_write(rt2x00dev, 210, 0x30);
6536         rt2800_bbp_glrt_write(rt2x00dev, 211, 0x6E);
6537
6538         /* BBP for G band DCOC function */
6539         rt2800_bbp_dcoc_write(rt2x00dev, 140, 0x0C);
6540         rt2800_bbp_dcoc_write(rt2x00dev, 141, 0x00);
6541         rt2800_bbp_dcoc_write(rt2x00dev, 142, 0x10);
6542         rt2800_bbp_dcoc_write(rt2x00dev, 143, 0x10);
6543         rt2800_bbp_dcoc_write(rt2x00dev, 144, 0x10);
6544         rt2800_bbp_dcoc_write(rt2x00dev, 145, 0x10);
6545         rt2800_bbp_dcoc_write(rt2x00dev, 146, 0x08);
6546         rt2800_bbp_dcoc_write(rt2x00dev, 147, 0x40);
6547         rt2800_bbp_dcoc_write(rt2x00dev, 148, 0x04);
6548         rt2800_bbp_dcoc_write(rt2x00dev, 149, 0x04);
6549         rt2800_bbp_dcoc_write(rt2x00dev, 150, 0x08);
6550         rt2800_bbp_dcoc_write(rt2x00dev, 151, 0x08);
6551         rt2800_bbp_dcoc_write(rt2x00dev, 152, 0x03);
6552         rt2800_bbp_dcoc_write(rt2x00dev, 153, 0x03);
6553         rt2800_bbp_dcoc_write(rt2x00dev, 154, 0x03);
6554         rt2800_bbp_dcoc_write(rt2x00dev, 155, 0x02);
6555         rt2800_bbp_dcoc_write(rt2x00dev, 156, 0x40);
6556         rt2800_bbp_dcoc_write(rt2x00dev, 157, 0x40);
6557         rt2800_bbp_dcoc_write(rt2x00dev, 158, 0x64);
6558         rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
6559
6560         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6561 }
6562
6563 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
6564 {
6565         unsigned int i;
6566         u16 eeprom;
6567         u8 reg_id;
6568         u8 value;
6569
6570         if (rt2800_is_305x_soc(rt2x00dev))
6571                 rt2800_init_bbp_305x_soc(rt2x00dev);
6572
6573         switch (rt2x00dev->chip.rt) {
6574         case RT2860:
6575         case RT2872:
6576         case RT2883:
6577                 rt2800_init_bbp_28xx(rt2x00dev);
6578                 break;
6579         case RT3070:
6580         case RT3071:
6581         case RT3090:
6582                 rt2800_init_bbp_30xx(rt2x00dev);
6583                 break;
6584         case RT3290:
6585                 rt2800_init_bbp_3290(rt2x00dev);
6586                 break;
6587         case RT3352:
6588         case RT5350:
6589                 rt2800_init_bbp_3352(rt2x00dev);
6590                 break;
6591         case RT3390:
6592                 rt2800_init_bbp_3390(rt2x00dev);
6593                 break;
6594         case RT3572:
6595                 rt2800_init_bbp_3572(rt2x00dev);
6596                 break;
6597         case RT3593:
6598                 rt2800_init_bbp_3593(rt2x00dev);
6599                 return;
6600         case RT5390:
6601         case RT5392:
6602                 rt2800_init_bbp_53xx(rt2x00dev);
6603                 break;
6604         case RT5592:
6605                 rt2800_init_bbp_5592(rt2x00dev);
6606                 return;
6607         case RT6352:
6608                 rt2800_init_bbp_6352(rt2x00dev);
6609                 break;
6610         }
6611
6612         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
6613                 eeprom = rt2800_eeprom_read_from_array(rt2x00dev,
6614                                                        EEPROM_BBP_START, i);
6615
6616                 if (eeprom != 0xffff && eeprom != 0x0000) {
6617                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
6618                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
6619                         rt2800_bbp_write(rt2x00dev, reg_id, value);
6620                 }
6621         }
6622 }
6623
6624 static void rt2800_led_open_drain_enable(struct rt2x00_dev *rt2x00dev)
6625 {
6626         u32 reg;
6627
6628         reg = rt2800_register_read(rt2x00dev, OPT_14_CSR);
6629         rt2x00_set_field32(&reg, OPT_14_CSR_BIT0, 1);
6630         rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
6631 }
6632
6633 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev, bool bw40,
6634                                 u8 filter_target)
6635 {
6636         unsigned int i;
6637         u8 bbp;
6638         u8 rfcsr;
6639         u8 passband;
6640         u8 stopband;
6641         u8 overtuned = 0;
6642         u8 rfcsr24 = (bw40) ? 0x27 : 0x07;
6643
6644         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6645
6646         bbp = rt2800_bbp_read(rt2x00dev, 4);
6647         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
6648         rt2800_bbp_write(rt2x00dev, 4, bbp);
6649
6650         rfcsr = rt2800_rfcsr_read(rt2x00dev, 31);
6651         rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
6652         rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
6653
6654         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6655         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
6656         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6657
6658         /*
6659          * Set power & frequency of passband test tone
6660          */
6661         rt2800_bbp_write(rt2x00dev, 24, 0);
6662
6663         for (i = 0; i < 100; i++) {
6664                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6665                 msleep(1);
6666
6667                 passband = rt2800_bbp_read(rt2x00dev, 55);
6668                 if (passband)
6669                         break;
6670         }
6671
6672         /*
6673          * Set power & frequency of stopband test tone
6674          */
6675         rt2800_bbp_write(rt2x00dev, 24, 0x06);
6676
6677         for (i = 0; i < 100; i++) {
6678                 rt2800_bbp_write(rt2x00dev, 25, 0x90);
6679                 msleep(1);
6680
6681                 stopband = rt2800_bbp_read(rt2x00dev, 55);
6682
6683                 if ((passband - stopband) <= filter_target) {
6684                         rfcsr24++;
6685                         overtuned += ((passband - stopband) == filter_target);
6686                 } else
6687                         break;
6688
6689                 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6690         }
6691
6692         rfcsr24 -= !!overtuned;
6693
6694         rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
6695         return rfcsr24;
6696 }
6697
6698 static void rt2800_rf_init_calibration(struct rt2x00_dev *rt2x00dev,
6699                                        const unsigned int rf_reg)
6700 {
6701         u8 rfcsr;
6702
6703         rfcsr = rt2800_rfcsr_read(rt2x00dev, rf_reg);
6704         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 1);
6705         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6706         msleep(1);
6707         rt2x00_set_field8(&rfcsr, FIELD8(0x80), 0);
6708         rt2800_rfcsr_write(rt2x00dev, rf_reg, rfcsr);
6709 }
6710
6711 static void rt2800_rx_filter_calibration(struct rt2x00_dev *rt2x00dev)
6712 {
6713         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6714         u8 filter_tgt_bw20;
6715         u8 filter_tgt_bw40;
6716         u8 rfcsr, bbp;
6717
6718         /*
6719          * TODO: sync filter_tgt values with vendor driver
6720          */
6721         if (rt2x00_rt(rt2x00dev, RT3070)) {
6722                 filter_tgt_bw20 = 0x16;
6723                 filter_tgt_bw40 = 0x19;
6724         } else {
6725                 filter_tgt_bw20 = 0x13;
6726                 filter_tgt_bw40 = 0x15;
6727         }
6728
6729         drv_data->calibration_bw20 =
6730                 rt2800_init_rx_filter(rt2x00dev, false, filter_tgt_bw20);
6731         drv_data->calibration_bw40 =
6732                 rt2800_init_rx_filter(rt2x00dev, true, filter_tgt_bw40);
6733
6734         /*
6735          * Save BBP 25 & 26 values for later use in channel switching (for 3052)
6736          */
6737         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
6738         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
6739
6740         /*
6741          * Set back to initial state
6742          */
6743         rt2800_bbp_write(rt2x00dev, 24, 0);
6744
6745         rfcsr = rt2800_rfcsr_read(rt2x00dev, 22);
6746         rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
6747         rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
6748
6749         /*
6750          * Set BBP back to BW20
6751          */
6752         bbp = rt2800_bbp_read(rt2x00dev, 4);
6753         rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
6754         rt2800_bbp_write(rt2x00dev, 4, bbp);
6755 }
6756
6757 static void rt2800_normal_mode_setup_3xxx(struct rt2x00_dev *rt2x00dev)
6758 {
6759         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6760         u8 min_gain, rfcsr, bbp;
6761         u16 eeprom;
6762
6763         rfcsr = rt2800_rfcsr_read(rt2x00dev, 17);
6764
6765         rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
6766         if (rt2x00_rt(rt2x00dev, RT3070) ||
6767             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6768             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
6769             rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
6770                 if (!rt2x00_has_cap_external_lna_bg(rt2x00dev))
6771                         rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
6772         }
6773
6774         min_gain = rt2x00_rt(rt2x00dev, RT3070) ? 1 : 2;
6775         if (drv_data->txmixer_gain_24g >= min_gain) {
6776                 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
6777                                   drv_data->txmixer_gain_24g);
6778         }
6779
6780         rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
6781
6782         if (rt2x00_rt(rt2x00dev, RT3090)) {
6783                 /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
6784                 bbp = rt2800_bbp_read(rt2x00dev, 138);
6785                 eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6786                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6787                         rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
6788                 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6789                         rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
6790                 rt2800_bbp_write(rt2x00dev, 138, bbp);
6791         }
6792
6793         if (rt2x00_rt(rt2x00dev, RT3070)) {
6794                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 27);
6795                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
6796                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
6797                 else
6798                         rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
6799                 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
6800                 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
6801                 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
6802                 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
6803         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6804                    rt2x00_rt(rt2x00dev, RT3090) ||
6805                    rt2x00_rt(rt2x00dev, RT3390)) {
6806                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6807                 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6808                 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
6809                 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
6810                 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
6811                 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
6812                 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6813
6814                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 15);
6815                 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
6816                 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
6817
6818                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 20);
6819                 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
6820                 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
6821
6822                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 21);
6823                 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
6824                 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
6825         }
6826 }
6827
6828 static void rt2800_normal_mode_setup_3593(struct rt2x00_dev *rt2x00dev)
6829 {
6830         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
6831         u8 rfcsr;
6832         u8 tx_gain;
6833
6834         rfcsr = rt2800_rfcsr_read(rt2x00dev, 50);
6835         rt2x00_set_field8(&rfcsr, RFCSR50_TX_LO2_EN, 0);
6836         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
6837
6838         rfcsr = rt2800_rfcsr_read(rt2x00dev, 51);
6839         tx_gain = rt2x00_get_field8(drv_data->txmixer_gain_24g,
6840                                     RFCSR17_TXMIXER_GAIN);
6841         rt2x00_set_field8(&rfcsr, RFCSR51_BITS24, tx_gain);
6842         rt2800_rfcsr_write(rt2x00dev, 51, rfcsr);
6843
6844         rfcsr = rt2800_rfcsr_read(rt2x00dev, 38);
6845         rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
6846         rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
6847
6848         rfcsr = rt2800_rfcsr_read(rt2x00dev, 39);
6849         rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
6850         rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
6851
6852         rfcsr = rt2800_rfcsr_read(rt2x00dev, 1);
6853         rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
6854         rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
6855         rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
6856
6857         rfcsr = rt2800_rfcsr_read(rt2x00dev, 30);
6858         rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
6859         rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
6860
6861         /* TODO: enable stream mode */
6862 }
6863
6864 static void rt2800_normal_mode_setup_5xxx(struct rt2x00_dev *rt2x00dev)
6865 {
6866         u8 reg;
6867         u16 eeprom;
6868
6869         /*  Turn off unused DAC1 and ADC1 to reduce power consumption */
6870         reg = rt2800_bbp_read(rt2x00dev, 138);
6871         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
6872         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
6873                 rt2x00_set_field8(&reg, BBP138_RX_ADC1, 0);
6874         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
6875                 rt2x00_set_field8(&reg, BBP138_TX_DAC1, 1);
6876         rt2800_bbp_write(rt2x00dev, 138, reg);
6877
6878         reg = rt2800_rfcsr_read(rt2x00dev, 38);
6879         rt2x00_set_field8(&reg, RFCSR38_RX_LO1_EN, 0);
6880         rt2800_rfcsr_write(rt2x00dev, 38, reg);
6881
6882         reg = rt2800_rfcsr_read(rt2x00dev, 39);
6883         rt2x00_set_field8(&reg, RFCSR39_RX_LO2_EN, 0);
6884         rt2800_rfcsr_write(rt2x00dev, 39, reg);
6885
6886         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
6887
6888         reg = rt2800_rfcsr_read(rt2x00dev, 30);
6889         rt2x00_set_field8(&reg, RFCSR30_RX_VCM, 2);
6890         rt2800_rfcsr_write(rt2x00dev, 30, reg);
6891 }
6892
6893 static void rt2800_init_rfcsr_305x_soc(struct rt2x00_dev *rt2x00dev)
6894 {
6895         rt2800_rf_init_calibration(rt2x00dev, 30);
6896
6897         rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
6898         rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
6899         rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
6900         rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
6901         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6902         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6903         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6904         rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
6905         rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
6906         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6907         rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
6908         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6909         rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
6910         rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
6911         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6912         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6913         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6914         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6915         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6916         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6917         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6918         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6919         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
6920         rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
6921         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
6922         rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
6923         rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
6924         rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
6925         rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
6926         rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
6927         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
6928         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
6929 }
6930
6931 static void rt2800_init_rfcsr_30xx(struct rt2x00_dev *rt2x00dev)
6932 {
6933         u8 rfcsr;
6934         u16 eeprom;
6935         u32 reg;
6936
6937         /* XXX vendor driver do this only for 3070 */
6938         rt2800_rf_init_calibration(rt2x00dev, 30);
6939
6940         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
6941         rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
6942         rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
6943         rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
6944         rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
6945         rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
6946         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
6947         rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
6948         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
6949         rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
6950         rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
6951         rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
6952         rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
6953         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
6954         rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
6955         rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
6956         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
6957         rt2800_rfcsr_write(rt2x00dev, 25, 0x03);
6958         rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
6959
6960         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
6961                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6962                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6963                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6964                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6965         } else if (rt2x00_rt(rt2x00dev, RT3071) ||
6966                    rt2x00_rt(rt2x00dev, RT3090)) {
6967                 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
6968
6969                 rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
6970                 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
6971                 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
6972
6973                 reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
6974                 rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
6975                 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6976                     rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
6977                         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
6978                         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
6979                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
6980                         else
6981                                 rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
6982                 }
6983                 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
6984
6985                 reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
6986                 rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
6987                 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
6988         }
6989
6990         rt2800_rx_filter_calibration(rt2x00dev);
6991
6992         if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
6993             rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
6994             rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E))
6995                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
6996
6997         rt2800_led_open_drain_enable(rt2x00dev);
6998         rt2800_normal_mode_setup_3xxx(rt2x00dev);
6999 }
7000
7001 static void rt2800_init_rfcsr_3290(struct rt2x00_dev *rt2x00dev)
7002 {
7003         u8 rfcsr;
7004
7005         rt2800_rf_init_calibration(rt2x00dev, 2);
7006
7007         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7008         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7009         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7010         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7011         rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7012         rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
7013         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7014         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7015         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7016         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7017         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7018         rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
7019         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7020         rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
7021         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7022         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7023         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7024         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7025         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7026         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7027         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7028         rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
7029         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7030         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7031         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7032         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7033         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7034         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7035         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7036         rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
7037         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7038         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7039         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7040         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7041         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7042         rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
7043         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7044         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7045         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7046         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7047         rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
7048         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7049         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7050         rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
7051         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7052         rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
7053
7054         rfcsr = rt2800_rfcsr_read(rt2x00dev, 29);
7055         rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
7056         rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
7057
7058         rt2800_led_open_drain_enable(rt2x00dev);
7059         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7060 }
7061
7062 static void rt2800_init_rfcsr_3352(struct rt2x00_dev *rt2x00dev)
7063 {
7064         int tx0_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX0,
7065                                   &rt2x00dev->cap_flags);
7066         int tx1_ext_pa = test_bit(CAPABILITY_EXTERNAL_PA_TX1,
7067                                   &rt2x00dev->cap_flags);
7068         u8 rfcsr;
7069
7070         rt2800_rf_init_calibration(rt2x00dev, 30);
7071
7072         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7073         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7074         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7075         rt2800_rfcsr_write(rt2x00dev, 3, 0x18);
7076         rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
7077         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7078         rt2800_rfcsr_write(rt2x00dev, 6, 0x33);
7079         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7080         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7081         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7082         rt2800_rfcsr_write(rt2x00dev, 10, 0xd2);
7083         rt2800_rfcsr_write(rt2x00dev, 11, 0x42);
7084         rt2800_rfcsr_write(rt2x00dev, 12, 0x1c);
7085         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
7086         rt2800_rfcsr_write(rt2x00dev, 14, 0x5a);
7087         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7088         rt2800_rfcsr_write(rt2x00dev, 16, 0x01);
7089         rt2800_rfcsr_write(rt2x00dev, 18, 0x45);
7090         rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
7091         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7092         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7093         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7094         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7095         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7096         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7097         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7098         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7099         rt2800_rfcsr_write(rt2x00dev, 28, 0x03);
7100         rt2800_rfcsr_write(rt2x00dev, 29, 0x00);
7101         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7102         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7103         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7104         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7105         rfcsr = 0x01;
7106         if (tx0_ext_pa)
7107                 rt2x00_set_field8(&rfcsr, RFCSR34_TX0_EXT_PA, 1);
7108         if (tx1_ext_pa)
7109                 rt2x00_set_field8(&rfcsr, RFCSR34_TX1_EXT_PA, 1);
7110         rt2800_rfcsr_write(rt2x00dev, 34, rfcsr);
7111         rt2800_rfcsr_write(rt2x00dev, 35, 0x03);
7112         rt2800_rfcsr_write(rt2x00dev, 36, 0xbd);
7113         rt2800_rfcsr_write(rt2x00dev, 37, 0x3c);
7114         rt2800_rfcsr_write(rt2x00dev, 38, 0x5f);
7115         rt2800_rfcsr_write(rt2x00dev, 39, 0xc5);
7116         rt2800_rfcsr_write(rt2x00dev, 40, 0x33);
7117         rfcsr = 0x52;
7118         if (!tx0_ext_pa) {
7119                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT1, 1);
7120                 rt2x00_set_field8(&rfcsr, RFCSR41_BIT4, 1);
7121         }
7122         rt2800_rfcsr_write(rt2x00dev, 41, rfcsr);
7123         rfcsr = 0x52;
7124         if (!tx1_ext_pa) {
7125                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT1, 1);
7126                 rt2x00_set_field8(&rfcsr, RFCSR42_BIT4, 1);
7127         }
7128         rt2800_rfcsr_write(rt2x00dev, 42, rfcsr);
7129         rt2800_rfcsr_write(rt2x00dev, 43, 0xdb);
7130         rt2800_rfcsr_write(rt2x00dev, 44, 0xdb);
7131         rt2800_rfcsr_write(rt2x00dev, 45, 0xdb);
7132         rt2800_rfcsr_write(rt2x00dev, 46, 0xdd);
7133         rt2800_rfcsr_write(rt2x00dev, 47, 0x0d);
7134         rt2800_rfcsr_write(rt2x00dev, 48, 0x14);
7135         rt2800_rfcsr_write(rt2x00dev, 49, 0x00);
7136         rfcsr = 0x2d;
7137         if (tx0_ext_pa)
7138                 rt2x00_set_field8(&rfcsr, RFCSR50_TX0_EXT_PA, 1);
7139         if (tx1_ext_pa)
7140                 rt2x00_set_field8(&rfcsr, RFCSR50_TX1_EXT_PA, 1);
7141         rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
7142         rt2800_rfcsr_write(rt2x00dev, 51, (tx0_ext_pa ? 0x52 : 0x7f));
7143         rt2800_rfcsr_write(rt2x00dev, 52, (tx0_ext_pa ? 0xc0 : 0x00));
7144         rt2800_rfcsr_write(rt2x00dev, 53, (tx0_ext_pa ? 0xd2 : 0x52));
7145         rt2800_rfcsr_write(rt2x00dev, 54, (tx0_ext_pa ? 0xc0 : 0x1b));
7146         rt2800_rfcsr_write(rt2x00dev, 55, (tx1_ext_pa ? 0x52 : 0x7f));
7147         rt2800_rfcsr_write(rt2x00dev, 56, (tx1_ext_pa ? 0xc0 : 0x00));
7148         rt2800_rfcsr_write(rt2x00dev, 57, (tx0_ext_pa ? 0x49 : 0x52));
7149         rt2800_rfcsr_write(rt2x00dev, 58, (tx1_ext_pa ? 0xc0 : 0x1b));
7150         rt2800_rfcsr_write(rt2x00dev, 59, 0x00);
7151         rt2800_rfcsr_write(rt2x00dev, 60, 0x00);
7152         rt2800_rfcsr_write(rt2x00dev, 61, 0x00);
7153         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7154         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7155
7156         rt2800_rx_filter_calibration(rt2x00dev);
7157         rt2800_led_open_drain_enable(rt2x00dev);
7158         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7159 }
7160
7161 static void rt2800_init_rfcsr_3390(struct rt2x00_dev *rt2x00dev)
7162 {
7163         u32 reg;
7164
7165         rt2800_rf_init_calibration(rt2x00dev, 30);
7166
7167         rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
7168         rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
7169         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7170         rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
7171         rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
7172         rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
7173         rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
7174         rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
7175         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
7176         rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
7177         rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
7178         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
7179         rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
7180         rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
7181         rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
7182         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7183         rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
7184         rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
7185         rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
7186         rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
7187         rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
7188         rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
7189         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7190         rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
7191         rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
7192         rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
7193         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7194         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7195         rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
7196         rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
7197         rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
7198         rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
7199
7200         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7201         rt2x00_set_field32(&reg, GPIO_SWITCH_5, 0);
7202         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7203
7204         rt2800_rx_filter_calibration(rt2x00dev);
7205
7206         if (rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
7207                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7208
7209         rt2800_led_open_drain_enable(rt2x00dev);
7210         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7211 }
7212
7213 static void rt2800_init_rfcsr_3572(struct rt2x00_dev *rt2x00dev)
7214 {
7215         u8 rfcsr;
7216         u32 reg;
7217
7218         rt2800_rf_init_calibration(rt2x00dev, 30);
7219
7220         rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
7221         rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
7222         rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
7223         rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
7224         rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
7225         rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
7226         rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
7227         rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
7228         rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
7229         rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
7230         rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
7231         rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
7232         rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
7233         rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
7234         rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
7235         rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
7236         rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
7237         rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
7238         rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
7239         rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
7240         rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
7241         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
7242         rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
7243         rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
7244         rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
7245         rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
7246         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
7247         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7248         rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
7249         rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
7250         rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
7251
7252         rfcsr = rt2800_rfcsr_read(rt2x00dev, 6);
7253         rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
7254         rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
7255
7256         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7257         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7258         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7259         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7260         msleep(1);
7261         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7262         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7263         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7264         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7265
7266         rt2800_rx_filter_calibration(rt2x00dev);
7267         rt2800_led_open_drain_enable(rt2x00dev);
7268         rt2800_normal_mode_setup_3xxx(rt2x00dev);
7269 }
7270
7271 static void rt3593_post_bbp_init(struct rt2x00_dev *rt2x00dev)
7272 {
7273         u8 bbp;
7274         bool txbf_enabled = false; /* FIXME */
7275
7276         bbp = rt2800_bbp_read(rt2x00dev, 105);
7277         if (rt2x00dev->default_ant.rx_chain_num == 1)
7278                 rt2x00_set_field8(&bbp, BBP105_MLD, 0);
7279         else
7280                 rt2x00_set_field8(&bbp, BBP105_MLD, 1);
7281         rt2800_bbp_write(rt2x00dev, 105, bbp);
7282
7283         rt2800_bbp4_mac_if_ctrl(rt2x00dev);
7284
7285         rt2800_bbp_write(rt2x00dev, 92, 0x02);
7286         rt2800_bbp_write(rt2x00dev, 82, 0x82);
7287         rt2800_bbp_write(rt2x00dev, 106, 0x05);
7288         rt2800_bbp_write(rt2x00dev, 104, 0x92);
7289         rt2800_bbp_write(rt2x00dev, 88, 0x90);
7290         rt2800_bbp_write(rt2x00dev, 148, 0xc8);
7291         rt2800_bbp_write(rt2x00dev, 47, 0x48);
7292         rt2800_bbp_write(rt2x00dev, 120, 0x50);
7293
7294         if (txbf_enabled)
7295                 rt2800_bbp_write(rt2x00dev, 163, 0xbd);
7296         else
7297                 rt2800_bbp_write(rt2x00dev, 163, 0x9d);
7298
7299         /* SNR mapping */
7300         rt2800_bbp_write(rt2x00dev, 142, 6);
7301         rt2800_bbp_write(rt2x00dev, 143, 160);
7302         rt2800_bbp_write(rt2x00dev, 142, 7);
7303         rt2800_bbp_write(rt2x00dev, 143, 161);
7304         rt2800_bbp_write(rt2x00dev, 142, 8);
7305         rt2800_bbp_write(rt2x00dev, 143, 162);
7306
7307         /* ADC/DAC control */
7308         rt2800_bbp_write(rt2x00dev, 31, 0x08);
7309
7310         /* RX AGC energy lower bound in log2 */
7311         rt2800_bbp_write(rt2x00dev, 68, 0x0b);
7312
7313         /* FIXME: BBP 105 owerwrite? */
7314         rt2800_bbp_write(rt2x00dev, 105, 0x04);
7315
7316 }
7317
7318 static void rt2800_init_rfcsr_3593(struct rt2x00_dev *rt2x00dev)
7319 {
7320         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7321         u32 reg;
7322         u8 rfcsr;
7323
7324         /* Disable GPIO #4 and #7 function for LAN PE control */
7325         reg = rt2800_register_read(rt2x00dev, GPIO_SWITCH);
7326         rt2x00_set_field32(&reg, GPIO_SWITCH_4, 0);
7327         rt2x00_set_field32(&reg, GPIO_SWITCH_7, 0);
7328         rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
7329
7330         /* Initialize default register values */
7331         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
7332         rt2800_rfcsr_write(rt2x00dev, 3, 0x80);
7333         rt2800_rfcsr_write(rt2x00dev, 5, 0x00);
7334         rt2800_rfcsr_write(rt2x00dev, 6, 0x40);
7335         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7336         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7337         rt2800_rfcsr_write(rt2x00dev, 10, 0xd3);
7338         rt2800_rfcsr_write(rt2x00dev, 11, 0x40);
7339         rt2800_rfcsr_write(rt2x00dev, 12, 0x4e);
7340         rt2800_rfcsr_write(rt2x00dev, 13, 0x12);
7341         rt2800_rfcsr_write(rt2x00dev, 18, 0x40);
7342         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7343         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7344         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7345         rt2800_rfcsr_write(rt2x00dev, 32, 0x78);
7346         rt2800_rfcsr_write(rt2x00dev, 33, 0x3b);
7347         rt2800_rfcsr_write(rt2x00dev, 34, 0x3c);
7348         rt2800_rfcsr_write(rt2x00dev, 35, 0xe0);
7349         rt2800_rfcsr_write(rt2x00dev, 38, 0x86);
7350         rt2800_rfcsr_write(rt2x00dev, 39, 0x23);
7351         rt2800_rfcsr_write(rt2x00dev, 44, 0xd3);
7352         rt2800_rfcsr_write(rt2x00dev, 45, 0xbb);
7353         rt2800_rfcsr_write(rt2x00dev, 46, 0x60);
7354         rt2800_rfcsr_write(rt2x00dev, 49, 0x8e);
7355         rt2800_rfcsr_write(rt2x00dev, 50, 0x86);
7356         rt2800_rfcsr_write(rt2x00dev, 51, 0x75);
7357         rt2800_rfcsr_write(rt2x00dev, 52, 0x45);
7358         rt2800_rfcsr_write(rt2x00dev, 53, 0x18);
7359         rt2800_rfcsr_write(rt2x00dev, 54, 0x18);
7360         rt2800_rfcsr_write(rt2x00dev, 55, 0x18);
7361         rt2800_rfcsr_write(rt2x00dev, 56, 0xdb);
7362         rt2800_rfcsr_write(rt2x00dev, 57, 0x6e);
7363
7364         /* Initiate calibration */
7365         /* TODO: use rt2800_rf_init_calibration ? */
7366         rfcsr = rt2800_rfcsr_read(rt2x00dev, 2);
7367         rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
7368         rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
7369
7370         rt2800_freq_cal_mode1(rt2x00dev);
7371
7372         rfcsr = rt2800_rfcsr_read(rt2x00dev, 18);
7373         rt2x00_set_field8(&rfcsr, RFCSR18_XO_TUNE_BYPASS, 1);
7374         rt2800_rfcsr_write(rt2x00dev, 18, rfcsr);
7375
7376         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7377         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 3);
7378         rt2x00_set_field32(&reg, LDO_CFG0_BGSEL, 1);
7379         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7380         usleep_range(1000, 1500);
7381         reg = rt2800_register_read(rt2x00dev, LDO_CFG0);
7382         rt2x00_set_field32(&reg, LDO_CFG0_LDO_CORE_VLEVEL, 0);
7383         rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
7384
7385         /* Set initial values for RX filter calibration */
7386         drv_data->calibration_bw20 = 0x1f;
7387         drv_data->calibration_bw40 = 0x2f;
7388
7389         /* Save BBP 25 & 26 values for later use in channel switching */
7390         drv_data->bbp25 = rt2800_bbp_read(rt2x00dev, 25);
7391         drv_data->bbp26 = rt2800_bbp_read(rt2x00dev, 26);
7392
7393         rt2800_led_open_drain_enable(rt2x00dev);
7394         rt2800_normal_mode_setup_3593(rt2x00dev);
7395
7396         rt3593_post_bbp_init(rt2x00dev);
7397
7398         /* TODO: enable stream mode support */
7399 }
7400
7401 static void rt2800_init_rfcsr_5350(struct rt2x00_dev *rt2x00dev)
7402 {
7403         rt2800_rfcsr_write(rt2x00dev, 0, 0xf0);
7404         rt2800_rfcsr_write(rt2x00dev, 1, 0x23);
7405         rt2800_rfcsr_write(rt2x00dev, 2, 0x50);
7406         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7407         rt2800_rfcsr_write(rt2x00dev, 4, 0x49);
7408         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7409         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7410         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7411         rt2800_rfcsr_write(rt2x00dev, 8, 0xf1);
7412         rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
7413         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7414         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7415         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7416         if (rt2800_clk_is_20mhz(rt2x00dev))
7417                 rt2800_rfcsr_write(rt2x00dev, 13, 0x1f);
7418         else
7419                 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7420         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7421         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7422         rt2800_rfcsr_write(rt2x00dev, 16, 0xc0);
7423         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7424         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7425         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7426         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7427         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7428         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7429         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7430         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7431         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7432         rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7433         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7434         rt2800_rfcsr_write(rt2x00dev, 29, 0xd0);
7435         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7436         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7437         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7438         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7439         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7440         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7441         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7442         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7443         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7444         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7445         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7446         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7447         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7448         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7449         rt2800_rfcsr_write(rt2x00dev, 44, 0x0c);
7450         rt2800_rfcsr_write(rt2x00dev, 45, 0xa6);
7451         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7452         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7453         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7454         rt2800_rfcsr_write(rt2x00dev, 49, 0x80);
7455         rt2800_rfcsr_write(rt2x00dev, 50, 0x00);
7456         rt2800_rfcsr_write(rt2x00dev, 51, 0x00);
7457         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7458         rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7459         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7460         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7461         rt2800_rfcsr_write(rt2x00dev, 56, 0x82);
7462         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7463         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7464         rt2800_rfcsr_write(rt2x00dev, 59, 0x0b);
7465         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7466         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7467         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7468         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7469 }
7470
7471 static void rt2800_init_rfcsr_5390(struct rt2x00_dev *rt2x00dev)
7472 {
7473         rt2800_rf_init_calibration(rt2x00dev, 2);
7474
7475         rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
7476         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7477         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7478         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7479         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7480                 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7481         else
7482                 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
7483         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7484         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7485         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7486         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7487         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7488         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7489         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7490         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7491         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7492         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
7493
7494         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7495         rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
7496         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7497         rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
7498         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
7499         if (rt2x00_is_usb(rt2x00dev) &&
7500             rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7501                 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7502         else
7503                 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
7504         rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
7505         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7506         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7507         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7508
7509         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7510         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7511         rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
7512         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
7513         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7514         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7515         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7516         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7517         rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
7518         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7519
7520         rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
7521         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7522         rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
7523         rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
7524         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7525         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7526         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7527                 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7528         else
7529                 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
7530         rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
7531         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7532         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7533
7534         rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
7535         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7536                 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
7537         else
7538                 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
7539         rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
7540         rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
7541         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
7542                 rt2800_rfcsr_write(rt2x00dev, 56, 0x42);
7543         else
7544                 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
7545         rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
7546         rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
7547         rt2800_rfcsr_write(rt2x00dev, 59, 0x8f);
7548
7549         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7550         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
7551                 if (rt2x00_is_usb(rt2x00dev))
7552                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
7553                 else
7554                         rt2800_rfcsr_write(rt2x00dev, 61, 0xd5);
7555         } else {
7556                 if (rt2x00_is_usb(rt2x00dev))
7557                         rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
7558                 else
7559                         rt2800_rfcsr_write(rt2x00dev, 61, 0xb5);
7560         }
7561         rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
7562         rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
7563
7564         rt2800_normal_mode_setup_5xxx(rt2x00dev);
7565
7566         rt2800_led_open_drain_enable(rt2x00dev);
7567 }
7568
7569 static void rt2800_init_rfcsr_5392(struct rt2x00_dev *rt2x00dev)
7570 {
7571         rt2800_rf_init_calibration(rt2x00dev, 2);
7572
7573         rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
7574         rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
7575         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7576         rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
7577         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7578         rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
7579         rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
7580         rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
7581         rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
7582         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7583         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7584         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7585         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7586         rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
7587         rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
7588         rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
7589         rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
7590         rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
7591         rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
7592         rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
7593         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7594         rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
7595         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7596         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7597         rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
7598         rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
7599         rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
7600         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7601         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7602         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7603         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
7604         rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
7605         rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
7606         rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
7607         rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
7608         rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
7609         rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
7610         rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
7611         rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
7612         rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
7613         rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
7614         rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
7615         rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
7616         rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
7617         rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
7618         rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
7619         rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
7620         rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
7621         rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
7622         rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
7623         rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
7624         rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
7625         rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
7626         rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
7627         rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
7628         rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
7629         rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
7630         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7631
7632         rt2800_normal_mode_setup_5xxx(rt2x00dev);
7633
7634         rt2800_led_open_drain_enable(rt2x00dev);
7635 }
7636
7637 static void rt2800_init_rfcsr_5592(struct rt2x00_dev *rt2x00dev)
7638 {
7639         rt2800_rf_init_calibration(rt2x00dev, 30);
7640
7641         rt2800_rfcsr_write(rt2x00dev, 1, 0x3F);
7642         rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
7643         rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
7644         rt2800_rfcsr_write(rt2x00dev, 6, 0xE4);
7645         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
7646         rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
7647         rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
7648         rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
7649         rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
7650         rt2800_rfcsr_write(rt2x00dev, 19, 0x4D);
7651         rt2800_rfcsr_write(rt2x00dev, 20, 0x10);
7652         rt2800_rfcsr_write(rt2x00dev, 21, 0x8D);
7653         rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
7654         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
7655         rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
7656         rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
7657         rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
7658         rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
7659         rt2800_rfcsr_write(rt2x00dev, 47, 0x0C);
7660         rt2800_rfcsr_write(rt2x00dev, 53, 0x22);
7661         rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
7662
7663         rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
7664         msleep(1);
7665
7666         rt2800_freq_cal_mode1(rt2x00dev);
7667
7668         /* Enable DC filter */
7669         if (rt2x00_rt_rev_gte(rt2x00dev, RT5592, REV_RT5592C))
7670                 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
7671
7672         rt2800_normal_mode_setup_5xxx(rt2x00dev);
7673
7674         if (rt2x00_rt_rev_lt(rt2x00dev, RT5592, REV_RT5592C))
7675                 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
7676
7677         rt2800_led_open_drain_enable(rt2x00dev);
7678 }
7679
7680 static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
7681                                        bool set_bw, bool is_ht40)
7682 {
7683         u8 bbp_val;
7684
7685         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7686         bbp_val |= 0x1;
7687         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7688         usleep_range(100, 200);
7689
7690         if (set_bw) {
7691                 bbp_val = rt2800_bbp_read(rt2x00dev, 4);
7692                 rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH, 2 * is_ht40);
7693                 rt2800_bbp_write(rt2x00dev, 4, bbp_val);
7694                 usleep_range(100, 200);
7695         }
7696
7697         bbp_val = rt2800_bbp_read(rt2x00dev, 21);
7698         bbp_val &= (~0x1);
7699         rt2800_bbp_write(rt2x00dev, 21, bbp_val);
7700         usleep_range(100, 200);
7701 }
7702
7703 static int rt2800_rf_lp_config(struct rt2x00_dev *rt2x00dev, bool btxcal)
7704 {
7705         u8 rf_val;
7706
7707         if (btxcal)
7708                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x04);
7709         else
7710                 rt2800_register_write(rt2x00dev, RF_CONTROL0, 0x02);
7711
7712         rt2800_register_write(rt2x00dev, RF_BYPASS0, 0x06);
7713
7714         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7715         rf_val |= 0x80;
7716         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, rf_val);
7717
7718         if (btxcal) {
7719                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xC1);
7720                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x20);
7721                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7722                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7723                 rf_val &= (~0x3F);
7724                 rf_val |= 0x3F;
7725                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7726                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7727                 rf_val &= (~0x3F);
7728                 rf_val |= 0x3F;
7729                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7730                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, 0x31);
7731         } else {
7732                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0xF1);
7733                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x18);
7734                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x02);
7735                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7736                 rf_val &= (~0x3F);
7737                 rf_val |= 0x34;
7738                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, rf_val);
7739                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7740                 rf_val &= (~0x3F);
7741                 rf_val |= 0x34;
7742                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, rf_val);
7743         }
7744
7745         return 0;
7746 }
7747
7748 static char rt2800_lp_tx_filter_bw_cal(struct rt2x00_dev *rt2x00dev)
7749 {
7750         unsigned int cnt;
7751         u8 bbp_val;
7752         char cal_val;
7753
7754         rt2800_bbp_dcoc_write(rt2x00dev, 0, 0x82);
7755
7756         cnt = 0;
7757         do {
7758                 usleep_range(500, 2000);
7759                 bbp_val = rt2800_bbp_read(rt2x00dev, 159);
7760                 if (bbp_val == 0x02 || cnt == 20)
7761                         break;
7762
7763                 cnt++;
7764         } while (cnt < 20);
7765
7766         bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 0x39);
7767         cal_val = bbp_val & 0x7F;
7768         if (cal_val >= 0x40)
7769                 cal_val -= 128;
7770
7771         return cal_val;
7772 }
7773
7774 static void rt2800_bw_filter_calibration(struct rt2x00_dev *rt2x00dev,
7775                                          bool btxcal)
7776 {
7777         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
7778         u8 tx_agc_fc = 0, rx_agc_fc = 0, cmm_agc_fc;
7779         u8 filter_target;
7780         u8 tx_filter_target_20m = 0x09, tx_filter_target_40m = 0x02;
7781         u8 rx_filter_target_20m = 0x27, rx_filter_target_40m = 0x31;
7782         int loop = 0, is_ht40, cnt;
7783         u8 bbp_val, rf_val;
7784         char cal_r32_init, cal_r32_val, cal_diff;
7785         u8 saverfb5r00, saverfb5r01, saverfb5r03, saverfb5r04, saverfb5r05;
7786         u8 saverfb5r06, saverfb5r07;
7787         u8 saverfb5r08, saverfb5r17, saverfb5r18, saverfb5r19, saverfb5r20;
7788         u8 saverfb5r37, saverfb5r38, saverfb5r39, saverfb5r40, saverfb5r41;
7789         u8 saverfb5r42, saverfb5r43, saverfb5r44, saverfb5r45, saverfb5r46;
7790         u8 saverfb5r58, saverfb5r59;
7791         u8 savebbp159r0, savebbp159r2, savebbpr23;
7792         u32 MAC_RF_CONTROL0, MAC_RF_BYPASS0;
7793
7794         /* Save MAC registers */
7795         MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
7796         MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
7797
7798         /* save BBP registers */
7799         savebbpr23 = rt2800_bbp_read(rt2x00dev, 23);
7800
7801         savebbp159r0 = rt2800_bbp_dcoc_read(rt2x00dev, 0);
7802         savebbp159r2 = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7803
7804         /* Save RF registers */
7805         saverfb5r00 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7806         saverfb5r01 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7807         saverfb5r03 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 3);
7808         saverfb5r04 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
7809         saverfb5r05 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 5);
7810         saverfb5r06 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7811         saverfb5r07 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7812         saverfb5r08 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7813         saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
7814         saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
7815         saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
7816         saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
7817
7818         saverfb5r37 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 37);
7819         saverfb5r38 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 38);
7820         saverfb5r39 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 39);
7821         saverfb5r40 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 40);
7822         saverfb5r41 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 41);
7823         saverfb5r42 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 42);
7824         saverfb5r43 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 43);
7825         saverfb5r44 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 44);
7826         saverfb5r45 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 45);
7827         saverfb5r46 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 46);
7828
7829         saverfb5r58 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7830         saverfb5r59 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7831
7832         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7833         rf_val |= 0x3;
7834         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7835
7836         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7837         rf_val |= 0x1;
7838         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, rf_val);
7839
7840         cnt = 0;
7841         do {
7842                 usleep_range(500, 2000);
7843                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 1);
7844                 if (((rf_val & 0x1) == 0x00) || (cnt == 40))
7845                         break;
7846                 cnt++;
7847         } while (cnt < 40);
7848
7849         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 0);
7850         rf_val &= (~0x3);
7851         rf_val |= 0x1;
7852         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, rf_val);
7853
7854         /* I-3 */
7855         bbp_val = rt2800_bbp_read(rt2x00dev, 23);
7856         bbp_val &= (~0x1F);
7857         bbp_val |= 0x10;
7858         rt2800_bbp_write(rt2x00dev, 23, bbp_val);
7859
7860         do {
7861                 /* I-4,5,6,7,8,9 */
7862                 if (loop == 0) {
7863                         is_ht40 = false;
7864
7865                         if (btxcal)
7866                                 filter_target = tx_filter_target_20m;
7867                         else
7868                                 filter_target = rx_filter_target_20m;
7869                 } else {
7870                         is_ht40 = true;
7871
7872                         if (btxcal)
7873                                 filter_target = tx_filter_target_40m;
7874                         else
7875                                 filter_target = rx_filter_target_40m;
7876                 }
7877
7878                 rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 8);
7879                 rf_val &= (~0x04);
7880                 if (loop == 1)
7881                         rf_val |= 0x4;
7882
7883                 rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, rf_val);
7884
7885                 rt2800_bbp_core_soft_reset(rt2x00dev, true, is_ht40);
7886
7887                 rt2800_rf_lp_config(rt2x00dev, btxcal);
7888                 if (btxcal) {
7889                         tx_agc_fc = 0;
7890                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7891                         rf_val &= (~0x7F);
7892                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7893                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7894                         rf_val &= (~0x7F);
7895                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7896                 } else {
7897                         rx_agc_fc = 0;
7898                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7899                         rf_val &= (~0x7F);
7900                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7901                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7902                         rf_val &= (~0x7F);
7903                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7904                 }
7905
7906                 usleep_range(1000, 2000);
7907
7908                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7909                 bbp_val &= (~0x6);
7910                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7911
7912                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7913
7914                 cal_r32_init = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7915
7916                 bbp_val = rt2800_bbp_dcoc_read(rt2x00dev, 2);
7917                 bbp_val |= 0x6;
7918                 rt2800_bbp_dcoc_write(rt2x00dev, 2, bbp_val);
7919 do_cal:
7920                 if (btxcal) {
7921                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 58);
7922                         rf_val &= (~0x7F);
7923                         rf_val |= tx_agc_fc;
7924                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, rf_val);
7925                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 59);
7926                         rf_val &= (~0x7F);
7927                         rf_val |= tx_agc_fc;
7928                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, rf_val);
7929                 } else {
7930                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 6);
7931                         rf_val &= (~0x7F);
7932                         rf_val |= rx_agc_fc;
7933                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, rf_val);
7934                         rf_val = rt2800_rfcsr_read_bank(rt2x00dev, 5, 7);
7935                         rf_val &= (~0x7F);
7936                         rf_val |= rx_agc_fc;
7937                         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, rf_val);
7938                 }
7939
7940                 usleep_range(500, 1000);
7941
7942                 rt2800_bbp_core_soft_reset(rt2x00dev, false, is_ht40);
7943
7944                 cal_r32_val = rt2800_lp_tx_filter_bw_cal(rt2x00dev);
7945
7946                 cal_diff = cal_r32_init - cal_r32_val;
7947
7948                 if (btxcal)
7949                         cmm_agc_fc = tx_agc_fc;
7950                 else
7951                         cmm_agc_fc = rx_agc_fc;
7952
7953                 if (((cal_diff > filter_target) && (cmm_agc_fc == 0)) ||
7954                     ((cal_diff < filter_target) && (cmm_agc_fc == 0x3f))) {
7955                         if (btxcal)
7956                                 tx_agc_fc = 0;
7957                         else
7958                                 rx_agc_fc = 0;
7959                 } else if ((cal_diff <= filter_target) && (cmm_agc_fc < 0x3f)) {
7960                         if (btxcal)
7961                                 tx_agc_fc++;
7962                         else
7963                                 rx_agc_fc++;
7964                         goto do_cal;
7965                 }
7966
7967                 if (btxcal) {
7968                         if (loop == 0)
7969                                 drv_data->tx_calibration_bw20 = tx_agc_fc;
7970                         else
7971                                 drv_data->tx_calibration_bw40 = tx_agc_fc;
7972                 } else {
7973                         if (loop == 0)
7974                                 drv_data->rx_calibration_bw20 = rx_agc_fc;
7975                         else
7976                                 drv_data->rx_calibration_bw40 = rx_agc_fc;
7977                 }
7978
7979                 loop++;
7980         } while (loop <= 1);
7981
7982         rt2800_rfcsr_write_bank(rt2x00dev, 5, 0, saverfb5r00);
7983         rt2800_rfcsr_write_bank(rt2x00dev, 5, 1, saverfb5r01);
7984         rt2800_rfcsr_write_bank(rt2x00dev, 5, 3, saverfb5r03);
7985         rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r04);
7986         rt2800_rfcsr_write_bank(rt2x00dev, 5, 5, saverfb5r05);
7987         rt2800_rfcsr_write_bank(rt2x00dev, 5, 6, saverfb5r06);
7988         rt2800_rfcsr_write_bank(rt2x00dev, 5, 7, saverfb5r07);
7989         rt2800_rfcsr_write_bank(rt2x00dev, 5, 8, saverfb5r08);
7990         rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
7991         rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
7992         rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
7993         rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
7994
7995         rt2800_rfcsr_write_bank(rt2x00dev, 5, 37, saverfb5r37);
7996         rt2800_rfcsr_write_bank(rt2x00dev, 5, 38, saverfb5r38);
7997         rt2800_rfcsr_write_bank(rt2x00dev, 5, 39, saverfb5r39);
7998         rt2800_rfcsr_write_bank(rt2x00dev, 5, 40, saverfb5r40);
7999         rt2800_rfcsr_write_bank(rt2x00dev, 5, 41, saverfb5r41);
8000         rt2800_rfcsr_write_bank(rt2x00dev, 5, 42, saverfb5r42);
8001         rt2800_rfcsr_write_bank(rt2x00dev, 5, 43, saverfb5r43);
8002         rt2800_rfcsr_write_bank(rt2x00dev, 5, 44, saverfb5r44);
8003         rt2800_rfcsr_write_bank(rt2x00dev, 5, 45, saverfb5r45);
8004         rt2800_rfcsr_write_bank(rt2x00dev, 5, 46, saverfb5r46);
8005
8006         rt2800_rfcsr_write_bank(rt2x00dev, 5, 58, saverfb5r58);
8007         rt2800_rfcsr_write_bank(rt2x00dev, 5, 59, saverfb5r59);
8008
8009         rt2800_bbp_write(rt2x00dev, 23, savebbpr23);
8010
8011         rt2800_bbp_dcoc_write(rt2x00dev, 0, savebbp159r0);
8012         rt2800_bbp_dcoc_write(rt2x00dev, 2, savebbp159r2);
8013
8014         bbp_val = rt2800_bbp_read(rt2x00dev, 4);
8015         rt2x00_set_field8(&bbp_val, BBP4_BANDWIDTH,
8016                           2 * test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags));
8017         rt2800_bbp_write(rt2x00dev, 4, bbp_val);
8018
8019         rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
8020         rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
8021 }
8022
8023 static void rt2800_init_rfcsr_6352(struct rt2x00_dev *rt2x00dev)
8024 {
8025         /* Initialize RF central register to default value */
8026         rt2800_rfcsr_write(rt2x00dev, 0, 0x02);
8027         rt2800_rfcsr_write(rt2x00dev, 1, 0x03);
8028         rt2800_rfcsr_write(rt2x00dev, 2, 0x33);
8029         rt2800_rfcsr_write(rt2x00dev, 3, 0xFF);
8030         rt2800_rfcsr_write(rt2x00dev, 4, 0x0C);
8031         rt2800_rfcsr_write(rt2x00dev, 5, 0x40);
8032         rt2800_rfcsr_write(rt2x00dev, 6, 0x00);
8033         rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
8034         rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
8035         rt2800_rfcsr_write(rt2x00dev, 9, 0x00);
8036         rt2800_rfcsr_write(rt2x00dev, 10, 0x00);
8037         rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
8038         rt2800_rfcsr_write(rt2x00dev, 12, rt2x00dev->freq_offset);
8039         rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8040         rt2800_rfcsr_write(rt2x00dev, 14, 0x40);
8041         rt2800_rfcsr_write(rt2x00dev, 15, 0x22);
8042         rt2800_rfcsr_write(rt2x00dev, 16, 0x4C);
8043         rt2800_rfcsr_write(rt2x00dev, 17, 0x00);
8044         rt2800_rfcsr_write(rt2x00dev, 18, 0x00);
8045         rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
8046         rt2800_rfcsr_write(rt2x00dev, 20, 0xA0);
8047         rt2800_rfcsr_write(rt2x00dev, 21, 0x12);
8048         rt2800_rfcsr_write(rt2x00dev, 22, 0x07);
8049         rt2800_rfcsr_write(rt2x00dev, 23, 0x13);
8050         rt2800_rfcsr_write(rt2x00dev, 24, 0xFE);
8051         rt2800_rfcsr_write(rt2x00dev, 25, 0x24);
8052         rt2800_rfcsr_write(rt2x00dev, 26, 0x7A);
8053         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8054         rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
8055         rt2800_rfcsr_write(rt2x00dev, 29, 0x05);
8056         rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
8057         rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
8058         rt2800_rfcsr_write(rt2x00dev, 32, 0x00);
8059         rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
8060         rt2800_rfcsr_write(rt2x00dev, 34, 0x00);
8061         rt2800_rfcsr_write(rt2x00dev, 35, 0x00);
8062         rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
8063         rt2800_rfcsr_write(rt2x00dev, 37, 0x00);
8064         rt2800_rfcsr_write(rt2x00dev, 38, 0x00);
8065         rt2800_rfcsr_write(rt2x00dev, 39, 0x00);
8066         rt2800_rfcsr_write(rt2x00dev, 40, 0x00);
8067         rt2800_rfcsr_write(rt2x00dev, 41, 0xD0);
8068         rt2800_rfcsr_write(rt2x00dev, 42, 0x5B);
8069         rt2800_rfcsr_write(rt2x00dev, 43, 0x00);
8070
8071         rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
8072         if (rt2800_clk_is_20mhz(rt2x00dev))
8073                 rt2800_rfcsr_write(rt2x00dev, 13, 0x03);
8074         else
8075                 rt2800_rfcsr_write(rt2x00dev, 13, 0x00);
8076         rt2800_rfcsr_write(rt2x00dev, 14, 0x7C);
8077         rt2800_rfcsr_write(rt2x00dev, 16, 0x80);
8078         rt2800_rfcsr_write(rt2x00dev, 17, 0x99);
8079         rt2800_rfcsr_write(rt2x00dev, 18, 0x99);
8080         rt2800_rfcsr_write(rt2x00dev, 19, 0x09);
8081         rt2800_rfcsr_write(rt2x00dev, 20, 0x50);
8082         rt2800_rfcsr_write(rt2x00dev, 21, 0xB0);
8083         rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
8084         rt2800_rfcsr_write(rt2x00dev, 23, 0x06);
8085         rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
8086         rt2800_rfcsr_write(rt2x00dev, 25, 0x00);
8087         rt2800_rfcsr_write(rt2x00dev, 26, 0x5D);
8088         rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
8089         rt2800_rfcsr_write(rt2x00dev, 28, 0x61);
8090         rt2800_rfcsr_write(rt2x00dev, 29, 0xB5);
8091         rt2800_rfcsr_write(rt2x00dev, 43, 0x02);
8092
8093         rt2800_rfcsr_write(rt2x00dev, 28, 0x62);
8094         rt2800_rfcsr_write(rt2x00dev, 29, 0xAD);
8095         rt2800_rfcsr_write(rt2x00dev, 39, 0x80);
8096
8097         /* Initialize RF channel register to default value */
8098         rt2800_rfcsr_write_chanreg(rt2x00dev, 0, 0x03);
8099         rt2800_rfcsr_write_chanreg(rt2x00dev, 1, 0x00);
8100         rt2800_rfcsr_write_chanreg(rt2x00dev, 2, 0x00);
8101         rt2800_rfcsr_write_chanreg(rt2x00dev, 3, 0x00);
8102         rt2800_rfcsr_write_chanreg(rt2x00dev, 4, 0x00);
8103         rt2800_rfcsr_write_chanreg(rt2x00dev, 5, 0x08);
8104         rt2800_rfcsr_write_chanreg(rt2x00dev, 6, 0x00);
8105         rt2800_rfcsr_write_chanreg(rt2x00dev, 7, 0x51);
8106         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x53);
8107         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x16);
8108         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x61);
8109         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8110         rt2800_rfcsr_write_chanreg(rt2x00dev, 12, 0x22);
8111         rt2800_rfcsr_write_chanreg(rt2x00dev, 13, 0x3D);
8112         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8113         rt2800_rfcsr_write_chanreg(rt2x00dev, 15, 0x13);
8114         rt2800_rfcsr_write_chanreg(rt2x00dev, 16, 0x22);
8115         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x27);
8116         rt2800_rfcsr_write_chanreg(rt2x00dev, 18, 0x02);
8117         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8118         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x01);
8119         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x52);
8120         rt2800_rfcsr_write_chanreg(rt2x00dev, 22, 0x80);
8121         rt2800_rfcsr_write_chanreg(rt2x00dev, 23, 0xB3);
8122         rt2800_rfcsr_write_chanreg(rt2x00dev, 24, 0x00);
8123         rt2800_rfcsr_write_chanreg(rt2x00dev, 25, 0x00);
8124         rt2800_rfcsr_write_chanreg(rt2x00dev, 26, 0x00);
8125         rt2800_rfcsr_write_chanreg(rt2x00dev, 27, 0x00);
8126         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x5C);
8127         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0x6B);
8128         rt2800_rfcsr_write_chanreg(rt2x00dev, 30, 0x6B);
8129         rt2800_rfcsr_write_chanreg(rt2x00dev, 31, 0x31);
8130         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x5D);
8131         rt2800_rfcsr_write_chanreg(rt2x00dev, 33, 0x00);
8132         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xE6);
8133         rt2800_rfcsr_write_chanreg(rt2x00dev, 35, 0x55);
8134         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x00);
8135         rt2800_rfcsr_write_chanreg(rt2x00dev, 37, 0xBB);
8136         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB3);
8137         rt2800_rfcsr_write_chanreg(rt2x00dev, 39, 0xB3);
8138         rt2800_rfcsr_write_chanreg(rt2x00dev, 40, 0x03);
8139         rt2800_rfcsr_write_chanreg(rt2x00dev, 41, 0x00);
8140         rt2800_rfcsr_write_chanreg(rt2x00dev, 42, 0x00);
8141         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xB3);
8142         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xD3);
8143         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8144         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x07);
8145         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x68);
8146         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xEF);
8147         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1C);
8148         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x07);
8149         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0xA8);
8150         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0x85);
8151         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x10);
8152         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x07);
8153         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6A);
8154         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0x85);
8155         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x10);
8156         rt2800_rfcsr_write_chanreg(rt2x00dev, 62, 0x1C);
8157         rt2800_rfcsr_write_chanreg(rt2x00dev, 63, 0x00);
8158
8159         rt2800_rfcsr_write_bank(rt2x00dev, 6, 45, 0xC5);
8160
8161         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x47);
8162         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x71);
8163         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x33);
8164         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x0E);
8165         rt2800_rfcsr_write_chanreg(rt2x00dev, 17, 0x23);
8166         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA4);
8167         rt2800_rfcsr_write_chanreg(rt2x00dev, 20, 0x02);
8168         rt2800_rfcsr_write_chanreg(rt2x00dev, 21, 0x12);
8169         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x1C);
8170         rt2800_rfcsr_write_chanreg(rt2x00dev, 29, 0xEB);
8171         rt2800_rfcsr_write_chanreg(rt2x00dev, 32, 0x7D);
8172         rt2800_rfcsr_write_chanreg(rt2x00dev, 34, 0xD6);
8173         rt2800_rfcsr_write_chanreg(rt2x00dev, 36, 0x08);
8174         rt2800_rfcsr_write_chanreg(rt2x00dev, 38, 0xB4);
8175         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8176         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xB3);
8177         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xD5);
8178         rt2800_rfcsr_write_chanreg(rt2x00dev, 46, 0x27);
8179         rt2800_rfcsr_write_bank(rt2x00dev, 4, 47, 0x67);
8180         rt2800_rfcsr_write_bank(rt2x00dev, 6, 47, 0x69);
8181         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFF);
8182         rt2800_rfcsr_write_bank(rt2x00dev, 4, 54, 0x27);
8183         rt2800_rfcsr_write_bank(rt2x00dev, 6, 54, 0x20);
8184         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8185         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xFF);
8186         rt2800_rfcsr_write_chanreg(rt2x00dev, 57, 0x1C);
8187         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x20);
8188         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8189         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xF7);
8190         rt2800_rfcsr_write_chanreg(rt2x00dev, 61, 0x09);
8191
8192         rt2800_rfcsr_write_chanreg(rt2x00dev, 10, 0x51);
8193         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x06);
8194         rt2800_rfcsr_write_chanreg(rt2x00dev, 19, 0xA7);
8195         rt2800_rfcsr_write_chanreg(rt2x00dev, 28, 0x2C);
8196         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x64);
8197         rt2800_rfcsr_write_chanreg(rt2x00dev, 8, 0x51);
8198         rt2800_rfcsr_write_chanreg(rt2x00dev, 9, 0x36);
8199         rt2800_rfcsr_write_chanreg(rt2x00dev, 11, 0x53);
8200         rt2800_rfcsr_write_chanreg(rt2x00dev, 14, 0x16);
8201
8202         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x6C);
8203         rt2800_rfcsr_write_chanreg(rt2x00dev, 48, 0xFC);
8204         rt2800_rfcsr_write_chanreg(rt2x00dev, 49, 0x1F);
8205         rt2800_rfcsr_write_chanreg(rt2x00dev, 54, 0x27);
8206         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x66);
8207         rt2800_rfcsr_write_chanreg(rt2x00dev, 59, 0x6B);
8208
8209         /* Initialize RF channel register for DRQFN */
8210         rt2800_rfcsr_write_chanreg(rt2x00dev, 43, 0xD3);
8211         rt2800_rfcsr_write_chanreg(rt2x00dev, 44, 0xE3);
8212         rt2800_rfcsr_write_chanreg(rt2x00dev, 45, 0xE5);
8213         rt2800_rfcsr_write_chanreg(rt2x00dev, 47, 0x28);
8214         rt2800_rfcsr_write_chanreg(rt2x00dev, 55, 0x68);
8215         rt2800_rfcsr_write_chanreg(rt2x00dev, 56, 0xF7);
8216         rt2800_rfcsr_write_chanreg(rt2x00dev, 58, 0x02);
8217         rt2800_rfcsr_write_chanreg(rt2x00dev, 60, 0xC7);
8218
8219         /* Initialize RF DC calibration register to default value */
8220         rt2800_rfcsr_write_dccal(rt2x00dev, 0, 0x47);
8221         rt2800_rfcsr_write_dccal(rt2x00dev, 1, 0x00);
8222         rt2800_rfcsr_write_dccal(rt2x00dev, 2, 0x00);
8223         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x00);
8224         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x00);
8225         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8226         rt2800_rfcsr_write_dccal(rt2x00dev, 6, 0x10);
8227         rt2800_rfcsr_write_dccal(rt2x00dev, 7, 0x10);
8228         rt2800_rfcsr_write_dccal(rt2x00dev, 8, 0x04);
8229         rt2800_rfcsr_write_dccal(rt2x00dev, 9, 0x00);
8230         rt2800_rfcsr_write_dccal(rt2x00dev, 10, 0x07);
8231         rt2800_rfcsr_write_dccal(rt2x00dev, 11, 0x01);
8232         rt2800_rfcsr_write_dccal(rt2x00dev, 12, 0x07);
8233         rt2800_rfcsr_write_dccal(rt2x00dev, 13, 0x07);
8234         rt2800_rfcsr_write_dccal(rt2x00dev, 14, 0x07);
8235         rt2800_rfcsr_write_dccal(rt2x00dev, 15, 0x20);
8236         rt2800_rfcsr_write_dccal(rt2x00dev, 16, 0x22);
8237         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x00);
8238         rt2800_rfcsr_write_dccal(rt2x00dev, 18, 0x00);
8239         rt2800_rfcsr_write_dccal(rt2x00dev, 19, 0x00);
8240         rt2800_rfcsr_write_dccal(rt2x00dev, 20, 0x00);
8241         rt2800_rfcsr_write_dccal(rt2x00dev, 21, 0xF1);
8242         rt2800_rfcsr_write_dccal(rt2x00dev, 22, 0x11);
8243         rt2800_rfcsr_write_dccal(rt2x00dev, 23, 0x02);
8244         rt2800_rfcsr_write_dccal(rt2x00dev, 24, 0x41);
8245         rt2800_rfcsr_write_dccal(rt2x00dev, 25, 0x20);
8246         rt2800_rfcsr_write_dccal(rt2x00dev, 26, 0x00);
8247         rt2800_rfcsr_write_dccal(rt2x00dev, 27, 0xD7);
8248         rt2800_rfcsr_write_dccal(rt2x00dev, 28, 0xA2);
8249         rt2800_rfcsr_write_dccal(rt2x00dev, 29, 0x20);
8250         rt2800_rfcsr_write_dccal(rt2x00dev, 30, 0x49);
8251         rt2800_rfcsr_write_dccal(rt2x00dev, 31, 0x20);
8252         rt2800_rfcsr_write_dccal(rt2x00dev, 32, 0x04);
8253         rt2800_rfcsr_write_dccal(rt2x00dev, 33, 0xF1);
8254         rt2800_rfcsr_write_dccal(rt2x00dev, 34, 0xA1);
8255         rt2800_rfcsr_write_dccal(rt2x00dev, 35, 0x01);
8256         rt2800_rfcsr_write_dccal(rt2x00dev, 41, 0x00);
8257         rt2800_rfcsr_write_dccal(rt2x00dev, 42, 0x00);
8258         rt2800_rfcsr_write_dccal(rt2x00dev, 43, 0x00);
8259         rt2800_rfcsr_write_dccal(rt2x00dev, 44, 0x00);
8260         rt2800_rfcsr_write_dccal(rt2x00dev, 45, 0x00);
8261         rt2800_rfcsr_write_dccal(rt2x00dev, 46, 0x00);
8262         rt2800_rfcsr_write_dccal(rt2x00dev, 47, 0x3E);
8263         rt2800_rfcsr_write_dccal(rt2x00dev, 48, 0x3D);
8264         rt2800_rfcsr_write_dccal(rt2x00dev, 49, 0x3E);
8265         rt2800_rfcsr_write_dccal(rt2x00dev, 50, 0x3D);
8266         rt2800_rfcsr_write_dccal(rt2x00dev, 51, 0x3E);
8267         rt2800_rfcsr_write_dccal(rt2x00dev, 52, 0x3D);
8268         rt2800_rfcsr_write_dccal(rt2x00dev, 53, 0x00);
8269         rt2800_rfcsr_write_dccal(rt2x00dev, 54, 0x00);
8270         rt2800_rfcsr_write_dccal(rt2x00dev, 55, 0x00);
8271         rt2800_rfcsr_write_dccal(rt2x00dev, 56, 0x00);
8272         rt2800_rfcsr_write_dccal(rt2x00dev, 57, 0x00);
8273         rt2800_rfcsr_write_dccal(rt2x00dev, 58, 0x10);
8274         rt2800_rfcsr_write_dccal(rt2x00dev, 59, 0x10);
8275         rt2800_rfcsr_write_dccal(rt2x00dev, 60, 0x0A);
8276         rt2800_rfcsr_write_dccal(rt2x00dev, 61, 0x00);
8277         rt2800_rfcsr_write_dccal(rt2x00dev, 62, 0x00);
8278         rt2800_rfcsr_write_dccal(rt2x00dev, 63, 0x00);
8279
8280         rt2800_rfcsr_write_dccal(rt2x00dev, 3, 0x08);
8281         rt2800_rfcsr_write_dccal(rt2x00dev, 4, 0x04);
8282         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x20);
8283
8284         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
8285         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
8286
8287         rt2800_bw_filter_calibration(rt2x00dev, true);
8288         rt2800_bw_filter_calibration(rt2x00dev, false);
8289 }
8290
8291 static void rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
8292 {
8293         if (rt2800_is_305x_soc(rt2x00dev)) {
8294                 rt2800_init_rfcsr_305x_soc(rt2x00dev);
8295                 return;
8296         }
8297
8298         switch (rt2x00dev->chip.rt) {
8299         case RT3070:
8300         case RT3071:
8301         case RT3090:
8302                 rt2800_init_rfcsr_30xx(rt2x00dev);
8303                 break;
8304         case RT3290:
8305                 rt2800_init_rfcsr_3290(rt2x00dev);
8306                 break;
8307         case RT3352:
8308                 rt2800_init_rfcsr_3352(rt2x00dev);
8309                 break;
8310         case RT3390:
8311                 rt2800_init_rfcsr_3390(rt2x00dev);
8312                 break;
8313         case RT3572:
8314                 rt2800_init_rfcsr_3572(rt2x00dev);
8315                 break;
8316         case RT3593:
8317                 rt2800_init_rfcsr_3593(rt2x00dev);
8318                 break;
8319         case RT5350:
8320                 rt2800_init_rfcsr_5350(rt2x00dev);
8321                 break;
8322         case RT5390:
8323                 rt2800_init_rfcsr_5390(rt2x00dev);
8324                 break;
8325         case RT5392:
8326                 rt2800_init_rfcsr_5392(rt2x00dev);
8327                 break;
8328         case RT5592:
8329                 rt2800_init_rfcsr_5592(rt2x00dev);
8330                 break;
8331         case RT6352:
8332                 rt2800_init_rfcsr_6352(rt2x00dev);
8333                 break;
8334         }
8335 }
8336
8337 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
8338 {
8339         u32 reg;
8340         u16 word;
8341
8342         /*
8343          * Initialize MAC registers.
8344          */
8345         if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
8346                      rt2800_init_registers(rt2x00dev)))
8347                 return -EIO;
8348
8349         /*
8350          * Wait BBP/RF to wake up.
8351          */
8352         if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev)))
8353                 return -EIO;
8354
8355         /*
8356          * Send signal during boot time to initialize firmware.
8357          */
8358         rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
8359         rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
8360         if (rt2x00_is_usb(rt2x00dev))
8361                 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
8362         rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
8363         msleep(1);
8364
8365         /*
8366          * Make sure BBP is up and running.
8367          */
8368         if (unlikely(rt2800_wait_bbp_ready(rt2x00dev)))
8369                 return -EIO;
8370
8371         /*
8372          * Initialize BBP/RF registers.
8373          */
8374         rt2800_init_bbp(rt2x00dev);
8375         rt2800_init_rfcsr(rt2x00dev);
8376
8377         if (rt2x00_is_usb(rt2x00dev) &&
8378             (rt2x00_rt(rt2x00dev, RT3070) ||
8379              rt2x00_rt(rt2x00dev, RT3071) ||
8380              rt2x00_rt(rt2x00dev, RT3572))) {
8381                 udelay(200);
8382                 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
8383                 udelay(10);
8384         }
8385
8386         /*
8387          * Enable RX.
8388          */
8389         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8390         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8391         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8392         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8393
8394         udelay(50);
8395
8396         reg = rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG);
8397         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
8398         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
8399         rt2x00_set_field32(&reg, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
8400         rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
8401
8402         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8403         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 1);
8404         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 1);
8405         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8406
8407         /*
8408          * Initialize LED control
8409          */
8410         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF);
8411         rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
8412                            word & 0xff, (word >> 8) & 0xff);
8413
8414         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF);
8415         rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
8416                            word & 0xff, (word >> 8) & 0xff);
8417
8418         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY);
8419         rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
8420                            word & 0xff, (word >> 8) & 0xff);
8421
8422         return 0;
8423 }
8424 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
8425
8426 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
8427 {
8428         u32 reg;
8429
8430         rt2800_disable_wpdma(rt2x00dev);
8431
8432         /* Wait for DMA, ignore error */
8433         rt2800_wait_wpdma_ready(rt2x00dev);
8434
8435         reg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
8436         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_TX, 0);
8437         rt2x00_set_field32(&reg, MAC_SYS_CTRL_ENABLE_RX, 0);
8438         rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
8439 }
8440 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
8441
8442 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
8443 {
8444         u32 reg;
8445         u16 efuse_ctrl_reg;
8446
8447         if (rt2x00_rt(rt2x00dev, RT3290))
8448                 efuse_ctrl_reg = EFUSE_CTRL_3290;
8449         else
8450                 efuse_ctrl_reg = EFUSE_CTRL;
8451
8452         reg = rt2800_register_read(rt2x00dev, efuse_ctrl_reg);
8453         return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
8454 }
8455 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
8456
8457 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
8458 {
8459         u32 reg;
8460         u16 efuse_ctrl_reg;
8461         u16 efuse_data0_reg;
8462         u16 efuse_data1_reg;
8463         u16 efuse_data2_reg;
8464         u16 efuse_data3_reg;
8465
8466         if (rt2x00_rt(rt2x00dev, RT3290)) {
8467                 efuse_ctrl_reg = EFUSE_CTRL_3290;
8468                 efuse_data0_reg = EFUSE_DATA0_3290;
8469                 efuse_data1_reg = EFUSE_DATA1_3290;
8470                 efuse_data2_reg = EFUSE_DATA2_3290;
8471                 efuse_data3_reg = EFUSE_DATA3_3290;
8472         } else {
8473                 efuse_ctrl_reg = EFUSE_CTRL;
8474                 efuse_data0_reg = EFUSE_DATA0;
8475                 efuse_data1_reg = EFUSE_DATA1;
8476                 efuse_data2_reg = EFUSE_DATA2;
8477                 efuse_data3_reg = EFUSE_DATA3;
8478         }
8479         mutex_lock(&rt2x00dev->csr_mutex);
8480
8481         reg = rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg);
8482         rt2x00_set_field32(&reg, EFUSE_CTRL_ADDRESS_IN, i);
8483         rt2x00_set_field32(&reg, EFUSE_CTRL_MODE, 0);
8484         rt2x00_set_field32(&reg, EFUSE_CTRL_KICK, 1);
8485         rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
8486
8487         /* Wait until the EEPROM has been loaded */
8488         rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, &reg);
8489         /* Apparently the data is read from end to start */
8490         reg = rt2800_register_read_lock(rt2x00dev, efuse_data3_reg);
8491         /* The returned value is in CPU order, but eeprom is le */
8492         *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
8493         reg = rt2800_register_read_lock(rt2x00dev, efuse_data2_reg);
8494         *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
8495         reg = rt2800_register_read_lock(rt2x00dev, efuse_data1_reg);
8496         *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
8497         reg = rt2800_register_read_lock(rt2x00dev, efuse_data0_reg);
8498         *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
8499
8500         mutex_unlock(&rt2x00dev->csr_mutex);
8501 }
8502
8503 int rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
8504 {
8505         unsigned int i;
8506
8507         for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
8508                 rt2800_efuse_read(rt2x00dev, i);
8509
8510         return 0;
8511 }
8512 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
8513
8514 static u8 rt2800_get_txmixer_gain_24g(struct rt2x00_dev *rt2x00dev)
8515 {
8516         u16 word;
8517
8518         if (rt2x00_rt(rt2x00dev, RT3593))
8519                 return 0;
8520
8521         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG);
8522         if ((word & 0x00ff) != 0x00ff)
8523                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
8524
8525         return 0;
8526 }
8527
8528 static u8 rt2800_get_txmixer_gain_5g(struct rt2x00_dev *rt2x00dev)
8529 {
8530         u16 word;
8531
8532         if (rt2x00_rt(rt2x00dev, RT3593))
8533                 return 0;
8534
8535         word = rt2800_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A);
8536         if ((word & 0x00ff) != 0x00ff)
8537                 return rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
8538
8539         return 0;
8540 }
8541
8542 static int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
8543 {
8544         struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
8545         u16 word;
8546         u8 *mac;
8547         u8 default_lna_gain;
8548         int retval;
8549
8550         /*
8551          * Read the EEPROM.
8552          */
8553         retval = rt2800_read_eeprom(rt2x00dev);
8554         if (retval)
8555                 return retval;
8556
8557         /*
8558          * Start validation of the data that has been read.
8559          */
8560         mac = rt2800_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
8561         rt2x00lib_set_mac_address(rt2x00dev, mac);
8562
8563         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8564         if (word == 0xffff) {
8565                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8566                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
8567                 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
8568                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8569                 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word);
8570         } else if (rt2x00_rt(rt2x00dev, RT2860) ||
8571                    rt2x00_rt(rt2x00dev, RT2872)) {
8572                 /*
8573                  * There is a max of 2 RX streams for RT28x0 series
8574                  */
8575                 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
8576                         rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
8577                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
8578         }
8579
8580         word = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8581         if (word == 0xffff) {
8582                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
8583                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
8584                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
8585                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
8586                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
8587                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
8588                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
8589                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
8590                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
8591                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
8592                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
8593                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
8594                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
8595                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
8596                 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
8597                 rt2800_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
8598                 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word);
8599         }
8600
8601         word = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8602         if ((word & 0x00ff) == 0x00ff) {
8603                 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
8604                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8605                 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word);
8606         }
8607         if ((word & 0xff00) == 0xff00) {
8608                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
8609                                    LED_MODE_TXRX_ACTIVITY);
8610                 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
8611                 rt2800_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
8612                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
8613                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
8614                 rt2800_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
8615                 rt2x00_eeprom_dbg(rt2x00dev, "Led Mode: 0x%04x\n", word);
8616         }
8617
8618         /*
8619          * During the LNA validation we are going to use
8620          * lna0 as correct value. Note that EEPROM_LNA
8621          * is never validated.
8622          */
8623         word = rt2800_eeprom_read(rt2x00dev, EEPROM_LNA);
8624         default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
8625
8626         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG);
8627         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
8628                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
8629         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
8630                 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
8631         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
8632
8633         drv_data->txmixer_gain_24g = rt2800_get_txmixer_gain_24g(rt2x00dev);
8634
8635         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2);
8636         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
8637                 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
8638         if (!rt2x00_rt(rt2x00dev, RT3593)) {
8639                 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
8640                     rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
8641                         rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
8642                                            default_lna_gain);
8643         }
8644         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
8645
8646         drv_data->txmixer_gain_5g = rt2800_get_txmixer_gain_5g(rt2x00dev);
8647
8648         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A);
8649         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
8650                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
8651         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
8652                 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
8653         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
8654
8655         word = rt2800_eeprom_read(rt2x00dev, EEPROM_RSSI_A2);
8656         if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
8657                 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
8658         if (!rt2x00_rt(rt2x00dev, RT3593)) {
8659                 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
8660                     rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
8661                         rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
8662                                            default_lna_gain);
8663         }
8664         rt2800_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
8665
8666         if (rt2x00_rt(rt2x00dev, RT3593)) {
8667                 word = rt2800_eeprom_read(rt2x00dev, EEPROM_EXT_LNA2);
8668                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0x00 ||
8669                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A1) == 0xff)
8670                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8671                                            default_lna_gain);
8672                 if (rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0x00 ||
8673                     rt2x00_get_field16(word, EEPROM_EXT_LNA2_A2) == 0xff)
8674                         rt2x00_set_field16(&word, EEPROM_EXT_LNA2_A1,
8675                                            default_lna_gain);
8676                 rt2800_eeprom_write(rt2x00dev, EEPROM_EXT_LNA2, word);
8677         }
8678
8679         return 0;
8680 }
8681
8682 static int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
8683 {
8684         u16 value;
8685         u16 eeprom;
8686         u16 rf;
8687
8688         /*
8689          * Read EEPROM word for configuration.
8690          */
8691         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0);
8692
8693         /*
8694          * Identify RF chipset by EEPROM value
8695          * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
8696          * RT53xx: defined in "EEPROM_CHIP_ID" field
8697          */
8698         if (rt2x00_rt(rt2x00dev, RT3290) ||
8699             rt2x00_rt(rt2x00dev, RT5390) ||
8700             rt2x00_rt(rt2x00dev, RT5392) ||
8701             rt2x00_rt(rt2x00dev, RT6352))
8702                 rf = rt2800_eeprom_read(rt2x00dev, EEPROM_CHIP_ID);
8703         else if (rt2x00_rt(rt2x00dev, RT3352))
8704                 rf = RF3322;
8705         else if (rt2x00_rt(rt2x00dev, RT5350))
8706                 rf = RF5350;
8707         else
8708                 rf = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
8709
8710         switch (rf) {
8711         case RF2820:
8712         case RF2850:
8713         case RF2720:
8714         case RF2750:
8715         case RF3020:
8716         case RF2020:
8717         case RF3021:
8718         case RF3022:
8719         case RF3052:
8720         case RF3053:
8721         case RF3070:
8722         case RF3290:
8723         case RF3320:
8724         case RF3322:
8725         case RF5350:
8726         case RF5360:
8727         case RF5362:
8728         case RF5370:
8729         case RF5372:
8730         case RF5390:
8731         case RF5392:
8732         case RF5592:
8733         case RF7620:
8734                 break;
8735         default:
8736                 rt2x00_err(rt2x00dev, "Invalid RF chipset 0x%04x detected\n",
8737                            rf);
8738                 return -ENODEV;
8739         }
8740
8741         rt2x00_set_rf(rt2x00dev, rf);
8742
8743         /*
8744          * Identify default antenna configuration.
8745          */
8746         rt2x00dev->default_ant.tx_chain_num =
8747             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
8748         rt2x00dev->default_ant.rx_chain_num =
8749             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
8750
8751         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8752
8753         if (rt2x00_rt(rt2x00dev, RT3070) ||
8754             rt2x00_rt(rt2x00dev, RT3090) ||
8755             rt2x00_rt(rt2x00dev, RT3352) ||
8756             rt2x00_rt(rt2x00dev, RT3390)) {
8757                 value = rt2x00_get_field16(eeprom,
8758                                 EEPROM_NIC_CONF1_ANT_DIVERSITY);
8759                 switch (value) {
8760                 case 0:
8761                 case 1:
8762                 case 2:
8763                         rt2x00dev->default_ant.tx = ANTENNA_A;
8764                         rt2x00dev->default_ant.rx = ANTENNA_A;
8765                         break;
8766                 case 3:
8767                         rt2x00dev->default_ant.tx = ANTENNA_A;
8768                         rt2x00dev->default_ant.rx = ANTENNA_B;
8769                         break;
8770                 }
8771         } else {
8772                 rt2x00dev->default_ant.tx = ANTENNA_A;
8773                 rt2x00dev->default_ant.rx = ANTENNA_A;
8774         }
8775
8776         if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
8777                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
8778                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
8779         }
8780
8781         /*
8782          * Determine external LNA informations.
8783          */
8784         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
8785                 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
8786         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
8787                 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
8788
8789         /*
8790          * Detect if this device has an hardware controlled radio.
8791          */
8792         if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
8793                 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
8794
8795         /*
8796          * Detect if this device has Bluetooth co-existence.
8797          */
8798         if (!rt2x00_rt(rt2x00dev, RT3352) &&
8799             rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
8800                 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
8801
8802         /*
8803          * Read frequency offset and RF programming sequence.
8804          */
8805         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_FREQ);
8806         rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
8807
8808         /*
8809          * Store led settings, for correct led behaviour.
8810          */
8811 #ifdef CONFIG_RT2X00_LIB_LEDS
8812         rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
8813         rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
8814         rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
8815
8816         rt2x00dev->led_mcu_reg = eeprom;
8817 #endif /* CONFIG_RT2X00_LIB_LEDS */
8818
8819         /*
8820          * Check if support EIRP tx power limit feature.
8821          */
8822         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER);
8823
8824         if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
8825                                         EIRP_MAX_TX_POWER_LIMIT)
8826                 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
8827
8828         /*
8829          * Detect if device uses internal or external PA
8830          */
8831         eeprom = rt2800_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1);
8832
8833         if (rt2x00_rt(rt2x00dev, RT3352)) {
8834                 if (rt2x00_get_field16(eeprom,
8835                     EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352))
8836                     __set_bit(CAPABILITY_EXTERNAL_PA_TX0,
8837                               &rt2x00dev->cap_flags);
8838                 if (rt2x00_get_field16(eeprom,
8839                     EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352))
8840                     __set_bit(CAPABILITY_EXTERNAL_PA_TX1,
8841                               &rt2x00dev->cap_flags);
8842         }
8843
8844         return 0;
8845 }
8846
8847 /*
8848  * RF value list for rt28xx
8849  * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
8850  */
8851 static const struct rf_channel rf_vals[] = {
8852         { 1,  0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
8853         { 2,  0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
8854         { 3,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
8855         { 4,  0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
8856         { 5,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
8857         { 6,  0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
8858         { 7,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
8859         { 8,  0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
8860         { 9,  0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
8861         { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
8862         { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
8863         { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
8864         { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
8865         { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
8866
8867         /* 802.11 UNI / HyperLan 2 */
8868         { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
8869         { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
8870         { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
8871         { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
8872         { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
8873         { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
8874         { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
8875         { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
8876         { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
8877         { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
8878         { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
8879         { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
8880
8881         /* 802.11 HyperLan 2 */
8882         { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
8883         { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
8884         { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
8885         { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
8886         { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
8887         { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
8888         { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
8889         { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
8890         { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
8891         { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
8892         { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
8893         { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
8894         { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
8895         { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
8896         { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
8897         { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
8898
8899         /* 802.11 UNII */
8900         { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
8901         { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
8902         { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
8903         { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
8904         { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
8905         { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
8906         { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
8907         { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
8908         { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
8909         { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
8910         { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
8911
8912         /* 802.11 Japan */
8913         { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
8914         { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
8915         { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
8916         { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
8917         { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
8918         { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
8919         { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
8920 };
8921
8922 /*
8923  * RF value list for rt3xxx
8924  * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052 & RF3053)
8925  */
8926 static const struct rf_channel rf_vals_3x[] = {
8927         {1,  241, 2, 2 },
8928         {2,  241, 2, 7 },
8929         {3,  242, 2, 2 },
8930         {4,  242, 2, 7 },
8931         {5,  243, 2, 2 },
8932         {6,  243, 2, 7 },
8933         {7,  244, 2, 2 },
8934         {8,  244, 2, 7 },
8935         {9,  245, 2, 2 },
8936         {10, 245, 2, 7 },
8937         {11, 246, 2, 2 },
8938         {12, 246, 2, 7 },
8939         {13, 247, 2, 2 },
8940         {14, 248, 2, 4 },
8941
8942         /* 802.11 UNI / HyperLan 2 */
8943         {36, 0x56, 0, 4},
8944         {38, 0x56, 0, 6},
8945         {40, 0x56, 0, 8},
8946         {44, 0x57, 0, 0},
8947         {46, 0x57, 0, 2},
8948         {48, 0x57, 0, 4},
8949         {52, 0x57, 0, 8},
8950         {54, 0x57, 0, 10},
8951         {56, 0x58, 0, 0},
8952         {60, 0x58, 0, 4},
8953         {62, 0x58, 0, 6},
8954         {64, 0x58, 0, 8},
8955
8956         /* 802.11 HyperLan 2 */
8957         {100, 0x5b, 0, 8},
8958         {102, 0x5b, 0, 10},
8959         {104, 0x5c, 0, 0},
8960         {108, 0x5c, 0, 4},
8961         {110, 0x5c, 0, 6},
8962         {112, 0x5c, 0, 8},
8963         {116, 0x5d, 0, 0},
8964         {118, 0x5d, 0, 2},
8965         {120, 0x5d, 0, 4},
8966         {124, 0x5d, 0, 8},
8967         {126, 0x5d, 0, 10},
8968         {128, 0x5e, 0, 0},
8969         {132, 0x5e, 0, 4},
8970         {134, 0x5e, 0, 6},
8971         {136, 0x5e, 0, 8},
8972         {140, 0x5f, 0, 0},
8973
8974         /* 802.11 UNII */
8975         {149, 0x5f, 0, 9},
8976         {151, 0x5f, 0, 11},
8977         {153, 0x60, 0, 1},
8978         {157, 0x60, 0, 5},
8979         {159, 0x60, 0, 7},
8980         {161, 0x60, 0, 9},
8981         {165, 0x61, 0, 1},
8982         {167, 0x61, 0, 3},
8983         {169, 0x61, 0, 5},
8984         {171, 0x61, 0, 7},
8985         {173, 0x61, 0, 9},
8986 };
8987
8988 /*
8989  * RF value list for rt3xxx with Xtal20MHz
8990  * Supports: 2.4 GHz (all) (RF3322)
8991  */
8992 static const struct rf_channel rf_vals_3x_xtal20[] = {
8993         {1,    0xE2,     2,  0x14},
8994         {2,    0xE3,     2,  0x14},
8995         {3,    0xE4,     2,  0x14},
8996         {4,    0xE5,     2,  0x14},
8997         {5,    0xE6,     2,  0x14},
8998         {6,    0xE7,     2,  0x14},
8999         {7,    0xE8,     2,  0x14},
9000         {8,    0xE9,     2,  0x14},
9001         {9,    0xEA,     2,  0x14},
9002         {10,   0xEB,     2,  0x14},
9003         {11,   0xEC,     2,  0x14},
9004         {12,   0xED,     2,  0x14},
9005         {13,   0xEE,     2,  0x14},
9006         {14,   0xF0,     2,  0x18},
9007 };
9008
9009 static const struct rf_channel rf_vals_5592_xtal20[] = {
9010         /* Channel, N, K, mod, R */
9011         {1, 482, 4, 10, 3},
9012         {2, 483, 4, 10, 3},
9013         {3, 484, 4, 10, 3},
9014         {4, 485, 4, 10, 3},
9015         {5, 486, 4, 10, 3},
9016         {6, 487, 4, 10, 3},
9017         {7, 488, 4, 10, 3},
9018         {8, 489, 4, 10, 3},
9019         {9, 490, 4, 10, 3},
9020         {10, 491, 4, 10, 3},
9021         {11, 492, 4, 10, 3},
9022         {12, 493, 4, 10, 3},
9023         {13, 494, 4, 10, 3},
9024         {14, 496, 8, 10, 3},
9025         {36, 172, 8, 12, 1},
9026         {38, 173, 0, 12, 1},
9027         {40, 173, 4, 12, 1},
9028         {42, 173, 8, 12, 1},
9029         {44, 174, 0, 12, 1},
9030         {46, 174, 4, 12, 1},
9031         {48, 174, 8, 12, 1},
9032         {50, 175, 0, 12, 1},
9033         {52, 175, 4, 12, 1},
9034         {54, 175, 8, 12, 1},
9035         {56, 176, 0, 12, 1},
9036         {58, 176, 4, 12, 1},
9037         {60, 176, 8, 12, 1},
9038         {62, 177, 0, 12, 1},
9039         {64, 177, 4, 12, 1},
9040         {100, 183, 4, 12, 1},
9041         {102, 183, 8, 12, 1},
9042         {104, 184, 0, 12, 1},
9043         {106, 184, 4, 12, 1},
9044         {108, 184, 8, 12, 1},
9045         {110, 185, 0, 12, 1},
9046         {112, 185, 4, 12, 1},
9047         {114, 185, 8, 12, 1},
9048         {116, 186, 0, 12, 1},
9049         {118, 186, 4, 12, 1},
9050         {120, 186, 8, 12, 1},
9051         {122, 187, 0, 12, 1},
9052         {124, 187, 4, 12, 1},
9053         {126, 187, 8, 12, 1},
9054         {128, 188, 0, 12, 1},
9055         {130, 188, 4, 12, 1},
9056         {132, 188, 8, 12, 1},
9057         {134, 189, 0, 12, 1},
9058         {136, 189, 4, 12, 1},
9059         {138, 189, 8, 12, 1},
9060         {140, 190, 0, 12, 1},
9061         {149, 191, 6, 12, 1},
9062         {151, 191, 10, 12, 1},
9063         {153, 192, 2, 12, 1},
9064         {155, 192, 6, 12, 1},
9065         {157, 192, 10, 12, 1},
9066         {159, 193, 2, 12, 1},
9067         {161, 193, 6, 12, 1},
9068         {165, 194, 2, 12, 1},
9069         {184, 164, 0, 12, 1},
9070         {188, 164, 4, 12, 1},
9071         {192, 165, 8, 12, 1},
9072         {196, 166, 0, 12, 1},
9073 };
9074
9075 static const struct rf_channel rf_vals_5592_xtal40[] = {
9076         /* Channel, N, K, mod, R */
9077         {1, 241, 2, 10, 3},
9078         {2, 241, 7, 10, 3},
9079         {3, 242, 2, 10, 3},
9080         {4, 242, 7, 10, 3},
9081         {5, 243, 2, 10, 3},
9082         {6, 243, 7, 10, 3},
9083         {7, 244, 2, 10, 3},
9084         {8, 244, 7, 10, 3},
9085         {9, 245, 2, 10, 3},
9086         {10, 245, 7, 10, 3},
9087         {11, 246, 2, 10, 3},
9088         {12, 246, 7, 10, 3},
9089         {13, 247, 2, 10, 3},
9090         {14, 248, 4, 10, 3},
9091         {36, 86, 4, 12, 1},
9092         {38, 86, 6, 12, 1},
9093         {40, 86, 8, 12, 1},
9094         {42, 86, 10, 12, 1},
9095         {44, 87, 0, 12, 1},
9096         {46, 87, 2, 12, 1},
9097         {48, 87, 4, 12, 1},
9098         {50, 87, 6, 12, 1},
9099         {52, 87, 8, 12, 1},
9100         {54, 87, 10, 12, 1},
9101         {56, 88, 0, 12, 1},
9102         {58, 88, 2, 12, 1},
9103         {60, 88, 4, 12, 1},
9104         {62, 88, 6, 12, 1},
9105         {64, 88, 8, 12, 1},
9106         {100, 91, 8, 12, 1},
9107         {102, 91, 10, 12, 1},
9108         {104, 92, 0, 12, 1},
9109         {106, 92, 2, 12, 1},
9110         {108, 92, 4, 12, 1},
9111         {110, 92, 6, 12, 1},
9112         {112, 92, 8, 12, 1},
9113         {114, 92, 10, 12, 1},
9114         {116, 93, 0, 12, 1},
9115         {118, 93, 2, 12, 1},
9116         {120, 93, 4, 12, 1},
9117         {122, 93, 6, 12, 1},
9118         {124, 93, 8, 12, 1},
9119         {126, 93, 10, 12, 1},
9120         {128, 94, 0, 12, 1},
9121         {130, 94, 2, 12, 1},
9122         {132, 94, 4, 12, 1},
9123         {134, 94, 6, 12, 1},
9124         {136, 94, 8, 12, 1},
9125         {138, 94, 10, 12, 1},
9126         {140, 95, 0, 12, 1},
9127         {149, 95, 9, 12, 1},
9128         {151, 95, 11, 12, 1},
9129         {153, 96, 1, 12, 1},
9130         {155, 96, 3, 12, 1},
9131         {157, 96, 5, 12, 1},
9132         {159, 96, 7, 12, 1},
9133         {161, 96, 9, 12, 1},
9134         {165, 97, 1, 12, 1},
9135         {184, 82, 0, 12, 1},
9136         {188, 82, 4, 12, 1},
9137         {192, 82, 8, 12, 1},
9138         {196, 83, 0, 12, 1},
9139 };
9140
9141 static const struct rf_channel rf_vals_7620[] = {
9142         {1, 0x50, 0x99, 0x99, 1},
9143         {2, 0x50, 0x44, 0x44, 2},
9144         {3, 0x50, 0xEE, 0xEE, 2},
9145         {4, 0x50, 0x99, 0x99, 3},
9146         {5, 0x51, 0x44, 0x44, 0},
9147         {6, 0x51, 0xEE, 0xEE, 0},
9148         {7, 0x51, 0x99, 0x99, 1},
9149         {8, 0x51, 0x44, 0x44, 2},
9150         {9, 0x51, 0xEE, 0xEE, 2},
9151         {10, 0x51, 0x99, 0x99, 3},
9152         {11, 0x52, 0x44, 0x44, 0},
9153         {12, 0x52, 0xEE, 0xEE, 0},
9154         {13, 0x52, 0x99, 0x99, 1},
9155         {14, 0x52, 0x33, 0x33, 3},
9156 };
9157
9158 static int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
9159 {
9160         struct hw_mode_spec *spec = &rt2x00dev->spec;
9161         struct channel_info *info;
9162         char *default_power1;
9163         char *default_power2;
9164         char *default_power3;
9165         unsigned int i, tx_chains, rx_chains;
9166         u32 reg;
9167
9168         /*
9169          * Disable powersaving as default.
9170          */
9171         rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
9172
9173         /*
9174          * Change default retry settings to values corresponding more closely
9175          * to rate[0].count setting of minstrel rate control algorithm.
9176          */
9177         rt2x00dev->hw->wiphy->retry_short = 2;
9178         rt2x00dev->hw->wiphy->retry_long = 2;
9179
9180         /*
9181          * Initialize all hw fields.
9182          */
9183         ieee80211_hw_set(rt2x00dev->hw, REPORTS_TX_ACK_STATUS);
9184         ieee80211_hw_set(rt2x00dev->hw, AMPDU_AGGREGATION);
9185         ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK);
9186         ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM);
9187         ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS);
9188
9189         /*
9190          * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
9191          * unless we are capable of sending the buffered frames out after the
9192          * DTIM transmission using rt2x00lib_beacondone. This will send out
9193          * multicast and broadcast traffic immediately instead of buffering it
9194          * infinitly and thus dropping it after some time.
9195          */
9196         if (!rt2x00_is_usb(rt2x00dev))
9197                 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING);
9198
9199         /* Set MFP if HW crypto is disabled. */
9200         if (rt2800_hwcrypt_disabled(rt2x00dev))
9201                 ieee80211_hw_set(rt2x00dev->hw, MFP_CAPABLE);
9202
9203         SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
9204         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
9205                                 rt2800_eeprom_addr(rt2x00dev,
9206                                                    EEPROM_MAC_ADDR_0));
9207
9208         /*
9209          * As rt2800 has a global fallback table we cannot specify
9210          * more then one tx rate per frame but since the hw will
9211          * try several rates (based on the fallback table) we should
9212          * initialize max_report_rates to the maximum number of rates
9213          * we are going to try. Otherwise mac80211 will truncate our
9214          * reported tx rates and the rc algortihm will end up with
9215          * incorrect data.
9216          */
9217         rt2x00dev->hw->max_rates = 1;
9218         rt2x00dev->hw->max_report_rates = 7;
9219         rt2x00dev->hw->max_rate_tries = 1;
9220
9221         /*
9222          * Initialize hw_mode information.
9223          */
9224         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
9225
9226         switch (rt2x00dev->chip.rf) {
9227         case RF2720:
9228         case RF2820:
9229                 spec->num_channels = 14;
9230                 spec->channels = rf_vals;
9231                 break;
9232
9233         case RF2750:
9234         case RF2850:
9235                 spec->num_channels = ARRAY_SIZE(rf_vals);
9236                 spec->channels = rf_vals;
9237                 break;
9238
9239         case RF2020:
9240         case RF3020:
9241         case RF3021:
9242         case RF3022:
9243         case RF3070:
9244         case RF3290:
9245         case RF3320:
9246         case RF3322:
9247         case RF5350:
9248         case RF5360:
9249         case RF5362:
9250         case RF5370:
9251         case RF5372:
9252         case RF5390:
9253         case RF5392:
9254                 spec->num_channels = 14;
9255                 if (rt2800_clk_is_20mhz(rt2x00dev))
9256                         spec->channels = rf_vals_3x_xtal20;
9257                 else
9258                         spec->channels = rf_vals_3x;
9259                 break;
9260
9261         case RF7620:
9262                 spec->num_channels = ARRAY_SIZE(rf_vals_7620);
9263                 spec->channels = rf_vals_7620;
9264                 break;
9265
9266         case RF3052:
9267         case RF3053:
9268                 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
9269                 spec->channels = rf_vals_3x;
9270                 break;
9271
9272         case RF5592:
9273                 reg = rt2800_register_read(rt2x00dev, MAC_DEBUG_INDEX);
9274                 if (rt2x00_get_field32(reg, MAC_DEBUG_INDEX_XTAL)) {
9275                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal40);
9276                         spec->channels = rf_vals_5592_xtal40;
9277                 } else {
9278                         spec->num_channels = ARRAY_SIZE(rf_vals_5592_xtal20);
9279                         spec->channels = rf_vals_5592_xtal20;
9280                 }
9281                 break;
9282         }
9283
9284         if (WARN_ON_ONCE(!spec->channels))
9285                 return -ENODEV;
9286
9287         spec->supported_bands = SUPPORT_BAND_2GHZ;
9288         if (spec->num_channels > 14)
9289                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
9290
9291         /*
9292          * Initialize HT information.
9293          */
9294         if (!rt2x00_rf(rt2x00dev, RF2020))
9295                 spec->ht.ht_supported = true;
9296         else
9297                 spec->ht.ht_supported = false;
9298
9299         spec->ht.cap =
9300             IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
9301             IEEE80211_HT_CAP_GRN_FLD |
9302             IEEE80211_HT_CAP_SGI_20 |
9303             IEEE80211_HT_CAP_SGI_40;
9304
9305         tx_chains = rt2x00dev->default_ant.tx_chain_num;
9306         rx_chains = rt2x00dev->default_ant.rx_chain_num;
9307
9308         if (tx_chains >= 2)
9309                 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
9310
9311         spec->ht.cap |= rx_chains << IEEE80211_HT_CAP_RX_STBC_SHIFT;
9312
9313         spec->ht.ampdu_factor = (rx_chains > 1) ? 3 : 2;
9314         spec->ht.ampdu_density = 4;
9315         spec->ht.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
9316         if (tx_chains != rx_chains) {
9317                 spec->ht.mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
9318                 spec->ht.mcs.tx_params |=
9319                     (tx_chains - 1) << IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT;
9320         }
9321
9322         switch (rx_chains) {
9323         case 3:
9324                 spec->ht.mcs.rx_mask[2] = 0xff;
9325         case 2:
9326                 spec->ht.mcs.rx_mask[1] = 0xff;
9327         case 1:
9328                 spec->ht.mcs.rx_mask[0] = 0xff;
9329                 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
9330                 break;
9331         }
9332
9333         /*
9334          * Create channel information array
9335          */
9336         info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
9337         if (!info)
9338                 return -ENOMEM;
9339
9340         spec->channels_info = info;
9341
9342         default_power1 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
9343         default_power2 = rt2800_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
9344
9345         if (rt2x00dev->default_ant.tx_chain_num > 2)
9346                 default_power3 = rt2800_eeprom_addr(rt2x00dev,
9347                                                     EEPROM_EXT_TXPOWER_BG3);
9348         else
9349                 default_power3 = NULL;
9350
9351         for (i = 0; i < 14; i++) {
9352                 info[i].default_power1 = default_power1[i];
9353                 info[i].default_power2 = default_power2[i];
9354                 if (default_power3)
9355                         info[i].default_power3 = default_power3[i];
9356         }
9357
9358         if (spec->num_channels > 14) {
9359                 default_power1 = rt2800_eeprom_addr(rt2x00dev,
9360                                                     EEPROM_TXPOWER_A1);
9361                 default_power2 = rt2800_eeprom_addr(rt2x00dev,
9362                                                     EEPROM_TXPOWER_A2);
9363
9364                 if (rt2x00dev->default_ant.tx_chain_num > 2)
9365                         default_power3 =
9366                                 rt2800_eeprom_addr(rt2x00dev,
9367                                                    EEPROM_EXT_TXPOWER_A3);
9368                 else
9369                         default_power3 = NULL;
9370
9371                 for (i = 14; i < spec->num_channels; i++) {
9372                         info[i].default_power1 = default_power1[i - 14];
9373                         info[i].default_power2 = default_power2[i - 14];
9374                         if (default_power3)
9375                                 info[i].default_power3 = default_power3[i - 14];
9376                 }
9377         }
9378
9379         switch (rt2x00dev->chip.rf) {
9380         case RF2020:
9381         case RF3020:
9382         case RF3021:
9383         case RF3022:
9384         case RF3320:
9385         case RF3052:
9386         case RF3053:
9387         case RF3070:
9388         case RF3290:
9389         case RF5350:
9390         case RF5360:
9391         case RF5362:
9392         case RF5370:
9393         case RF5372:
9394         case RF5390:
9395         case RF5392:
9396         case RF5592:
9397         case RF7620:
9398                 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
9399                 break;
9400         }
9401
9402         return 0;
9403 }
9404
9405 static int rt2800_probe_rt(struct rt2x00_dev *rt2x00dev)
9406 {
9407         u32 reg;
9408         u32 rt;
9409         u32 rev;
9410
9411         if (rt2x00_rt(rt2x00dev, RT3290))
9412                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0_3290);
9413         else
9414                 reg = rt2800_register_read(rt2x00dev, MAC_CSR0);
9415
9416         rt = rt2x00_get_field32(reg, MAC_CSR0_CHIPSET);
9417         rev = rt2x00_get_field32(reg, MAC_CSR0_REVISION);
9418
9419         switch (rt) {
9420         case RT2860:
9421         case RT2872:
9422         case RT2883:
9423         case RT3070:
9424         case RT3071:
9425         case RT3090:
9426         case RT3290:
9427         case RT3352:
9428         case RT3390:
9429         case RT3572:
9430         case RT3593:
9431         case RT5350:
9432         case RT5390:
9433         case RT5392:
9434         case RT5592:
9435                 break;
9436         default:
9437                 rt2x00_err(rt2x00dev, "Invalid RT chipset 0x%04x, rev %04x detected\n",
9438                            rt, rev);
9439                 return -ENODEV;
9440         }
9441
9442         if (rt == RT5390 && rt2x00_is_soc(rt2x00dev))
9443                 rt = RT6352;
9444
9445         rt2x00_set_rt(rt2x00dev, rt, rev);
9446
9447         return 0;
9448 }
9449
9450 int rt2800_probe_hw(struct rt2x00_dev *rt2x00dev)
9451 {
9452         int retval;
9453         u32 reg;
9454
9455         retval = rt2800_probe_rt(rt2x00dev);
9456         if (retval)
9457                 return retval;
9458
9459         /*
9460          * Allocate eeprom data.
9461          */
9462         retval = rt2800_validate_eeprom(rt2x00dev);
9463         if (retval)
9464                 return retval;
9465
9466         retval = rt2800_init_eeprom(rt2x00dev);
9467         if (retval)
9468                 return retval;
9469
9470         /*
9471          * Enable rfkill polling by setting GPIO direction of the
9472          * rfkill switch GPIO pin correctly.
9473          */
9474         reg = rt2800_register_read(rt2x00dev, GPIO_CTRL);
9475         rt2x00_set_field32(&reg, GPIO_CTRL_DIR2, 1);
9476         rt2800_register_write(rt2x00dev, GPIO_CTRL, reg);
9477
9478         /*
9479          * Initialize hw specifications.
9480          */
9481         retval = rt2800_probe_hw_mode(rt2x00dev);
9482         if (retval)
9483                 return retval;
9484
9485         /*
9486          * Set device capabilities.
9487          */
9488         __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
9489         __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
9490         if (!rt2x00_is_usb(rt2x00dev))
9491                 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
9492
9493         /*
9494          * Set device requirements.
9495          */
9496         if (!rt2x00_is_soc(rt2x00dev))
9497                 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
9498         __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
9499         __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
9500         if (!rt2800_hwcrypt_disabled(rt2x00dev))
9501                 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
9502         __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
9503         __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
9504         if (rt2x00_is_usb(rt2x00dev))
9505                 __set_bit(REQUIRE_PS_AUTOWAKE, &rt2x00dev->cap_flags);
9506         else {
9507                 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
9508                 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
9509         }
9510
9511         /*
9512          * Set the rssi offset.
9513          */
9514         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
9515
9516         return 0;
9517 }
9518 EXPORT_SYMBOL_GPL(rt2800_probe_hw);
9519
9520 /*
9521  * IEEE80211 stack callback functions.
9522  */
9523 void rt2800_get_key_seq(struct ieee80211_hw *hw,
9524                         struct ieee80211_key_conf *key,
9525                         struct ieee80211_key_seq *seq)
9526 {
9527         struct rt2x00_dev *rt2x00dev = hw->priv;
9528         struct mac_iveiv_entry iveiv_entry;
9529         u32 offset;
9530
9531         if (key->cipher != WLAN_CIPHER_SUITE_TKIP)
9532                 return;
9533
9534         offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
9535         rt2800_register_multiread(rt2x00dev, offset,
9536                                       &iveiv_entry, sizeof(iveiv_entry));
9537
9538         memcpy(&seq->tkip.iv16, &iveiv_entry.iv[0], 2);
9539         memcpy(&seq->tkip.iv32, &iveiv_entry.iv[4], 4);
9540 }
9541 EXPORT_SYMBOL_GPL(rt2800_get_key_seq);
9542
9543 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
9544 {
9545         struct rt2x00_dev *rt2x00dev = hw->priv;
9546         u32 reg;
9547         bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
9548
9549         reg = rt2800_register_read(rt2x00dev, TX_RTS_CFG);
9550         rt2x00_set_field32(&reg, TX_RTS_CFG_RTS_THRES, value);
9551         rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
9552
9553         reg = rt2800_register_read(rt2x00dev, CCK_PROT_CFG);
9554         rt2x00_set_field32(&reg, CCK_PROT_CFG_RTS_TH_EN, enabled);
9555         rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
9556
9557         reg = rt2800_register_read(rt2x00dev, OFDM_PROT_CFG);
9558         rt2x00_set_field32(&reg, OFDM_PROT_CFG_RTS_TH_EN, enabled);
9559         rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
9560
9561         reg = rt2800_register_read(rt2x00dev, MM20_PROT_CFG);
9562         rt2x00_set_field32(&reg, MM20_PROT_CFG_RTS_TH_EN, enabled);
9563         rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
9564
9565         reg = rt2800_register_read(rt2x00dev, MM40_PROT_CFG);
9566         rt2x00_set_field32(&reg, MM40_PROT_CFG_RTS_TH_EN, enabled);
9567         rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
9568
9569         reg = rt2800_register_read(rt2x00dev, GF20_PROT_CFG);
9570         rt2x00_set_field32(&reg, GF20_PROT_CFG_RTS_TH_EN, enabled);
9571         rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
9572
9573         reg = rt2800_register_read(rt2x00dev, GF40_PROT_CFG);
9574         rt2x00_set_field32(&reg, GF40_PROT_CFG_RTS_TH_EN, enabled);
9575         rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
9576
9577         return 0;
9578 }
9579 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
9580
9581 int rt2800_conf_tx(struct ieee80211_hw *hw,
9582                    struct ieee80211_vif *vif, u16 queue_idx,
9583                    const struct ieee80211_tx_queue_params *params)
9584 {
9585         struct rt2x00_dev *rt2x00dev = hw->priv;
9586         struct data_queue *queue;
9587         struct rt2x00_field32 field;
9588         int retval;
9589         u32 reg;
9590         u32 offset;
9591
9592         /*
9593          * First pass the configuration through rt2x00lib, that will
9594          * update the queue settings and validate the input. After that
9595          * we are free to update the registers based on the value
9596          * in the queue parameter.
9597          */
9598         retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
9599         if (retval)
9600                 return retval;
9601
9602         /*
9603          * We only need to perform additional register initialization
9604          * for WMM queues/
9605          */
9606         if (queue_idx >= 4)
9607                 return 0;
9608
9609         queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
9610
9611         /* Update WMM TXOP register */
9612         offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
9613         field.bit_offset = (queue_idx & 1) * 16;
9614         field.bit_mask = 0xffff << field.bit_offset;
9615
9616         reg = rt2800_register_read(rt2x00dev, offset);
9617         rt2x00_set_field32(&reg, field, queue->txop);
9618         rt2800_register_write(rt2x00dev, offset, reg);
9619
9620         /* Update WMM registers */
9621         field.bit_offset = queue_idx * 4;
9622         field.bit_mask = 0xf << field.bit_offset;
9623
9624         reg = rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG);
9625         rt2x00_set_field32(&reg, field, queue->aifs);
9626         rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
9627
9628         reg = rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG);
9629         rt2x00_set_field32(&reg, field, queue->cw_min);
9630         rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
9631
9632         reg = rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG);
9633         rt2x00_set_field32(&reg, field, queue->cw_max);
9634         rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
9635
9636         /* Update EDCA registers */
9637         offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
9638
9639         reg = rt2800_register_read(rt2x00dev, offset);
9640         rt2x00_set_field32(&reg, EDCA_AC0_CFG_TX_OP, queue->txop);
9641         rt2x00_set_field32(&reg, EDCA_AC0_CFG_AIFSN, queue->aifs);
9642         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMIN, queue->cw_min);
9643         rt2x00_set_field32(&reg, EDCA_AC0_CFG_CWMAX, queue->cw_max);
9644         rt2800_register_write(rt2x00dev, offset, reg);
9645
9646         return 0;
9647 }
9648 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
9649
9650 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
9651 {
9652         struct rt2x00_dev *rt2x00dev = hw->priv;
9653         u64 tsf;
9654         u32 reg;
9655
9656         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW1);
9657         tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
9658         reg = rt2800_register_read(rt2x00dev, TSF_TIMER_DW0);
9659         tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
9660
9661         return tsf;
9662 }
9663 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
9664
9665 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
9666                         struct ieee80211_ampdu_params *params)
9667 {
9668         struct ieee80211_sta *sta = params->sta;
9669         enum ieee80211_ampdu_mlme_action action = params->action;
9670         u16 tid = params->tid;
9671         struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
9672         int ret = 0;
9673
9674         /*
9675          * Don't allow aggregation for stations the hardware isn't aware
9676          * of because tx status reports for frames to an unknown station
9677          * always contain wcid=WCID_END+1 and thus we can't distinguish
9678          * between multiple stations which leads to unwanted situations
9679          * when the hw reorders frames due to aggregation.
9680          */
9681         if (sta_priv->wcid > WCID_END)
9682                 return 1;
9683
9684         switch (action) {
9685         case IEEE80211_AMPDU_RX_START:
9686         case IEEE80211_AMPDU_RX_STOP:
9687                 /*
9688                  * The hw itself takes care of setting up BlockAck mechanisms.
9689                  * So, we only have to allow mac80211 to nagotiate a BlockAck
9690                  * agreement. Once that is done, the hw will BlockAck incoming
9691                  * AMPDUs without further setup.
9692                  */
9693                 break;
9694         case IEEE80211_AMPDU_TX_START:
9695                 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9696                 break;
9697         case IEEE80211_AMPDU_TX_STOP_CONT:
9698         case IEEE80211_AMPDU_TX_STOP_FLUSH:
9699         case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
9700                 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
9701                 break;
9702         case IEEE80211_AMPDU_TX_OPERATIONAL:
9703                 break;
9704         default:
9705                 rt2x00_warn((struct rt2x00_dev *)hw->priv,
9706                             "Unknown AMPDU action\n");
9707         }
9708
9709         return ret;
9710 }
9711 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
9712
9713 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
9714                       struct survey_info *survey)
9715 {
9716         struct rt2x00_dev *rt2x00dev = hw->priv;
9717         struct ieee80211_conf *conf = &hw->conf;
9718         u32 idle, busy, busy_ext;
9719
9720         if (idx != 0)
9721                 return -ENOENT;
9722
9723         survey->channel = conf->chandef.chan;
9724
9725         idle = rt2800_register_read(rt2x00dev, CH_IDLE_STA);
9726         busy = rt2800_register_read(rt2x00dev, CH_BUSY_STA);
9727         busy_ext = rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC);
9728
9729         if (idle || busy) {
9730                 survey->filled = SURVEY_INFO_TIME |
9731                                  SURVEY_INFO_TIME_BUSY |
9732                                  SURVEY_INFO_TIME_EXT_BUSY;
9733
9734                 survey->time = (idle + busy) / 1000;
9735                 survey->time_busy = busy / 1000;
9736                 survey->time_ext_busy = busy_ext / 1000;
9737         }
9738
9739         if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
9740                 survey->filled |= SURVEY_INFO_IN_USE;
9741
9742         return 0;
9743
9744 }
9745 EXPORT_SYMBOL_GPL(rt2800_get_survey);
9746
9747 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
9748 MODULE_VERSION(DRV_VERSION);
9749 MODULE_DESCRIPTION("Ralink RT2800 library");
9750 MODULE_LICENSE("GPL");