1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
8 #include <linux/spi/spi.h>
9 #include <linux/crc7.h>
10 #include <linux/crc-itu-t.h>
11 #include <linux/gpio/consumer.h>
16 #define SPI_MODALIAS "wilc1000_spi"
18 static bool enable_crc7; /* protect SPI commands with CRC7 */
19 module_param(enable_crc7, bool, 0644);
20 MODULE_PARM_DESC(enable_crc7,
21 "Enable CRC7 checksum to protect command transfers\n"
22 "\t\t\tagainst corruption during the SPI transfer.\n"
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
24 "\t\t\tof enabling this is small.");
26 static bool enable_crc16; /* protect SPI data with CRC16 */
27 module_param(enable_crc16, bool, 0644);
28 MODULE_PARM_DESC(enable_crc16,
29 "Enable CRC16 checksum to protect data transfers\n"
30 "\t\t\tagainst corruption during the SPI transfer.\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
32 "\t\t\tof enabling this may be substantial.");
35 * For CMD_SINGLE_READ and CMD_INTERNAL_READ, WILC may insert one or
36 * more zero bytes between the command response and the DATA Start tag
37 * (0xf3). This behavior appears to be undocumented in "ATWILC1000
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
39 * zero bytes when the SPI bus operates at 48MHz and none when it
42 #define WILC_SPI_RSP_HDR_EXTRA_DATA 8
45 bool isinit; /* true if SPI protocol has been configured */
46 bool probing_crc; /* true if we're probing chip's CRC config */
47 bool crc7_enabled; /* true if crc7 is currently enabled */
48 bool crc16_enabled; /* true if crc16 is currently enabled */
50 struct gpio_desc *enable; /* ENABLE GPIO or NULL */
51 struct gpio_desc *reset; /* RESET GPIO or NULL */
55 static const struct wilc_hif_func wilc_hif_spi;
57 static int wilc_spi_reset(struct wilc *wilc);
59 /********************************************
61 * Spi protocol Function
63 ********************************************/
65 #define CMD_DMA_WRITE 0xc1
66 #define CMD_DMA_READ 0xc2
67 #define CMD_INTERNAL_WRITE 0xc3
68 #define CMD_INTERNAL_READ 0xc4
69 #define CMD_TERMINATE 0xc5
70 #define CMD_REPEAT 0xc6
71 #define CMD_DMA_EXT_WRITE 0xc7
72 #define CMD_DMA_EXT_READ 0xc8
73 #define CMD_SINGLE_WRITE 0xc9
74 #define CMD_SINGLE_READ 0xca
75 #define CMD_RESET 0xcf
77 #define SPI_ENABLE_VMM_RETRY_LIMIT 2
79 /* SPI response fields (section 11.1.2 in ATWILC1000 User Guide): */
80 #define RSP_START_FIELD GENMASK(7, 4)
81 #define RSP_TYPE_FIELD GENMASK(3, 0)
83 /* SPI response values for the response fields: */
84 #define RSP_START_TAG 0xc
85 #define RSP_TYPE_FIRST_PACKET 0x1
86 #define RSP_TYPE_INNER_PACKET 0x2
87 #define RSP_TYPE_LAST_PACKET 0x3
88 #define RSP_STATE_NO_ERROR 0x00
90 #define PROTOCOL_REG_PKT_SZ_MASK GENMASK(6, 4)
91 #define PROTOCOL_REG_CRC16_MASK GENMASK(3, 3)
92 #define PROTOCOL_REG_CRC7_MASK GENMASK(2, 2)
95 * The SPI data packet size may be any integer power of two in the
96 * range from 256 to 8192 bytes.
98 #define DATA_PKT_LOG_SZ_MIN 8 /* 256 B */
99 #define DATA_PKT_LOG_SZ_MAX 13 /* 8 KiB */
102 * Select the data packet size (log2 of number of bytes): Use the
103 * maximum data packet size. We only retransmit complete packets, so
104 * there is no benefit from using smaller data packets.
106 #define DATA_PKT_LOG_SZ DATA_PKT_LOG_SZ_MAX
107 #define DATA_PKT_SZ (1 << DATA_PKT_LOG_SZ)
109 #define WILC_SPI_COMMAND_STAT_SUCCESS 0
110 #define WILC_GET_RESP_HDR_START(h) (((h) >> 4) & 0xf)
112 struct wilc_spi_cmd {
118 } __packed simple_cmd;
128 } __packed dma_cmd_ext;
133 } __packed internal_w_cmd;
142 struct wilc_spi_read_rsp_data {
148 struct wilc_spi_rsp_data {
154 struct wilc_spi_special_cmd_rsp {
160 static int wilc_parse_gpios(struct wilc *wilc)
162 struct spi_device *spi = to_spi_device(wilc->dev);
163 struct wilc_spi *spi_priv = wilc->bus_data;
164 struct wilc_gpios *gpios = &spi_priv->gpios;
166 /* get ENABLE pin and deassert it (if it is defined): */
167 gpios->enable = devm_gpiod_get_optional(&spi->dev,
168 "enable", GPIOD_OUT_LOW);
169 /* get RESET pin and assert it (if it is defined): */
171 /* if enable pin exists, reset must exist as well */
172 gpios->reset = devm_gpiod_get(&spi->dev,
173 "reset", GPIOD_OUT_HIGH);
174 if (IS_ERR(gpios->reset)) {
175 dev_err(&spi->dev, "missing reset gpio.\n");
176 return PTR_ERR(gpios->reset);
179 gpios->reset = devm_gpiod_get_optional(&spi->dev,
180 "reset", GPIOD_OUT_HIGH);
185 static void wilc_wlan_power(struct wilc *wilc, bool on)
187 struct wilc_spi *spi_priv = wilc->bus_data;
188 struct wilc_gpios *gpios = &spi_priv->gpios;
192 gpiod_set_value(gpios->enable, 1);
194 /* deassert RESET: */
195 gpiod_set_value(gpios->reset, 0);
198 gpiod_set_value(gpios->reset, 1);
199 /* deassert ENABLE: */
200 gpiod_set_value(gpios->enable, 0);
204 static int wilc_bus_probe(struct spi_device *spi)
208 struct wilc_spi *spi_priv;
210 spi_priv = kzalloc(sizeof(*spi_priv), GFP_KERNEL);
214 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi);
218 spi_set_drvdata(spi, wilc);
219 wilc->dev = &spi->dev;
220 wilc->bus_data = spi_priv;
221 wilc->dev_irq_num = spi->irq;
223 ret = wilc_parse_gpios(wilc);
227 wilc->rtc_clk = devm_clk_get_optional(&spi->dev, "rtc");
228 if (IS_ERR(wilc->rtc_clk)) {
229 ret = PTR_ERR(wilc->rtc_clk);
232 clk_prepare_enable(wilc->rtc_clk);
237 wilc_netdev_cleanup(wilc);
243 static void wilc_bus_remove(struct spi_device *spi)
245 struct wilc *wilc = spi_get_drvdata(spi);
246 struct wilc_spi *spi_priv = wilc->bus_data;
248 clk_disable_unprepare(wilc->rtc_clk);
249 wilc_netdev_cleanup(wilc);
253 static const struct of_device_id wilc_of_match[] = {
254 { .compatible = "microchip,wilc1000", },
257 MODULE_DEVICE_TABLE(of, wilc_of_match);
259 static const struct spi_device_id wilc_spi_id[] = {
263 MODULE_DEVICE_TABLE(spi, wilc_spi_id);
265 static struct spi_driver wilc_spi_driver = {
267 .name = SPI_MODALIAS,
268 .of_match_table = wilc_of_match,
270 .id_table = wilc_spi_id,
271 .probe = wilc_bus_probe,
272 .remove = wilc_bus_remove,
274 module_spi_driver(wilc_spi_driver);
275 MODULE_LICENSE("GPL");
277 static int wilc_spi_tx(struct wilc *wilc, u8 *b, u32 len)
279 struct spi_device *spi = to_spi_device(wilc->dev);
281 struct spi_message msg;
284 struct spi_transfer tr = {
289 .unit = SPI_DELAY_UNIT_USECS
292 char *r_buffer = kzalloc(len, GFP_KERNEL);
297 tr.rx_buf = r_buffer;
298 dev_dbg(&spi->dev, "Request writing %d bytes\n", len);
300 memset(&msg, 0, sizeof(msg));
301 spi_message_init(&msg);
303 spi_message_add_tail(&tr, &msg);
305 ret = spi_sync(spi, &msg);
307 dev_err(&spi->dev, "SPI transaction failed\n");
312 "can't write data with the following length: %d\n",
320 static int wilc_spi_rx(struct wilc *wilc, u8 *rb, u32 rlen)
322 struct spi_device *spi = to_spi_device(wilc->dev);
326 struct spi_message msg;
327 struct spi_transfer tr = {
332 .unit = SPI_DELAY_UNIT_USECS
336 char *t_buffer = kzalloc(rlen, GFP_KERNEL);
341 tr.tx_buf = t_buffer;
343 memset(&msg, 0, sizeof(msg));
344 spi_message_init(&msg);
346 spi_message_add_tail(&tr, &msg);
348 ret = spi_sync(spi, &msg);
350 dev_err(&spi->dev, "SPI transaction failed\n");
354 "can't read data with the following length: %u\n",
362 static int wilc_spi_tx_rx(struct wilc *wilc, u8 *wb, u8 *rb, u32 rlen)
364 struct spi_device *spi = to_spi_device(wilc->dev);
368 struct spi_message msg;
369 struct spi_transfer tr = {
376 .unit = SPI_DELAY_UNIT_USECS
381 memset(&msg, 0, sizeof(msg));
382 spi_message_init(&msg);
385 spi_message_add_tail(&tr, &msg);
386 ret = spi_sync(spi, &msg);
388 dev_err(&spi->dev, "SPI transaction failed\n");
391 "can't read data with the following length: %u\n",
399 static int spi_data_write(struct wilc *wilc, u8 *b, u32 sz)
401 struct spi_device *spi = to_spi_device(wilc->dev);
402 struct wilc_spi *spi_priv = wilc->bus_data;
405 u8 cmd, order, crc[2];
413 if (sz <= DATA_PKT_SZ) {
417 nbytes = DATA_PKT_SZ;
430 if (wilc_spi_tx(wilc, &cmd, 1)) {
432 "Failed data block cmd write, bus error...\n");
440 if (wilc_spi_tx(wilc, &b[ix], nbytes)) {
442 "Failed data block write, bus error...\n");
450 if (spi_priv->crc16_enabled) {
451 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
452 crc[0] = crc_calc >> 8;
454 if (wilc_spi_tx(wilc, crc, 2)) {
455 dev_err(&spi->dev, "Failed data block crc write, bus error...\n");
462 * No need to wait for response
471 /********************************************
473 * Spi Internal Read/Write Function
475 ********************************************/
476 static u8 wilc_get_crc7(u8 *buffer, u32 len)
478 return crc7_be(0xfe, buffer, len);
481 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b,
484 struct spi_device *spi = to_spi_device(wilc->dev);
485 struct wilc_spi *spi_priv = wilc->bus_data;
487 int cmd_len, resp_len, i;
488 u16 crc_calc, crc_recv;
489 struct wilc_spi_cmd *c;
490 struct wilc_spi_rsp_data *r;
491 struct wilc_spi_read_rsp_data *r_data;
493 memset(wb, 0x0, sizeof(wb));
494 memset(rb, 0x0, sizeof(rb));
495 c = (struct wilc_spi_cmd *)wb;
497 if (cmd == CMD_SINGLE_READ) {
498 c->u.simple_cmd.addr[0] = adr >> 16;
499 c->u.simple_cmd.addr[1] = adr >> 8;
500 c->u.simple_cmd.addr[2] = adr;
501 } else if (cmd == CMD_INTERNAL_READ) {
502 c->u.simple_cmd.addr[0] = adr >> 8;
504 c->u.simple_cmd.addr[0] |= BIT(7);
505 c->u.simple_cmd.addr[1] = adr;
506 c->u.simple_cmd.addr[2] = 0x0;
508 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd);
512 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
513 resp_len = sizeof(*r) + sizeof(*r_data) + WILC_SPI_RSP_HDR_EXTRA_DATA;
515 if (spi_priv->crc7_enabled) {
516 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
521 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
523 "spi buffer size too small (%d) (%d) (%zu)\n",
524 cmd_len, resp_len, ARRAY_SIZE(wb));
528 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
529 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
533 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
534 if (r->rsp_cmd_type != cmd && !clockless) {
535 if (!spi_priv->probing_crc)
537 "Failed cmd, cmd (%02x), resp (%02x)\n",
538 cmd, r->rsp_cmd_type);
542 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
543 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
548 for (i = 0; i < WILC_SPI_RSP_HDR_EXTRA_DATA; ++i)
549 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf)
552 if (i >= WILC_SPI_RSP_HDR_EXTRA_DATA) {
553 dev_err(&spi->dev, "Error, data start missing\n");
557 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i];
560 memcpy(b, r_data->data, 4);
562 if (!clockless && spi_priv->crc16_enabled) {
563 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1];
564 crc_calc = crc_itu_t(0xffff, r_data->data, 4);
565 if (crc_recv != crc_calc) {
566 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
567 "(calculated 0x%04x)\n", __func__,
576 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data,
579 struct spi_device *spi = to_spi_device(wilc->dev);
580 struct wilc_spi *spi_priv = wilc->bus_data;
582 int cmd_len, resp_len;
583 struct wilc_spi_cmd *c;
584 struct wilc_spi_rsp_data *r;
586 memset(wb, 0x0, sizeof(wb));
587 memset(rb, 0x0, sizeof(rb));
588 c = (struct wilc_spi_cmd *)wb;
590 if (cmd == CMD_INTERNAL_WRITE) {
591 c->u.internal_w_cmd.addr[0] = adr >> 8;
593 c->u.internal_w_cmd.addr[0] |= BIT(7);
595 c->u.internal_w_cmd.addr[1] = adr;
596 c->u.internal_w_cmd.data = cpu_to_be32(data);
597 cmd_len = offsetof(struct wilc_spi_cmd, u.internal_w_cmd.crc);
598 if (spi_priv->crc7_enabled)
599 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
600 } else if (cmd == CMD_SINGLE_WRITE) {
601 c->u.w_cmd.addr[0] = adr >> 16;
602 c->u.w_cmd.addr[1] = adr >> 8;
603 c->u.w_cmd.addr[2] = adr;
604 c->u.w_cmd.data = cpu_to_be32(data);
605 cmd_len = offsetof(struct wilc_spi_cmd, u.w_cmd.crc);
606 if (spi_priv->crc7_enabled)
607 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
609 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd);
613 if (spi_priv->crc7_enabled)
616 resp_len = sizeof(*r);
618 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
620 "spi buffer size too small (%d) (%d) (%zu)\n",
621 cmd_len, resp_len, ARRAY_SIZE(wb));
625 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
626 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
630 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
632 * Clockless registers operations might return unexptected responses,
633 * even if successful.
635 if (r->rsp_cmd_type != cmd && !clockless) {
637 "Failed cmd response, cmd (%02x), resp (%02x)\n",
638 cmd, r->rsp_cmd_type);
642 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) {
643 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
651 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz)
653 struct spi_device *spi = to_spi_device(wilc->dev);
654 struct wilc_spi *spi_priv = wilc->bus_data;
655 u16 crc_recv, crc_calc;
657 int cmd_len, resp_len;
660 struct wilc_spi_cmd *c;
661 struct wilc_spi_rsp_data *r;
663 memset(wb, 0x0, sizeof(wb));
664 memset(rb, 0x0, sizeof(rb));
665 c = (struct wilc_spi_cmd *)wb;
667 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) {
668 c->u.dma_cmd.addr[0] = adr >> 16;
669 c->u.dma_cmd.addr[1] = adr >> 8;
670 c->u.dma_cmd.addr[2] = adr;
671 c->u.dma_cmd.size[0] = sz >> 8;
672 c->u.dma_cmd.size[1] = sz;
673 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd.crc);
674 if (spi_priv->crc7_enabled)
675 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
676 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) {
677 c->u.dma_cmd_ext.addr[0] = adr >> 16;
678 c->u.dma_cmd_ext.addr[1] = adr >> 8;
679 c->u.dma_cmd_ext.addr[2] = adr;
680 c->u.dma_cmd_ext.size[0] = sz >> 16;
681 c->u.dma_cmd_ext.size[1] = sz >> 8;
682 c->u.dma_cmd_ext.size[2] = sz;
683 cmd_len = offsetof(struct wilc_spi_cmd, u.dma_cmd_ext.crc);
684 if (spi_priv->crc7_enabled)
685 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len);
687 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n",
691 if (spi_priv->crc7_enabled)
694 resp_len = sizeof(*r);
696 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
697 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n",
698 cmd_len, resp_len, ARRAY_SIZE(wb));
702 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
703 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
707 r = (struct wilc_spi_rsp_data *)&rb[cmd_len];
708 if (r->rsp_cmd_type != cmd) {
710 "Failed cmd response, cmd (%02x), resp (%02x)\n",
711 cmd, r->rsp_cmd_type);
715 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
716 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
721 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE)
728 nbytes = min_t(u32, sz, DATA_PKT_SZ);
731 * Data Response header
735 if (wilc_spi_rx(wilc, &rsp, 1)) {
737 "Failed resp read, bus err\n");
740 if (WILC_GET_RESP_HDR_START(rsp) == 0xf)
747 if (wilc_spi_rx(wilc, &b[ix], nbytes)) {
749 "Failed block read, bus err\n");
756 if (spi_priv->crc16_enabled) {
757 if (wilc_spi_rx(wilc, crc, 2)) {
759 "Failed block CRC read, bus err\n");
762 crc_recv = (crc[0] << 8) | crc[1];
763 crc_calc = crc_itu_t(0xffff, &b[ix], nbytes);
764 if (crc_recv != crc_calc) {
765 dev_err(&spi->dev, "%s: bad CRC 0x%04x "
766 "(calculated 0x%04x)\n", __func__,
778 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd)
780 struct spi_device *spi = to_spi_device(wilc->dev);
781 struct wilc_spi *spi_priv = wilc->bus_data;
783 int cmd_len, resp_len = 0;
784 struct wilc_spi_cmd *c;
785 struct wilc_spi_special_cmd_rsp *r;
787 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET)
790 memset(wb, 0x0, sizeof(wb));
791 memset(rb, 0x0, sizeof(rb));
792 c = (struct wilc_spi_cmd *)wb;
795 if (cmd == CMD_RESET)
796 memset(c->u.simple_cmd.addr, 0xFF, 3);
798 cmd_len = offsetof(struct wilc_spi_cmd, u.simple_cmd.crc);
799 resp_len = sizeof(*r);
801 if (spi_priv->crc7_enabled) {
802 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len);
805 if (cmd_len + resp_len > ARRAY_SIZE(wb)) {
806 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n",
807 cmd_len, resp_len, ARRAY_SIZE(wb));
811 if (wilc_spi_tx_rx(wilc, wb, rb, cmd_len + resp_len)) {
812 dev_err(&spi->dev, "Failed cmd write, bus error...\n");
816 r = (struct wilc_spi_special_cmd_rsp *)&rb[cmd_len];
817 if (r->rsp_cmd_type != cmd) {
818 if (!spi_priv->probing_crc)
820 "Failed cmd response, cmd (%02x), resp (%02x)\n",
821 cmd, r->rsp_cmd_type);
825 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) {
826 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n",
833 static int wilc_spi_read_reg(struct wilc *wilc, u32 addr, u32 *data)
835 struct spi_device *spi = to_spi_device(wilc->dev);
837 u8 cmd = CMD_SINGLE_READ;
840 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
841 /* Clockless register */
842 cmd = CMD_INTERNAL_READ;
846 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless);
848 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr);
857 static int wilc_spi_read(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
859 struct spi_device *spi = to_spi_device(wilc->dev);
865 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_READ, addr, buf, size);
867 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr);
874 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat)
876 struct spi_device *spi = to_spi_device(wilc->dev);
879 result = wilc_spi_write_cmd(wilc, CMD_INTERNAL_WRITE, adr, dat, 0);
881 dev_err(&spi->dev, "Failed internal write cmd...\n");
888 static int spi_internal_read(struct wilc *wilc, u32 adr, u32 *data)
890 struct spi_device *spi = to_spi_device(wilc->dev);
891 struct wilc_spi *spi_priv = wilc->bus_data;
894 result = wilc_spi_single_read(wilc, CMD_INTERNAL_READ, adr, data, 0);
896 if (!spi_priv->probing_crc)
897 dev_err(&spi->dev, "Failed internal read cmd...\n");
906 /********************************************
910 ********************************************/
912 static int wilc_spi_write_reg(struct wilc *wilc, u32 addr, u32 data)
914 struct spi_device *spi = to_spi_device(wilc->dev);
916 u8 cmd = CMD_SINGLE_WRITE;
919 if (addr < WILC_SPI_CLOCKLESS_ADDR_LIMIT) {
920 /* Clockless register */
921 cmd = CMD_INTERNAL_WRITE;
925 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless);
927 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr);
934 static int spi_data_rsp(struct wilc *wilc, u8 cmd)
936 struct spi_device *spi = to_spi_device(wilc->dev);
941 * The response to data packets is two bytes long. For
942 * efficiency's sake, wilc_spi_write() wisely ignores the
943 * responses for all packets but the final one. The downside
944 * of that optimization is that when the final data packet is
945 * short, we may receive (part of) the response to the
946 * second-to-last packet before the one for the final packet.
947 * To handle this, we always read 4 bytes and then search for
948 * the last byte that contains the "Response Start" code (0xc
949 * in the top 4 bits). We then know that this byte is the
950 * first response byte of the final data packet.
952 result = wilc_spi_rx(wilc, rsp, sizeof(rsp));
954 dev_err(&spi->dev, "Failed bus error...\n");
958 for (i = sizeof(rsp) - 2; i >= 0; --i)
959 if (FIELD_GET(RSP_START_FIELD, rsp[i]) == RSP_START_TAG)
964 "Data packet response missing (%02x %02x %02x %02x)\n",
965 rsp[0], rsp[1], rsp[2], rsp[3]);
969 /* rsp[i] is the last response start byte */
971 if (FIELD_GET(RSP_TYPE_FIELD, rsp[i]) != RSP_TYPE_LAST_PACKET
972 || rsp[i + 1] != RSP_STATE_NO_ERROR) {
973 dev_err(&spi->dev, "Data response error (%02x %02x)\n",
980 static int wilc_spi_write(struct wilc *wilc, u32 addr, u8 *buf, u32 size)
982 struct spi_device *spi = to_spi_device(wilc->dev);
986 * has to be greated than 4
991 result = wilc_spi_dma_rw(wilc, CMD_DMA_EXT_WRITE, addr, NULL, size);
994 "Failed cmd, write block (%08x)...\n", addr);
1001 result = spi_data_write(wilc, buf, size);
1003 dev_err(&spi->dev, "Failed block data write...\n");
1010 return spi_data_rsp(wilc, CMD_DMA_EXT_WRITE);
1013 /********************************************
1017 ********************************************/
1019 static int wilc_spi_reset(struct wilc *wilc)
1021 struct spi_device *spi = to_spi_device(wilc->dev);
1022 struct wilc_spi *spi_priv = wilc->bus_data;
1025 result = wilc_spi_special_cmd(wilc, CMD_RESET);
1026 if (result && !spi_priv->probing_crc)
1027 dev_err(&spi->dev, "Failed cmd reset\n");
1032 static int wilc_spi_deinit(struct wilc *wilc)
1034 struct wilc_spi *spi_priv = wilc->bus_data;
1036 spi_priv->isinit = false;
1037 wilc_wlan_power(wilc, false);
1041 static int wilc_spi_init(struct wilc *wilc, bool resume)
1043 struct spi_device *spi = to_spi_device(wilc->dev);
1044 struct wilc_spi *spi_priv = wilc->bus_data;
1049 if (spi_priv->isinit) {
1050 /* Confirm we can read chipid register without error: */
1051 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1055 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1058 wilc_wlan_power(wilc, true);
1061 * configure protocol
1065 * Infer the CRC settings that are currently in effect. This
1066 * is necessary because we can't be sure that the chip has
1067 * been RESET (e.g, after module unload and reload).
1069 spi_priv->probing_crc = true;
1070 spi_priv->crc7_enabled = enable_crc7;
1071 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */
1072 for (i = 0; i < 2; ++i) {
1073 ret = spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1076 spi_priv->crc7_enabled = !enable_crc7;
1079 dev_err(&spi->dev, "Failed with CRC7 on and off.\n");
1083 /* set up the desired CRC configuration: */
1084 reg &= ~(PROTOCOL_REG_CRC7_MASK | PROTOCOL_REG_CRC16_MASK);
1086 reg |= PROTOCOL_REG_CRC7_MASK;
1088 reg |= PROTOCOL_REG_CRC16_MASK;
1090 /* set up the data packet size: */
1091 BUILD_BUG_ON(DATA_PKT_LOG_SZ < DATA_PKT_LOG_SZ_MIN
1092 || DATA_PKT_LOG_SZ > DATA_PKT_LOG_SZ_MAX);
1093 reg &= ~PROTOCOL_REG_PKT_SZ_MASK;
1094 reg |= FIELD_PREP(PROTOCOL_REG_PKT_SZ_MASK,
1095 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN);
1097 /* establish the new setup: */
1098 ret = spi_internal_write(wilc, WILC_SPI_PROTOCOL_OFFSET, reg);
1101 "[wilc spi %d]: Failed internal write reg\n",
1105 /* update our state to match new protocol settings: */
1106 spi_priv->crc7_enabled = enable_crc7;
1107 spi_priv->crc16_enabled = enable_crc16;
1109 /* re-read to make sure new settings are in effect: */
1110 spi_internal_read(wilc, WILC_SPI_PROTOCOL_OFFSET, ®);
1112 spi_priv->probing_crc = false;
1115 * make sure can read chip id without protocol error
1117 ret = wilc_spi_read_reg(wilc, WILC_CHIPID, &chipid);
1119 dev_err(&spi->dev, "Fail cmd read chip id...\n");
1123 spi_priv->isinit = true;
1128 static int wilc_spi_read_size(struct wilc *wilc, u32 *size)
1132 ret = spi_internal_read(wilc,
1133 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size);
1134 *size = FIELD_GET(IRQ_DMA_WD_CNT_MASK, *size);
1139 static int wilc_spi_read_int(struct wilc *wilc, u32 *int_status)
1141 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE,
1145 static int wilc_spi_clear_int_ext(struct wilc *wilc, u32 val)
1148 int retry = SPI_ENABLE_VMM_RETRY_LIMIT;
1152 ret = spi_internal_write(wilc,
1153 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1158 ret = spi_internal_read(wilc,
1159 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE,
1161 if (ret || ((check & EN_VMM) == (val & EN_VMM)))
1169 static int wilc_spi_sync_ext(struct wilc *wilc, int nint)
1171 struct spi_device *spi = to_spi_device(wilc->dev);
1175 if (nint > MAX_NUM_INT) {
1176 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint);
1181 * interrupt pin mux select
1183 ret = wilc_spi_read_reg(wilc, WILC_PIN_MUX_0, ®);
1185 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1190 ret = wilc_spi_write_reg(wilc, WILC_PIN_MUX_0, reg);
1192 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1200 ret = wilc_spi_read_reg(wilc, WILC_INTR_ENABLE, ®);
1202 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1207 for (i = 0; (i < 5) && (nint > 0); i++, nint--)
1208 reg |= (BIT((27 + i)));
1210 ret = wilc_spi_write_reg(wilc, WILC_INTR_ENABLE, reg);
1212 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1217 ret = wilc_spi_read_reg(wilc, WILC_INTR2_ENABLE, ®);
1219 dev_err(&spi->dev, "Failed read reg (%08x)...\n",
1224 for (i = 0; (i < 3) && (nint > 0); i++, nint--)
1227 ret = wilc_spi_write_reg(wilc, WILC_INTR2_ENABLE, reg);
1229 dev_err(&spi->dev, "Failed write reg (%08x)...\n",
1238 /* Global spi HIF function table */
1239 static const struct wilc_hif_func wilc_hif_spi = {
1240 .hif_init = wilc_spi_init,
1241 .hif_deinit = wilc_spi_deinit,
1242 .hif_read_reg = wilc_spi_read_reg,
1243 .hif_write_reg = wilc_spi_write_reg,
1244 .hif_block_rx = wilc_spi_read,
1245 .hif_block_tx = wilc_spi_write,
1246 .hif_read_int = wilc_spi_read_int,
1247 .hif_clear_int_ext = wilc_spi_clear_int_ext,
1248 .hif_read_size = wilc_spi_read_size,
1249 .hif_block_tx_ext = wilc_spi_write,
1250 .hif_block_rx_ext = wilc_spi_read,
1251 .hif_sync_ext = wilc_spi_sync_ext,
1252 .hif_reset = wilc_spi_reset,