2 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
3 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
18 #include <linux/bitfield.h>
19 #include <linux/kernel.h>
20 #include <linux/device.h>
21 #include <linux/mutex.h>
22 #include <linux/usb.h>
23 #include <linux/completion.h>
24 #include <net/mac80211.h>
25 #include <linux/debugfs.h>
26 #include <linux/average.h>
30 #define MT_CALIBRATE_INTERVAL (4 * HZ)
32 #define MT_FREQ_CAL_INIT_DELAY (30 * HZ)
33 #define MT_FREQ_CAL_CHECK_INTERVAL (10 * HZ)
34 #define MT_FREQ_CAL_ADJ_INTERVAL (HZ / 2)
36 #define MT_BBP_REG_VERSION 0x00
38 #define MT_USB_AGGR_SIZE_LIMIT 28 /* * 1024B */
39 #define MT_USB_AGGR_TIMEOUT 0x80 /* * 33ns */
41 #define MT_RX_URB_SIZE (PAGE_SIZE << MT_RX_ORDER)
43 struct mt7601u_dma_buf {
55 struct mt7601u_dma_buf resp;
56 struct completion resp_cmpl;
59 struct mt7601u_freq_cal {
60 struct delayed_work work;
74 #define N_RX_ENTRIES 16
75 struct mt7601u_rx_queue {
76 struct mt7601u_dev *dev;
78 struct mt7601u_dma_buf_rx {
89 #define N_TX_ENTRIES 64
91 struct mt7601u_tx_queue {
92 struct mt7601u_dev *dev;
94 struct mt7601u_dma_buf_tx {
101 unsigned int entries;
103 unsigned int fifo_seq;
114 #define GROUP_WCID(idx) (N_WCIDS - 2 - idx)
116 struct mt7601u_eeprom_params;
118 #define MT_EE_TEMPERATURE_SLOPE 39
119 #define MT_FREQ_OFFSET_INVALID -128
133 MT7601U_STATE_INITIALIZED,
134 MT7601U_STATE_REMOVED,
135 MT7601U_STATE_WLAN_RUNNING,
136 MT7601U_STATE_MCU_RUNNING,
137 MT7601U_STATE_SCANNING,
138 MT7601U_STATE_READING_STATS,
139 MT7601U_STATE_MORE_STATS,
142 DECLARE_EWMA(rssi, 10, 4);
145 * struct mt7601u_dev - adapter structure
146 * @lock: protects @wcid->tx_rate.
147 * @mac_lock: locks out mac80211's tx status and rx paths.
148 * @tx_lock: protects @tx_q and changes of MT7601U_STATE_*_STATS
150 * @rx_lock: protects @rx_q.
151 * @con_mon_lock: protects @ap_bssid, @bcn_*, @avg_rssi.
152 * @mutex: ensures exclusive access from mac80211 callbacks.
153 * @vendor_req_mutex: protects @vend_buf, ensures atomicity of read/write
155 * @reg_atomic_mutex: ensures atomicity of indirect register accesses
156 * (accesses to RF and BBP).
157 * @hw_atomic_mutex: ensures exclusive access to HW during critical
158 * operations (power management, channel switch).
161 struct ieee80211_hw *hw;
168 unsigned long wcid_mask[N_WCIDS / BITS_PER_LONG];
170 struct cfg80211_chan_def chandef;
171 struct ieee80211_supported_band *sband_2g;
173 struct mt7601u_mcu mcu;
175 struct delayed_work cal_work;
176 struct delayed_work mac_work;
178 struct workqueue_struct *stat_wq;
179 struct delayed_work stat_work;
181 struct mt76_wcid *mon_wcid;
182 struct mt76_wcid __rcu *wcid[N_WCIDS];
187 const u16 *beacon_offsets;
189 u8 macaddr[ETH_ALEN];
190 struct mt7601u_eeprom_params *ee;
192 struct mutex vendor_req_mutex;
195 struct mutex reg_atomic_mutex;
196 struct mutex hw_atomic_mutex;
208 struct tasklet_struct tx_tasklet;
209 struct mt7601u_tx_queue *tx_q;
210 struct sk_buff_head tx_skb_done;
212 atomic_t avg_ampdu_len;
216 struct tasklet_struct rx_tasklet;
217 struct mt7601u_rx_queue rx_q;
219 /* Connection monitoring things */
220 spinlock_t con_mon_lock;
221 u8 ap_bssid[ETH_ALEN];
226 struct ewma_rssi avg_rssi;
230 struct mt7601u_freq_cal freq_cal;
236 s16 tssi_init_hvga_offset_db;
240 enum mt_temp_mode temp_mode;
244 bool pll_lock_protect;
252 struct mac_stats stats;
255 struct mt7601u_tssi_params {
272 struct mt76_wcid group_wcid;
276 struct mt76_wcid wcid;
277 u16 agg_ssn[IEEE80211_NUM_TIDS];
280 struct mt76_reg_pair {
287 extern const struct ieee80211_ops mt7601u_ops;
289 void mt7601u_init_debugfs(struct mt7601u_dev *dev);
291 u32 mt7601u_rr(struct mt7601u_dev *dev, u32 offset);
292 void mt7601u_wr(struct mt7601u_dev *dev, u32 offset, u32 val);
293 u32 mt7601u_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
294 u32 mt7601u_rmc(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val);
295 void mt7601u_wr_copy(struct mt7601u_dev *dev, u32 offset,
296 const void *data, int len);
298 int mt7601u_wait_asic_ready(struct mt7601u_dev *dev);
299 bool mt76_poll(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
301 bool mt76_poll_msec(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val,
304 /* Compatibility with mt76 */
305 #define mt76_rmw_field(_dev, _reg, _field, _val) \
306 mt76_rmw(_dev, _reg, _field, FIELD_PREP(_field, _val))
308 static inline u32 mt76_rr(struct mt7601u_dev *dev, u32 offset)
310 return mt7601u_rr(dev, offset);
313 static inline void mt76_wr(struct mt7601u_dev *dev, u32 offset, u32 val)
315 return mt7601u_wr(dev, offset, val);
319 mt76_rmw(struct mt7601u_dev *dev, u32 offset, u32 mask, u32 val)
321 return mt7601u_rmw(dev, offset, mask, val);
324 static inline u32 mt76_set(struct mt7601u_dev *dev, u32 offset, u32 val)
326 return mt76_rmw(dev, offset, 0, val);
329 static inline u32 mt76_clear(struct mt7601u_dev *dev, u32 offset, u32 val)
331 return mt76_rmw(dev, offset, val, 0);
334 int mt7601u_write_reg_pairs(struct mt7601u_dev *dev, u32 base,
335 const struct mt76_reg_pair *data, int len);
336 int mt7601u_burst_write_regs(struct mt7601u_dev *dev, u32 offset,
337 const u32 *data, int n);
338 void mt7601u_addr_wr(struct mt7601u_dev *dev, const u32 offset, const u8 *addr);
341 struct mt7601u_dev *mt7601u_alloc_device(struct device *dev);
342 int mt7601u_init_hardware(struct mt7601u_dev *dev);
343 int mt7601u_register_device(struct mt7601u_dev *dev);
344 void mt7601u_cleanup(struct mt7601u_dev *dev);
346 int mt7601u_mac_start(struct mt7601u_dev *dev);
347 void mt7601u_mac_stop(struct mt7601u_dev *dev);
350 int mt7601u_phy_init(struct mt7601u_dev *dev);
351 int mt7601u_wait_bbp_ready(struct mt7601u_dev *dev);
352 void mt7601u_set_rx_path(struct mt7601u_dev *dev, u8 path);
353 void mt7601u_set_tx_dac(struct mt7601u_dev *dev, u8 path);
354 int mt7601u_bbp_set_bw(struct mt7601u_dev *dev, int bw);
355 void mt7601u_agc_save(struct mt7601u_dev *dev);
356 void mt7601u_agc_restore(struct mt7601u_dev *dev);
357 int mt7601u_phy_set_channel(struct mt7601u_dev *dev,
358 struct cfg80211_chan_def *chandef);
359 void mt7601u_phy_recalibrate_after_assoc(struct mt7601u_dev *dev);
360 int mt7601u_phy_get_rssi(struct mt7601u_dev *dev,
361 struct mt7601u_rxwi *rxwi, u16 rate);
362 void mt7601u_phy_con_cal_onoff(struct mt7601u_dev *dev,
363 struct ieee80211_bss_conf *info);
366 void mt7601u_mac_work(struct work_struct *work);
367 void mt7601u_mac_set_protection(struct mt7601u_dev *dev, bool legacy_prot,
369 void mt7601u_mac_set_short_preamble(struct mt7601u_dev *dev, bool short_preamb);
370 void mt7601u_mac_config_tsf(struct mt7601u_dev *dev, bool enable, int interval);
372 mt7601u_mac_wcid_setup(struct mt7601u_dev *dev, u8 idx, u8 vif_idx, u8 *mac);
373 void mt7601u_mac_set_ampdu_factor(struct mt7601u_dev *dev);
376 void mt7601u_tx(struct ieee80211_hw *hw, struct ieee80211_tx_control *control,
377 struct sk_buff *skb);
378 int mt7601u_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
379 u16 queue, const struct ieee80211_tx_queue_params *params);
380 void mt7601u_tx_status(struct mt7601u_dev *dev, struct sk_buff *skb);
381 void mt7601u_tx_stat(struct work_struct *work);
384 void mt76_remove_hdr_pad(struct sk_buff *skb);
385 int mt76_insert_hdr_pad(struct sk_buff *skb);
387 u32 mt7601u_bbp_set_ctrlch(struct mt7601u_dev *dev, bool below);
389 static inline u32 mt7601u_mac_set_ctrlch(struct mt7601u_dev *dev, bool below)
391 return mt7601u_rmc(dev, MT_TX_BAND_CFG, 1, below);
394 int mt7601u_dma_init(struct mt7601u_dev *dev);
395 void mt7601u_dma_cleanup(struct mt7601u_dev *dev);
397 int mt7601u_dma_enqueue_tx(struct mt7601u_dev *dev, struct sk_buff *skb,
398 struct mt76_wcid *wcid, int hw_q);