2 * (c) Copyright 2002-2010, Ralink Technology, Inc.
3 * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
4 * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
24 mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable)
28 /* Note: we don't turn off WLAN_CLK because that makes the device
29 * not respond properly on the probe path.
30 * In case anyone (PSM?) wants to use this function we can
31 * bring the clock stuff back and fixup the probe path.
35 val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
36 MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
38 val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
40 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
44 set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
46 clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
50 for (i = 200; i; i--) {
51 val = mt7601u_rr(dev, MT_CMB_CTRL);
53 if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD)
59 /* Note: vendor driver tries to disable/enable wlan here and retry
60 * but the code which does it is so buggy it must have never
61 * triggered, so don't bother.
64 dev_err(dev->dev, "Error: PLL and XTAL check failed!\n");
67 static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset)
71 mutex_lock(&dev->hw_atomic_mutex);
73 val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
76 val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
77 val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
79 if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
80 val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
81 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
82 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
85 val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
86 MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
90 mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
93 mt7601u_set_wlan_state(dev, val, enable);
95 mutex_unlock(&dev->hw_atomic_mutex);
98 static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev)
100 mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
101 MT_MAC_SYS_CTRL_RESET_BBP));
102 mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
104 mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
107 static void mt7601u_init_usb_dma(struct mt7601u_dev *dev)
111 val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |
112 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT,
113 MT_USB_AGGR_SIZE_LIMIT) |
114 MT_USB_DMA_CFG_RX_BULK_EN |
115 MT_USB_DMA_CFG_TX_BULK_EN;
116 if (dev->in_max_packet == 512)
117 val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN;
118 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
120 val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
121 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
122 val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
123 mt7601u_wr(dev, MT_USB_DMA_CFG, val);
126 static int mt7601u_init_bbp(struct mt7601u_dev *dev)
130 ret = mt7601u_wait_bbp_ready(dev);
134 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals,
135 ARRAY_SIZE(bbp_common_vals));
139 return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals,
140 ARRAY_SIZE(bbp_chip_vals));
144 mt76_init_beacon_offsets(struct mt7601u_dev *dev)
146 u16 base = MT_BEACON_BASE;
150 for (i = 0; i < 16; i++) {
151 u16 addr = dev->beacon_offsets[i];
153 regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
156 for (i = 0; i < 4; i++)
157 mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
160 static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev)
164 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals,
165 ARRAY_SIZE(mac_common_vals));
168 ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN,
169 mac_chip_vals, ARRAY_SIZE(mac_chip_vals));
173 mt76_init_beacon_offsets(dev);
175 mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
180 static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev)
185 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
189 for (i = 0; i < N_WCIDS; i++) {
190 vals[i * 2] = 0xffffffff;
191 vals[i * 2 + 1] = 0x00ffffff;
194 ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE,
201 static int mt7601u_init_key_mem(struct mt7601u_dev *dev)
205 return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
206 vals, ARRAY_SIZE(vals));
209 static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev)
214 vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
218 for (i = 0; i < N_WCIDS * 2; i++)
221 ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE,
228 static void mt7601u_reset_counters(struct mt7601u_dev *dev)
230 mt7601u_rr(dev, MT_RX_STA_CNT0);
231 mt7601u_rr(dev, MT_RX_STA_CNT1);
232 mt7601u_rr(dev, MT_RX_STA_CNT2);
233 mt7601u_rr(dev, MT_TX_STA_CNT0);
234 mt7601u_rr(dev, MT_TX_STA_CNT1);
235 mt7601u_rr(dev, MT_TX_STA_CNT2);
238 int mt7601u_mac_start(struct mt7601u_dev *dev)
240 mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
242 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
243 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000))
246 dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
247 MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC |
248 MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP |
249 MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND |
250 MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS |
251 MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL |
252 MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV;
253 mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
255 mt7601u_wr(dev, MT_MAC_SYS_CTRL,
256 MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
258 if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
259 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50))
265 static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev)
269 if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
272 mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
273 MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN |
274 MT_BEACON_TIME_CFG_BEACON_TX);
276 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
277 dev_warn(dev->dev, "Warning: TX DMA did not stop!\n");
279 /* Page count on TxQ */
281 while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
282 (mt76_rr(dev, 0x0a30) & 0x000000ff) ||
283 (mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
286 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
287 dev_warn(dev->dev, "Warning: MAC TX did not stop!\n");
289 mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
290 MT_MAC_SYS_CTRL_ENABLE_TX);
292 /* Page count on RxQ */
296 if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
297 !mt76_rr(dev, 0x0a30) &&
298 !mt76_rr(dev, 0x0a34)) {
306 if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
307 dev_warn(dev->dev, "Warning: MAC RX did not stop!\n");
309 if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
310 dev_warn(dev->dev, "Warning: RX DMA did not stop!\n");
313 void mt7601u_mac_stop(struct mt7601u_dev *dev)
315 mt7601u_mac_stop_hw(dev);
316 flush_delayed_work(&dev->stat_work);
317 cancel_delayed_work_sync(&dev->stat_work);
320 static void mt7601u_stop_hardware(struct mt7601u_dev *dev)
322 mt7601u_chip_onoff(dev, false, false);
325 int mt7601u_init_hardware(struct mt7601u_dev *dev)
327 static const u16 beacon_offsets[16] = {
328 /* 512 byte per beacon */
329 0xc000, 0xc200, 0xc400, 0xc600,
330 0xc800, 0xca00, 0xcc00, 0xce00,
331 0xd000, 0xd200, 0xd400, 0xd600,
332 0xd800, 0xda00, 0xdc00, 0xde00
336 dev->beacon_offsets = beacon_offsets;
338 mt7601u_chip_onoff(dev, true, false);
340 ret = mt7601u_wait_asic_ready(dev);
343 ret = mt7601u_mcu_init(dev);
347 if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
348 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
349 MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) {
354 /* Wait for ASIC ready after FW load. */
355 ret = mt7601u_wait_asic_ready(dev);
359 mt7601u_reset_csr_bbp(dev);
360 mt7601u_init_usb_dma(dev);
362 ret = mt7601u_mcu_cmd_init(dev);
365 ret = mt7601u_dma_init(dev);
368 ret = mt7601u_write_mac_initvals(dev);
372 if (!mt76_poll_msec(dev, MT_MAC_STATUS,
373 MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) {
378 ret = mt7601u_init_bbp(dev);
381 ret = mt7601u_init_wcid_mem(dev);
384 ret = mt7601u_init_key_mem(dev);
387 ret = mt7601u_init_wcid_attr_mem(dev);
391 mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
392 MT_BEACON_TIME_CFG_SYNC_MODE |
393 MT_BEACON_TIME_CFG_TBTT_EN |
394 MT_BEACON_TIME_CFG_BEACON_TX));
396 mt7601u_reset_counters(dev);
398 mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
400 mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
401 FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |
402 FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
404 ret = mt7601u_eeprom_init(dev);
408 ret = mt7601u_phy_init(dev);
412 mt7601u_set_rx_path(dev, 0);
413 mt7601u_set_tx_dac(dev, 0);
415 mt7601u_mac_set_ctrlch(dev, false);
416 mt7601u_bbp_set_ctrlch(dev, false);
417 mt7601u_bbp_set_bw(dev, MT_BW_20);
422 mt7601u_dma_cleanup(dev);
424 mt7601u_mcu_cmd_deinit(dev);
426 mt7601u_chip_onoff(dev, false, false);
430 void mt7601u_cleanup(struct mt7601u_dev *dev)
432 if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state))
435 mt7601u_stop_hardware(dev);
436 mt7601u_dma_cleanup(dev);
437 mt7601u_mcu_cmd_deinit(dev);
440 struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev)
442 struct ieee80211_hw *hw;
443 struct mt7601u_dev *dev;
445 hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops);
452 mutex_init(&dev->vendor_req_mutex);
453 mutex_init(&dev->reg_atomic_mutex);
454 mutex_init(&dev->hw_atomic_mutex);
455 mutex_init(&dev->mutex);
456 spin_lock_init(&dev->tx_lock);
457 spin_lock_init(&dev->rx_lock);
458 spin_lock_init(&dev->lock);
459 spin_lock_init(&dev->mac_lock);
460 spin_lock_init(&dev->con_mon_lock);
461 atomic_set(&dev->avg_ampdu_len, 1);
462 skb_queue_head_init(&dev->tx_skb_done);
464 dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0);
466 ieee80211_free_hw(hw);
473 #define CHAN2G(_idx, _freq) { \
474 .band = NL80211_BAND_2GHZ, \
475 .center_freq = (_freq), \
476 .hw_value = (_idx), \
480 static const struct ieee80211_channel mt76_channels_2ghz[] = {
497 #define CCK_RATE(_idx, _rate) { \
499 .flags = IEEE80211_RATE_SHORT_PREAMBLE, \
500 .hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
501 .hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
504 #define OFDM_RATE(_idx, _rate) { \
506 .hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
507 .hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
510 static struct ieee80211_rate mt76_rates[] = {
526 mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband,
527 const struct ieee80211_channel *chan, int n_chan,
528 struct ieee80211_rate *rates, int n_rates)
530 struct ieee80211_sta_ht_cap *ht_cap;
534 size = n_chan * sizeof(*chan);
535 chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
539 sband->channels = chanlist;
540 sband->n_channels = n_chan;
541 sband->bitrates = rates;
542 sband->n_bitrates = n_rates;
544 ht_cap = &sband->ht_cap;
545 ht_cap->ht_supported = true;
546 ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
547 IEEE80211_HT_CAP_GRN_FLD |
548 IEEE80211_HT_CAP_SGI_20 |
549 IEEE80211_HT_CAP_SGI_40 |
550 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
552 ht_cap->mcs.rx_mask[0] = 0xff;
553 ht_cap->mcs.rx_mask[4] = 0x1;
554 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
555 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
556 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
558 dev->chandef.chan = &sband->channels[0];
564 mt76_init_sband_2g(struct mt7601u_dev *dev)
566 dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
568 dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
570 WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
571 ARRAY_SIZE(mt76_channels_2ghz));
573 return mt76_init_sband(dev, dev->sband_2g,
574 &mt76_channels_2ghz[dev->ee->reg.start - 1],
576 mt76_rates, ARRAY_SIZE(mt76_rates));
579 int mt7601u_register_device(struct mt7601u_dev *dev)
581 struct ieee80211_hw *hw = dev->hw;
582 struct wiphy *wiphy = hw->wiphy;
585 /* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
586 * entry no. 1 like it does in the vendor driver.
588 dev->wcid_mask[0] |= 1;
590 /* init fake wcid for monitor interfaces */
591 dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid),
595 dev->mon_wcid->idx = 0xff;
596 dev->mon_wcid->hw_key_idx = -1;
598 SET_IEEE80211_DEV(hw, dev->dev);
601 ieee80211_hw_set(hw, SIGNAL_DBM);
602 ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
603 ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
604 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
605 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
607 hw->max_report_rates = 7;
608 hw->max_rate_tries = 1;
610 hw->sta_data_size = sizeof(struct mt76_sta);
611 hw->vif_data_size = sizeof(struct mt76_vif);
613 SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
615 wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
616 wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
618 wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
620 ret = mt76_init_sband_2g(dev);
624 INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work);
625 INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat);
627 ret = ieee80211_register_hw(hw);
631 mt7601u_init_debugfs(dev);