1 // SPDX-License-Identifier: ISC
2 /* Copyright (C) 2022 MediaTek Inc. */
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/platform_device.h>
7 #include <linux/pinctrl/consumer.h>
9 #include <linux/of_device.h>
10 #include <linux/of_reserved_mem.h>
11 #include <linux/of_gpio.h>
12 #include <linux/iopoll.h>
13 #include <linux/reset.h>
14 #include <linux/of_net.h>
15 #include <linux/clk.h>
20 #define MT_INFRACFG_CONN2AP_SLPPROT 0x0d0
21 #define MT_INFRACFG_AP2CONN_SLPPROT 0x0d4
23 #define MT_INFRACFG_RX_EN_MASK BIT(16)
24 #define MT_INFRACFG_TX_RDY_MASK BIT(4)
25 #define MT_INFRACFG_TX_EN_MASK BIT(0)
28 #define MT_TOP_POS_FAST_CTRL 0x114
29 #define MT_TOP_POS_FAST_EN_MASK BIT(3)
31 #define MT_TOP_POS_SKU 0x21c
32 #define MT_TOP_POS_SKU_MASK GENMASK(31, 28)
33 #define MT_TOP_POS_SKU_ADIE_DBDC_MASK BIT(2)
41 mt76_wmac_spi_read(struct mt7915_dev *dev, u8 adie, u32 addr, u32 *val)
46 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
47 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
48 dev, MT_TOP_SPI_BUSY_CR(adie));
52 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
53 MT_TOP_SPI_READ_ADDR_FORMAT | addr);
54 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0);
56 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
57 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
58 dev, MT_TOP_SPI_BUSY_CR(adie));
62 *val = mt76_rr(dev, MT_TOP_SPI_READ_DATA_CR(adie));
68 mt76_wmac_spi_write(struct mt7915_dev *dev, u8 adie, u32 addr, u32 val)
73 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
74 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
75 dev, MT_TOP_SPI_BUSY_CR(adie));
79 mt76_wr(dev, MT_TOP_SPI_ADDR_CR(adie),
80 MT_TOP_SPI_WRITE_ADDR_FORMAT | addr);
81 mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), val);
83 return read_poll_timeout(mt76_rr, cur, !(cur & MT_TOP_SPI_POLLING_BIT),
84 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
85 dev, MT_TOP_SPI_BUSY_CR(adie));
89 mt76_wmac_spi_rmw(struct mt7915_dev *dev, u8 adie,
90 u32 addr, u32 mask, u32 val)
94 ret = mt76_wmac_spi_read(dev, adie, addr, &cur);
101 return mt76_wmac_spi_write(dev, adie, addr, cur);
105 mt7986_wmac_adie_efuse_read(struct mt7915_dev *dev, u8 adie,
111 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_EFUSE_CFG,
112 MT_ADIE_EFUSE_CTRL_MASK);
116 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0);
120 mask = (MT_ADIE_EFUSE_MODE_MASK | MT_ADIE_EFUSE_ADDR_MASK |
121 MT_ADIE_EFUSE_KICK_MASK);
122 val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) |
123 FIELD_PREP(MT_ADIE_EFUSE_ADDR_MASK, addr) |
124 FIELD_PREP(MT_ADIE_EFUSE_KICK_MASK, 1);
125 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, mask, val);
129 ret = read_poll_timeout(mt76_wmac_spi_read, temp,
130 !temp && !FIELD_GET(MT_ADIE_EFUSE_KICK_MASK, val),
131 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
132 dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
136 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE2_CTRL, &val);
140 if (FIELD_GET(MT_ADIE_EFUSE_VALID_MASK, val) == 1)
141 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_EFUSE_RDATA0,
147 static inline void mt76_wmac_spi_lock(struct mt7915_dev *dev)
151 read_poll_timeout(mt76_rr, cur,
152 FIELD_GET(MT_SEMA_RFSPI_STATUS_MASK, cur),
153 1000, 1000 * MSEC_PER_SEC, false, dev,
154 MT_SEMA_RFSPI_STATUS);
157 static inline void mt76_wmac_spi_unlock(struct mt7915_dev *dev)
159 mt76_wr(dev, MT_SEMA_RFSPI_RELEASE, 1);
162 static u32 mt76_wmac_rmw(void __iomem *base, u32 offset, u32 mask, u32 val)
164 val |= readl(base + offset) & ~mask;
165 writel(val, base + offset);
170 static u8 mt7986_wmac_check_adie_type(struct mt7915_dev *dev)
174 val = readl(dev->sku + MT_TOP_POS_SKU);
176 return FIELD_GET(MT_TOP_POS_SKU_ADIE_DBDC_MASK, val);
179 static int mt7986_wmac_consys_reset(struct mt7915_dev *dev, bool enable)
182 return reset_control_assert(dev->rstc);
184 mt76_wmac_rmw(dev->sku, MT_TOP_POS_FAST_CTRL,
185 MT_TOP_POS_FAST_EN_MASK,
186 FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1));
188 return reset_control_deassert(dev->rstc);
191 static int mt7986_wmac_gpio_setup(struct mt7915_dev *dev)
193 struct pinctrl_state *state;
194 struct pinctrl *pinctrl;
198 type = mt7986_wmac_check_adie_type(dev);
199 pinctrl = devm_pinctrl_get(dev->mt76.dev);
201 return PTR_ERR(pinctrl);
205 state = pinctrl_lookup_state(pinctrl, "default");
206 if (IS_ERR_OR_NULL(state))
210 state = pinctrl_lookup_state(pinctrl, "dbdc");
211 if (IS_ERR_OR_NULL(state))
218 ret = pinctrl_select_state(pinctrl, state);
222 usleep_range(500, 1000);
227 static int mt7986_wmac_consys_lockup(struct mt7915_dev *dev, bool enable)
232 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
233 MT_INFRACFG_RX_EN_MASK,
234 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
235 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_RX_EN_MASK),
236 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
237 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
241 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_AP2CONN_SLPPROT,
242 MT_INFRACFG_TX_EN_MASK,
243 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
244 ret = read_poll_timeout(readl, cur, !(cur & MT_INFRACFG_TX_RDY_MASK),
245 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
246 dev->dcm + MT_INFRACFG_AP2CONN_SLPPROT);
250 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
251 MT_INFRACFG_RX_EN_MASK,
252 FIELD_PREP(MT_INFRACFG_RX_EN_MASK, enable));
253 mt76_wmac_rmw(dev->dcm, MT_INFRACFG_CONN2AP_SLPPROT,
254 MT_INFRACFG_TX_EN_MASK,
255 FIELD_PREP(MT_INFRACFG_TX_EN_MASK, enable));
260 static int mt7986_wmac_coninfra_check(struct mt7915_dev *dev)
264 return read_poll_timeout(mt76_rr, cur, (cur == 0x02070000),
265 USEC_PER_MSEC, 50 * USEC_PER_MSEC,
266 false, dev, MT_CONN_INFRA_BASE);
269 static int mt7986_wmac_coninfra_setup(struct mt7915_dev *dev)
271 struct device *pdev = dev->mt76.dev;
272 struct reserved_mem *rmem;
273 struct device_node *np;
276 np = of_parse_phandle(pdev->of_node, "memory-region", 0);
280 rmem = of_reserved_mem_lookup(np);
284 val = (rmem->base >> 16) & MT_TOP_MCU_EMI_BASE_MASK;
286 /* Set conninfra subsys PLL check */
287 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
288 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
289 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
290 MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);
292 mt76_rmw_field(dev, MT_TOP_MCU_EMI_BASE,
293 MT_TOP_MCU_EMI_BASE_MASK, val);
295 mt76_wr(dev, MT_INFRA_BUS_EMI_START, rmem->base);
296 mt76_wr(dev, MT_INFRA_BUS_EMI_END, rmem->size);
298 mt76_rr(dev, MT_CONN_INFRA_EFUSE);
300 /* Set conninfra sysram */
301 mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0);
302 mt76_wr(dev, MT_TOP_RGU_SYSRAM_SLP, 1);
307 static int mt7986_wmac_sku_setup(struct mt7915_dev *dev, u32 *adie_type)
310 u32 adie_main, adie_ext;
312 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
313 MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1);
314 mt76_rmw_field(dev, MT_CONN_INFRA_ADIE_RESET,
315 MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1);
317 mt76_wmac_spi_lock(dev);
319 ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main);
323 ret = mt76_wmac_spi_read(dev, 1, MT_ADIE_CHIP_ID, &adie_ext);
327 *adie_type = FIELD_GET(MT_ADIE_CHIP_ID_MASK, adie_main) |
328 (MT_ADIE_CHIP_ID_MASK & adie_ext);
331 mt76_wmac_spi_unlock(dev);
336 static inline u16 mt7986_adie_idx(u8 adie, u32 adie_type)
339 return u32_get_bits(adie_type, MT_ADIE_IDX0);
341 return u32_get_bits(adie_type, MT_ADIE_IDX1);
344 static inline bool is_7975(struct mt7915_dev *dev, u8 adie, u32 adie_type)
346 return mt7986_adie_idx(adie, adie_type) == 0x7975;
349 static inline bool is_7976(struct mt7915_dev *dev, u8 adie, u32 adie_type)
351 return mt7986_adie_idx(adie, adie_type) == 0x7976;
354 static int mt7986_wmac_adie_thermal_cal(struct mt7915_dev *dev, u8 adie)
359 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_ANALOG,
361 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
362 val = FIELD_GET(MT_ADIE_VRPI_SEL_EFUSE_MASK, data);
363 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC_BG,
364 MT_ADIE_VRPI_SEL_CR_MASK,
365 FIELD_PREP(MT_ADIE_VRPI_SEL_CR_MASK, val));
369 val = FIELD_GET(MT_ADIE_PGA_GAIN_EFUSE_MASK, data);
370 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
371 MT_ADIE_PGA_GAIN_MASK,
372 FIELD_PREP(MT_ADIE_PGA_GAIN_MASK, val));
377 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_THADC_SLOP,
379 if (ret || FIELD_GET(MT_ADIE_ANA_EN_MASK, data)) {
380 val = FIELD_GET(MT_ADIE_LDO_CTRL_EFUSE_MASK, data);
382 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_RG_TOP_THADC,
383 MT_ADIE_LDO_CTRL_MASK,
384 FIELD_PREP(MT_ADIE_LDO_CTRL_MASK, val));
391 mt7986_read_efuse_xo_trim_7976(struct mt7915_dev *dev, u8 adie,
392 bool is_40m, int *result)
397 addr = is_40m ? MT_ADIE_XTAL_AXM_40M_OSC : MT_ADIE_XTAL_AXM_80M_OSC;
398 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
402 if (!FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data)) {
405 *result = FIELD_GET(MT_ADIE_TRIM_MASK, data);
406 addr = is_40m ? MT_ADIE_XTAL_TRIM1_40M_OSC :
407 MT_ADIE_XTAL_TRIM1_80M_OSC;
408 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
412 if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data) &&
413 FIELD_GET(MT_ADIE_XTAL_DECREASE_MASK, data))
414 *result -= FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
415 else if (FIELD_GET(MT_ADIE_XO_TRIM_EN_MASK, data))
416 *result += FIELD_GET(MT_ADIE_EFUSE_TRIM_MASK, data);
418 *result = max(0, min(127, *result));
424 static int mt7986_wmac_adie_xtal_trim_7976(struct mt7915_dev *dev, u8 adie)
426 int ret, trim_80m, trim_40m;
429 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_XO_TRIM_FLOW,
431 if (ret || !FIELD_GET(BIT(1), data))
434 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, false, &trim_80m);
438 ret = mt7986_read_efuse_xo_trim_7976(dev, adie, true, &trim_40m);
442 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_RG_STRAP_PIN_IN, &val);
446 mode = FIELD_PREP(GENMASK(6, 4), val);
447 if (!mode || mode == 0x2) {
448 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
450 FIELD_PREP(GENMASK(31, 24), trim_80m));
454 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
456 FIELD_PREP(GENMASK(31, 24), trim_80m));
457 } else if (mode == 0x3 || mode == 0x4 || mode == 0x6) {
458 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C1,
460 FIELD_PREP(GENMASK(23, 16), trim_40m));
464 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_XTAL_C2,
466 FIELD_PREP(GENMASK(23, 16), trim_40m));
472 static int mt7986_wmac_adie_patch_7976(struct mt7915_dev *dev, u8 adie)
474 u32 id, version, rg_xo_01, rg_xo_03;
477 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_CHIP_ID, &id);
481 version = FIELD_GET(MT_ADIE_VERSION_MASK, id);
483 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00);
487 if (version == 0x8a00 || version == 0x8a10 || version == 0x8b00) {
488 rg_xo_01 = 0x1d59080f;
489 rg_xo_03 = 0x34c00fe0;
491 rg_xo_01 = 0x1959f80f;
492 rg_xo_03 = 0x34d00fe0;
495 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_01, rg_xo_01);
499 return mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_XO_03, rg_xo_03);
503 mt7986_read_efuse_xo_trim_7975(struct mt7915_dev *dev, u8 adie,
504 u32 addr, u32 *result)
509 ret = mt7986_wmac_adie_efuse_read(dev, adie, addr, &data);
513 if ((data & MT_ADIE_XO_TRIM_EN_MASK)) {
514 if ((data & MT_ADIE_XTAL_DECREASE_MASK))
515 *result -= (data & MT_ADIE_EFUSE_TRIM_MASK);
517 *result += (data & MT_ADIE_EFUSE_TRIM_MASK);
519 *result = (*result & MT_ADIE_TRIM_MASK);
525 static int mt7986_wmac_adie_xtal_trim_7975(struct mt7915_dev *dev, u8 adie)
528 u32 data, result = 0, value;
530 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_EN,
532 if (ret || !(data & BIT(1)))
535 ret = mt7986_wmac_adie_efuse_read(dev, adie, MT_ADIE_7975_XTAL_CAL,
540 if (data & MT_ADIE_XO_TRIM_EN_MASK)
541 result = (data & MT_ADIE_TRIM_MASK);
543 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM2,
548 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM3,
553 ret = mt7986_read_efuse_xo_trim_7975(dev, adie, MT_ADIE_7975_XO_TRIM4,
558 /* Update trim value to C1 and C2*/
559 value = FIELD_GET(MT_ADIE_7975_XO_CTRL2_C1_MASK, result) |
560 FIELD_GET(MT_ADIE_7975_XO_CTRL2_C2_MASK, result);
561 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL2,
562 MT_ADIE_7975_XO_CTRL2_MASK, value);
566 ret = mt76_wmac_spi_read(dev, adie, MT_ADIE_7975_XTAL, &value);
570 if (value & MT_ADIE_7975_XTAL_EN_MASK) {
571 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_2,
572 MT_ADIE_7975_XO_2_FIX_EN, 0x0);
577 return mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_XO_CTRL6,
578 MT_ADIE_7975_XO_CTRL6_MASK, 0x1);
581 static int mt7986_wmac_adie_patch_7975(struct mt7915_dev *dev, u8 adie)
585 /* disable CAL LDO and fine tune RFDIG LDO */
586 ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002);
590 ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002);
594 ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002);
598 ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002);
602 /* set CKA driving and filter */
603 ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa);
607 /* set CKB LDO to 1.4V */
608 ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a);
612 /* turn on SX0 LTBUF */
613 ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002);
617 /* CK_BUF_SW_EN = 1 (all buf in manual mode.) */
618 ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0);
622 /* BT mode/WF normal mode 00000005 */
623 ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005);
627 /* BG thermal sensor offset update */
628 ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088);
632 ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088);
636 ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088);
640 ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088);
644 /* set WCON VDD IPTAT to "0000" */
645 ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000);
649 /* change back LTBUF SX3 drving to default value */
650 ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa);
654 /* SM input cap off */
655 ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000);
659 /* set CKB driving and filter */
660 return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072);
663 static int mt7986_wmac_adie_cfg(struct mt7915_dev *dev, u8 adie, u32 adie_type)
667 mt76_wmac_spi_lock(dev);
668 ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0);
672 if (is_7975(dev, adie, adie_type)) {
673 ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_7975_COCLK,
678 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
682 ret = mt7986_wmac_adie_xtal_trim_7975(dev, adie);
686 ret = mt7986_wmac_adie_patch_7975(dev, adie);
687 } else if (is_7976(dev, adie, adie_type)) {
688 if (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC) {
689 ret = mt76_wmac_spi_write(dev, adie,
690 MT_ADIE_WRI_CK_SEL, 0x1c);
695 ret = mt7986_wmac_adie_thermal_cal(dev, adie);
699 ret = mt7986_wmac_adie_xtal_trim_7976(dev, adie);
703 ret = mt7986_wmac_adie_patch_7976(dev, adie);
706 mt76_wmac_spi_unlock(dev);
712 mt7986_wmac_afe_cal(struct mt7915_dev *dev, u8 adie, bool dbdc, u32 adie_type)
717 mt76_wmac_spi_lock(dev);
718 if (is_7975(dev, adie, adie_type))
719 ret = mt76_wmac_spi_write(dev, adie,
720 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
723 ret = mt76_wmac_spi_write(dev, adie,
724 MT_AFE_RG_ENCAL_WBTAC_IF_SW,
729 idx = dbdc ? ADIE_DBDC : adie;
731 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
732 MT_AFE_RG_WBG_EN_RCK_MASK, 0x1);
733 usleep_range(60, 100);
735 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
736 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0);
738 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
739 MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1);
740 usleep_range(30, 100);
742 mt76_rmw_field(dev, MT_AFE_DIG_EN_03(idx),
743 MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1);
744 usleep_range(60, 100);
746 mt76_rmw_field(dev, MT_AFE_DIG_EN_01(idx),
747 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x1f);
748 usleep_range(800, 1000);
750 mt76_rmw(dev, MT_AFE_DIG_EN_01(idx),
751 MT_AFE_RG_WBG_EN_TXCAL_MASK, 0x0);
752 mt76_rmw(dev, MT_AFE_DIG_EN_03(idx),
753 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0);
755 ret = mt76_wmac_spi_write(dev, adie, MT_AFE_RG_ENCAL_WBTAC_IF_SW,
759 mt76_wmac_spi_unlock(dev);
764 static void mt7986_wmac_subsys_pll_initial(struct mt7915_dev *dev, u8 band)
766 mt76_rmw(dev, MT_AFE_PLL_STB_TIME(band),
767 MT_AFE_PLL_STB_TIME_MASK, MT_AFE_PLL_STB_TIME_VAL);
769 mt76_rmw(dev, MT_AFE_DIG_EN_02(band),
770 MT_AFE_PLL_CFG_MASK, MT_AFE_PLL_CFG_VAL);
772 mt76_rmw(dev, MT_AFE_DIG_TOP_01(band),
773 MT_AFE_DIG_TOP_01_MASK, MT_AFE_DIG_TOP_01_VAL);
776 static void mt7986_wmac_subsys_setting(struct mt7915_dev *dev)
778 /* Subsys pll init */
779 mt7986_wmac_subsys_pll_initial(dev, 0);
780 mt7986_wmac_subsys_pll_initial(dev, 1);
782 /* Set legacy OSC control stable time*/
783 mt76_rmw(dev, MT_CONN_INFRA_OSC_RC_EN,
784 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0);
785 mt76_rmw(dev, MT_CONN_INFRA_OSC_CTRL,
786 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706);
788 /* prevent subsys from power on/of in a short time interval */
789 mt76_rmw(dev, MT_TOP_WFSYS_PWR,
790 MT_TOP_PWR_ACK_MASK | MT_TOP_PWR_KEY_MASK,
794 static int mt7986_wmac_bus_timeout(struct mt7915_dev *dev)
796 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
797 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2);
799 mt76_rmw_field(dev, MT_INFRA_BUS_OFF_TIMEOUT,
800 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
802 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
803 MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc);
805 mt76_rmw_field(dev, MT_INFRA_BUS_ON_TIMEOUT,
806 MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);
808 return mt7986_wmac_coninfra_check(dev);
811 static void mt7986_wmac_clock_enable(struct mt7915_dev *dev, u32 adie_type)
815 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
816 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
818 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
819 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);
821 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_1,
822 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
824 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS_WPLL_DIV_2,
825 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
827 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
828 MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8);
830 mt76_rmw_field(dev, MT_INFRA_CKGEN_RFSPI_WPLL_DIV,
831 MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);
833 mt76_rmw_field(dev, MT_INFRA_CKGEN_BUS,
834 MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0);
836 mt76_rmw_field(dev, MT_CONN_INFRA_HW_CTRL,
837 MT_CONN_INFRA_HW_CTRL_MASK, 0x1);
839 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
840 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1);
842 usleep_range(900, 1000);
844 mt76_wmac_spi_lock(dev);
845 if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) {
846 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),
847 MT_SLP_CTRL_EN_MASK, 0x1);
849 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
850 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
851 dev, MT_ADIE_SLP_CTRL_CK0(0));
853 if (is_7975(dev, 1, adie_type) || is_7976(dev, 1, adie_type)) {
854 mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(1),
855 MT_SLP_CTRL_EN_MASK, 0x1);
857 read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_CTRL_BSY_MASK),
858 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
859 dev, MT_ADIE_SLP_CTRL_CK0(0));
861 mt76_wmac_spi_unlock(dev);
863 mt76_rmw(dev, MT_TOP_CONN_INFRA_WAKEUP,
864 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0);
865 usleep_range(900, 1000);
868 static int mt7986_wmac_top_wfsys_wakeup(struct mt7915_dev *dev, bool enable)
870 mt76_rmw_field(dev, MT_TOP_WFSYS_WAKEUP,
871 MT_TOP_WFSYS_WAKEUP_MASK, enable);
873 usleep_range(900, 1000);
878 return mt7986_wmac_coninfra_check(dev);
881 static int mt7986_wmac_wm_enable(struct mt7915_dev *dev, bool enable)
885 mt76_rmw_field(dev, MT7986_TOP_WM_RESET,
886 MT7986_TOP_WM_RESET_MASK, enable);
890 return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e),
891 USEC_PER_MSEC, 5000 * USEC_PER_MSEC, false,
892 dev, MT_TOP_CFG_ON_ROM_IDX);
895 static int mt7986_wmac_wfsys_poweron(struct mt7915_dev *dev, bool enable)
897 u32 mask = MT_TOP_PWR_EN_MASK | MT_TOP_PWR_KEY_MASK;
900 mt76_rmw(dev, MT_TOP_WFSYS_PWR, mask,
901 MT_TOP_PWR_KEY | FIELD_PREP(MT_TOP_PWR_EN_MASK, enable));
903 return read_poll_timeout(mt76_rr, cur,
904 (FIELD_GET(MT_TOP_WFSYS_RESET_STATUS_MASK, cur) == enable),
905 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
906 dev, MT_TOP_WFSYS_RESET_STATUS);
909 static int mt7986_wmac_wfsys_setting(struct mt7915_dev *dev)
914 /* Turn off wfsys2conn bus sleep protect */
915 mt76_rmw(dev, MT_CONN_INFRA_WF_SLP_PROT,
916 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0);
918 ret = mt7986_wmac_wfsys_poweron(dev, true);
922 /* Check bus sleep protect */
924 ret = read_poll_timeout(mt76_rr, cur,
925 !(cur & MT_CONN_INFRA_CONN_WF_MASK),
926 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
927 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
931 ret = read_poll_timeout(mt76_rr, cur, !(cur & MT_SLP_WFDMA2CONN_MASK),
932 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
937 return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000),
938 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
939 dev, MT_TOP_CFG_IP_VERSION_ADDR);
942 static void mt7986_wmac_wfsys_set_timeout(struct mt7915_dev *dev)
944 u32 mask = MT_MCU_BUS_TIMEOUT_SET_MASK |
945 MT_MCU_BUS_TIMEOUT_CG_EN_MASK |
946 MT_MCU_BUS_TIMEOUT_EN_MASK;
947 u32 val = FIELD_PREP(MT_MCU_BUS_TIMEOUT_SET_MASK, 1) |
948 FIELD_PREP(MT_MCU_BUS_TIMEOUT_CG_EN_MASK, 1) |
949 FIELD_PREP(MT_MCU_BUS_TIMEOUT_EN_MASK, 1);
951 mt76_rmw(dev, MT_MCU_BUS_TIMEOUT, mask, val);
953 mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000);
955 mask = MT_MCU_BUS_DBG_TIMEOUT_SET_MASK |
956 MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK |
957 MT_MCU_BUS_DBG_TIMEOUT_EN_MASK;
958 val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) |
959 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK, 1) |
960 FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_EN_MASK, 1);
962 mt76_rmw(dev, MT_MCU_BUS_DBG_TIMEOUT, mask, val);
965 static int mt7986_wmac_sku_update(struct mt7915_dev *dev, u32 adie_type)
969 if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type))
971 else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type))
973 else if (is_7976(dev, 0, adie_type))
975 else if (is_7975(dev, 1, adie_type))
977 else if (is_7976(dev, 1, adie_type))
982 mt76_wmac_rmw(dev->sku, MT_TOP_POS_SKU, MT_TOP_POS_SKU_MASK,
983 FIELD_PREP(MT_TOP_POS_SKU_MASK, val));
985 mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, val);
991 mt7986_wmac_adie_setup(struct mt7915_dev *dev, u8 adie, u32 adie_type)
995 if (!(is_7975(dev, adie, adie_type) || is_7976(dev, adie, adie_type)))
998 ret = mt7986_wmac_adie_cfg(dev, adie, adie_type);
1002 ret = mt7986_wmac_afe_cal(dev, adie, false, adie_type);
1006 if (!adie && (mt7986_wmac_check_adie_type(dev) == ADIE_DBDC))
1007 ret = mt7986_wmac_afe_cal(dev, adie, true, adie_type);
1012 static int mt7986_wmac_subsys_powerup(struct mt7915_dev *dev, u32 adie_type)
1016 mt7986_wmac_subsys_setting(dev);
1018 ret = mt7986_wmac_bus_timeout(dev);
1022 mt7986_wmac_clock_enable(dev, adie_type);
1027 static int mt7986_wmac_wfsys_powerup(struct mt7915_dev *dev)
1031 ret = mt7986_wmac_wm_enable(dev, false);
1035 ret = mt7986_wmac_wfsys_setting(dev);
1039 mt7986_wmac_wfsys_set_timeout(dev);
1041 return mt7986_wmac_wm_enable(dev, true);
1044 int mt7986_wmac_enable(struct mt7915_dev *dev)
1049 ret = mt7986_wmac_consys_reset(dev, true);
1053 ret = mt7986_wmac_gpio_setup(dev);
1057 ret = mt7986_wmac_consys_lockup(dev, false);
1061 ret = mt7986_wmac_coninfra_check(dev);
1065 ret = mt7986_wmac_coninfra_setup(dev);
1069 ret = mt7986_wmac_sku_setup(dev, &adie_type);
1073 ret = mt7986_wmac_adie_setup(dev, 0, adie_type);
1077 ret = mt7986_wmac_adie_setup(dev, 1, adie_type);
1081 ret = mt7986_wmac_subsys_powerup(dev, adie_type);
1085 ret = mt7986_wmac_top_wfsys_wakeup(dev, true);
1089 ret = mt7986_wmac_wfsys_powerup(dev);
1093 return mt7986_wmac_sku_update(dev, adie_type);
1096 void mt7986_wmac_disable(struct mt7915_dev *dev)
1100 mt7986_wmac_top_wfsys_wakeup(dev, true);
1102 /* Turn on wfsys2conn bus sleep protect */
1103 mt76_rmw_field(dev, MT_CONN_INFRA_WF_SLP_PROT,
1104 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1);
1106 /* Check wfsys2conn bus sleep protect */
1107 read_poll_timeout(mt76_rr, cur, !(cur ^ MT_CONN_INFRA_CONN),
1108 USEC_PER_MSEC, 50 * USEC_PER_MSEC, false,
1109 dev, MT_CONN_INFRA_WF_SLP_PROT_RDY);
1111 mt7986_wmac_wfsys_poweron(dev, false);
1113 /* Turn back wpll setting */
1114 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);
1115 mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);
1118 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1119 MT_CONN_INFRA_EMI_REQ_MASK, 0x1);
1120 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1121 MT_CONN_INFRA_EMI_REQ_MASK, 0x0);
1122 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1123 MT_CONN_INFRA_INFRA_REQ_MASK, 0x1);
1124 mt76_rmw_field(dev, MT_CONN_INFRA_EMI_REQ,
1125 MT_CONN_INFRA_INFRA_REQ_MASK, 0x0);
1127 mt7986_wmac_top_wfsys_wakeup(dev, false);
1128 mt7986_wmac_consys_lockup(dev, true);
1129 mt7986_wmac_consys_reset(dev, false);
1132 static int mt7986_wmac_init(struct mt7915_dev *dev)
1134 struct device *pdev = dev->mt76.dev;
1135 struct platform_device *pfdev = to_platform_device(pdev);
1136 struct clk *mcu_clk, *ap_conn_clk;
1138 mcu_clk = devm_clk_get(pdev, "mcu");
1139 if (IS_ERR(mcu_clk))
1140 dev_err(pdev, "mcu clock not found\n");
1141 else if (clk_prepare_enable(mcu_clk))
1142 dev_err(pdev, "mcu clock configuration failed\n");
1144 ap_conn_clk = devm_clk_get(pdev, "ap2conn");
1145 if (IS_ERR(ap_conn_clk))
1146 dev_err(pdev, "ap2conn clock not found\n");
1147 else if (clk_prepare_enable(ap_conn_clk))
1148 dev_err(pdev, "ap2conn clock configuration failed\n");
1150 dev->dcm = devm_platform_ioremap_resource(pfdev, 1);
1151 if (IS_ERR(dev->dcm))
1152 return PTR_ERR(dev->dcm);
1154 dev->sku = devm_platform_ioremap_resource(pfdev, 2);
1155 if (IS_ERR(dev->sku))
1156 return PTR_ERR(dev->sku);
1158 dev->rstc = devm_reset_control_get(pdev, "consys");
1159 if (IS_ERR(dev->rstc))
1160 return PTR_ERR(dev->rstc);
1165 static int mt7986_wmac_probe(struct platform_device *pdev)
1167 void __iomem *mem_base;
1168 struct mt7915_dev *dev;
1169 struct mt76_dev *mdev;
1173 chip_id = (uintptr_t)of_device_get_match_data(&pdev->dev);
1175 irq = platform_get_irq(pdev, 0);
1179 mem_base = devm_platform_ioremap_resource(pdev, 0);
1180 if (IS_ERR(mem_base)) {
1181 dev_err(&pdev->dev, "Failed to get memory resource\n");
1182 return PTR_ERR(mem_base);
1185 dev = mt7915_mmio_probe(&pdev->dev, mem_base, chip_id);
1187 return PTR_ERR(dev);
1190 ret = devm_request_irq(mdev->dev, irq, mt7915_irq_handler,
1191 IRQF_SHARED, KBUILD_MODNAME, dev);
1195 ret = mt7986_wmac_init(dev);
1199 mt7915_wfsys_reset(dev);
1201 ret = mt7915_register_device(dev);
1208 devm_free_irq(mdev->dev, irq, dev);
1211 mt76_free_device(&dev->mt76);
1216 static int mt7986_wmac_remove(struct platform_device *pdev)
1218 struct mt7915_dev *dev = platform_get_drvdata(pdev);
1220 mt7915_unregister_device(dev);
1225 static const struct of_device_id mt7986_wmac_of_match[] = {
1226 { .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 },
1230 struct platform_driver mt7986_wmac_driver = {
1232 .name = "mt7986-wmac",
1233 .of_match_table = mt7986_wmac_of_match,
1235 .probe = mt7986_wmac_probe,
1236 .remove = mt7986_wmac_remove,