drivers/net/wireless/mediatek/mt76/mt7915/mmio.c

   1 // SPDX-License-Identifier: ISC
   2 /* Copyright (C) 2020 MediaTek Inc. */
   3
   4 #include <linux/kernel.h>
   5 #include <linux/module.h>
   6 #include <linux/platform_device.h>
   7 #include <linux/pci.h>
   8
   9 #include "mt7915.h"
  10 #include "mac.h"
  11 #include "../trace.h"
  12
  13 static const u32 mt7915_reg[] = {
  14         [INT_SOURCE_CSR]        = 0xd7010,
  15         [INT_MASK_CSR]          = 0xd7014,
  16         [INT1_SOURCE_CSR]       = 0xd7088,
  17         [INT1_MASK_CSR]         = 0xd708c,
  18         [INT_MCU_CMD_SOURCE]    = 0xd51f0,
  19         [INT_MCU_CMD_EVENT]     = 0x3108,
  20         [WFDMA0_ADDR]           = 0xd4000,
  21         [WFDMA0_PCIE1_ADDR]     = 0xd8000,
  22         [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
  23         [CBTOP1_PHY_END]        = 0x77ffffff,
  24         [INFRA_MCU_ADDR_END]    = 0x7c3fffff,
  25         [FW_EXCEPTION_ADDR]     = 0x219848,
  26         [SWDEF_BASE_ADDR]       = 0x41f200,
  27 };
  28
  29 static const u32 mt7916_reg[] = {
  30         [INT_SOURCE_CSR]        = 0xd4200,
  31         [INT_MASK_CSR]          = 0xd4204,
  32         [INT1_SOURCE_CSR]       = 0xd8200,
  33         [INT1_MASK_CSR]         = 0xd8204,
  34         [INT_MCU_CMD_SOURCE]    = 0xd41f0,
  35         [INT_MCU_CMD_EVENT]     = 0x2108,
  36         [WFDMA0_ADDR]           = 0xd4000,
  37         [WFDMA0_PCIE1_ADDR]     = 0xd8000,
  38         [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
  39         [CBTOP1_PHY_END]        = 0x7fffffff,
  40         [INFRA_MCU_ADDR_END]    = 0x7c085fff,
  41         [FW_EXCEPTION_ADDR]     = 0x022050bc,
  42         [SWDEF_BASE_ADDR]       = 0x411400,
  43 };
  44
  45 static const u32 mt7986_reg[] = {
  46         [INT_SOURCE_CSR]        = 0x24200,
  47         [INT_MASK_CSR]          = 0x24204,
  48         [INT1_SOURCE_CSR]       = 0x28200,
  49         [INT1_MASK_CSR]         = 0x28204,
  50         [INT_MCU_CMD_SOURCE]    = 0x241f0,
  51         [INT_MCU_CMD_EVENT]     = 0x54000108,
  52         [WFDMA0_ADDR]           = 0x24000,
  53         [WFDMA0_PCIE1_ADDR]     = 0x28000,
  54         [WFDMA_EXT_CSR_ADDR]    = 0x27000,
  55         [CBTOP1_PHY_END]        = 0x7fffffff,
  56         [INFRA_MCU_ADDR_END]    = 0x7c085fff,
  57         [FW_EXCEPTION_ADDR]     = 0x02204ffc,
  58         [SWDEF_BASE_ADDR]       = 0x411400,
  59 };
  60
  61 static const u32 mt7915_offs[] = {
  62         [TMAC_CDTR]             = 0x090,
  63         [TMAC_ODTR]             = 0x094,
  64         [TMAC_ATCR]             = 0x098,
  65         [TMAC_TRCR0]            = 0x09c,
  66         [TMAC_ICR0]             = 0x0a4,
  67         [TMAC_ICR1]             = 0x0b4,
  68         [TMAC_CTCR0]            = 0x0f4,
  69         [TMAC_TFCR0]            = 0x1e0,
  70         [MDP_BNRCFR0]           = 0x070,
  71         [MDP_BNRCFR1]           = 0x074,
  72         [ARB_DRNGR0]            = 0x194,
  73         [ARB_SCR]               = 0x080,
  74         [RMAC_MIB_AIRTIME14]    = 0x3b8,
  75         [AGG_AWSCR0]            = 0x05c,
  76         [AGG_PCR0]              = 0x06c,
  77         [AGG_ACR0]              = 0x084,
  78         [AGG_MRCR]              = 0x098,
  79         [AGG_ATCR1]             = 0x0f0,
  80         [AGG_ATCR3]             = 0x0f4,
  81         [LPON_UTTR0]            = 0x080,
  82         [LPON_UTTR1]            = 0x084,
  83         [LPON_FRCR]             = 0x314,
  84         [MIB_SDR3]              = 0x014,
  85         [MIB_SDR4]              = 0x018,
  86         [MIB_SDR5]              = 0x01c,
  87         [MIB_SDR7]              = 0x024,
  88         [MIB_SDR8]              = 0x028,
  89         [MIB_SDR9]              = 0x02c,
  90         [MIB_SDR10]             = 0x030,
  91         [MIB_SDR11]             = 0x034,
  92         [MIB_SDR12]             = 0x038,
  93         [MIB_SDR13]             = 0x03c,
  94         [MIB_SDR14]             = 0x040,
  95         [MIB_SDR15]             = 0x044,
  96         [MIB_SDR16]             = 0x048,
  97         [MIB_SDR17]             = 0x04c,
  98         [MIB_SDR18]             = 0x050,
  99         [MIB_SDR19]             = 0x054,
 100         [MIB_SDR20]             = 0x058,
 101         [MIB_SDR21]             = 0x05c,
 102         [MIB_SDR22]             = 0x060,
 103         [MIB_SDR23]             = 0x064,
 104         [MIB_SDR24]             = 0x068,
 105         [MIB_SDR25]             = 0x06c,
 106         [MIB_SDR27]             = 0x074,
 107         [MIB_SDR28]             = 0x078,
 108         [MIB_SDR29]             = 0x07c,
 109         [MIB_SDRVEC]            = 0x080,
 110         [MIB_SDR31]             = 0x084,
 111         [MIB_SDR32]             = 0x088,
 112         [MIB_SDRMUBF]           = 0x090,
 113         [MIB_DR8]               = 0x0c0,
 114         [MIB_DR9]               = 0x0c4,
 115         [MIB_DR11]              = 0x0cc,
 116         [MIB_MB_SDR0]           = 0x100,
 117         [MIB_MB_SDR1]           = 0x104,
 118         [TX_AGG_CNT]            = 0x0a8,
 119         [TX_AGG_CNT2]           = 0x164,
 120         [MIB_ARNG]              = 0x4b8,
 121         [WTBLON_TOP_WDUCR]      = 0x0,
 122         [WTBL_UPDATE]           = 0x030,
 123         [PLE_FL_Q_EMPTY]        = 0x0b0,
 124         [PLE_FL_Q_CTRL]         = 0x1b0,
 125         [PLE_AC_QEMPTY]         = 0x500,
 126         [PLE_FREEPG_CNT]        = 0x100,
 127         [PLE_FREEPG_HEAD_TAIL]  = 0x104,
 128         [PLE_PG_HIF_GROUP]      = 0x110,
 129         [PLE_HIF_PG_INFO]       = 0x114,
 130         [AC_OFFSET]             = 0x040,
 131         [ETBF_PAR_RPT0]         = 0x068,
 132 };
 133
 134 static const u32 mt7916_offs[] = {
 135         [TMAC_CDTR]             = 0x0c8,
 136         [TMAC_ODTR]             = 0x0cc,
 137         [TMAC_ATCR]             = 0x00c,
 138         [TMAC_TRCR0]            = 0x010,
 139         [TMAC_ICR0]             = 0x014,
 140         [TMAC_ICR1]             = 0x018,
 141         [TMAC_CTCR0]            = 0x114,
 142         [TMAC_TFCR0]            = 0x0e4,
 143         [MDP_BNRCFR0]           = 0x090,
 144         [MDP_BNRCFR1]           = 0x094,
 145         [ARB_DRNGR0]            = 0x1e0,
 146         [ARB_SCR]               = 0x000,
 147         [RMAC_MIB_AIRTIME14]    = 0x0398,
 148         [AGG_AWSCR0]            = 0x030,
 149         [AGG_PCR0]              = 0x040,
 150         [AGG_ACR0]              = 0x054,
 151         [AGG_MRCR]              = 0x068,
 152         [AGG_ATCR1]             = 0x1a8,
 153         [AGG_ATCR3]             = 0x080,
 154         [LPON_UTTR0]            = 0x360,
 155         [LPON_UTTR1]            = 0x364,
 156         [LPON_FRCR]             = 0x37c,
 157         [MIB_SDR3]              = 0x698,
 158         [MIB_SDR4]              = 0x788,
 159         [MIB_SDR5]              = 0x780,
 160         [MIB_SDR7]              = 0x5a8,
 161         [MIB_SDR8]              = 0x78c,
 162         [MIB_SDR9]              = 0x024,
 163         [MIB_SDR10]             = 0x76c,
 164         [MIB_SDR11]             = 0x790,
 165         [MIB_SDR12]             = 0x558,
 166         [MIB_SDR13]             = 0x560,
 167         [MIB_SDR14]             = 0x564,
 168         [MIB_SDR15]             = 0x568,
 169         [MIB_SDR16]             = 0x7fc,
 170         [MIB_SDR17]             = 0x800,
 171         [MIB_SDR18]             = 0x030,
 172         [MIB_SDR19]             = 0x5ac,
 173         [MIB_SDR20]             = 0x5b0,
 174         [MIB_SDR21]             = 0x5b4,
 175         [MIB_SDR22]             = 0x770,
 176         [MIB_SDR23]             = 0x774,
 177         [MIB_SDR24]             = 0x778,
 178         [MIB_SDR25]             = 0x77c,
 179         [MIB_SDR27]             = 0x080,
 180         [MIB_SDR28]             = 0x084,
 181         [MIB_SDR29]             = 0x650,
 182         [MIB_SDRVEC]            = 0x5a8,
 183         [MIB_SDR31]             = 0x55c,
 184         [MIB_SDR32]             = 0x7a8,
 185         [MIB_SDRMUBF]           = 0x7ac,
 186         [MIB_DR8]               = 0x56c,
 187         [MIB_DR9]               = 0x570,
 188         [MIB_DR11]              = 0x574,
 189         [MIB_MB_SDR0]           = 0x688,
 190         [MIB_MB_SDR1]           = 0x690,
 191         [TX_AGG_CNT]            = 0x7dc,
 192         [TX_AGG_CNT2]           = 0x7ec,
 193         [MIB_ARNG]              = 0x0b0,
 194         [WTBLON_TOP_WDUCR]      = 0x200,
 195         [WTBL_UPDATE]           = 0x230,
 196         [PLE_FL_Q_EMPTY]        = 0x360,
 197         [PLE_FL_Q_CTRL]         = 0x3e0,
 198         [PLE_AC_QEMPTY]         = 0x600,
 199         [PLE_FREEPG_CNT]        = 0x380,
 200         [PLE_FREEPG_HEAD_TAIL]  = 0x384,
 201         [PLE_PG_HIF_GROUP]      = 0x00c,
 202         [PLE_HIF_PG_INFO]       = 0x388,
 203         [AC_OFFSET]             = 0x080,
 204         [ETBF_PAR_RPT0]         = 0x100,
 205 };
 206
 207 static const struct __map mt7915_reg_map[] = {
 208         { 0x00400000, 0x80000, 0x10000 }, /* WF_MCU_SYSRAM */
 209         { 0x00410000, 0x90000, 0x10000 }, /* WF_MCU_SYSRAM (configure regs) */
 210         { 0x40000000, 0x70000, 0x10000 }, /* WF_UMAC_SYSRAM */
 211         { 0x54000000, 0x02000, 0x1000 }, /* WFDMA PCIE0 MCU DMA0 */
 212         { 0x55000000, 0x03000, 0x1000 }, /* WFDMA PCIE0 MCU DMA1 */
 213         { 0x58000000, 0x06000, 0x1000 }, /* WFDMA PCIE1 MCU DMA0 (MEM_DMA) */
 214         { 0x59000000, 0x07000, 0x1000 }, /* WFDMA PCIE1 MCU DMA1 */
 215         { 0x7c000000, 0xf0000, 0x10000 }, /* CONN_INFRA */
 216         { 0x7c020000, 0xd0000, 0x10000 }, /* CONN_INFRA, WFDMA */
 217         { 0x80020000, 0xb0000, 0x10000 }, /* WF_TOP_MISC_OFF */
 218         { 0x81020000, 0xc0000, 0x10000 }, /* WF_TOP_MISC_ON */
 219         { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
 220         { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
 221         { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
 222         { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
 223         { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
 224         { 0x820d0000, 0x30000, 0x10000 }, /* WF_LMAC_TOP (WF_WTBLON) */
 225         { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
 226         { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
 227         { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
 228         { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
 229         { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
 230         { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
 231         { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
 232         { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
 233         { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
 234         { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
 235         { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
 236         { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
 237         { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
 238         { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
 239         { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
 240         { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
 241         { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
 242         { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
 243         { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
 244         { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
 245         { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
 246         { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
 247         { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
 248         { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
 249         { 0x0, 0x0, 0x0 }, /* imply end of search */
 250 };
 251
 252 static const struct __map mt7916_reg_map[] = {
 253         { 0x54000000, 0x02000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
 254         { 0x55000000, 0x03000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
 255         { 0x56000000, 0x04000, 0x1000 }, /* WFDMA_2 (Reserved) */
 256         { 0x57000000, 0x05000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
 257         { 0x58000000, 0x06000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
 258         { 0x59000000, 0x07000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
 259         { 0x820c0000, 0x08000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
 260         { 0x820c8000, 0x0c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
 261         { 0x820cc000, 0x0e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
 262         { 0x820e0000, 0x20000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
 263         { 0x820e1000, 0x20400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
 264         { 0x820e2000, 0x20800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
 265         { 0x820e3000, 0x20c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
 266         { 0x820e4000, 0x21000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
 267         { 0x820e5000, 0x21400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
 268         { 0x820ce000, 0x21c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
 269         { 0x820e7000, 0x21e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
 270         { 0x820cf000, 0x22000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
 271         { 0x820e9000, 0x23400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
 272         { 0x820ea000, 0x24000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
 273         { 0x820eb000, 0x24200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
 274         { 0x820ec000, 0x24600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
 275         { 0x820ed000, 0x24800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
 276         { 0x820ca000, 0x26000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
 277         { 0x820d0000, 0x30000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
 278         { 0x00400000, 0x80000, 0x10000}, /* WF_MCU_SYSRAM */
 279         { 0x00410000, 0x90000, 0x10000}, /* WF_MCU_SYSRAM (configure cr) */
 280         { 0x820f0000, 0xa0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
 281         { 0x820f1000, 0xa0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
 282         { 0x820f2000, 0xa0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
 283         { 0x820f3000, 0xa0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
 284         { 0x820f4000, 0xa1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
 285         { 0x820f5000, 0xa1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
 286         { 0x820f7000, 0xa1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
 287         { 0x820f9000, 0xa3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
 288         { 0x820fa000, 0xa4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
 289         { 0x820fb000, 0xa4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
 290         { 0x820fc000, 0xa4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
 291         { 0x820fd000, 0xa4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
 292         { 0x820c4000, 0xa8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
 293         { 0x820b0000, 0xae000, 0x1000 }, /* [APB2] WFSYS_ON */
 294         { 0x80020000, 0xb0000, 0x10000}, /* WF_TOP_MISC_OFF */
 295         { 0x81020000, 0xc0000, 0x10000}, /* WF_TOP_MISC_ON */
 296         { 0x0, 0x0, 0x0 }, /* imply end of search */
 297 };
 298
 299 static const struct __map mt7986_reg_map[] = {
 300         { 0x54000000, 0x402000, 0x1000 }, /* WFDMA_0 (PCIE0 MCU DMA0) */
 301         { 0x55000000, 0x403000, 0x1000 }, /* WFDMA_1 (PCIE0 MCU DMA1) */
 302         { 0x56000000, 0x404000, 0x1000 }, /* WFDMA_2 (Reserved) */
 303         { 0x57000000, 0x405000, 0x1000 }, /* WFDMA_3 (MCU wrap CR) */
 304         { 0x58000000, 0x406000, 0x1000 }, /* WFDMA_4 (PCIE1 MCU DMA0) */
 305         { 0x59000000, 0x407000, 0x1000 }, /* WFDMA_5 (PCIE1 MCU DMA1) */
 306         { 0x820c0000, 0x408000, 0x4000 }, /* WF_UMAC_TOP (PLE) */
 307         { 0x820c8000, 0x40c000, 0x2000 }, /* WF_UMAC_TOP (PSE) */
 308         { 0x820cc000, 0x40e000, 0x2000 }, /* WF_UMAC_TOP (PP) */
 309         { 0x820e0000, 0x420000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_CFG) */
 310         { 0x820e1000, 0x420400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_TRB) */
 311         { 0x820e2000, 0x420800, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_AGG) */
 312         { 0x820e3000, 0x420c00, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_ARB) */
 313         { 0x820e4000, 0x421000, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_TMAC) */
 314         { 0x820e5000, 0x421400, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_RMAC) */
 315         { 0x820ce000, 0x421c00, 0x0200 }, /* WF_LMAC_TOP (WF_SEC) */
 316         { 0x820e7000, 0x421e00, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_DMA) */
 317         { 0x820cf000, 0x422000, 0x1000 }, /* WF_LMAC_TOP (WF_PF) */
 318         { 0x820e9000, 0x423400, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_WTBLOFF) */
 319         { 0x820ea000, 0x424000, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_ETBF) */
 320         { 0x820eb000, 0x424200, 0x0400 }, /* WF_LMAC_TOP BN0 (WF_LPON) */
 321         { 0x820ec000, 0x424600, 0x0200 }, /* WF_LMAC_TOP BN0 (WF_INT) */
 322         { 0x820ed000, 0x424800, 0x0800 }, /* WF_LMAC_TOP BN0 (WF_MIB) */
 323         { 0x820ca000, 0x426000, 0x2000 }, /* WF_LMAC_TOP BN0 (WF_MUCOP) */
 324         { 0x820d0000, 0x430000, 0x10000}, /* WF_LMAC_TOP (WF_WTBLON) */
 325         { 0x00400000, 0x480000, 0x10000}, /* WF_MCU_SYSRAM */
 326         { 0x00410000, 0x490000, 0x10000}, /* WF_MCU_SYSRAM */
 327         { 0x820f0000, 0x4a0000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_CFG) */
 328         { 0x820f1000, 0x4a0600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_TRB) */
 329         { 0x820f2000, 0x4a0800, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_AGG) */
 330         { 0x820f3000, 0x4a0c00, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_ARB) */
 331         { 0x820f4000, 0x4a1000, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_TMAC) */
 332         { 0x820f5000, 0x4a1400, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_RMAC) */
 333         { 0x820f7000, 0x4a1e00, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_DMA) */
 334         { 0x820f9000, 0x4a3400, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_WTBLOFF) */
 335         { 0x820fa000, 0x4a4000, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_ETBF) */
 336         { 0x820fb000, 0x4a4200, 0x0400 }, /* WF_LMAC_TOP BN1 (WF_LPON) */
 337         { 0x820fc000, 0x4a4600, 0x0200 }, /* WF_LMAC_TOP BN1 (WF_INT) */
 338         { 0x820fd000, 0x4a4800, 0x0800 }, /* WF_LMAC_TOP BN1 (WF_MIB) */
 339         { 0x820c4000, 0x4a8000, 0x1000 }, /* WF_LMAC_TOP (WF_UWTBL ) */
 340         { 0x820b0000, 0x4ae000, 0x1000 }, /* [APB2] WFSYS_ON */
 341         { 0x80020000, 0x4b0000, 0x10000}, /* WF_TOP_MISC_OFF */
 342         { 0x81020000, 0x4c0000, 0x10000}, /* WF_TOP_MISC_ON */
 343         { 0x89000000, 0x4d0000, 0x1000 }, /* WF_MCU_CFG_ON */
 344         { 0x89010000, 0x4d1000, 0x1000 }, /* WF_MCU_CIRQ */
 345         { 0x89020000, 0x4d2000, 0x1000 }, /* WF_MCU_GPT */
 346         { 0x89030000, 0x4d3000, 0x1000 }, /* WF_MCU_WDT */
 347         { 0x80010000, 0x4d4000, 0x1000 }, /* WF_AXIDMA */
 348         { 0x0, 0x0, 0x0 }, /* imply end of search */
 349 };
 350
 351 static u32 mt7915_reg_map_l1(struct mt7915_dev *dev, u32 addr)
 352 {
 353         u32 offset = FIELD_GET(MT_HIF_REMAP_L1_OFFSET, addr);
 354         u32 base = FIELD_GET(MT_HIF_REMAP_L1_BASE, addr);
 355         u32 l1_remap;
 356
 357         if (is_mt7986(&dev->mt76))
 358                 return MT_CONN_INFRA_OFFSET(addr);
 359
 360         l1_remap = is_mt7915(&dev->mt76) ?
 361                    MT_HIF_REMAP_L1 : MT_HIF_REMAP_L1_MT7916;
 362
 363         dev->bus_ops->rmw(&dev->mt76, l1_remap,
 364                           MT_HIF_REMAP_L1_MASK,
 365                           FIELD_PREP(MT_HIF_REMAP_L1_MASK, base));
 366         /* use read to push write */
 367         dev->bus_ops->rr(&dev->mt76, l1_remap);
 368
 369         return MT_HIF_REMAP_BASE_L1 + offset;
 370 }
 371
 372 static u32 mt7915_reg_map_l2(struct mt7915_dev *dev, u32 addr)
 373 {
 374         u32 offset, base;
 375
 376         if (is_mt7915(&dev->mt76)) {
 377                 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET, addr);
 378                 base = FIELD_GET(MT_HIF_REMAP_L2_BASE, addr);
 379
 380                 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2,
 381                                   MT_HIF_REMAP_L2_MASK,
 382                                   FIELD_PREP(MT_HIF_REMAP_L2_MASK, base));
 383
 384                 /* use read to push write */
 385                 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2);
 386         } else {
 387                 u32 ofs = is_mt7986(&dev->mt76) ? 0x400000 : 0;
 388
 389                 offset = FIELD_GET(MT_HIF_REMAP_L2_OFFSET_MT7916, addr);
 390                 base = FIELD_GET(MT_HIF_REMAP_L2_BASE_MT7916, addr);
 391
 392                 dev->bus_ops->rmw(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs,
 393                                   MT_HIF_REMAP_L2_MASK_MT7916,
 394                                   FIELD_PREP(MT_HIF_REMAP_L2_MASK_MT7916, base));
 395
 396                 /* use read to push write */
 397                 dev->bus_ops->rr(&dev->mt76, MT_HIF_REMAP_L2_MT7916 + ofs);
 398
 399                 offset += (MT_HIF_REMAP_BASE_L2_MT7916 + ofs);
 400         }
 401
 402         return offset;
 403 }
 404
 405 static u32 __mt7915_reg_addr(struct mt7915_dev *dev, u32 addr)
 406 {
 407         int i;
 408
 409         if (addr < 0x100000)
 410                 return addr;
 411
 412         if (!dev->reg.map) {
 413                 dev_err(dev->mt76.dev, "err: reg_map is null\n");
 414                 return addr;
 415         }
 416
 417         for (i = 0; i < dev->reg.map_size; i++) {
 418                 u32 ofs;
 419
 420                 if (addr < dev->reg.map[i].phys)
 421                         continue;
 422
 423                 ofs = addr - dev->reg.map[i].phys;
 424                 if (ofs > dev->reg.map[i].size)
 425                         continue;
 426
 427                 return dev->reg.map[i].maps + ofs;
 428         }
 429
 430         if ((addr >= MT_INFRA_BASE && addr < MT_WFSYS0_PHY_START) ||
 431             (addr >= MT_WFSYS0_PHY_START && addr < MT_WFSYS1_PHY_START) ||
 432             (addr >= MT_WFSYS1_PHY_START && addr <= MT_WFSYS1_PHY_END))
 433                 return mt7915_reg_map_l1(dev, addr);
 434
 435         if (dev_is_pci(dev->mt76.dev) &&
 436             ((addr >= MT_CBTOP1_PHY_START && addr <= MT_CBTOP1_PHY_END) ||
 437              (addr >= MT_CBTOP2_PHY_START && addr <= MT_CBTOP2_PHY_END)))
 438                 return mt7915_reg_map_l1(dev, addr);
 439
 440         /* CONN_INFRA: covert to phyiscal addr and use layer 1 remap */
 441         if (addr >= MT_INFRA_MCU_START && addr <= MT_INFRA_MCU_END) {
 442                 addr = addr - MT_INFRA_MCU_START + MT_INFRA_BASE;
 443                 return mt7915_reg_map_l1(dev, addr);
 444         }
 445
 446         return mt7915_reg_map_l2(dev, addr);
 447 }
 448
 449 static u32 mt7915_rr(struct mt76_dev *mdev, u32 offset)
 450 {
 451         struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
 452         u32 addr = __mt7915_reg_addr(dev, offset);
 453
 454         return dev->bus_ops->rr(mdev, addr);
 455 }
 456
 457 static void mt7915_wr(struct mt76_dev *mdev, u32 offset, u32 val)
 458 {
 459         struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
 460         u32 addr = __mt7915_reg_addr(dev, offset);
 461
 462         dev->bus_ops->wr(mdev, addr, val);
 463 }
 464
 465 static u32 mt7915_rmw(struct mt76_dev *mdev, u32 offset, u32 mask, u32 val)
 466 {
 467         struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
 468         u32 addr = __mt7915_reg_addr(dev, offset);
 469
 470         return dev->bus_ops->rmw(mdev, addr, mask, val);
 471 }
 472
 473 static int mt7915_mmio_init(struct mt76_dev *mdev,
 474                             void __iomem *mem_base,
 475                             u32 device_id)
 476 {
 477         struct mt76_bus_ops *bus_ops;
 478         struct mt7915_dev *dev;
 479
 480         dev = container_of(mdev, struct mt7915_dev, mt76);
 481         mt76_mmio_init(&dev->mt76, mem_base);
 482
 483         switch (device_id) {
 484         case 0x7915:
 485                 dev->reg.reg_rev = mt7915_reg;
 486                 dev->reg.offs_rev = mt7915_offs;
 487                 dev->reg.map = mt7915_reg_map;
 488                 dev->reg.map_size = ARRAY_SIZE(mt7915_reg_map);
 489                 break;
 490         case 0x7906:
 491                 dev->reg.reg_rev = mt7916_reg;
 492                 dev->reg.offs_rev = mt7916_offs;
 493                 dev->reg.map = mt7916_reg_map;
 494                 dev->reg.map_size = ARRAY_SIZE(mt7916_reg_map);
 495                 break;
 496         case 0x7986:
 497                 dev->reg.reg_rev = mt7986_reg;
 498                 dev->reg.offs_rev = mt7916_offs;
 499                 dev->reg.map = mt7986_reg_map;
 500                 dev->reg.map_size = ARRAY_SIZE(mt7986_reg_map);
 501                 break;
 502         default:
 503                 return -EINVAL;
 504         }
 505
 506         dev->bus_ops = dev->mt76.bus;
 507         bus_ops = devm_kmemdup(dev->mt76.dev, dev->bus_ops, sizeof(*bus_ops),
 508                                GFP_KERNEL);
 509         if (!bus_ops)
 510                 return -ENOMEM;
 511
 512         bus_ops->rr = mt7915_rr;
 513         bus_ops->wr = mt7915_wr;
 514         bus_ops->rmw = mt7915_rmw;
 515         dev->mt76.bus = bus_ops;
 516
 517         mdev->rev = (device_id << 16) |
 518                     (mt76_rr(dev, MT_HW_REV) & 0xff);
 519         dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
 520
 521         return 0;
 522 }
 523
 524 void mt7915_dual_hif_set_irq_mask(struct mt7915_dev *dev,
 525                                   bool write_reg,
 526                                   u32 clear, u32 set)
 527 {
 528         struct mt76_dev *mdev = &dev->mt76;
 529         unsigned long flags;
 530
 531         spin_lock_irqsave(&mdev->mmio.irq_lock, flags);
 532
 533         mdev->mmio.irqmask &= ~clear;
 534         mdev->mmio.irqmask |= set;
 535
 536         if (write_reg) {
 537                 mt76_wr(dev, MT_INT_MASK_CSR, mdev->mmio.irqmask);
 538                 mt76_wr(dev, MT_INT1_MASK_CSR, mdev->mmio.irqmask);
 539         }
 540
 541         spin_unlock_irqrestore(&mdev->mmio.irq_lock, flags);
 542 }
 543
 544 static void mt7915_rx_poll_complete(struct mt76_dev *mdev,
 545                                     enum mt76_rxq_id q)
 546 {
 547         struct mt7915_dev *dev = container_of(mdev, struct mt7915_dev, mt76);
 548
 549         mt7915_irq_enable(dev, MT_INT_RX(q));
 550 }
 551
 552 /* TODO: support 2/4/6/8 MSI-X vectors */
 553 static void mt7915_irq_tasklet(struct tasklet_struct *t)
 554 {
 555         struct mt7915_dev *dev = from_tasklet(dev, t, irq_tasklet);
 556         struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
 557         u32 intr, intr1, mask;
 558
 559         if (mtk_wed_device_active(wed)) {
 560                 mtk_wed_device_irq_set_mask(wed, 0);
 561                 intr = mtk_wed_device_irq_get(wed, dev->mt76.mmio.irqmask);
 562         } else {
 563                 mt76_wr(dev, MT_INT_MASK_CSR, 0);
 564                 if (dev->hif2)
 565                         mt76_wr(dev, MT_INT1_MASK_CSR, 0);
 566
 567                 intr = mt76_rr(dev, MT_INT_SOURCE_CSR);
 568                 intr &= dev->mt76.mmio.irqmask;
 569                 mt76_wr(dev, MT_INT_SOURCE_CSR, intr);
 570         }
 571
 572         if (dev->hif2) {
 573                 intr1 = mt76_rr(dev, MT_INT1_SOURCE_CSR);
 574                 intr1 &= dev->mt76.mmio.irqmask;
 575                 mt76_wr(dev, MT_INT1_SOURCE_CSR, intr1);
 576
 577                 intr |= intr1;
 578         }
 579
 580         trace_dev_irq(&dev->mt76, intr, dev->mt76.mmio.irqmask);
 581
 582         mask = intr & MT_INT_RX_DONE_ALL;
 583         if (intr & MT_INT_TX_DONE_MCU)
 584                 mask |= MT_INT_TX_DONE_MCU;
 585
 586         mt7915_irq_disable(dev, mask);
 587
 588         if (intr & MT_INT_TX_DONE_MCU)
 589                 napi_schedule(&dev->mt76.tx_napi);
 590
 591         if (intr & MT_INT_RX(MT_RXQ_MAIN))
 592                 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN]);
 593
 594         if (intr & MT_INT_RX(MT_RXQ_EXT))
 595                 napi_schedule(&dev->mt76.napi[MT_RXQ_EXT]);
 596
 597         if (intr & MT_INT_RX(MT_RXQ_MCU))
 598                 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU]);
 599
 600         if (intr & MT_INT_RX(MT_RXQ_MCU_WA))
 601                 napi_schedule(&dev->mt76.napi[MT_RXQ_MCU_WA]);
 602
 603         if (!is_mt7915(&dev->mt76) &&
 604             (intr & MT_INT_RX(MT_RXQ_MAIN_WA)))
 605                 napi_schedule(&dev->mt76.napi[MT_RXQ_MAIN_WA]);
 606
 607         if (intr & MT_INT_RX(MT_RXQ_EXT_WA))
 608                 napi_schedule(&dev->mt76.napi[MT_RXQ_EXT_WA]);
 609
 610         if (intr & MT_INT_MCU_CMD) {
 611                 u32 val = mt76_rr(dev, MT_MCU_CMD);
 612
 613                 mt76_wr(dev, MT_MCU_CMD, val);
 614                 if (val & MT_MCU_CMD_ERROR_MASK) {
 615                         dev->reset_state = val;
 616                         queue_work(dev->mt76.wq, &dev->reset_work);
 617                         wake_up(&dev->reset_wait);
 618                 }
 619         }
 620 }
 621
 622 irqreturn_t mt7915_irq_handler(int irq, void *dev_instance)
 623 {
 624         struct mt7915_dev *dev = dev_instance;
 625         struct mtk_wed_device *wed = &dev->mt76.mmio.wed;
 626
 627         if (mtk_wed_device_active(wed)) {
 628                 mtk_wed_device_irq_set_mask(wed, 0);
 629         } else {
 630                 mt76_wr(dev, MT_INT_MASK_CSR, 0);
 631                 if (dev->hif2)
 632                         mt76_wr(dev, MT_INT1_MASK_CSR, 0);
 633         }
 634
 635         if (!test_bit(MT76_STATE_INITIALIZED, &dev->mphy.state))
 636                 return IRQ_NONE;
 637
 638         tasklet_schedule(&dev->irq_tasklet);
 639
 640         return IRQ_HANDLED;
 641 }
 642
 643 struct mt7915_dev *mt7915_mmio_probe(struct device *pdev,
 644                                      void __iomem *mem_base, u32 device_id)
 645 {
 646         static const struct mt76_driver_ops drv_ops = {
 647                 /* txwi_size = txd size + txp size */
 648                 .txwi_size = MT_TXD_SIZE + sizeof(struct mt7915_txp),
 649                 .drv_flags = MT_DRV_TXWI_NO_FREE | MT_DRV_HW_MGMT_TXQ,
 650                 .survey_flags = SURVEY_INFO_TIME_TX |
 651                                 SURVEY_INFO_TIME_RX |
 652                                 SURVEY_INFO_TIME_BSS_RX,
 653                 .token_size = MT7915_TOKEN_SIZE,
 654                 .tx_prepare_skb = mt7915_tx_prepare_skb,
 655                 .tx_complete_skb = mt7915_tx_complete_skb,
 656                 .rx_skb = mt7915_queue_rx_skb,
 657                 .rx_check = mt7915_rx_check,
 658                 .rx_poll_complete = mt7915_rx_poll_complete,
 659                 .sta_ps = mt7915_sta_ps,
 660                 .sta_add = mt7915_mac_sta_add,
 661                 .sta_remove = mt7915_mac_sta_remove,
 662                 .update_survey = mt7915_update_channel,
 663         };
 664         struct ieee80211_ops *ops;
 665         struct mt7915_dev *dev;
 666         struct mt76_dev *mdev;
 667         int ret;
 668
 669         ops = devm_kmemdup(pdev, &mt7915_ops, sizeof(mt7915_ops), GFP_KERNEL);
 670         if (!ops)
 671                 return ERR_PTR(-ENOMEM);
 672
 673         mdev = mt76_alloc_device(pdev, sizeof(*dev), ops, &drv_ops);
 674         if (!mdev)
 675                 return ERR_PTR(-ENOMEM);
 676
 677         dev = container_of(mdev, struct mt7915_dev, mt76);
 678
 679         ret = mt7915_mmio_init(mdev, mem_base, device_id);
 680         if (ret)
 681                 goto error;
 682
 683         tasklet_setup(&dev->irq_tasklet, mt7915_irq_tasklet);
 684
 685         return dev;
 686
 687 error:
 688         mt76_free_device(&dev->mt76);
 689
 690         return ERR_PTR(ret);
 691 }
 692
 693 static int __init mt7915_init(void)
 694 {
 695         int ret;
 696
 697         ret = pci_register_driver(&mt7915_hif_driver);
 698         if (ret)
 699                 return ret;
 700
 701         ret = pci_register_driver(&mt7915_pci_driver);
 702         if (ret)
 703                 goto error_pci;
 704
 705         if (IS_ENABLED(CONFIG_MT7986_WMAC)) {
 706                 ret = platform_driver_register(&mt7986_wmac_driver);
 707                 if (ret)
 708                         goto error_wmac;
 709         }
 710
 711         return 0;
 712
 713 error_wmac:
 714         pci_unregister_driver(&mt7915_pci_driver);
 715 error_pci:
 716         pci_unregister_driver(&mt7915_hif_driver);
 717
 718         return ret;
 719 }
 720
 721 static void __exit mt7915_exit(void)
 722 {
 723         if (IS_ENABLED(CONFIG_MT7986_WMAC))
 724                 platform_driver_unregister(&mt7986_wmac_driver);
 725
 726         pci_unregister_driver(&mt7915_pci_driver);
 727         pci_unregister_driver(&mt7915_hif_driver);
 728 }
 729
 730 module_init(mt7915_init);
 731 module_exit(mt7915_exit);
 732 MODULE_LICENSE("Dual BSD/GPL");