2 * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/firmware.h>
20 #include "mt76x2_eeprom.h"
22 #define MT_CMD_HDR_LEN 4
23 #define MT_INBAND_PACKET_MAX_LEN 192
24 #define MT_MCU_MEMMAP_WLAN 0x410000
26 #define MCU_FW_URB_MAX_PAYLOAD 0x3900
27 #define MCU_ROM_PATCH_MAX_PAYLOAD 2048
29 #define MT76U_MCU_ILM_OFFSET 0x80000
30 #define MT76U_MCU_DLM_OFFSET 0x110000
31 #define MT76U_MCU_ROM_PATCH_OFFSET 0x90000
34 mt76x2u_mcu_function_select(struct mt76x2_dev *dev, enum mcu_function func,
40 } __packed __aligned(4) msg = {
41 .id = cpu_to_le32(func),
42 .value = cpu_to_le32(val),
46 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
49 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_FUN_SET_OP,
53 int mt76x2u_mcu_set_radio_state(struct mt76x2_dev *dev, bool val)
58 } __packed __aligned(4) msg = {
59 .mode = cpu_to_le32(val ? RADIO_ON : RADIO_OFF),
60 .level = cpu_to_le32(0),
64 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
67 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_POWER_SAVING_OP,
71 int mt76x2u_mcu_load_cr(struct mt76x2_dev *dev, u8 type, u8 temp_level,
80 } __packed __aligned(4) msg = {
89 val |= (mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0) >> 8) & 0x00ff;
90 val |= (mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1) << 8) & 0xff00;
91 msg.cfg = cpu_to_le32(val);
93 /* first set the channel without the extension channel info */
94 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
97 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_LOAD_CR, true);
100 int mt76x2u_mcu_set_channel(struct mt76x2_dev *dev, u8 channel, u8 bw,
101 u8 bw_index, bool scan)
113 } __packed __aligned(4) msg = {
117 .chainmask = cpu_to_le16(dev->chainmask),
121 /* first set the channel without the extension channel info */
122 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
126 mt76u_mcu_send_msg(&dev->mt76, skb, CMD_SWITCH_CHANNEL_OP, true);
128 usleep_range(5000, 10000);
130 msg.ext_chan = 0xe0 + bw_index;
131 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
135 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_SWITCH_CHANNEL_OP, true);
138 int mt76x2u_mcu_calibrate(struct mt76x2_dev *dev, enum mcu_calibration type,
144 } __packed __aligned(4) msg = {
145 .id = cpu_to_le32(type),
146 .value = cpu_to_le32(val),
150 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
153 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_CALIBRATION_OP, true);
156 int mt76x2u_mcu_init_gain(struct mt76x2_dev *dev, u8 channel, u32 gain,
162 } __packed __aligned(4) msg = {
163 .channel = cpu_to_le32(channel),
164 .gain_val = cpu_to_le32(gain),
169 msg.channel |= cpu_to_le32(BIT(31));
171 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
174 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_INIT_GAIN_OP, true);
177 int mt76x2u_mcu_set_dynamic_vga(struct mt76x2_dev *dev, u8 channel, bool ap,
178 bool ext, int rssi, u32 false_cca)
183 __le32 false_cca_val;
184 } __packed __aligned(4) msg = {
185 .rssi_val = cpu_to_le32(rssi),
186 .false_cca_val = cpu_to_le32(false_cca),
195 msg.channel = cpu_to_le32(val);
197 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
200 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_DYNC_VGA_OP, true);
203 int mt76x2u_mcu_tssi_comp(struct mt76x2_dev *dev,
204 struct mt76x2_tssi_comp *tssi_data)
208 struct mt76x2_tssi_comp data;
209 } __packed __aligned(4) msg = {
210 .id = cpu_to_le32(MCU_CAL_TSSI_COMP),
215 skb = mt76u_mcu_msg_alloc(&msg, sizeof(msg));
218 return mt76u_mcu_send_msg(&dev->mt76, skb, CMD_CALIBRATION_OP, true);
221 static void mt76x2u_mcu_load_ivb(struct mt76x2_dev *dev)
223 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE,
224 USB_DIR_OUT | USB_TYPE_VENDOR,
228 static void mt76x2u_mcu_enable_patch(struct mt76x2_dev *dev)
230 struct mt76_usb *usb = &dev->mt76.usb;
232 0x6f, 0xfc, 0x08, 0x01,
233 0x20, 0x04, 0x00, 0x00,
237 memcpy(usb->data, data, sizeof(data));
238 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE,
239 USB_DIR_OUT | USB_TYPE_CLASS,
240 0x12, 0, usb->data, sizeof(data));
243 static void mt76x2u_mcu_reset_wmt(struct mt76x2_dev *dev)
245 struct mt76_usb *usb = &dev->mt76.usb;
247 0x6f, 0xfc, 0x05, 0x01,
248 0x07, 0x01, 0x00, 0x04
251 memcpy(usb->data, data, sizeof(data));
252 mt76u_vendor_request(&dev->mt76, MT_VEND_DEV_MODE,
253 USB_DIR_OUT | USB_TYPE_CLASS,
254 0x12, 0, usb->data, sizeof(data));
257 static int mt76x2u_mcu_load_rom_patch(struct mt76x2_dev *dev)
259 bool rom_protect = !is_mt7612(dev);
260 struct mt76x2_patch_header *hdr;
261 u32 val, patch_mask, patch_reg;
262 const struct firmware *fw;
266 !mt76_poll_msec(dev, MT_MCU_SEMAPHORE_03, 1, 1, 600)) {
267 dev_err(dev->mt76.dev,
268 "could not get hardware semaphore for ROM PATCH\n");
272 if (mt76xx_rev(dev) >= MT76XX_REV_E3) {
274 patch_reg = MT_MCU_CLOCK_CTL;
277 patch_reg = MT_MCU_COM_REG0;
280 if (rom_protect && (mt76_rr(dev, patch_reg) & patch_mask)) {
281 dev_info(dev->mt76.dev, "ROM patch already applied\n");
285 err = reject_firmware(&fw, MT7662U_ROM_PATCH, dev->mt76.dev);
289 if (!fw || !fw->data || fw->size <= sizeof(*hdr)) {
290 dev_err(dev->mt76.dev, "failed to load firmware\n");
295 hdr = (struct mt76x2_patch_header *)fw->data;
296 dev_info(dev->mt76.dev, "ROM patch build: %.15s\n", hdr->build_time);
298 /* enable USB_DMA_CFG */
299 val = MT_USB_DMA_CFG_RX_BULK_EN |
300 MT_USB_DMA_CFG_TX_BULK_EN |
301 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, 0x20);
302 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
305 mt76u_mcu_fw_reset(&dev->mt76);
306 usleep_range(5000, 10000);
308 /* enable FCE to send in-band cmd */
309 mt76_wr(dev, MT_FCE_PSE_CTRL, 0x1);
310 /* FCE tx_fs_base_ptr */
311 mt76_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230);
312 /* FCE tx_fs_max_cnt */
313 mt76_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 0x1);
314 /* FCE pdma enable */
315 mt76_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44);
317 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3);
319 err = mt76u_mcu_fw_send_data(&dev->mt76, fw->data + sizeof(*hdr),
320 fw->size - sizeof(*hdr),
321 MCU_ROM_PATCH_MAX_PAYLOAD,
322 MT76U_MCU_ROM_PATCH_OFFSET);
328 mt76x2u_mcu_enable_patch(dev);
329 mt76x2u_mcu_reset_wmt(dev);
332 if (!mt76_poll_msec(dev, patch_reg, patch_mask, patch_mask, 100)) {
333 dev_err(dev->mt76.dev, "failed to load ROM patch\n");
339 mt76_wr(dev, MT_MCU_SEMAPHORE_03, 1);
340 release_firmware(fw);
344 static int mt76x2u_mcu_load_firmware(struct mt76x2_dev *dev)
346 u32 val, dlm_offset = MT76U_MCU_DLM_OFFSET;
347 const struct mt76x2_fw_header *hdr;
348 int err, len, ilm_len, dlm_len;
349 const struct firmware *fw;
351 err = reject_firmware(&fw, MT7662U_FIRMWARE, dev->mt76.dev);
355 if (!fw || !fw->data || fw->size < sizeof(*hdr)) {
360 hdr = (const struct mt76x2_fw_header *)fw->data;
361 ilm_len = le32_to_cpu(hdr->ilm_len);
362 dlm_len = le32_to_cpu(hdr->dlm_len);
363 len = sizeof(*hdr) + ilm_len + dlm_len;
364 if (fw->size != len) {
369 val = le16_to_cpu(hdr->fw_ver);
370 dev_info(dev->mt76.dev, "Firmware Version: %d.%d.%02d\n",
371 (val >> 12) & 0xf, (val >> 8) & 0xf, val & 0xf);
373 val = le16_to_cpu(hdr->build_ver);
374 dev_info(dev->mt76.dev, "Build: %x\n", val);
375 dev_info(dev->mt76.dev, "Build Time: %.16s\n", hdr->build_time);
378 mt76u_mcu_fw_reset(&dev->mt76);
379 usleep_range(5000, 10000);
381 /* enable USB_DMA_CFG */
382 val = MT_USB_DMA_CFG_RX_BULK_EN |
383 MT_USB_DMA_CFG_TX_BULK_EN |
384 FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, 0x20);
385 mt76_wr(dev, MT_VEND_ADDR(CFG, MT_USB_U3DMA_CFG), val);
386 /* enable FCE to send in-band cmd */
387 mt76_wr(dev, MT_FCE_PSE_CTRL, 0x1);
388 /* FCE tx_fs_base_ptr */
389 mt76_wr(dev, MT_TX_CPU_FROM_FCE_BASE_PTR, 0x400230);
390 /* FCE tx_fs_max_cnt */
391 mt76_wr(dev, MT_TX_CPU_FROM_FCE_MAX_COUNT, 0x1);
392 /* FCE pdma enable */
393 mt76_wr(dev, MT_FCE_PDMA_GLOBAL_CONF, 0x44);
395 mt76_wr(dev, MT_FCE_SKIP_FS, 0x3);
398 err = mt76u_mcu_fw_send_data(&dev->mt76, fw->data + sizeof(*hdr),
399 ilm_len, MCU_FW_URB_MAX_PAYLOAD,
400 MT76U_MCU_ILM_OFFSET);
407 if (mt76xx_rev(dev) >= MT76XX_REV_E3)
409 err = mt76u_mcu_fw_send_data(&dev->mt76,
410 fw->data + sizeof(*hdr) + ilm_len,
411 dlm_len, MCU_FW_URB_MAX_PAYLOAD,
418 mt76x2u_mcu_load_ivb(dev);
419 if (!mt76_poll_msec(dev, MT_MCU_COM_REG0, 1, 1, 100)) {
420 dev_err(dev->mt76.dev, "firmware failed to start\n");
425 mt76_set(dev, MT_MCU_COM_REG0, BIT(1));
426 /* enable FCE to send in-band cmd */
427 mt76_wr(dev, MT_FCE_PSE_CTRL, 0x1);
428 dev_dbg(dev->mt76.dev, "firmware running\n");
431 release_firmware(fw);
435 int mt76x2u_mcu_fw_init(struct mt76x2_dev *dev)
439 err = mt76x2u_mcu_load_rom_patch(dev);
443 return mt76x2u_mcu_load_firmware(dev);
446 int mt76x2u_mcu_init(struct mt76x2_dev *dev)
450 err = mt76x2u_mcu_function_select(dev, Q_SELECT, 1);
454 return mt76x2u_mcu_set_radio_state(dev, true);
457 void mt76x2u_mcu_deinit(struct mt76x2_dev *dev)
459 struct mt76_usb *usb = &dev->mt76.usb;
461 usb_kill_urb(usb->mcu.res.urb);
462 mt76u_buf_free(&usb->mcu.res);