2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #ifndef __MT76x2_REGS_H
18 #define __MT76x2_REGS_H
20 #define MT_ASIC_VERSION 0x0000
22 #define MT76XX_REV_E3 0x22
23 #define MT76XX_REV_E4 0x33
25 #define MT_CMB_CTRL 0x0020
26 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
27 #define MT_CMB_CTRL_PLL_LD BIT(23)
29 #define MT_EFUSE_CTRL 0x0024
30 #define MT_EFUSE_CTRL_AOUT GENMASK(5, 0)
31 #define MT_EFUSE_CTRL_MODE GENMASK(7, 6)
32 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
33 #define MT_EFUSE_CTRL_LDO_ON_TIME GENMASK(15, 14)
34 #define MT_EFUSE_CTRL_AIN GENMASK(25, 16)
35 #define MT_EFUSE_CTRL_KICK BIT(30)
36 #define MT_EFUSE_CTRL_SEL BIT(31)
38 #define MT_EFUSE_DATA_BASE 0x0028
39 #define MT_EFUSE_DATA(_n) (MT_EFUSE_DATA_BASE + ((_n) << 2))
41 #define MT_COEXCFG0 0x0040
42 #define MT_COEXCFG0_COEX_EN BIT(0)
44 #define MT_WLAN_FUN_CTRL 0x0080
45 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
46 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
47 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
49 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
50 #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */
52 #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)
53 #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)
54 #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)
55 #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)
57 #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */
58 #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */
60 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
61 #define MT_WLAN_FUN_CTRL_GPIO_OUT GENMASK(23, 16) /* MT76x0 */
62 #define MT_WLAN_FUN_CTRL_GPIO_OUT_EN GENMASK(31, 24) /* MT76x0 */
64 #define MT_XO_CTRL0 0x0100
65 #define MT_XO_CTRL1 0x0104
66 #define MT_XO_CTRL2 0x0108
67 #define MT_XO_CTRL3 0x010c
68 #define MT_XO_CTRL4 0x0110
70 #define MT_XO_CTRL5 0x0114
71 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
73 #define MT_XO_CTRL6 0x0118
74 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
76 #define MT_XO_CTRL7 0x011c
78 #define MT_USB_U3DMA_CFG 0x9018
79 #define MT_USB_DMA_CFG_RX_BULK_AGG_TOUT GENMASK(7, 0)
80 #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
81 #define MT_USB_DMA_CFG_UDMA_TX_WL_DROP BIT(16)
82 #define MT_USB_DMA_CFG_WAKE_UP_EN BIT(17)
83 #define MT_USB_DMA_CFG_RX_DROP_OR_PAD BIT(18)
84 #define MT_USB_DMA_CFG_TX_CLR BIT(19)
85 #define MT_USB_DMA_CFG_TXOP_HALT BIT(20)
86 #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)
87 #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)
88 #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)
89 #define MT_USB_DMA_CFG_EP_OUT_VALID GENMASK(29, 24)
90 #define MT_USB_DMA_CFG_RX_BUSY BIT(30)
91 #define MT_USB_DMA_CFG_TX_BUSY BIT(31)
93 #define MT_WLAN_MTC_CTRL 0x10148
94 #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
95 #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)
96 #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)
97 #define MT_WLAN_MTC_CTRL_BBP_MEM_PD GENMASK(19, 16)
98 #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)
99 #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)
100 #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)
101 #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)
102 #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)
103 #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)
104 #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)
105 #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)
107 #define MT_INT_SOURCE_CSR 0x0200
108 #define MT_INT_MASK_CSR 0x0204
110 #define MT_INT_RX_DONE(_n) BIT(_n)
111 #define MT_INT_RX_DONE_ALL GENMASK(1, 0)
112 #define MT_INT_TX_DONE_ALL GENMASK(13, 4)
113 #define MT_INT_TX_DONE(_n) BIT(_n + 4)
114 #define MT_INT_RX_COHERENT BIT(16)
115 #define MT_INT_TX_COHERENT BIT(17)
116 #define MT_INT_ANY_COHERENT BIT(18)
117 #define MT_INT_MCU_CMD BIT(19)
118 #define MT_INT_TBTT BIT(20)
119 #define MT_INT_PRE_TBTT BIT(21)
120 #define MT_INT_TX_STAT BIT(22)
121 #define MT_INT_AUTO_WAKEUP BIT(23)
122 #define MT_INT_GPTIMER BIT(24)
123 #define MT_INT_RXDELAYINT BIT(26)
124 #define MT_INT_TXDELAYINT BIT(27)
126 #define MT_WPDMA_GLO_CFG 0x0208
127 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
128 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
129 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
130 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
131 #define MT_WPDMA_GLO_CFG_DMA_BURST_SIZE GENMASK(5, 4)
132 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
133 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
134 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
135 #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
136 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
138 #define MT_WPDMA_RST_IDX 0x020c
140 #define MT_WPDMA_DELAY_INT_CFG 0x0210
142 #define MT_WMM_AIFSN 0x0214
143 #define MT_WMM_AIFSN_MASK GENMASK(3, 0)
144 #define MT_WMM_AIFSN_SHIFT(_n) ((_n) * 4)
146 #define MT_WMM_CWMIN 0x0218
147 #define MT_WMM_CWMIN_MASK GENMASK(3, 0)
148 #define MT_WMM_CWMIN_SHIFT(_n) ((_n) * 4)
150 #define MT_WMM_CWMAX 0x021c
151 #define MT_WMM_CWMAX_MASK GENMASK(3, 0)
152 #define MT_WMM_CWMAX_SHIFT(_n) ((_n) * 4)
154 #define MT_WMM_TXOP_BASE 0x0220
155 #define MT_WMM_TXOP(_n) (MT_WMM_TXOP_BASE + (((_n) / 2) << 2))
156 #define MT_WMM_TXOP_SHIFT(_n) ((_n & 1) * 16)
157 #define MT_WMM_TXOP_MASK GENMASK(15, 0)
159 #define MT_TSO_CTRL 0x0250
160 #define MT_HEADER_TRANS_CTRL_REG 0x0260
162 #define MT_TX_RING_BASE 0x0300
163 #define MT_RX_RING_BASE 0x03c0
165 #define MT_TX_HW_QUEUE_MCU 8
166 #define MT_TX_HW_QUEUE_MGMT 9
168 #define MT_US_CYC_CFG 0x02a4
169 #define MT_US_CYC_CNT GENMASK(7, 0)
171 #define MT_PBF_SYS_CTRL 0x0400
172 #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
173 #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
174 #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)
175 #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)
176 #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)
178 #define MT_PBF_CFG 0x0404
179 #define MT_PBF_CFG_TX0Q_EN BIT(0)
180 #define MT_PBF_CFG_TX1Q_EN BIT(1)
181 #define MT_PBF_CFG_TX2Q_EN BIT(2)
182 #define MT_PBF_CFG_TX3Q_EN BIT(3)
183 #define MT_PBF_CFG_RX0Q_EN BIT(4)
184 #define MT_PBF_CFG_RX_DROP_EN BIT(8)
186 #define MT_PBF_TX_MAX_PCNT 0x0408
187 #define MT_PBF_RX_MAX_PCNT 0x040c
189 #define MT_BCN_OFFSET_BASE 0x041c
190 #define MT_BCN_OFFSET(_n) (MT_BCN_OFFSET_BASE + ((_n) << 2))
192 #define MT_RF_BYPASS_0 0x0504
193 #define MT_RF_BYPASS_1 0x0508
194 #define MT_RF_SETTING_0 0x050c
196 #define MT_RF_DATA_WRITE 0x0524
198 #define MT_RF_CTRL 0x0528
199 #define MT_RF_CTRL_ADDR GENMASK(11, 0)
200 #define MT_RF_CTRL_WRITE BIT(12)
201 #define MT_RF_CTRL_BUSY BIT(13)
202 #define MT_RF_CTRL_IDX BIT(16)
204 #define MT_RF_DATA_READ 0x052c
206 #define MT_FCE_PSE_CTRL 0x0800
207 #define MT_FCE_PARAMETERS 0x0804
208 #define MT_FCE_CSO 0x0808
210 #define MT_FCE_L2_STUFF 0x080c
211 #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
212 #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)
213 #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)
214 #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)
215 #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)
216 #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)
217 #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
218 #define MT_FCE_L2_STUFF_TS_LEN_EN GENMASK(23, 16)
219 #define MT_FCE_L2_STUFF_OTHER_PORT GENMASK(25, 24)
221 #define MT_FCE_WLAN_FLOW_CONTROL1 0x0824
223 #define MT_TX_CPU_FROM_FCE_BASE_PTR 0x09a0
224 #define MT_TX_CPU_FROM_FCE_MAX_COUNT 0x09a4
225 #define MT_FCE_PDMA_GLOBAL_CONF 0x09c4
226 #define MT_FCE_SKIP_FS 0x0a6c
228 #define MT_PAUSE_ENABLE_CONTROL1 0x0a38
230 #define MT_MAC_CSR0 0x1000
232 #define MT_MAC_SYS_CTRL 0x1004
233 #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
234 #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)
235 #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)
236 #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)
238 #define MT_MAC_ADDR_DW0 0x1008
239 #define MT_MAC_ADDR_DW1 0x100c
240 #define MT_MAC_ADDR_DW1_U2ME_MASK GENMASK(23, 16)
242 #define MT_MAC_BSSID_DW0 0x1010
243 #define MT_MAC_BSSID_DW1 0x1014
244 #define MT_MAC_BSSID_DW1_ADDR GENMASK(15, 0)
245 #define MT_MAC_BSSID_DW1_MBSS_MODE GENMASK(17, 16)
246 #define MT_MAC_BSSID_DW1_MBEACON_N GENMASK(20, 18)
247 #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)
248 #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)
249 #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)
250 #define MT_MAC_BSSID_DW1_MBSS_IDX_BYTE GENMASK(26, 24)
252 #define MT_MAX_LEN_CFG 0x1018
254 #define MT_AMPDU_MAX_LEN_20M1S 0x1030
255 #define MT_AMPDU_MAX_LEN_20M2S 0x1034
256 #define MT_AMPDU_MAX_LEN_40M1S 0x1038
257 #define MT_AMPDU_MAX_LEN_40M2S 0x103c
258 #define MT_AMPDU_MAX_LEN 0x1040
260 #define MT_WCID_DROP_BASE 0x106c
261 #define MT_WCID_DROP(_n) (MT_WCID_DROP_BASE + ((_n) >> 5) * 4)
262 #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32)
264 #define MT_BCN_BYPASS_MASK 0x108c
266 #define MT_MAC_APC_BSSID_BASE 0x1090
267 #define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8))
268 #define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4))
269 #define MT_MAC_APC_BSSID_H_ADDR GENMASK(15, 0)
270 #define MT_MAC_APC_BSSID0_H_EN BIT(16)
272 #define MT_XIFS_TIME_CFG 0x1100
273 #define MT_XIFS_TIME_CFG_CCK_SIFS GENMASK(7, 0)
274 #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
275 #define MT_XIFS_TIME_CFG_OFDM_XIFS GENMASK(19, 16)
276 #define MT_XIFS_TIME_CFG_EIFS GENMASK(28, 20)
277 #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)
279 #define MT_BKOFF_SLOT_CFG 0x1104
280 #define MT_BKOFF_SLOT_CFG_SLOTTIME GENMASK(7, 0)
281 #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
283 #define MT_CH_TIME_CFG 0x110c
284 #define MT_CH_TIME_CFG_TIMER_EN BIT(0)
285 #define MT_CH_TIME_CFG_TX_AS_BUSY BIT(1)
286 #define MT_CH_TIME_CFG_RX_AS_BUSY BIT(2)
287 #define MT_CH_TIME_CFG_NAV_AS_BUSY BIT(3)
288 #define MT_CH_TIME_CFG_EIFS_AS_BUSY BIT(4)
289 #define MT_CH_TIME_CFG_MDRDY_CNT_EN BIT(5)
290 #define MT_CH_TIME_CFG_CH_TIMER_CLR GENMASK(9, 8)
291 #define MT_CH_TIME_CFG_MDRDY_CLR GENMASK(11, 10)
293 #define MT_PBF_LIFE_TIMER 0x1110
295 #define MT_BEACON_TIME_CFG 0x1114
296 #define MT_BEACON_TIME_CFG_INTVAL GENMASK(15, 0)
297 #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)
298 #define MT_BEACON_TIME_CFG_SYNC_MODE GENMASK(18, 17)
299 #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)
300 #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)
301 #define MT_BEACON_TIME_CFG_TSF_COMP GENMASK(31, 24)
303 #define MT_TBTT_SYNC_CFG 0x1118
304 #define MT_TBTT_TIMER_CFG 0x1124
306 #define MT_INT_TIMER_CFG 0x1128
307 #define MT_INT_TIMER_CFG_PRE_TBTT GENMASK(15, 0)
308 #define MT_INT_TIMER_CFG_GP_TIMER GENMASK(31, 16)
310 #define MT_INT_TIMER_EN 0x112c
311 #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
312 #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)
314 #define MT_CH_IDLE 0x1130
315 #define MT_CH_BUSY 0x1134
316 #define MT_EXT_CH_BUSY 0x1138
317 #define MT_ED_CCA_TIMER 0x1140
319 #define MT_MAC_STATUS 0x1200
320 #define MT_MAC_STATUS_TX BIT(0)
321 #define MT_MAC_STATUS_RX BIT(1)
323 #define MT_PWR_PIN_CFG 0x1204
324 #define MT_AUX_CLK_CFG 0x120c
326 #define MT_BB_PA_MODE_CFG0 0x1214
327 #define MT_BB_PA_MODE_CFG1 0x1218
328 #define MT_RF_PA_MODE_CFG0 0x121c
329 #define MT_RF_PA_MODE_CFG1 0x1220
331 #define MT_RF_PA_MODE_ADJ0 0x1228
332 #define MT_RF_PA_MODE_ADJ1 0x122c
334 #define MT_DACCLK_EN_DLY_CFG 0x1264
336 #define MT_EDCA_CFG_BASE 0x1300
337 #define MT_EDCA_CFG_AC(_n) (MT_EDCA_CFG_BASE + ((_n) << 2))
338 #define MT_EDCA_CFG_TXOP GENMASK(7, 0)
339 #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
340 #define MT_EDCA_CFG_CWMIN GENMASK(15, 12)
341 #define MT_EDCA_CFG_CWMAX GENMASK(19, 16)
343 #define MT_TX_PWR_CFG_0 0x1314
344 #define MT_TX_PWR_CFG_1 0x1318
345 #define MT_TX_PWR_CFG_2 0x131c
346 #define MT_TX_PWR_CFG_3 0x1320
347 #define MT_TX_PWR_CFG_4 0x1324
348 #define MT_TX_PIN_CFG 0x1328
349 #define MT_TX_PIN_CFG_TXANT GENMASK(3, 0)
351 #define MT_TX_BAND_CFG 0x132c
352 #define MT_TX_BAND_CFG_UPPER_40M BIT(0)
353 #define MT_TX_BAND_CFG_5G BIT(1)
354 #define MT_TX_BAND_CFG_2G BIT(2)
356 #define MT_HT_FBK_TO_LEGACY 0x1384
357 #define MT_TX_MPDU_ADJ_INT 0x1388
359 #define MT_TX_PWR_CFG_7 0x13d4
360 #define MT_TX_PWR_CFG_8 0x13d8
361 #define MT_TX_PWR_CFG_9 0x13dc
363 #define MT_TX_SW_CFG0 0x1330
364 #define MT_TX_SW_CFG1 0x1334
365 #define MT_TX_SW_CFG2 0x1338
367 #define MT_TXOP_CTRL_CFG 0x1340
369 #define MT_TX_RTS_CFG 0x1344
370 #define MT_TX_RTS_CFG_RETRY_LIMIT GENMASK(7, 0)
371 #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
372 #define MT_TX_RTS_FALLBACK BIT(24)
374 #define MT_TX_TIMEOUT_CFG 0x1348
375 #define MT_TX_TIMEOUT_CFG_ACKTO GENMASK(15, 8)
377 #define MT_TX_RETRY_CFG 0x134c
378 #define MT_TX_LINK_CFG 0x1350
379 #define MT_VHT_HT_FBK_CFG1 0x1358
381 #define MT_PROT_CFG_RATE GENMASK(15, 0)
382 #define MT_PROT_CFG_CTRL GENMASK(17, 16)
383 #define MT_PROT_CFG_NAV GENMASK(19, 18)
384 #define MT_PROT_CFG_TXOP_ALLOW GENMASK(25, 20)
385 #define MT_PROT_CFG_RTS_THRESH BIT(26)
387 #define MT_CCK_PROT_CFG 0x1364
388 #define MT_OFDM_PROT_CFG 0x1368
389 #define MT_MM20_PROT_CFG 0x136c
390 #define MT_MM40_PROT_CFG 0x1370
391 #define MT_GF20_PROT_CFG 0x1374
392 #define MT_GF40_PROT_CFG 0x1378
394 #define MT_EXP_ACK_TIME 0x1380
396 #define MT_TX_PWR_CFG_0_EXT 0x1390
397 #define MT_TX_PWR_CFG_1_EXT 0x1394
399 #define MT_TX_FBK_LIMIT 0x1398
400 #define MT_TX_FBK_LIMIT_MPDU_FBK GENMASK(7, 0)
401 #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
402 #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)
403 #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)
404 #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)
406 #define MT_TX0_RF_GAIN_CORR 0x13a0
407 #define MT_TX1_RF_GAIN_CORR 0x13a4
409 #define MT_TX_ALC_CFG_0 0x13b0
410 #define MT_TX_ALC_CFG_0_CH_INIT_0 GENMASK(5, 0)
411 #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
412 #define MT_TX_ALC_CFG_0_LIMIT_0 GENMASK(21, 16)
413 #define MT_TX_ALC_CFG_0_LIMIT_1 GENMASK(29, 24)
415 #define MT_TX_ALC_CFG_1 0x13b4
416 #define MT_TX_ALC_CFG_1_TEMP_COMP GENMASK(5, 0)
418 #define MT_TX_ALC_CFG_2 0x13a8
419 #define MT_TX_ALC_CFG_2_TEMP_COMP GENMASK(5, 0)
421 #define MT_TX_ALC_CFG_3 0x13ac
422 #define MT_TX_ALC_CFG_4 0x13c0
423 #define MT_TX_ALC_CFG_4_LOWGAIN_CH_EN BIT(31)
425 #define MT_TX_ALC_VGA3 0x13c8
427 #define MT_TX_PROT_CFG6 0x13e0
428 #define MT_TX_PROT_CFG7 0x13e4
429 #define MT_TX_PROT_CFG8 0x13e8
431 #define MT_PIFS_TX_CFG 0x13ec
433 #define MT_RX_FILTR_CFG 0x1400
435 #define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
436 #define MT_RX_FILTR_CFG_PHY_ERR BIT(1)
437 #define MT_RX_FILTR_CFG_PROMISC BIT(2)
438 #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)
439 #define MT_RX_FILTR_CFG_VER_ERR BIT(4)
440 #define MT_RX_FILTR_CFG_MCAST BIT(5)
441 #define MT_RX_FILTR_CFG_BCAST BIT(6)
442 #define MT_RX_FILTR_CFG_DUP BIT(7)
443 #define MT_RX_FILTR_CFG_CFACK BIT(8)
444 #define MT_RX_FILTR_CFG_CFEND BIT(9)
445 #define MT_RX_FILTR_CFG_ACK BIT(10)
446 #define MT_RX_FILTR_CFG_CTS BIT(11)
447 #define MT_RX_FILTR_CFG_RTS BIT(12)
448 #define MT_RX_FILTR_CFG_PSPOLL BIT(13)
449 #define MT_RX_FILTR_CFG_BA BIT(14)
450 #define MT_RX_FILTR_CFG_BAR BIT(15)
451 #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)
453 #define MT_AUTO_RSP_CFG 0x1404
454 #define MT_LEGACY_BASIC_RATE 0x1408
455 #define MT_HT_BASIC_RATE 0x140c
457 #define MT_HT_CTRL_CFG 0x1410
459 #define MT_EXT_CCA_CFG 0x141c
460 #define MT_EXT_CCA_CFG_CCA0 GENMASK(1, 0)
461 #define MT_EXT_CCA_CFG_CCA1 GENMASK(3, 2)
462 #define MT_EXT_CCA_CFG_CCA2 GENMASK(5, 4)
463 #define MT_EXT_CCA_CFG_CCA3 GENMASK(7, 6)
464 #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
465 #define MT_EXT_CCA_CFG_ED_CCA_MASK GENMASK(15, 12)
467 #define MT_TX_SW_CFG3 0x1478
469 #define MT_PN_PAD_MODE 0x150c
471 #define MT_TXOP_HLDR_ET 0x1608
473 #define MT_PROT_AUTO_TX_CFG 0x1648
474 #define MT_PROT_AUTO_TX_CFG_PROT_PADJ GENMASK(11, 8)
475 #define MT_PROT_AUTO_TX_CFG_AUTO_PADJ GENMASK(27, 24)
477 #define MT_RX_STAT_0 0x1700
478 #define MT_RX_STAT_0_CRC_ERRORS GENMASK(15, 0)
479 #define MT_RX_STAT_0_PHY_ERRORS GENMASK(31, 16)
481 #define MT_RX_STAT_1 0x1704
482 #define MT_RX_STAT_1_CCA_ERRORS GENMASK(15, 0)
483 #define MT_RX_STAT_1_PLCP_ERRORS GENMASK(31, 16)
485 #define MT_RX_STAT_2 0x1708
486 #define MT_RX_STAT_2_DUP_ERRORS GENMASK(15, 0)
487 #define MT_RX_STAT_2_OVERFLOW_ERRORS GENMASK(31, 16)
489 #define MT_TX_STA_0 0x170c
490 #define MT_TX_STA_1 0x1710
491 #define MT_TX_STA_2 0x1714
493 #define MT_TX_STAT_FIFO 0x1718
494 #define MT_TX_STAT_FIFO_VALID BIT(0)
495 #define MT_TX_STAT_FIFO_SUCCESS BIT(5)
496 #define MT_TX_STAT_FIFO_AGGR BIT(6)
497 #define MT_TX_STAT_FIFO_ACKREQ BIT(7)
498 #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
499 #define MT_TX_STAT_FIFO_RATE GENMASK(31, 16)
501 #define MT_TX_AGG_CNT_BASE0 0x1720
502 #define MT_TX_AGG_CNT_BASE1 0x174c
504 #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
505 MT_TX_AGG_CNT_BASE0 + ((_id) << 2) : \
506 MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2))
508 #define MT_TX_STAT_FIFO_EXT 0x1798
509 #define MT_TX_STAT_FIFO_EXT_RETRY GENMASK(7, 0)
510 #define MT_TX_STAT_FIFO_EXT_PKTID GENMASK(15, 8)
512 #define MT_WCID_TX_RATE_BASE 0x1c00
513 #define MT_WCID_TX_RATE(_i) (MT_WCID_TX_RATE_BASE + ((_i) << 3))
515 #define MT_BBP_CORE_BASE 0x2000
516 #define MT_BBP_IBI_BASE 0x2100
517 #define MT_BBP_AGC_BASE 0x2300
518 #define MT_BBP_TXC_BASE 0x2400
519 #define MT_BBP_RXC_BASE 0x2500
520 #define MT_BBP_TXO_BASE 0x2600
521 #define MT_BBP_TXBE_BASE 0x2700
522 #define MT_BBP_RXFE_BASE 0x2800
523 #define MT_BBP_RXO_BASE 0x2900
524 #define MT_BBP_DFS_BASE 0x2a00
525 #define MT_BBP_TR_BASE 0x2b00
526 #define MT_BBP_CAL_BASE 0x2c00
527 #define MT_BBP_DSC_BASE 0x2e00
528 #define MT_BBP_PFMU_BASE 0x2f00
530 #define MT_BBP(_type, _n) (MT_BBP_##_type##_BASE + ((_n) << 2))
532 #define MT_BBP_CORE_R1_BW GENMASK(4, 3)
534 #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
535 #define MT_BBP_AGC_R0_BW GENMASK(14, 12)
538 #define MT_BBP_AGC_LNA_HIGH_GAIN GENMASK(21, 16)
539 #define MT_BBP_AGC_LNA_MID_GAIN GENMASK(13, 8)
540 #define MT_BBP_AGC_LNA_LOW_GAIN GENMASK(5, 0)
543 #define MT_BBP_AGC_LNA_ULOW_GAIN GENMASK(5, 0)
546 #define MT_BBP_AGC_LNA_GAIN_MODE GENMASK(7, 6)
547 #define MT_BBP_AGC_GAIN GENMASK(14, 8)
549 #define MT_BBP_AGC20_RSSI0 GENMASK(7, 0)
550 #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
552 #define MT_BBP_TXBE_R0_CTRL_CHAN GENMASK(1, 0)
554 #define MT_WCID_ADDR_BASE 0x1800
555 #define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8)
557 #define MT_SRAM_BASE 0x4000
559 #define MT_WCID_KEY_BASE 0x8000
560 #define MT_WCID_KEY(_n) (MT_WCID_KEY_BASE + (_n) * 32)
562 #define MT_WCID_IV_BASE 0xa000
563 #define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8)
565 #define MT_WCID_ATTR_BASE 0xa800
566 #define MT_WCID_ATTR(_n) (MT_WCID_ATTR_BASE + (_n) * 4)
568 #define MT_WCID_ATTR_PAIRWISE BIT(0)
569 #define MT_WCID_ATTR_PKEY_MODE GENMASK(3, 1)
570 #define MT_WCID_ATTR_BSS_IDX GENMASK(6, 4)
571 #define MT_WCID_ATTR_RXWI_UDF GENMASK(9, 7)
572 #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)
573 #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)
574 #define MT_WCID_ATTR_WAPI_MCBC BIT(15)
575 #define MT_WCID_ATTR_WAPI_KEYID GENMASK(31, 24)
577 #define MT_SKEY_BASE_0 0xac00
578 #define MT_SKEY_BASE_1 0xb400
579 #define MT_SKEY_0(_bss, _idx) (MT_SKEY_BASE_0 + (4 * (_bss) + _idx) * 32)
580 #define MT_SKEY_1(_bss, _idx) (MT_SKEY_BASE_1 + (4 * ((_bss) & 7) + _idx) * 32)
581 #define MT_SKEY(_bss, _idx) ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
583 #define MT_SKEY_MODE_BASE_0 0xb000
584 #define MT_SKEY_MODE_BASE_1 0xb3f0
585 #define MT_SKEY_MODE_0(_bss) (MT_SKEY_MODE_BASE_0 + ((_bss / 2) << 2))
586 #define MT_SKEY_MODE_1(_bss) (MT_SKEY_MODE_BASE_1 + ((((_bss) & 7) / 2) << 2))
587 #define MT_SKEY_MODE(_bss) ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss))
588 #define MT_SKEY_MODE_MASK GENMASK(3, 0)
589 #define MT_SKEY_MODE_SHIFT(_bss, _idx) (4 * ((_idx) + 4 * (_bss & 1)))
591 #define MT_BEACON_BASE 0xc000
593 #define MT_TEMP_SENSOR 0x1d000
594 #define MT_TEMP_SENSOR_VAL GENMASK(6, 0)
596 struct mt76_wcid_addr {
599 } __packed __aligned(4);
601 struct mt76_wcid_key {
605 } __packed __aligned(4);
607 enum mt76x2_cipher_type {