2 * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <asm/unaligned.h>
19 #include "mt76x2_eeprom.h"
21 #define EE_FIELD(_name, _value) [MT_EE_##_name] = (_value) | 1
24 mt76x2_eeprom_copy(struct mt76x2_dev *dev, enum mt76x2_eeprom_field field,
27 if (field + len > dev->mt76.eeprom.size)
30 memcpy(dest, dev->mt76.eeprom.data + field, len);
35 mt76x2_eeprom_get_macaddr(struct mt76x2_dev *dev)
37 void *src = dev->mt76.eeprom.data + MT_EE_MAC_ADDR;
39 memcpy(dev->mt76.macaddr, src, ETH_ALEN);
43 void mt76x2_eeprom_parse_hw_cap(struct mt76x2_dev *dev)
45 u16 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0);
47 switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, val)) {
49 dev->mt76.cap.has_5ghz = true;
52 dev->mt76.cap.has_2ghz = true;
55 dev->mt76.cap.has_2ghz = true;
56 dev->mt76.cap.has_5ghz = true;
60 EXPORT_SYMBOL_GPL(mt76x2_eeprom_parse_hw_cap);
63 mt76x2_efuse_read(struct mt76x2_dev *dev, u16 addr, u8 *data)
68 val = mt76_rr(dev, MT_EFUSE_CTRL);
69 val &= ~(MT_EFUSE_CTRL_AIN |
71 val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf);
72 val |= MT_EFUSE_CTRL_KICK;
73 mt76_wr(dev, MT_EFUSE_CTRL, val);
75 if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
80 val = mt76_rr(dev, MT_EFUSE_CTRL);
81 if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
82 memset(data, 0xff, 16);
86 for (i = 0; i < 4; i++) {
87 val = mt76_rr(dev, MT_EFUSE_DATA(i));
88 put_unaligned_le32(val, data + 4 * i);
95 mt76x2_get_efuse_data(struct mt76x2_dev *dev, void *buf, int len)
99 for (i = 0; i + 16 <= len; i += 16) {
100 ret = mt76x2_efuse_read(dev, i, buf + i);
109 mt76x2_has_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
111 u16 *efuse_w = (u16 *) efuse;
113 if (efuse_w[MT_EE_NIC_CONF_0] != 0)
116 if (efuse_w[MT_EE_XTAL_TRIM_1] == 0xffff)
119 if (efuse_w[MT_EE_TX_POWER_DELTA_BW40] != 0)
122 if (efuse_w[MT_EE_TX_POWER_0_START_2G] == 0xffff)
125 if (efuse_w[MT_EE_TX_POWER_0_GRP3_TX_POWER_DELTA] != 0)
128 if (efuse_w[MT_EE_TX_POWER_0_GRP4_TSSI_SLOPE] == 0xffff)
135 mt76x2_apply_cal_free_data(struct mt76x2_dev *dev, u8 *efuse)
137 #define GROUP_5G(_id) \
138 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
139 MT_EE_TX_POWER_0_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1, \
140 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id), \
141 MT_EE_TX_POWER_1_START_5G + MT_TX_POWER_GROUP_SIZE_5G * (_id) + 1
143 static const u8 cal_free_bytes[] = {
145 MT_EE_TX_POWER_EXT_PA_5G + 1,
146 MT_EE_TX_POWER_0_START_2G,
147 MT_EE_TX_POWER_0_START_2G + 1,
148 MT_EE_TX_POWER_1_START_2G,
149 MT_EE_TX_POWER_1_START_2G + 1,
156 MT_EE_RF_2G_TSSI_OFF_TXPOWER,
157 MT_EE_RF_2G_RX_HIGH_GAIN + 1,
158 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN,
159 MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN + 1,
160 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN,
161 MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN + 1,
162 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN,
163 MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN + 1,
165 u8 *eeprom = dev->mt76.eeprom.data;
167 eeprom[MT_EE_TX_POWER_0_START_5G],
168 eeprom[MT_EE_TX_POWER_0_START_5G + 1],
169 eeprom[MT_EE_TX_POWER_1_START_5G],
170 eeprom[MT_EE_TX_POWER_1_START_5G + 1]
175 if (!mt76x2_has_cal_free_data(dev, efuse))
178 for (i = 0; i < ARRAY_SIZE(cal_free_bytes); i++) {
179 int offset = cal_free_bytes[i];
181 eeprom[offset] = efuse[offset];
184 if (!(efuse[MT_EE_TX_POWER_0_START_5G] |
185 efuse[MT_EE_TX_POWER_0_START_5G + 1]))
186 memcpy(eeprom + MT_EE_TX_POWER_0_START_5G, prev_grp0, 2);
187 if (!(efuse[MT_EE_TX_POWER_1_START_5G] |
188 efuse[MT_EE_TX_POWER_1_START_5G + 1]))
189 memcpy(eeprom + MT_EE_TX_POWER_1_START_5G, prev_grp0 + 2, 2);
191 val = get_unaligned_le16(efuse + MT_EE_BT_RCAL_RESULT);
193 eeprom[MT_EE_BT_RCAL_RESULT] = val & 0xff;
195 val = get_unaligned_le16(efuse + MT_EE_BT_VCDL_CALIBRATION);
197 eeprom[MT_EE_BT_VCDL_CALIBRATION + 1] = val >> 8;
199 val = get_unaligned_le16(efuse + MT_EE_BT_PMUCFG);
201 eeprom[MT_EE_BT_PMUCFG] = val & 0xff;
204 static int mt76x2_check_eeprom(struct mt76x2_dev *dev)
206 u16 val = get_unaligned_le16(dev->mt76.eeprom.data);
209 val = get_unaligned_le16(dev->mt76.eeprom.data + MT_EE_PCI_ID);
216 dev_err(dev->mt76.dev, "EEPROM data check failed: %04x\n", val);
222 mt76x2_eeprom_load(struct mt76x2_dev *dev)
228 ret = mt76_eeprom_init(&dev->mt76, MT7662_EEPROM_SIZE);
234 found = !mt76x2_check_eeprom(dev);
236 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, MT7662_EEPROM_SIZE,
238 dev->mt76.otp.size = MT7662_EEPROM_SIZE;
239 if (!dev->mt76.otp.data)
242 efuse = dev->mt76.otp.data;
244 if (mt76x2_get_efuse_data(dev, efuse, MT7662_EEPROM_SIZE))
248 mt76x2_apply_cal_free_data(dev, efuse);
250 /* FIXME: check if efuse data is complete */
252 memcpy(dev->mt76.eeprom.data, efuse, MT7662_EEPROM_SIZE);
263 mt76x2_sign_extend(u32 val, unsigned int size)
265 bool sign = val & BIT(size - 1);
267 val &= BIT(size - 1) - 1;
269 return sign ? val : -val;
273 mt76x2_sign_extend_optional(u32 val, unsigned int size)
275 bool enable = val & BIT(size);
277 return enable ? mt76x2_sign_extend(val, size) : 0;
283 return val != 0 && val != 0xff;
287 mt76x2_set_rx_gain_group(struct mt76x2_dev *dev, u8 val)
289 s8 *dest = dev->cal.rx.high_gain;
291 if (!field_valid(val)) {
297 dest[0] = mt76x2_sign_extend(val, 4);
298 dest[1] = mt76x2_sign_extend(val >> 4, 4);
302 mt76x2_set_rssi_offset(struct mt76x2_dev *dev, int chain, u8 val)
304 s8 *dest = dev->cal.rx.rssi_offset;
306 if (!field_valid(val)) {
311 dest[chain] = mt76x2_sign_extend_optional(val, 7);
314 static enum mt76x2_cal_channel_group
315 mt76x2_get_cal_channel_group(int channel)
317 if (channel >= 184 && channel <= 196)
318 return MT_CH_5G_JAPAN;
320 return MT_CH_5G_UNII_1;
322 return MT_CH_5G_UNII_2;
324 return MT_CH_5G_UNII_2E_1;
326 return MT_CH_5G_UNII_2E_2;
327 return MT_CH_5G_UNII_3;
331 mt76x2_get_5g_rx_gain(struct mt76x2_dev *dev, u8 channel)
333 enum mt76x2_cal_channel_group group;
335 group = mt76x2_get_cal_channel_group(channel);
338 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN);
339 case MT_CH_5G_UNII_1:
340 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP0_1_RX_HIGH_GAIN) >> 8;
341 case MT_CH_5G_UNII_2:
342 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN);
343 case MT_CH_5G_UNII_2E_1:
344 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP2_3_RX_HIGH_GAIN) >> 8;
345 case MT_CH_5G_UNII_2E_2:
346 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN);
348 return mt76x2_eeprom_get(dev, MT_EE_RF_5G_GRP4_5_RX_HIGH_GAIN) >> 8;
352 void mt76x2_read_rx_gain(struct mt76x2_dev *dev)
354 struct ieee80211_channel *chan = dev->mt76.chandef.chan;
355 int channel = chan->hw_value;
356 s8 lna_5g[3], lna_2g;
360 if (chan->band == NL80211_BAND_2GHZ)
361 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN) >> 8;
363 val = mt76x2_get_5g_rx_gain(dev, channel);
365 mt76x2_set_rx_gain_group(dev, val);
367 if (chan->band == NL80211_BAND_2GHZ) {
368 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_0);
369 mt76x2_set_rssi_offset(dev, 0, val);
370 mt76x2_set_rssi_offset(dev, 1, val >> 8);
372 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_0);
373 mt76x2_set_rssi_offset(dev, 0, val);
374 mt76x2_set_rssi_offset(dev, 1, val >> 8);
377 val = mt76x2_eeprom_get(dev, MT_EE_LNA_GAIN);
379 lna_5g[0] = val >> 8;
381 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_2G_1);
382 lna_5g[1] = val >> 8;
384 val = mt76x2_eeprom_get(dev, MT_EE_RSSI_OFFSET_5G_1);
385 lna_5g[2] = val >> 8;
387 if (!field_valid(lna_5g[1]))
388 lna_5g[1] = lna_5g[0];
390 if (!field_valid(lna_5g[2]))
391 lna_5g[2] = lna_5g[0];
393 dev->cal.rx.mcu_gain = (lna_2g & 0xff);
394 dev->cal.rx.mcu_gain |= (lna_5g[0] & 0xff) << 8;
395 dev->cal.rx.mcu_gain |= (lna_5g[1] & 0xff) << 16;
396 dev->cal.rx.mcu_gain |= (lna_5g[2] & 0xff) << 24;
398 val = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_1);
399 if (val & MT_EE_NIC_CONF_1_LNA_EXT_2G)
401 if (val & MT_EE_NIC_CONF_1_LNA_EXT_5G)
402 memset(lna_5g, 0, sizeof(lna_5g));
404 if (chan->band == NL80211_BAND_2GHZ)
406 else if (channel <= 64)
408 else if (channel <= 128)
416 dev->cal.rx.lna_gain = mt76x2_sign_extend(lna, 8);
418 EXPORT_SYMBOL_GPL(mt76x2_read_rx_gain);
421 mt76x2_rate_power_val(u8 val)
423 if (!field_valid(val))
426 return mt76x2_sign_extend_optional(val, 7);
429 void mt76x2_get_rate_power(struct mt76x2_dev *dev, struct mt76_rate_power *t,
430 struct ieee80211_channel *chan)
435 is_5ghz = chan->band == NL80211_BAND_5GHZ;
437 memset(t, 0, sizeof(*t));
439 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_CCK);
440 t->cck[0] = t->cck[1] = mt76x2_rate_power_val(val);
441 t->cck[2] = t->cck[3] = mt76x2_rate_power_val(val >> 8);
444 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_6M);
446 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_6M);
447 t->ofdm[0] = t->ofdm[1] = mt76x2_rate_power_val(val);
448 t->ofdm[2] = t->ofdm[3] = mt76x2_rate_power_val(val >> 8);
451 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_5G_24M);
453 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_OFDM_2G_24M);
454 t->ofdm[4] = t->ofdm[5] = mt76x2_rate_power_val(val);
455 t->ofdm[6] = t->ofdm[7] = mt76x2_rate_power_val(val >> 8);
457 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS0);
458 t->ht[0] = t->ht[1] = mt76x2_rate_power_val(val);
459 t->ht[2] = t->ht[3] = mt76x2_rate_power_val(val >> 8);
461 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS4);
462 t->ht[4] = t->ht[5] = mt76x2_rate_power_val(val);
463 t->ht[6] = t->ht[7] = mt76x2_rate_power_val(val >> 8);
465 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS8);
466 t->ht[8] = t->ht[9] = mt76x2_rate_power_val(val);
467 t->ht[10] = t->ht[11] = mt76x2_rate_power_val(val >> 8);
469 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_HT_MCS12);
470 t->ht[12] = t->ht[13] = mt76x2_rate_power_val(val);
471 t->ht[14] = t->ht[15] = mt76x2_rate_power_val(val >> 8);
473 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS0);
474 t->vht[0] = t->vht[1] = mt76x2_rate_power_val(val);
475 t->vht[2] = t->vht[3] = mt76x2_rate_power_val(val >> 8);
477 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS4);
478 t->vht[4] = t->vht[5] = mt76x2_rate_power_val(val);
479 t->vht[6] = t->vht[7] = mt76x2_rate_power_val(val >> 8);
481 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_VHT_MCS8);
484 t->vht[8] = t->vht[9] = mt76x2_rate_power_val(val >> 8);
486 EXPORT_SYMBOL_GPL(mt76x2_get_rate_power);
488 int mt76x2_get_max_rate_power(struct mt76_rate_power *r)
493 for (i = 0; i < sizeof(r->all); i++)
494 ret = max(ret, r->all[i]);
498 EXPORT_SYMBOL_GPL(mt76x2_get_max_rate_power);
501 mt76x2_get_power_info_2g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
502 struct ieee80211_channel *chan, int chain, int offset)
504 int channel = chan->hw_value;
511 else if (channel < 11)
516 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
518 t->chain[chain].tssi_slope = data[0];
519 t->chain[chain].tssi_offset = data[1];
520 t->chain[chain].target_power = data[2];
521 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
523 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_TSSI_OFF_TXPOWER);
524 t->target_power = val >> 8;
528 mt76x2_get_power_info_5g(struct mt76x2_dev *dev, struct mt76x2_tx_power_info *t,
529 struct ieee80211_channel *chan, int chain, int offset)
531 int channel = chan->hw_value;
532 enum mt76x2_cal_channel_group group;
537 group = mt76x2_get_cal_channel_group(channel);
538 offset += group * MT_TX_POWER_GROUP_SIZE_5G;
542 else if (channel >= 184)
544 else if (channel < 44)
546 else if (channel < 52)
548 else if (channel < 58)
550 else if (channel < 98)
552 else if (channel < 106)
554 else if (channel < 116)
556 else if (channel < 130)
558 else if (channel < 149)
560 else if (channel < 157)
565 mt76x2_eeprom_copy(dev, offset, data, sizeof(data));
567 t->chain[chain].tssi_slope = data[0];
568 t->chain[chain].tssi_offset = data[1];
569 t->chain[chain].target_power = data[2];
570 t->chain[chain].delta = mt76x2_sign_extend_optional(data[delta_idx], 7);
572 val = mt76x2_eeprom_get(dev, MT_EE_RF_2G_RX_HIGH_GAIN);
573 t->target_power = val & 0xff;
576 void mt76x2_get_power_info(struct mt76x2_dev *dev,
577 struct mt76x2_tx_power_info *t,
578 struct ieee80211_channel *chan)
582 memset(t, 0, sizeof(*t));
584 bw40 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW40);
585 bw80 = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80);
587 if (chan->band == NL80211_BAND_5GHZ) {
589 mt76x2_get_power_info_5g(dev, t, chan, 0,
590 MT_EE_TX_POWER_0_START_5G);
591 mt76x2_get_power_info_5g(dev, t, chan, 1,
592 MT_EE_TX_POWER_1_START_5G);
594 mt76x2_get_power_info_2g(dev, t, chan, 0,
595 MT_EE_TX_POWER_0_START_2G);
596 mt76x2_get_power_info_2g(dev, t, chan, 1,
597 MT_EE_TX_POWER_1_START_2G);
600 if (mt76x2_tssi_enabled(dev) || !field_valid(t->target_power))
601 t->target_power = t->chain[0].target_power;
603 t->delta_bw40 = mt76x2_rate_power_val(bw40);
604 t->delta_bw80 = mt76x2_rate_power_val(bw80);
606 EXPORT_SYMBOL_GPL(mt76x2_get_power_info);
608 int mt76x2_get_temp_comp(struct mt76x2_dev *dev, struct mt76x2_temp_comp *t)
610 enum nl80211_band band = dev->mt76.chandef.chan->band;
614 memset(t, 0, sizeof(*t));
616 if (!mt76x2_temp_tx_alc_enabled(dev))
619 if (!mt76x2_ext_pa_enabled(dev, band))
622 val = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G) >> 8;
623 t->temp_25_ref = val & 0x7f;
624 if (band == NL80211_BAND_5GHZ) {
625 slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_5G);
626 bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_EXT_PA_5G);
628 slope = mt76x2_eeprom_get(dev, MT_EE_RF_TEMP_COMP_SLOPE_2G);
629 bounds = mt76x2_eeprom_get(dev, MT_EE_TX_POWER_DELTA_BW80) >> 8;
632 t->high_slope = slope & 0xff;
633 t->low_slope = slope >> 8;
634 t->lower_bound = 0 - (bounds & 0xf);
635 t->upper_bound = (bounds >> 4) & 0xf;
639 EXPORT_SYMBOL_GPL(mt76x2_get_temp_comp);
641 bool mt76x2_ext_pa_enabled(struct mt76x2_dev *dev, enum nl80211_band band)
643 u16 conf0 = mt76x2_eeprom_get(dev, MT_EE_NIC_CONF_0);
645 if (band == NL80211_BAND_5GHZ)
646 return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_5G);
648 return !(conf0 & MT_EE_NIC_CONF_0_PA_INT_2G);
650 EXPORT_SYMBOL_GPL(mt76x2_ext_pa_enabled);
652 int mt76x2_eeprom_init(struct mt76x2_dev *dev)
656 ret = mt76x2_eeprom_load(dev);
660 mt76x2_eeprom_parse_hw_cap(dev);
661 mt76x2_eeprom_get_macaddr(dev);
662 mt76_eeprom_override(&dev->mt76);
663 dev->mt76.macaddr[0] &= ~BIT(1);
667 EXPORT_SYMBOL_GPL(mt76x2_eeprom_init);
669 MODULE_LICENSE("Dual BSD/GPL");