1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2014 Intel Mobile Communications GmbH
6 * Portions of this file are derived from the ipw3945 project, as well
7 * as portions of the ieee80211 subsystem header files.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
22 * The full GNU General Public License is included in this distribution in the
23 * file called LICENSE.
25 * Contact Information:
26 * Intel Linux Wireless <ilw@linux.intel.com>
27 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
29 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/slab.h>
32 #include <linux/sched.h>
34 #include "iwl-debug.h"
39 #include "iwl-op-mode.h"
41 /* FIXME: need to abstract out TX command (once we know what it looks like) */
42 #include "dvm/commands.h"
44 #define IWL_TX_CRC_SIZE 4
45 #define IWL_TX_DELIMITER_SIZE 4
47 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
52 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
53 * of buffer descriptors, each of which points to one or more data buffers for
54 * the device to read from or fill. Driver and device exchange status of each
55 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
56 * entries in each circular buffer, to protect against confusing empty and full
59 * The device reads or writes the data in the queues via the device's several
60 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
62 * For Tx queue, there are low mark and high mark limits. If, after queuing
63 * the packet for Tx, free space become < low mark, Tx queue stopped. When
64 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
67 ***************************************************/
68 static int iwl_queue_space(const struct iwl_queue *q)
74 * To avoid ambiguity between empty and completely full queues, there
75 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
76 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
77 * to reserve any queue entries for this purpose.
79 if (q->n_window < TFD_QUEUE_SIZE_MAX)
82 max = TFD_QUEUE_SIZE_MAX - 1;
85 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
86 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
88 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
90 if (WARN_ON(used > max))
97 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
99 static int iwl_queue_init(struct iwl_queue *q, int slots_num, u32 id)
101 q->n_window = slots_num;
104 /* slots_num must be power-of-two size, otherwise
105 * get_cmd_index is broken. */
106 if (WARN_ON(!is_power_of_2(slots_num)))
109 q->low_mark = q->n_window / 4;
113 q->high_mark = q->n_window / 8;
114 if (q->high_mark < 2)
123 static int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
124 struct iwl_dma_ptr *ptr, size_t size)
126 if (WARN_ON(ptr->addr))
129 ptr->addr = dma_alloc_coherent(trans->dev, size,
130 &ptr->dma, GFP_KERNEL);
137 static void iwl_pcie_free_dma_ptr(struct iwl_trans *trans,
138 struct iwl_dma_ptr *ptr)
140 if (unlikely(!ptr->addr))
143 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
144 memset(ptr, 0, sizeof(*ptr));
147 static void iwl_pcie_txq_stuck_timer(unsigned long data)
149 struct iwl_txq *txq = (void *)data;
150 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
151 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
152 u32 scd_sram_addr = trans_pcie->scd_base_addr +
153 SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
157 spin_lock(&txq->lock);
158 /* check if triggered erroneously */
159 if (txq->q.read_ptr == txq->q.write_ptr) {
160 spin_unlock(&txq->lock);
163 spin_unlock(&txq->lock);
165 IWL_ERR(trans, "Queue %d stuck for %u ms.\n", txq->q.id,
166 jiffies_to_msecs(txq->wd_timeout));
167 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
168 txq->q.read_ptr, txq->q.write_ptr);
170 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
172 iwl_print_hex_error(trans, buf, sizeof(buf));
174 for (i = 0; i < FH_TCSR_CHNL_NUM; i++)
175 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", i,
176 iwl_read_direct32(trans, FH_TX_TRB_REG(i)));
178 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
179 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(i));
180 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
181 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
183 iwl_trans_read_mem32(trans,
184 trans_pcie->scd_base_addr +
185 SCD_TRANS_TBL_OFFSET_QUEUE(i));
188 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
190 tbl_dw = tbl_dw & 0x0000FFFF;
193 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
194 i, active ? "" : "in", fifo, tbl_dw,
195 iwl_read_prph(trans, SCD_QUEUE_RDPTR(i)) &
196 (TFD_QUEUE_SIZE_MAX - 1),
197 iwl_read_prph(trans, SCD_QUEUE_WRPTR(i)));
200 iwl_force_nmi(trans);
204 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
206 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
207 struct iwl_txq *txq, u16 byte_cnt)
209 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
210 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 int write_ptr = txq->q.write_ptr;
212 int txq_id = txq->q.id;
215 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
217 struct iwl_tx_cmd *tx_cmd =
218 (void *) txq->entries[txq->q.write_ptr].cmd->payload;
220 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
222 sta_id = tx_cmd->sta_id;
223 sec_ctl = tx_cmd->sec_ctl;
225 switch (sec_ctl & TX_CMD_SEC_MSK) {
227 len += IEEE80211_CCMP_MIC_LEN;
229 case TX_CMD_SEC_TKIP:
230 len += IEEE80211_TKIP_ICV_LEN;
233 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
237 if (trans_pcie->bc_table_dword)
238 len = DIV_ROUND_UP(len, 4);
240 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
243 bc_ent = cpu_to_le16(len | (sta_id << 12));
245 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
247 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
249 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
252 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
255 struct iwl_trans_pcie *trans_pcie =
256 IWL_TRANS_GET_PCIE_TRANS(trans);
257 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
258 int txq_id = txq->q.id;
259 int read_ptr = txq->q.read_ptr;
262 struct iwl_tx_cmd *tx_cmd =
263 (void *)txq->entries[txq->q.read_ptr].cmd->payload;
265 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
267 if (txq_id != trans_pcie->cmd_queue)
268 sta_id = tx_cmd->sta_id;
270 bc_ent = cpu_to_le16(1 | (sta_id << 12));
271 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
273 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
275 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
279 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
281 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
284 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
286 int txq_id = txq->q.id;
288 lockdep_assert_held(&txq->lock);
291 * explicitly wake up the NIC if:
292 * 1. shadow registers aren't enabled
293 * 2. NIC is woken up for CMD regardless of shadow outside this function
294 * 3. there is a chance that the NIC is asleep
296 if (!trans->cfg->base_params->shadow_reg_enable &&
297 txq_id != trans_pcie->cmd_queue &&
298 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
300 * wake up nic if it's powered down ...
301 * uCode will wake up, and interrupt us again, so next
302 * time we'll skip this part.
304 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
306 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
307 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
309 iwl_set_bit(trans, CSR_GP_CNTRL,
310 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
311 txq->need_update = true;
317 * if not in power-save mode, uCode will never sleep when we're
318 * trying to tx (during RFKILL, we're not trying to tx).
320 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->q.write_ptr);
321 iwl_write32(trans, HBUS_TARG_WRPTR, txq->q.write_ptr | (txq_id << 8));
324 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
329 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
330 struct iwl_txq *txq = &trans_pcie->txq[i];
332 spin_lock_bh(&txq->lock);
333 if (trans_pcie->txq[i].need_update) {
334 iwl_pcie_txq_inc_wr_ptr(trans, txq);
335 trans_pcie->txq[i].need_update = false;
337 spin_unlock_bh(&txq->lock);
341 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
343 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
345 dma_addr_t addr = get_unaligned_le32(&tb->lo);
346 if (sizeof(dma_addr_t) > sizeof(u32))
348 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
353 static inline void iwl_pcie_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
354 dma_addr_t addr, u16 len)
356 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
357 u16 hi_n_len = len << 4;
359 put_unaligned_le32(addr, &tb->lo);
360 if (sizeof(dma_addr_t) > sizeof(u32))
361 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
363 tb->hi_n_len = cpu_to_le16(hi_n_len);
365 tfd->num_tbs = idx + 1;
368 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_tfd *tfd)
370 return tfd->num_tbs & 0x1f;
373 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
374 struct iwl_cmd_meta *meta,
380 /* Sanity check on number of chunks */
381 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
383 if (num_tbs >= IWL_NUM_OF_TBS) {
384 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
385 /* @todo issue fatal error, it is quite serious situation */
389 /* first TB is never freed - it's the scratchbuf data */
391 for (i = 1; i < num_tbs; i++) {
392 if (meta->flags & BIT(i + CMD_TB_BITMAP_POS))
393 dma_unmap_page(trans->dev,
394 iwl_pcie_tfd_tb_get_addr(tfd, i),
395 iwl_pcie_tfd_tb_get_len(tfd, i),
398 dma_unmap_single(trans->dev,
399 iwl_pcie_tfd_tb_get_addr(tfd, i),
400 iwl_pcie_tfd_tb_get_len(tfd, i),
407 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
408 * @trans - transport private data
410 * @dma_dir - the direction of the DMA mapping
412 * Does NOT advance any TFD circular buffer read/write indexes
413 * Does NOT free the TFD itself (which is within circular buffer)
415 static void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
417 struct iwl_tfd *tfd_tmp = txq->tfds;
419 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
420 * idx is bounded by n_window
422 int rd_ptr = txq->q.read_ptr;
423 int idx = get_cmd_index(&txq->q, rd_ptr);
425 lockdep_assert_held(&txq->lock);
427 /* We have only q->n_window txq->entries, but we use
428 * TFD_QUEUE_SIZE_MAX tfds
430 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, &tfd_tmp[rd_ptr]);
436 skb = txq->entries[idx].skb;
438 /* Can be called from irqs-disabled context
439 * If skb is not NULL, it means that the whole queue is being
440 * freed and that the queue is not empty - free the skb
443 iwl_op_mode_free_skb(trans->op_mode, skb);
444 txq->entries[idx].skb = NULL;
449 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
450 dma_addr_t addr, u16 len, bool reset)
453 struct iwl_tfd *tfd, *tfd_tmp;
458 tfd = &tfd_tmp[q->write_ptr];
461 memset(tfd, 0, sizeof(*tfd));
463 num_tbs = iwl_pcie_tfd_get_num_tbs(tfd);
465 /* Each TFD can point to a maximum 20 Tx buffers */
466 if (num_tbs >= IWL_NUM_OF_TBS) {
467 IWL_ERR(trans, "Error can not send more than %d chunks\n",
472 if (WARN(addr & ~IWL_TX_DMA_MASK,
473 "Unaligned address = %llx\n", (unsigned long long)addr))
476 iwl_pcie_tfd_set_tb(tfd, num_tbs, addr, len);
481 static int iwl_pcie_txq_alloc(struct iwl_trans *trans,
482 struct iwl_txq *txq, int slots_num,
485 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
486 size_t tfd_sz = sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX;
487 size_t scratchbuf_sz;
490 if (WARN_ON(txq->entries || txq->tfds))
493 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
495 txq->trans_pcie = trans_pcie;
497 txq->q.n_window = slots_num;
499 txq->entries = kcalloc(slots_num,
500 sizeof(struct iwl_pcie_txq_entry),
506 if (txq_id == trans_pcie->cmd_queue)
507 for (i = 0; i < slots_num; i++) {
508 txq->entries[i].cmd =
509 kmalloc(sizeof(struct iwl_device_cmd),
511 if (!txq->entries[i].cmd)
515 /* Circular buffer of transmit frame descriptors (TFDs),
516 * shared with device */
517 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
518 &txq->q.dma_addr, GFP_KERNEL);
522 BUILD_BUG_ON(IWL_HCMD_SCRATCHBUF_SIZE != sizeof(*txq->scratchbufs));
523 BUILD_BUG_ON(offsetof(struct iwl_pcie_txq_scratch_buf, scratch) !=
524 sizeof(struct iwl_cmd_header) +
525 offsetof(struct iwl_tx_cmd, scratch));
527 scratchbuf_sz = sizeof(*txq->scratchbufs) * slots_num;
529 txq->scratchbufs = dma_alloc_coherent(trans->dev, scratchbuf_sz,
530 &txq->scratchbufs_dma,
532 if (!txq->scratchbufs)
539 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->q.dma_addr);
541 if (txq->entries && txq_id == trans_pcie->cmd_queue)
542 for (i = 0; i < slots_num; i++)
543 kfree(txq->entries[i].cmd);
551 static int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
552 int slots_num, u32 txq_id)
556 txq->need_update = false;
558 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
559 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
560 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
562 /* Initialize queue's high/low-water marks, and head/tail indexes */
563 ret = iwl_queue_init(&txq->q, slots_num, txq_id);
567 spin_lock_init(&txq->lock);
570 * Tell nic where to find circular buffer of Tx Frame Descriptors for
571 * given Tx queue, and enable the DMA channel used for that queue.
572 * Circular buffer (TFD queue in DRAM) physical base address */
573 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
574 txq->q.dma_addr >> 8);
580 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
582 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
584 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
585 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
589 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
595 spin_lock_bh(&txq->lock);
596 while (q->write_ptr != q->read_ptr) {
597 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
598 txq_id, q->read_ptr);
599 iwl_pcie_txq_free_tfd(trans, txq);
600 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr);
603 spin_unlock_bh(&txq->lock);
605 /* just in case - this queue may have been stopped */
606 iwl_wake_queue(trans, txq);
610 * iwl_pcie_txq_free - Deallocate DMA queue.
611 * @txq: Transmit queue to deallocate.
613 * Empty queue by removing and destroying all BD's.
615 * 0-fill, but do not free "txq" descriptor structure.
617 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
619 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
620 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
621 struct device *dev = trans->dev;
627 iwl_pcie_txq_unmap(trans, txq_id);
629 /* De-alloc array of command/tx buffers */
630 if (txq_id == trans_pcie->cmd_queue)
631 for (i = 0; i < txq->q.n_window; i++) {
632 kzfree(txq->entries[i].cmd);
633 kzfree(txq->entries[i].free_buf);
636 /* De-alloc circular buffer of TFDs */
638 dma_free_coherent(dev,
639 sizeof(struct iwl_tfd) * TFD_QUEUE_SIZE_MAX,
640 txq->tfds, txq->q.dma_addr);
644 dma_free_coherent(dev,
645 sizeof(*txq->scratchbufs) * txq->q.n_window,
646 txq->scratchbufs, txq->scratchbufs_dma);
652 del_timer_sync(&txq->stuck_timer);
654 /* 0-fill queue descriptor structure */
655 memset(txq, 0, sizeof(*txq));
658 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
660 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
661 int nq = trans->cfg->base_params->num_of_queues;
664 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
665 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
667 /* make sure all queue are not stopped/used */
668 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
669 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
671 trans_pcie->scd_base_addr =
672 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
674 WARN_ON(scd_base_addr != 0 &&
675 scd_base_addr != trans_pcie->scd_base_addr);
677 /* reset context data, TX status and translation data */
678 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
679 SCD_CONTEXT_MEM_LOWER_BOUND,
682 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
683 trans_pcie->scd_bc_tbls.dma >> 10);
685 /* The chain extension of the SCD doesn't work well. This feature is
686 * enabled by default by the HW, so we need to disable it manually.
688 if (trans->cfg->base_params->scd_chain_ext_wa)
689 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
691 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
692 trans_pcie->cmd_fifo,
693 trans_pcie->cmd_q_wdg_timeout);
695 /* Activate all Tx DMA/FIFO channels */
696 iwl_scd_activate_fifos(trans);
698 /* Enable DMA channel */
699 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
700 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
701 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
702 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
704 /* Update FH chicken bits */
705 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
706 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
707 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
709 /* Enable L1-Active */
710 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
711 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
712 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
715 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
717 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
720 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
722 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
724 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(txq_id),
725 txq->q.dma_addr >> 8);
726 iwl_pcie_txq_unmap(trans, txq_id);
728 txq->q.write_ptr = 0;
731 /* Tell NIC where to find the "keep warm" buffer */
732 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
733 trans_pcie->kw.dma >> 4);
736 * Send 0 as the scd_base_addr since the device may have be reset
737 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
740 iwl_pcie_tx_start(trans, 0);
743 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
745 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
750 spin_lock(&trans_pcie->irq_lock);
752 if (!iwl_trans_grab_nic_access(trans, false, &flags))
755 /* Stop each Tx DMA channel */
756 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
757 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
758 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
761 /* Wait for DMA channels to be idle */
762 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
765 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
766 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
768 iwl_trans_release_nic_access(trans, &flags);
771 spin_unlock(&trans_pcie->irq_lock);
775 * iwl_pcie_tx_stop - Stop all Tx DMA channels
777 int iwl_pcie_tx_stop(struct iwl_trans *trans)
779 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
782 /* Turn off all Tx DMA fifos */
783 iwl_scd_deactivate_fifos(trans);
785 /* Turn off all Tx DMA channels */
786 iwl_pcie_tx_stop_fh(trans);
789 * This function can be called before the op_mode disabled the
790 * queues. This happens when we have an rfkill interrupt.
791 * Since we stop Tx altogether - mark the queues as stopped.
793 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
794 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
796 /* This can happen: start_hw, stop_device */
797 if (!trans_pcie->txq)
800 /* Unmap DMA from host system and free skb's */
801 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
803 iwl_pcie_txq_unmap(trans, txq_id);
809 * iwl_trans_tx_free - Free TXQ Context
811 * Destroy all TX DMA queues and structures
813 void iwl_pcie_tx_free(struct iwl_trans *trans)
816 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
819 if (trans_pcie->txq) {
821 txq_id < trans->cfg->base_params->num_of_queues; txq_id++)
822 iwl_pcie_txq_free(trans, txq_id);
825 kfree(trans_pcie->txq);
826 trans_pcie->txq = NULL;
828 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
830 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
834 * iwl_pcie_tx_alloc - allocate TX context
835 * Allocate all Tx DMA structures and initialize them
837 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
840 int txq_id, slots_num;
841 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
843 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
844 sizeof(struct iwlagn_scd_bc_tbl);
846 /*It is not allowed to alloc twice, so warn when this happens.
847 * We cannot rely on the previous allocation, so free and fail */
848 if (WARN_ON(trans_pcie->txq)) {
853 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
856 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
860 /* Alloc keep-warm buffer */
861 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
863 IWL_ERR(trans, "Keep Warm allocation failed\n");
867 trans_pcie->txq = kcalloc(trans->cfg->base_params->num_of_queues,
868 sizeof(struct iwl_txq), GFP_KERNEL);
869 if (!trans_pcie->txq) {
870 IWL_ERR(trans, "Not enough memory for txq\n");
875 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
876 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
878 slots_num = (txq_id == trans_pcie->cmd_queue) ?
879 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
880 ret = iwl_pcie_txq_alloc(trans, &trans_pcie->txq[txq_id],
883 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
891 iwl_pcie_tx_free(trans);
895 int iwl_pcie_tx_init(struct iwl_trans *trans)
897 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
899 int txq_id, slots_num;
902 if (!trans_pcie->txq) {
903 ret = iwl_pcie_tx_alloc(trans);
909 spin_lock(&trans_pcie->irq_lock);
911 /* Turn off all Tx DMA fifos */
912 iwl_scd_deactivate_fifos(trans);
914 /* Tell NIC where to find the "keep warm" buffer */
915 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
916 trans_pcie->kw.dma >> 4);
918 spin_unlock(&trans_pcie->irq_lock);
920 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
921 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
923 slots_num = (txq_id == trans_pcie->cmd_queue) ?
924 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
925 ret = iwl_pcie_txq_init(trans, &trans_pcie->txq[txq_id],
928 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
933 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
934 if (trans->cfg->base_params->num_of_queues > 20)
935 iwl_set_bits_prph(trans, SCD_GP_CTRL,
936 SCD_GP_CTRL_ENABLE_31_QUEUES);
940 /*Upon error, free only if we allocated something */
942 iwl_pcie_tx_free(trans);
946 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
948 lockdep_assert_held(&txq->lock);
950 if (!txq->wd_timeout)
954 * station is asleep and we send data - that must
955 * be uAPSD or PS-Poll. Don't rearm the timer.
961 * if empty delete timer, otherwise move timer forward
962 * since we're making progress on this queue
964 if (txq->q.read_ptr == txq->q.write_ptr)
965 del_timer(&txq->stuck_timer);
967 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
970 /* Frees buffers until index _not_ inclusive */
971 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
972 struct sk_buff_head *skbs)
974 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
975 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
976 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
977 struct iwl_queue *q = &txq->q;
980 /* This function is not meant to release cmd queue*/
981 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
984 spin_lock_bh(&txq->lock);
987 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
992 if (txq->q.read_ptr == tfd_num)
995 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
996 txq_id, txq->q.read_ptr, tfd_num, ssn);
998 /*Since we free until index _not_ inclusive, the one before index is
999 * the last we will free. This one must be used */
1000 last_to_free = iwl_queue_dec_wrap(tfd_num);
1002 if (!iwl_queue_used(q, last_to_free)) {
1004 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1005 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1006 q->write_ptr, q->read_ptr);
1010 if (WARN_ON(!skb_queue_empty(skbs)))
1014 q->read_ptr != tfd_num;
1015 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1017 if (WARN_ON_ONCE(txq->entries[txq->q.read_ptr].skb == NULL))
1020 __skb_queue_tail(skbs, txq->entries[txq->q.read_ptr].skb);
1022 txq->entries[txq->q.read_ptr].skb = NULL;
1024 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1026 iwl_pcie_txq_free_tfd(trans, txq);
1029 iwl_pcie_txq_progress(txq);
1031 if (iwl_queue_space(&txq->q) > txq->q.low_mark)
1032 iwl_wake_queue(trans, txq);
1034 if (q->read_ptr == q->write_ptr) {
1035 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", q->id);
1036 iwl_trans_pcie_unref(trans);
1040 spin_unlock_bh(&txq->lock);
1043 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1044 const struct iwl_host_cmd *cmd)
1046 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1049 lockdep_assert_held(&trans_pcie->reg_lock);
1051 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1052 !trans_pcie->ref_cmd_in_flight) {
1053 trans_pcie->ref_cmd_in_flight = true;
1054 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1055 iwl_trans_pcie_ref(trans);
1059 * wake up the NIC to make sure that the firmware will see the host
1060 * command - we will let the NIC sleep once all the host commands
1061 * returned. This needs to be done only on NICs that have
1062 * apmg_wake_up_wa set.
1064 if (trans->cfg->base_params->apmg_wake_up_wa &&
1065 !trans_pcie->cmd_hold_nic_awake) {
1066 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1067 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1069 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1070 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1071 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1072 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1075 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1076 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1077 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1080 trans_pcie->cmd_hold_nic_awake = true;
1086 static int iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
1088 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1090 lockdep_assert_held(&trans_pcie->reg_lock);
1092 if (trans_pcie->ref_cmd_in_flight) {
1093 trans_pcie->ref_cmd_in_flight = false;
1094 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
1095 iwl_trans_pcie_unref(trans);
1098 if (trans->cfg->base_params->apmg_wake_up_wa) {
1099 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
1102 trans_pcie->cmd_hold_nic_awake = false;
1103 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1104 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1110 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1112 * When FW advances 'R' index, all entries between old and new 'R' index
1113 * need to be reclaimed. As result, some free space forms. If there is
1114 * enough free space (> low mark), wake the stack that feeds us.
1116 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1118 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1119 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1120 struct iwl_queue *q = &txq->q;
1121 unsigned long flags;
1124 lockdep_assert_held(&txq->lock);
1126 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(q, idx))) {
1128 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1129 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1130 q->write_ptr, q->read_ptr);
1134 for (idx = iwl_queue_inc_wrap(idx); q->read_ptr != idx;
1135 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr)) {
1138 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1139 idx, q->write_ptr, q->read_ptr);
1140 iwl_force_nmi(trans);
1144 if (q->read_ptr == q->write_ptr) {
1145 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1146 iwl_pcie_clear_cmd_in_flight(trans);
1147 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1150 iwl_pcie_txq_progress(txq);
1153 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1156 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1161 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1163 tbl_dw_addr = trans_pcie->scd_base_addr +
1164 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1166 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1169 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1171 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1173 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1178 /* Receiver address (actually, Rx station's index into station table),
1179 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1180 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1182 void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1183 const struct iwl_trans_txq_scd_cfg *cfg,
1184 unsigned int wdg_timeout)
1186 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1187 struct iwl_txq *txq = &trans_pcie->txq[txq_id];
1190 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1191 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1193 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1198 /* Disable the scheduler prior configuring the cmd queue */
1199 if (txq_id == trans_pcie->cmd_queue &&
1200 trans_pcie->scd_set_active)
1201 iwl_scd_enable_set_active(trans, 0);
1203 /* Stop this Tx queue before configuring it */
1204 iwl_scd_txq_set_inactive(trans, txq_id);
1206 /* Set this queue as a chain-building queue unless it is CMD */
1207 if (txq_id != trans_pcie->cmd_queue)
1208 iwl_scd_txq_set_chain(trans, txq_id);
1210 if (cfg->aggregate) {
1211 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1213 /* Map receiver-address / traffic-ID to this queue */
1214 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1216 /* enable aggregations for the queue */
1217 iwl_scd_txq_enable_agg(trans, txq_id);
1221 * disable aggregations for the queue, this will also
1222 * make the ra_tid mapping configuration irrelevant
1223 * since it is now a non-AGG queue.
1225 iwl_scd_txq_disable_agg(trans, txq_id);
1227 ssn = txq->q.read_ptr;
1231 /* Place first TFD at index corresponding to start sequence number.
1232 * Assumes that ssn_idx is valid (!= 0xFFF) */
1233 txq->q.read_ptr = (ssn & 0xff);
1234 txq->q.write_ptr = (ssn & 0xff);
1235 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1236 (ssn & 0xff) | (txq_id << 8));
1239 u8 frame_limit = cfg->frame_limit;
1241 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1243 /* Set up Tx window size and frame limit for this queue */
1244 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1245 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1246 iwl_trans_write_mem32(trans,
1247 trans_pcie->scd_base_addr +
1248 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1249 ((frame_limit << SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1250 SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1251 ((frame_limit << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1252 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1254 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1255 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1256 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1257 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1258 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1259 SCD_QUEUE_STTS_REG_MSK);
1261 /* enable the scheduler for this queue (only) */
1262 if (txq_id == trans_pcie->cmd_queue &&
1263 trans_pcie->scd_set_active)
1264 iwl_scd_enable_set_active(trans, BIT(txq_id));
1266 IWL_DEBUG_TX_QUEUES(trans,
1267 "Activate queue %d on FIFO %d WrPtr: %d\n",
1268 txq_id, fifo, ssn & 0xff);
1270 IWL_DEBUG_TX_QUEUES(trans,
1271 "Activate queue %d WrPtr: %d\n",
1272 txq_id, ssn & 0xff);
1278 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1281 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1282 u32 stts_addr = trans_pcie->scd_base_addr +
1283 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1284 static const u32 zero_val[4] = {};
1286 trans_pcie->txq[txq_id].frozen_expiry_remainder = 0;
1287 trans_pcie->txq[txq_id].frozen = false;
1290 * Upon HW Rfkill - we stop the device, and then stop the queues
1291 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1292 * allow the op_mode to call txq_disable after it already called
1295 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1296 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1297 "queue %d not used", txq_id);
1301 if (configure_scd) {
1302 iwl_scd_txq_set_inactive(trans, txq_id);
1304 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1305 ARRAY_SIZE(zero_val));
1308 iwl_pcie_txq_unmap(trans, txq_id);
1309 trans_pcie->txq[txq_id].ampdu = false;
1311 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1314 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1317 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1318 * @priv: device private data point
1319 * @cmd: a pointer to the ucode command structure
1321 * The function returns < 0 values to indicate the operation
1322 * failed. On success, it returns the index (>= 0) of command in the
1325 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1326 struct iwl_host_cmd *cmd)
1328 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1329 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1330 struct iwl_queue *q = &txq->q;
1331 struct iwl_device_cmd *out_cmd;
1332 struct iwl_cmd_meta *out_meta;
1333 unsigned long flags;
1334 void *dup_buf = NULL;
1335 dma_addr_t phys_addr;
1337 u16 copy_size, cmd_size, scratch_size;
1338 bool had_nocopy = false;
1339 u8 group_id = iwl_cmd_groupid(cmd->id);
1342 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1343 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1344 unsigned long flags2;
1346 if (WARN(!trans_pcie->wide_cmd_header &&
1347 group_id > IWL_ALWAYS_LONG_GROUP,
1348 "unsupported wide command %#x\n", cmd->id))
1351 if (group_id != 0) {
1352 copy_size = sizeof(struct iwl_cmd_header_wide);
1353 cmd_size = sizeof(struct iwl_cmd_header_wide);
1355 copy_size = sizeof(struct iwl_cmd_header);
1356 cmd_size = sizeof(struct iwl_cmd_header);
1359 /* need one for the header if the first is NOCOPY */
1360 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1362 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1363 cmddata[i] = cmd->data[i];
1364 cmdlen[i] = cmd->len[i];
1369 /* need at least IWL_HCMD_SCRATCHBUF_SIZE copied */
1370 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1371 int copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1373 if (copy > cmdlen[i])
1380 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1382 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1386 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1388 * This is also a chunk that isn't copied
1389 * to the static buffer so set had_nocopy.
1393 /* only allowed once */
1394 if (WARN_ON(dup_buf)) {
1399 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1404 /* NOCOPY must not be followed by normal! */
1405 if (WARN_ON(had_nocopy)) {
1409 copy_size += cmdlen[i];
1411 cmd_size += cmd->len[i];
1415 * If any of the command structures end up being larger than
1416 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1417 * allocated into separate TFDs, then we will need to
1418 * increase the size of the buffers.
1420 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1421 "Command %s (%#x) is too large (%d bytes)\n",
1422 get_cmd_string(trans_pcie, cmd->id), cmd->id, copy_size)) {
1427 spin_lock_irqsave(&txq->lock, flags2);
1429 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1430 spin_unlock_irqrestore(&txq->lock, flags2);
1432 IWL_ERR(trans, "No space in command queue\n");
1433 iwl_op_mode_cmd_queue_full(trans->op_mode);
1438 idx = get_cmd_index(q, q->write_ptr);
1439 out_cmd = txq->entries[idx].cmd;
1440 out_meta = &txq->entries[idx].meta;
1442 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1443 if (cmd->flags & CMD_WANT_SKB)
1444 out_meta->source = cmd;
1446 /* set up the header */
1447 if (group_id != 0) {
1448 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1449 out_cmd->hdr_wide.group_id = group_id;
1450 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1451 out_cmd->hdr_wide.length =
1452 cpu_to_le16(cmd_size -
1453 sizeof(struct iwl_cmd_header_wide));
1454 out_cmd->hdr_wide.reserved = 0;
1455 out_cmd->hdr_wide.sequence =
1456 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1457 INDEX_TO_SEQ(q->write_ptr));
1459 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1460 copy_size = sizeof(struct iwl_cmd_header_wide);
1462 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1463 out_cmd->hdr.sequence =
1464 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1465 INDEX_TO_SEQ(q->write_ptr));
1466 out_cmd->hdr.group_id = 0;
1468 cmd_pos = sizeof(struct iwl_cmd_header);
1469 copy_size = sizeof(struct iwl_cmd_header);
1472 /* and copy the data that needs to be copied */
1473 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1479 /* copy everything if not nocopy/dup */
1480 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1481 IWL_HCMD_DFL_DUP))) {
1484 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1491 * Otherwise we need at least IWL_HCMD_SCRATCHBUF_SIZE copied
1492 * in total (for the scratchbuf handling), but copy up to what
1493 * we can fit into the payload for debug dump purposes.
1495 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1497 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1500 /* However, treat copy_size the proper way, we need it below */
1501 if (copy_size < IWL_HCMD_SCRATCHBUF_SIZE) {
1502 copy = IWL_HCMD_SCRATCHBUF_SIZE - copy_size;
1504 if (copy > cmd->len[i])
1511 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1512 get_cmd_string(trans_pcie, out_cmd->hdr.cmd),
1513 group_id, out_cmd->hdr.cmd,
1514 le16_to_cpu(out_cmd->hdr.sequence),
1515 cmd_size, q->write_ptr, idx, trans_pcie->cmd_queue);
1517 /* start the TFD with the scratchbuf */
1518 scratch_size = min_t(int, copy_size, IWL_HCMD_SCRATCHBUF_SIZE);
1519 memcpy(&txq->scratchbufs[idx], &out_cmd->hdr, scratch_size);
1520 iwl_pcie_txq_build_tfd(trans, txq,
1521 iwl_pcie_get_scratchbuf_dma(txq, idx),
1522 scratch_size, true);
1524 /* map first command fragment, if any remains */
1525 if (copy_size > scratch_size) {
1526 phys_addr = dma_map_single(trans->dev,
1527 ((u8 *)&out_cmd->hdr) + scratch_size,
1528 copy_size - scratch_size,
1530 if (dma_mapping_error(trans->dev, phys_addr)) {
1531 iwl_pcie_tfd_unmap(trans, out_meta,
1532 &txq->tfds[q->write_ptr]);
1537 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1538 copy_size - scratch_size, false);
1541 /* map the remaining (adjusted) nocopy/dup fragments */
1542 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1543 const void *data = cmddata[i];
1547 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1550 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1552 phys_addr = dma_map_single(trans->dev, (void *)data,
1553 cmdlen[i], DMA_TO_DEVICE);
1554 if (dma_mapping_error(trans->dev, phys_addr)) {
1555 iwl_pcie_tfd_unmap(trans, out_meta,
1556 &txq->tfds[q->write_ptr]);
1561 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1564 BUILD_BUG_ON(IWL_NUM_OF_TBS + CMD_TB_BITMAP_POS >
1565 sizeof(out_meta->flags) * BITS_PER_BYTE);
1566 out_meta->flags = cmd->flags;
1567 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1568 kzfree(txq->entries[idx].free_buf);
1569 txq->entries[idx].free_buf = dup_buf;
1571 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1573 /* start timer if queue currently empty */
1574 if (q->read_ptr == q->write_ptr && txq->wd_timeout)
1575 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1577 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1578 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1581 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1585 /* Increment and update queue's write index */
1586 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1587 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1589 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1592 spin_unlock_irqrestore(&txq->lock, flags2);
1600 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1601 * @rxb: Rx buffer to reclaim
1603 * If an Rx buffer has an async callback associated with it the callback
1604 * will be executed. The attached skb (if present) will only be freed
1605 * if the callback returns 1
1607 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1608 struct iwl_rx_cmd_buffer *rxb)
1610 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1611 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1612 int txq_id = SEQ_TO_QUEUE(sequence);
1613 int index = SEQ_TO_INDEX(sequence);
1615 struct iwl_device_cmd *cmd;
1616 struct iwl_cmd_meta *meta;
1617 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1618 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1620 /* If a Tx command is being handled and it isn't in the actual
1621 * command queue then there a command routing bug has been introduced
1622 * in the queue management code. */
1623 if (WARN(txq_id != trans_pcie->cmd_queue,
1624 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1625 txq_id, trans_pcie->cmd_queue, sequence,
1626 trans_pcie->txq[trans_pcie->cmd_queue].q.read_ptr,
1627 trans_pcie->txq[trans_pcie->cmd_queue].q.write_ptr)) {
1628 iwl_print_hex_error(trans, pkt, 32);
1632 spin_lock_bh(&txq->lock);
1634 cmd_index = get_cmd_index(&txq->q, index);
1635 cmd = txq->entries[cmd_index].cmd;
1636 meta = &txq->entries[cmd_index].meta;
1638 iwl_pcie_tfd_unmap(trans, meta, &txq->tfds[index]);
1640 /* Input error checking is done when commands are added to queue. */
1641 if (meta->flags & CMD_WANT_SKB) {
1642 struct page *p = rxb_steal_page(rxb);
1644 meta->source->resp_pkt = pkt;
1645 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1646 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1649 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1651 if (!(meta->flags & CMD_ASYNC)) {
1652 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1654 "HCMD_ACTIVE already clear for command %s\n",
1655 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1657 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1658 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1659 get_cmd_string(trans_pcie, cmd->hdr.cmd));
1660 wake_up(&trans_pcie->wait_command_queue);
1665 spin_unlock_bh(&txq->lock);
1668 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1670 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1671 struct iwl_host_cmd *cmd)
1673 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1676 /* An asynchronous command can not expect an SKB to be set. */
1677 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1680 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1683 "Error sending %s: enqueue_hcmd failed: %d\n",
1684 get_cmd_string(trans_pcie, cmd->id), ret);
1690 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1691 struct iwl_host_cmd *cmd)
1693 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1697 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1698 get_cmd_string(trans_pcie, cmd->id));
1700 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1702 "Command %s: a command is already active!\n",
1703 get_cmd_string(trans_pcie, cmd->id)))
1706 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1707 get_cmd_string(trans_pcie, cmd->id));
1709 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1712 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1714 "Error sending %s: enqueue_hcmd failed: %d\n",
1715 get_cmd_string(trans_pcie, cmd->id), ret);
1719 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1720 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1722 HOST_COMPLETE_TIMEOUT);
1724 struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1725 struct iwl_queue *q = &txq->q;
1727 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1728 get_cmd_string(trans_pcie, cmd->id),
1729 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1731 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1732 q->read_ptr, q->write_ptr);
1734 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1735 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1736 get_cmd_string(trans_pcie, cmd->id));
1739 iwl_force_nmi(trans);
1740 iwl_trans_fw_error(trans);
1745 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1746 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1747 get_cmd_string(trans_pcie, cmd->id));
1753 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1754 test_bit(STATUS_RFKILL, &trans->status)) {
1755 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1760 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1761 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1762 get_cmd_string(trans_pcie, cmd->id));
1770 if (cmd->flags & CMD_WANT_SKB) {
1772 * Cancel the CMD_WANT_SKB flag for the cmd in the
1773 * TX cmd queue. Otherwise in case the cmd comes
1774 * in later, it will possibly set an invalid
1775 * address (cmd->meta.source).
1777 trans_pcie->txq[trans_pcie->cmd_queue].
1778 entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1781 if (cmd->resp_pkt) {
1783 cmd->resp_pkt = NULL;
1789 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1791 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1792 test_bit(STATUS_RFKILL, &trans->status)) {
1793 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1798 if (cmd->flags & CMD_ASYNC)
1799 return iwl_pcie_send_hcmd_async(trans, cmd);
1801 /* We still can fail on RFKILL that can be asserted while we wait */
1802 return iwl_pcie_send_hcmd_sync(trans, cmd);
1805 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
1806 struct iwl_device_cmd *dev_cmd, int txq_id)
1808 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1809 struct ieee80211_hdr *hdr;
1810 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
1811 struct iwl_cmd_meta *out_meta;
1812 struct iwl_txq *txq;
1813 struct iwl_queue *q;
1814 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
1816 u16 len, tb1_len, tb2_len;
1817 bool wait_write_ptr;
1823 txq = &trans_pcie->txq[txq_id];
1826 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
1827 "TX on unused queue %d\n", txq_id))
1830 if (skb_is_nonlinear(skb) &&
1831 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS &&
1832 __skb_linearize(skb))
1835 /* mac80211 always puts the full header into the SKB's head,
1836 * so there's no need to check if it's readable there
1838 hdr = (struct ieee80211_hdr *)skb->data;
1839 fc = hdr->frame_control;
1840 hdr_len = ieee80211_hdrlen(fc);
1842 spin_lock(&txq->lock);
1844 /* In AGG mode, the index in the ring must correspond to the WiFi
1845 * sequence number. This is a HW requirements to help the SCD to parse
1847 * Check here that the packets are in the right place on the ring.
1849 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
1850 WARN_ONCE(txq->ampdu &&
1851 (wifi_seq & 0xff) != q->write_ptr,
1852 "Q: %d WiFi Seq %d tfdNum %d",
1853 txq_id, wifi_seq, q->write_ptr);
1855 /* Set up driver data for this TFD */
1856 txq->entries[q->write_ptr].skb = skb;
1857 txq->entries[q->write_ptr].cmd = dev_cmd;
1859 dev_cmd->hdr.sequence =
1860 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
1861 INDEX_TO_SEQ(q->write_ptr)));
1863 tb0_phys = iwl_pcie_get_scratchbuf_dma(txq, q->write_ptr);
1864 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
1865 offsetof(struct iwl_tx_cmd, scratch);
1867 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
1868 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
1870 /* Set up first empty entry in queue's array of Tx/cmd buffers */
1871 out_meta = &txq->entries[q->write_ptr].meta;
1872 out_meta->flags = 0;
1875 * The second TB (tb1) points to the remainder of the TX command
1876 * and the 802.11 header - dword aligned size
1877 * (This calculation modifies the TX command, so do it before the
1878 * setup of the first TB)
1880 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
1881 hdr_len - IWL_HCMD_SCRATCHBUF_SIZE;
1882 tb1_len = ALIGN(len, 4);
1884 /* Tell NIC about any 2-byte padding after MAC header */
1886 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
1888 /* The first TB points to the scratchbuf data - min_copy bytes */
1889 memcpy(&txq->scratchbufs[q->write_ptr], &dev_cmd->hdr,
1890 IWL_HCMD_SCRATCHBUF_SIZE);
1891 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
1892 IWL_HCMD_SCRATCHBUF_SIZE, true);
1894 /* there must be data left over for TB1 or this code must be changed */
1895 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_HCMD_SCRATCHBUF_SIZE);
1897 /* map the data for TB1 */
1898 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_HCMD_SCRATCHBUF_SIZE;
1899 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
1900 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
1902 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
1905 * Set up TFD's third entry to point directly to remainder
1906 * of skb's head, if any
1908 tb2_len = skb_headlen(skb) - hdr_len;
1910 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1911 skb->data + hdr_len,
1912 tb2_len, DMA_TO_DEVICE);
1913 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1914 iwl_pcie_tfd_unmap(trans, out_meta,
1915 &txq->tfds[q->write_ptr]);
1918 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1921 /* set up the remaining entries to point to the data */
1922 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1923 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1927 if (!skb_frag_size(frag))
1930 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1931 skb_frag_size(frag), DMA_TO_DEVICE);
1933 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1934 iwl_pcie_tfd_unmap(trans, out_meta,
1935 &txq->tfds[q->write_ptr]);
1938 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
1939 skb_frag_size(frag), false);
1941 out_meta->flags |= BIT(tb_idx + CMD_TB_BITMAP_POS);
1944 /* Set up entry for this TFD in Tx byte-count array */
1945 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len));
1947 trace_iwlwifi_dev_tx(trans->dev, skb,
1948 &txq->tfds[txq->q.write_ptr],
1949 sizeof(struct iwl_tfd),
1950 &dev_cmd->hdr, IWL_HCMD_SCRATCHBUF_SIZE + tb1_len,
1951 skb->data + hdr_len, tb2_len);
1952 trace_iwlwifi_dev_tx_data(trans->dev, skb,
1953 hdr_len, skb->len - hdr_len);
1955 wait_write_ptr = ieee80211_has_morefrags(fc);
1957 /* start timer if queue currently empty */
1958 if (q->read_ptr == q->write_ptr) {
1959 if (txq->wd_timeout) {
1961 * If the TXQ is active, then set the timer, if not,
1962 * set the timer in remainder so that the timer will
1963 * be armed with the right value when the station will
1967 mod_timer(&txq->stuck_timer,
1968 jiffies + txq->wd_timeout);
1970 txq->frozen_expiry_remainder = txq->wd_timeout;
1972 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", q->id);
1973 iwl_trans_pcie_ref(trans);
1976 /* Tell device the write index *just past* this latest filled TFD */
1977 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr);
1978 if (!wait_write_ptr)
1979 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1982 * At this point the frame is "transmitted" successfully
1983 * and we will get a TX status notification eventually.
1985 if (iwl_queue_space(q) < q->high_mark) {
1987 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1989 iwl_stop_queue(trans, txq);
1991 spin_unlock(&txq->lock);
1994 spin_unlock(&txq->lock);