1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
7 * Portions of this file are derived from the ipw3945 project, as well
8 * as portions of the ieee80211 subsystem header files.
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program; if not, write to the Free Software Foundation, Inc.,
21 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *****************************************************************************/
31 #include <linux/etherdevice.h>
32 #include <linux/ieee80211.h>
33 #include <linux/slab.h>
34 #include <linux/sched.h>
35 #include <linux/pm_runtime.h>
36 #include <net/ip6_checksum.h>
39 #include "iwl-debug.h"
44 #include "iwl-op-mode.h"
46 #include "fw/api/tx.h"
48 #define IWL_TX_CRC_SIZE 4
49 #define IWL_TX_DELIMITER_SIZE 4
51 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
56 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
57 * of buffer descriptors, each of which points to one or more data buffers for
58 * the device to read from or fill. Driver and device exchange status of each
59 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
60 * entries in each circular buffer, to protect against confusing empty and full
63 * The device reads or writes the data in the queues via the device's several
64 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
66 * For Tx queue, there are low mark and high mark limits. If, after queuing
67 * the packet for Tx, free space become < low mark, Tx queue stopped. When
68 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
71 ***************************************************/
73 int iwl_queue_space(const struct iwl_txq *q)
79 * To avoid ambiguity between empty and completely full queues, there
80 * should always be less than TFD_QUEUE_SIZE_MAX elements in the queue.
81 * If q->n_window is smaller than TFD_QUEUE_SIZE_MAX, there is no need
82 * to reserve any queue entries for this purpose.
84 if (q->n_window < TFD_QUEUE_SIZE_MAX)
87 max = TFD_QUEUE_SIZE_MAX - 1;
90 * TFD_QUEUE_SIZE_MAX is a power of 2, so the following is equivalent to
91 * modulo by TFD_QUEUE_SIZE_MAX and is well defined.
93 used = (q->write_ptr - q->read_ptr) & (TFD_QUEUE_SIZE_MAX - 1);
95 if (WARN_ON(used > max))
102 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
104 static int iwl_queue_init(struct iwl_txq *q, int slots_num)
106 q->n_window = slots_num;
108 /* slots_num must be power-of-two size, otherwise
109 * iwl_pcie_get_cmd_index is broken. */
110 if (WARN_ON(!is_power_of_2(slots_num)))
113 q->low_mark = q->n_window / 4;
117 q->high_mark = q->n_window / 8;
118 if (q->high_mark < 2)
127 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans,
128 struct iwl_dma_ptr *ptr, size_t size)
130 if (WARN_ON(ptr->addr))
133 ptr->addr = dma_alloc_coherent(trans->dev, size,
134 &ptr->dma, GFP_KERNEL);
141 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr)
143 if (unlikely(!ptr->addr))
146 dma_free_coherent(trans->dev, ptr->size, ptr->addr, ptr->dma);
147 memset(ptr, 0, sizeof(*ptr));
150 static void iwl_pcie_txq_stuck_timer(unsigned long data)
152 struct iwl_txq *txq = (void *)data;
153 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
154 struct iwl_trans *trans = iwl_trans_pcie_get_trans(trans_pcie);
156 spin_lock(&txq->lock);
157 /* check if triggered erroneously */
158 if (txq->read_ptr == txq->write_ptr) {
159 spin_unlock(&txq->lock);
162 spin_unlock(&txq->lock);
164 iwl_trans_pcie_log_scd_error(trans, txq);
166 iwl_force_nmi(trans);
170 * iwl_pcie_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
172 static void iwl_pcie_txq_update_byte_cnt_tbl(struct iwl_trans *trans,
173 struct iwl_txq *txq, u16 byte_cnt,
176 struct iwlagn_scd_bc_tbl *scd_bc_tbl;
177 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
178 int write_ptr = txq->write_ptr;
179 int txq_id = txq->id;
181 u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
183 struct iwl_tx_cmd *tx_cmd =
184 (void *)txq->entries[txq->write_ptr].cmd->payload;
185 u8 sta_id = tx_cmd->sta_id;
187 scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
189 sec_ctl = tx_cmd->sec_ctl;
191 switch (sec_ctl & TX_CMD_SEC_MSK) {
193 len += IEEE80211_CCMP_MIC_LEN;
195 case TX_CMD_SEC_TKIP:
196 len += IEEE80211_TKIP_ICV_LEN;
199 len += IEEE80211_WEP_IV_LEN + IEEE80211_WEP_ICV_LEN;
202 if (trans_pcie->bc_table_dword)
203 len = DIV_ROUND_UP(len, 4);
205 if (WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX))
208 bc_ent = cpu_to_le16(len | (sta_id << 12));
210 scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
212 if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
214 tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
217 static void iwl_pcie_txq_inval_byte_cnt_tbl(struct iwl_trans *trans,
220 struct iwl_trans_pcie *trans_pcie =
221 IWL_TRANS_GET_PCIE_TRANS(trans);
222 struct iwlagn_scd_bc_tbl *scd_bc_tbl = trans_pcie->scd_bc_tbls.addr;
223 int txq_id = txq->id;
224 int read_ptr = txq->read_ptr;
227 struct iwl_tx_cmd *tx_cmd =
228 (void *)txq->entries[read_ptr].cmd->payload;
230 WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
232 if (txq_id != trans_pcie->cmd_queue)
233 sta_id = tx_cmd->sta_id;
235 bc_ent = cpu_to_le16(1 | (sta_id << 12));
237 scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
239 if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
241 tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
245 * iwl_pcie_txq_inc_wr_ptr - Send new write index to hardware
247 static void iwl_pcie_txq_inc_wr_ptr(struct iwl_trans *trans,
250 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
252 int txq_id = txq->id;
254 lockdep_assert_held(&txq->lock);
257 * explicitly wake up the NIC if:
258 * 1. shadow registers aren't enabled
259 * 2. NIC is woken up for CMD regardless of shadow outside this function
260 * 3. there is a chance that the NIC is asleep
262 if (!trans->cfg->base_params->shadow_reg_enable &&
263 txq_id != trans_pcie->cmd_queue &&
264 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
266 * wake up nic if it's powered down ...
267 * uCode will wake up, and interrupt us again, so next
268 * time we'll skip this part.
270 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
272 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
273 IWL_DEBUG_INFO(trans, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
275 iwl_set_bit(trans, CSR_GP_CNTRL,
276 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
277 txq->need_update = true;
283 * if not in power-save mode, uCode will never sleep when we're
284 * trying to tx (during RFKILL, we're not trying to tx).
286 IWL_DEBUG_TX(trans, "Q:%d WR: 0x%x\n", txq_id, txq->write_ptr);
288 iwl_write32(trans, HBUS_TARG_WRPTR,
289 txq->write_ptr | (txq_id << 8));
292 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans)
294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
297 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
298 struct iwl_txq *txq = trans_pcie->txq[i];
300 if (!test_bit(i, trans_pcie->queue_used))
303 spin_lock_bh(&txq->lock);
304 if (txq->need_update) {
305 iwl_pcie_txq_inc_wr_ptr(trans, txq);
306 txq->need_update = false;
308 spin_unlock_bh(&txq->lock);
312 static inline dma_addr_t iwl_pcie_tfd_tb_get_addr(struct iwl_trans *trans,
316 if (trans->cfg->use_tfh) {
317 struct iwl_tfh_tfd *tfd = _tfd;
318 struct iwl_tfh_tb *tb = &tfd->tbs[idx];
320 return (dma_addr_t)(le64_to_cpu(tb->addr));
322 struct iwl_tfd *tfd = _tfd;
323 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
324 dma_addr_t addr = get_unaligned_le32(&tb->lo);
327 if (sizeof(dma_addr_t) <= sizeof(u32))
330 hi_len = le16_to_cpu(tb->hi_n_len) & 0xF;
333 * shift by 16 twice to avoid warnings on 32-bit
334 * (where this code never runs anyway due to the
335 * if statement above)
337 return addr | ((hi_len << 16) << 16);
341 static inline void iwl_pcie_tfd_set_tb(struct iwl_trans *trans, void *tfd,
342 u8 idx, dma_addr_t addr, u16 len)
344 struct iwl_tfd *tfd_fh = (void *)tfd;
345 struct iwl_tfd_tb *tb = &tfd_fh->tbs[idx];
347 u16 hi_n_len = len << 4;
349 put_unaligned_le32(addr, &tb->lo);
350 hi_n_len |= iwl_get_dma_hi_addr(addr);
352 tb->hi_n_len = cpu_to_le16(hi_n_len);
354 tfd_fh->num_tbs = idx + 1;
357 static inline u8 iwl_pcie_tfd_get_num_tbs(struct iwl_trans *trans, void *_tfd)
359 if (trans->cfg->use_tfh) {
360 struct iwl_tfh_tfd *tfd = _tfd;
362 return le16_to_cpu(tfd->num_tbs) & 0x1f;
364 struct iwl_tfd *tfd = _tfd;
366 return tfd->num_tbs & 0x1f;
370 static void iwl_pcie_tfd_unmap(struct iwl_trans *trans,
371 struct iwl_cmd_meta *meta,
372 struct iwl_txq *txq, int index)
374 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
376 void *tfd = iwl_pcie_get_tfd(trans, txq, index);
378 /* Sanity check on number of chunks */
379 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
381 if (num_tbs >= trans_pcie->max_tbs) {
382 IWL_ERR(trans, "Too many chunks: %i\n", num_tbs);
383 /* @todo issue fatal error, it is quite serious situation */
387 /* first TB is never freed - it's the bidirectional DMA data */
389 for (i = 1; i < num_tbs; i++) {
390 if (meta->tbs & BIT(i))
391 dma_unmap_page(trans->dev,
392 iwl_pcie_tfd_tb_get_addr(trans, tfd, i),
393 iwl_pcie_tfd_tb_get_len(trans, tfd, i),
396 dma_unmap_single(trans->dev,
397 iwl_pcie_tfd_tb_get_addr(trans, tfd,
399 iwl_pcie_tfd_tb_get_len(trans, tfd,
406 if (trans->cfg->use_tfh) {
407 struct iwl_tfh_tfd *tfd_fh = (void *)tfd;
411 struct iwl_tfd *tfd_fh = (void *)tfd;
419 * iwl_pcie_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
420 * @trans - transport private data
422 * @dma_dir - the direction of the DMA mapping
424 * Does NOT advance any TFD circular buffer read/write indexes
425 * Does NOT free the TFD itself (which is within circular buffer)
427 void iwl_pcie_txq_free_tfd(struct iwl_trans *trans, struct iwl_txq *txq)
429 /* rd_ptr is bounded by TFD_QUEUE_SIZE_MAX and
430 * idx is bounded by n_window
432 int rd_ptr = txq->read_ptr;
433 int idx = iwl_pcie_get_cmd_index(txq, rd_ptr);
435 lockdep_assert_held(&txq->lock);
437 /* We have only q->n_window txq->entries, but we use
438 * TFD_QUEUE_SIZE_MAX tfds
440 iwl_pcie_tfd_unmap(trans, &txq->entries[idx].meta, txq, rd_ptr);
446 skb = txq->entries[idx].skb;
448 /* Can be called from irqs-disabled context
449 * If skb is not NULL, it means that the whole queue is being
450 * freed and that the queue is not empty - free the skb
453 iwl_op_mode_free_skb(trans->op_mode, skb);
454 txq->entries[idx].skb = NULL;
459 static int iwl_pcie_txq_build_tfd(struct iwl_trans *trans, struct iwl_txq *txq,
460 dma_addr_t addr, u16 len, bool reset)
462 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
466 tfd = txq->tfds + trans_pcie->tfd_size * txq->write_ptr;
469 memset(tfd, 0, trans_pcie->tfd_size);
471 num_tbs = iwl_pcie_tfd_get_num_tbs(trans, tfd);
473 /* Each TFD can point to a maximum max_tbs Tx buffers */
474 if (num_tbs >= trans_pcie->max_tbs) {
475 IWL_ERR(trans, "Error can not send more than %d chunks\n",
476 trans_pcie->max_tbs);
480 if (WARN(addr & ~IWL_TX_DMA_MASK,
481 "Unaligned address = %llx\n", (unsigned long long)addr))
484 iwl_pcie_tfd_set_tb(trans, tfd, num_tbs, addr, len);
489 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq,
490 int slots_num, bool cmd_queue)
492 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
493 size_t tfd_sz = trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX;
497 if (WARN_ON(txq->entries || txq->tfds))
500 setup_timer(&txq->stuck_timer, iwl_pcie_txq_stuck_timer,
502 txq->trans_pcie = trans_pcie;
504 txq->n_window = slots_num;
506 txq->entries = kcalloc(slots_num,
507 sizeof(struct iwl_pcie_txq_entry),
514 for (i = 0; i < slots_num; i++) {
515 txq->entries[i].cmd =
516 kmalloc(sizeof(struct iwl_device_cmd),
518 if (!txq->entries[i].cmd)
522 /* Circular buffer of transmit frame descriptors (TFDs),
523 * shared with device */
524 txq->tfds = dma_alloc_coherent(trans->dev, tfd_sz,
525 &txq->dma_addr, GFP_KERNEL);
529 BUILD_BUG_ON(IWL_FIRST_TB_SIZE_ALIGN != sizeof(*txq->first_tb_bufs));
531 tb0_buf_sz = sizeof(*txq->first_tb_bufs) * slots_num;
533 txq->first_tb_bufs = dma_alloc_coherent(trans->dev, tb0_buf_sz,
536 if (!txq->first_tb_bufs)
541 dma_free_coherent(trans->dev, tfd_sz, txq->tfds, txq->dma_addr);
543 if (txq->entries && cmd_queue)
544 for (i = 0; i < slots_num; i++)
545 kfree(txq->entries[i].cmd);
553 int iwl_pcie_txq_init(struct iwl_trans *trans, struct iwl_txq *txq,
554 int slots_num, bool cmd_queue)
558 txq->need_update = false;
560 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
561 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
562 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
564 /* Initialize queue's high/low-water marks, and head/tail indexes */
565 ret = iwl_queue_init(txq, slots_num);
569 spin_lock_init(&txq->lock);
572 static struct lock_class_key iwl_pcie_cmd_queue_lock_class;
574 lockdep_set_class(&txq->lock, &iwl_pcie_cmd_queue_lock_class);
577 __skb_queue_head_init(&txq->overflow_q);
582 void iwl_pcie_free_tso_page(struct iwl_trans_pcie *trans_pcie,
585 struct page **page_ptr;
587 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
590 __free_page(*page_ptr);
595 static void iwl_pcie_clear_cmd_in_flight(struct iwl_trans *trans)
597 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
599 lockdep_assert_held(&trans_pcie->reg_lock);
601 if (trans_pcie->ref_cmd_in_flight) {
602 trans_pcie->ref_cmd_in_flight = false;
603 IWL_DEBUG_RPM(trans, "clear ref_cmd_in_flight - unref\n");
604 iwl_trans_unref(trans);
607 if (!trans->cfg->base_params->apmg_wake_up_wa)
609 if (WARN_ON(!trans_pcie->cmd_hold_nic_awake))
612 trans_pcie->cmd_hold_nic_awake = false;
613 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
614 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
618 * iwl_pcie_txq_unmap - Unmap any remaining DMA mappings and free skb's
620 static void iwl_pcie_txq_unmap(struct iwl_trans *trans, int txq_id)
622 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
623 struct iwl_txq *txq = trans_pcie->txq[txq_id];
626 IWL_ERR(trans, "Trying to free a queue that wasn't allocated?\n");
630 spin_lock_bh(&txq->lock);
631 while (txq->write_ptr != txq->read_ptr) {
632 IWL_DEBUG_TX_REPLY(trans, "Q %d Free %d\n",
633 txq_id, txq->read_ptr);
635 if (txq_id != trans_pcie->cmd_queue) {
636 struct sk_buff *skb = txq->entries[txq->read_ptr].skb;
638 if (WARN_ON_ONCE(!skb))
641 iwl_pcie_free_tso_page(trans_pcie, skb);
643 iwl_pcie_txq_free_tfd(trans, txq);
644 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr);
646 if (txq->read_ptr == txq->write_ptr) {
649 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
650 if (txq_id != trans_pcie->cmd_queue) {
651 IWL_DEBUG_RPM(trans, "Q %d - last tx freed\n",
653 iwl_trans_unref(trans);
655 iwl_pcie_clear_cmd_in_flight(trans);
657 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
661 while (!skb_queue_empty(&txq->overflow_q)) {
662 struct sk_buff *skb = __skb_dequeue(&txq->overflow_q);
664 iwl_op_mode_free_skb(trans->op_mode, skb);
667 spin_unlock_bh(&txq->lock);
669 /* just in case - this queue may have been stopped */
670 iwl_wake_queue(trans, txq);
674 * iwl_pcie_txq_free - Deallocate DMA queue.
675 * @txq: Transmit queue to deallocate.
677 * Empty queue by removing and destroying all BD's.
679 * 0-fill, but do not free "txq" descriptor structure.
681 static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
683 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
684 struct iwl_txq *txq = trans_pcie->txq[txq_id];
685 struct device *dev = trans->dev;
691 iwl_pcie_txq_unmap(trans, txq_id);
693 /* De-alloc array of command/tx buffers */
694 if (txq_id == trans_pcie->cmd_queue)
695 for (i = 0; i < txq->n_window; i++) {
696 kzfree(txq->entries[i].cmd);
697 kzfree(txq->entries[i].free_buf);
700 /* De-alloc circular buffer of TFDs */
702 dma_free_coherent(dev,
703 trans_pcie->tfd_size * TFD_QUEUE_SIZE_MAX,
704 txq->tfds, txq->dma_addr);
708 dma_free_coherent(dev,
709 sizeof(*txq->first_tb_bufs) * txq->n_window,
710 txq->first_tb_bufs, txq->first_tb_dma);
716 del_timer_sync(&txq->stuck_timer);
718 /* 0-fill queue descriptor structure */
719 memset(txq, 0, sizeof(*txq));
722 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
724 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
725 int nq = trans->cfg->base_params->num_of_queues;
728 int clear_dwords = (SCD_TRANS_TBL_OFFSET_QUEUE(nq) -
729 SCD_CONTEXT_MEM_LOWER_BOUND) / sizeof(u32);
731 /* make sure all queue are not stopped/used */
732 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
733 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
735 trans_pcie->scd_base_addr =
736 iwl_read_prph(trans, SCD_SRAM_BASE_ADDR);
738 WARN_ON(scd_base_addr != 0 &&
739 scd_base_addr != trans_pcie->scd_base_addr);
741 /* reset context data, TX status and translation data */
742 iwl_trans_write_mem(trans, trans_pcie->scd_base_addr +
743 SCD_CONTEXT_MEM_LOWER_BOUND,
746 iwl_write_prph(trans, SCD_DRAM_BASE_ADDR,
747 trans_pcie->scd_bc_tbls.dma >> 10);
749 /* The chain extension of the SCD doesn't work well. This feature is
750 * enabled by default by the HW, so we need to disable it manually.
752 if (trans->cfg->base_params->scd_chain_ext_wa)
753 iwl_write_prph(trans, SCD_CHAINEXT_EN, 0);
755 iwl_trans_ac_txq_enable(trans, trans_pcie->cmd_queue,
756 trans_pcie->cmd_fifo,
757 trans_pcie->cmd_q_wdg_timeout);
759 /* Activate all Tx DMA/FIFO channels */
760 iwl_scd_activate_fifos(trans);
762 /* Enable DMA channel */
763 for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
764 iwl_write_direct32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
765 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
766 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
768 /* Update FH chicken bits */
769 reg_val = iwl_read_direct32(trans, FH_TX_CHICKEN_BITS_REG);
770 iwl_write_direct32(trans, FH_TX_CHICKEN_BITS_REG,
771 reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
773 /* Enable L1-Active */
774 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
775 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
776 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
779 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans)
781 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
785 * we should never get here in gen2 trans mode return early to avoid
786 * having invalid accesses
788 if (WARN_ON_ONCE(trans->cfg->gen2))
791 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
793 struct iwl_txq *txq = trans_pcie->txq[txq_id];
794 if (trans->cfg->use_tfh)
795 iwl_write_direct64(trans,
796 FH_MEM_CBBC_QUEUE(trans, txq_id),
799 iwl_write_direct32(trans,
800 FH_MEM_CBBC_QUEUE(trans, txq_id),
802 iwl_pcie_txq_unmap(trans, txq_id);
807 /* Tell NIC where to find the "keep warm" buffer */
808 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
809 trans_pcie->kw.dma >> 4);
812 * Send 0 as the scd_base_addr since the device may have be reset
813 * while we were in WoWLAN in which case SCD_SRAM_BASE_ADDR will
816 iwl_pcie_tx_start(trans, 0);
819 static void iwl_pcie_tx_stop_fh(struct iwl_trans *trans)
821 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
826 spin_lock(&trans_pcie->irq_lock);
828 if (!iwl_trans_grab_nic_access(trans, &flags))
831 /* Stop each Tx DMA channel */
832 for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
833 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
834 mask |= FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch);
837 /* Wait for DMA channels to be idle */
838 ret = iwl_poll_bit(trans, FH_TSSR_TX_STATUS_REG, mask, mask, 5000);
841 "Failing on timeout while stopping DMA channel %d [0x%08x]\n",
842 ch, iwl_read32(trans, FH_TSSR_TX_STATUS_REG));
844 iwl_trans_release_nic_access(trans, &flags);
847 spin_unlock(&trans_pcie->irq_lock);
851 * iwl_pcie_tx_stop - Stop all Tx DMA channels
853 int iwl_pcie_tx_stop(struct iwl_trans *trans)
855 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
858 /* Turn off all Tx DMA fifos */
859 iwl_scd_deactivate_fifos(trans);
861 /* Turn off all Tx DMA channels */
862 iwl_pcie_tx_stop_fh(trans);
865 * This function can be called before the op_mode disabled the
866 * queues. This happens when we have an rfkill interrupt.
867 * Since we stop Tx altogether - mark the queues as stopped.
869 memset(trans_pcie->queue_stopped, 0, sizeof(trans_pcie->queue_stopped));
870 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
872 /* This can happen: start_hw, stop_device */
873 if (!trans_pcie->txq_memory)
876 /* Unmap DMA from host system and free skb's */
877 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
879 iwl_pcie_txq_unmap(trans, txq_id);
885 * iwl_trans_tx_free - Free TXQ Context
887 * Destroy all TX DMA queues and structures
889 void iwl_pcie_tx_free(struct iwl_trans *trans)
892 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
894 memset(trans_pcie->queue_used, 0, sizeof(trans_pcie->queue_used));
897 if (trans_pcie->txq_memory) {
899 txq_id < trans->cfg->base_params->num_of_queues;
901 iwl_pcie_txq_free(trans, txq_id);
902 trans_pcie->txq[txq_id] = NULL;
906 kfree(trans_pcie->txq_memory);
907 trans_pcie->txq_memory = NULL;
909 iwl_pcie_free_dma_ptr(trans, &trans_pcie->kw);
911 iwl_pcie_free_dma_ptr(trans, &trans_pcie->scd_bc_tbls);
915 * iwl_pcie_tx_alloc - allocate TX context
916 * Allocate all Tx DMA structures and initialize them
918 static int iwl_pcie_tx_alloc(struct iwl_trans *trans)
921 int txq_id, slots_num;
922 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
924 u16 scd_bc_tbls_size = trans->cfg->base_params->num_of_queues *
925 sizeof(struct iwlagn_scd_bc_tbl);
927 /*It is not allowed to alloc twice, so warn when this happens.
928 * We cannot rely on the previous allocation, so free and fail */
929 if (WARN_ON(trans_pcie->txq_memory)) {
934 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->scd_bc_tbls,
937 IWL_ERR(trans, "Scheduler BC Table allocation failed\n");
941 /* Alloc keep-warm buffer */
942 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->kw, IWL_KW_SIZE);
944 IWL_ERR(trans, "Keep Warm allocation failed\n");
948 trans_pcie->txq_memory = kcalloc(trans->cfg->base_params->num_of_queues,
949 sizeof(struct iwl_txq), GFP_KERNEL);
950 if (!trans_pcie->txq_memory) {
951 IWL_ERR(trans, "Not enough memory for txq\n");
956 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
957 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
959 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
961 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
962 trans_pcie->txq[txq_id] = &trans_pcie->txq_memory[txq_id];
963 ret = iwl_pcie_txq_alloc(trans, trans_pcie->txq[txq_id],
964 slots_num, cmd_queue);
966 IWL_ERR(trans, "Tx %d queue alloc failed\n", txq_id);
969 trans_pcie->txq[txq_id]->id = txq_id;
975 iwl_pcie_tx_free(trans);
980 int iwl_pcie_tx_init(struct iwl_trans *trans)
982 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
984 int txq_id, slots_num;
987 if (!trans_pcie->txq_memory) {
988 ret = iwl_pcie_tx_alloc(trans);
994 spin_lock(&trans_pcie->irq_lock);
996 /* Turn off all Tx DMA fifos */
997 iwl_scd_deactivate_fifos(trans);
999 /* Tell NIC where to find the "keep warm" buffer */
1000 iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
1001 trans_pcie->kw.dma >> 4);
1003 spin_unlock(&trans_pcie->irq_lock);
1005 /* Alloc and init all Tx queues, including the command queue (#4/#9) */
1006 for (txq_id = 0; txq_id < trans->cfg->base_params->num_of_queues;
1008 bool cmd_queue = (txq_id == trans_pcie->cmd_queue);
1010 slots_num = cmd_queue ? TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1011 ret = iwl_pcie_txq_init(trans, trans_pcie->txq[txq_id],
1012 slots_num, cmd_queue);
1014 IWL_ERR(trans, "Tx %d queue init failed\n", txq_id);
1019 * Tell nic where to find circular buffer of TFDs for a
1020 * given Tx queue, and enable the DMA channel used for that
1022 * Circular buffer (TFD queue in DRAM) physical base address
1024 iwl_write_direct32(trans, FH_MEM_CBBC_QUEUE(trans, txq_id),
1025 trans_pcie->txq[txq_id]->dma_addr >> 8);
1028 iwl_set_bits_prph(trans, SCD_GP_CTRL, SCD_GP_CTRL_AUTO_ACTIVE_MODE);
1029 if (trans->cfg->base_params->num_of_queues > 20)
1030 iwl_set_bits_prph(trans, SCD_GP_CTRL,
1031 SCD_GP_CTRL_ENABLE_31_QUEUES);
1035 /*Upon error, free only if we allocated something */
1037 iwl_pcie_tx_free(trans);
1041 static inline void iwl_pcie_txq_progress(struct iwl_txq *txq)
1043 lockdep_assert_held(&txq->lock);
1045 if (!txq->wd_timeout)
1049 * station is asleep and we send data - that must
1050 * be uAPSD or PS-Poll. Don't rearm the timer.
1056 * if empty delete timer, otherwise move timer forward
1057 * since we're making progress on this queue
1059 if (txq->read_ptr == txq->write_ptr)
1060 del_timer(&txq->stuck_timer);
1062 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1065 /* Frees buffers until index _not_ inclusive */
1066 void iwl_trans_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn,
1067 struct sk_buff_head *skbs)
1069 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1070 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1071 int tfd_num = ssn & (TFD_QUEUE_SIZE_MAX - 1);
1074 /* This function is not meant to release cmd queue*/
1075 if (WARN_ON(txq_id == trans_pcie->cmd_queue))
1078 spin_lock_bh(&txq->lock);
1080 if (!test_bit(txq_id, trans_pcie->queue_used)) {
1081 IWL_DEBUG_TX_QUEUES(trans, "Q %d inactive - ignoring idx %d\n",
1086 if (txq->read_ptr == tfd_num)
1089 IWL_DEBUG_TX_REPLY(trans, "[Q %d] %d -> %d (%d)\n",
1090 txq_id, txq->read_ptr, tfd_num, ssn);
1092 /*Since we free until index _not_ inclusive, the one before index is
1093 * the last we will free. This one must be used */
1094 last_to_free = iwl_queue_dec_wrap(tfd_num);
1096 if (!iwl_queue_used(txq, last_to_free)) {
1098 "%s: Read index for DMA queue txq id (%d), last_to_free %d is out of range [0-%d] %d %d.\n",
1099 __func__, txq_id, last_to_free, TFD_QUEUE_SIZE_MAX,
1100 txq->write_ptr, txq->read_ptr);
1104 if (WARN_ON(!skb_queue_empty(skbs)))
1108 txq->read_ptr != tfd_num;
1109 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1110 int idx = iwl_pcie_get_cmd_index(txq, txq->read_ptr);
1111 struct sk_buff *skb = txq->entries[idx].skb;
1113 if (WARN_ON_ONCE(!skb))
1116 iwl_pcie_free_tso_page(trans_pcie, skb);
1118 __skb_queue_tail(skbs, skb);
1120 txq->entries[idx].skb = NULL;
1122 if (!trans->cfg->use_tfh)
1123 iwl_pcie_txq_inval_byte_cnt_tbl(trans, txq);
1125 iwl_pcie_txq_free_tfd(trans, txq);
1128 iwl_pcie_txq_progress(txq);
1130 if (iwl_queue_space(txq) > txq->low_mark &&
1131 test_bit(txq_id, trans_pcie->queue_stopped)) {
1132 struct sk_buff_head overflow_skbs;
1134 __skb_queue_head_init(&overflow_skbs);
1135 skb_queue_splice_init(&txq->overflow_q, &overflow_skbs);
1138 * This is tricky: we are in reclaim path which is non
1139 * re-entrant, so noone will try to take the access the
1140 * txq data from that path. We stopped tx, so we can't
1141 * have tx as well. Bottom line, we can unlock and re-lock
1144 spin_unlock_bh(&txq->lock);
1146 while (!skb_queue_empty(&overflow_skbs)) {
1147 struct sk_buff *skb = __skb_dequeue(&overflow_skbs);
1148 struct iwl_device_cmd *dev_cmd_ptr;
1150 dev_cmd_ptr = *(void **)((u8 *)skb->cb +
1151 trans_pcie->dev_cmd_offs);
1154 * Note that we can very well be overflowing again.
1155 * In that case, iwl_queue_space will be small again
1156 * and we won't wake mac80211's queue.
1158 iwl_trans_pcie_tx(trans, skb, dev_cmd_ptr, txq_id);
1160 spin_lock_bh(&txq->lock);
1162 if (iwl_queue_space(txq) > txq->low_mark)
1163 iwl_wake_queue(trans, txq);
1166 if (txq->read_ptr == txq->write_ptr) {
1167 IWL_DEBUG_RPM(trans, "Q %d - last tx reclaimed\n", txq->id);
1168 iwl_trans_unref(trans);
1172 spin_unlock_bh(&txq->lock);
1175 static int iwl_pcie_set_cmd_in_flight(struct iwl_trans *trans,
1176 const struct iwl_host_cmd *cmd)
1178 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1181 lockdep_assert_held(&trans_pcie->reg_lock);
1183 if (!(cmd->flags & CMD_SEND_IN_IDLE) &&
1184 !trans_pcie->ref_cmd_in_flight) {
1185 trans_pcie->ref_cmd_in_flight = true;
1186 IWL_DEBUG_RPM(trans, "set ref_cmd_in_flight - ref\n");
1187 iwl_trans_ref(trans);
1191 * wake up the NIC to make sure that the firmware will see the host
1192 * command - we will let the NIC sleep once all the host commands
1193 * returned. This needs to be done only on NICs that have
1194 * apmg_wake_up_wa set.
1196 if (trans->cfg->base_params->apmg_wake_up_wa &&
1197 !trans_pcie->cmd_hold_nic_awake) {
1198 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1199 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1201 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1202 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1203 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1204 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
1207 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1208 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1209 IWL_ERR(trans, "Failed to wake NIC for hcmd\n");
1212 trans_pcie->cmd_hold_nic_awake = true;
1219 * iwl_pcie_cmdq_reclaim - Reclaim TX command queue entries already Tx'd
1221 * When FW advances 'R' index, all entries between old and new 'R' index
1222 * need to be reclaimed. As result, some free space forms. If there is
1223 * enough free space (> low mark), wake the stack that feeds us.
1225 static void iwl_pcie_cmdq_reclaim(struct iwl_trans *trans, int txq_id, int idx)
1227 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1228 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1229 unsigned long flags;
1232 lockdep_assert_held(&txq->lock);
1234 if ((idx >= TFD_QUEUE_SIZE_MAX) || (!iwl_queue_used(txq, idx))) {
1236 "%s: Read index for DMA queue txq id (%d), index %d is out of range [0-%d] %d %d.\n",
1237 __func__, txq_id, idx, TFD_QUEUE_SIZE_MAX,
1238 txq->write_ptr, txq->read_ptr);
1242 for (idx = iwl_queue_inc_wrap(idx); txq->read_ptr != idx;
1243 txq->read_ptr = iwl_queue_inc_wrap(txq->read_ptr)) {
1246 IWL_ERR(trans, "HCMD skipped: index (%d) %d %d\n",
1247 idx, txq->write_ptr, txq->read_ptr);
1248 iwl_force_nmi(trans);
1252 if (txq->read_ptr == txq->write_ptr) {
1253 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1254 iwl_pcie_clear_cmd_in_flight(trans);
1255 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1258 iwl_pcie_txq_progress(txq);
1261 static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
1264 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1269 scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
1271 tbl_dw_addr = trans_pcie->scd_base_addr +
1272 SCD_TRANS_TBL_OFFSET_QUEUE(txq_id);
1274 tbl_dw = iwl_trans_read_mem32(trans, tbl_dw_addr);
1277 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
1279 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
1281 iwl_trans_write_mem32(trans, tbl_dw_addr, tbl_dw);
1286 /* Receiver address (actually, Rx station's index into station table),
1287 * combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
1288 #define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
1290 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, u16 ssn,
1291 const struct iwl_trans_txq_scd_cfg *cfg,
1292 unsigned int wdg_timeout)
1294 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1295 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1297 bool scd_bug = false;
1299 if (test_and_set_bit(txq_id, trans_pcie->queue_used))
1300 WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
1302 txq->wd_timeout = msecs_to_jiffies(wdg_timeout);
1307 /* Disable the scheduler prior configuring the cmd queue */
1308 if (txq_id == trans_pcie->cmd_queue &&
1309 trans_pcie->scd_set_active)
1310 iwl_scd_enable_set_active(trans, 0);
1312 /* Stop this Tx queue before configuring it */
1313 iwl_scd_txq_set_inactive(trans, txq_id);
1315 /* Set this queue as a chain-building queue unless it is CMD */
1316 if (txq_id != trans_pcie->cmd_queue)
1317 iwl_scd_txq_set_chain(trans, txq_id);
1319 if (cfg->aggregate) {
1320 u16 ra_tid = BUILD_RAxTID(cfg->sta_id, cfg->tid);
1322 /* Map receiver-address / traffic-ID to this queue */
1323 iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
1325 /* enable aggregations for the queue */
1326 iwl_scd_txq_enable_agg(trans, txq_id);
1330 * disable aggregations for the queue, this will also
1331 * make the ra_tid mapping configuration irrelevant
1332 * since it is now a non-AGG queue.
1334 iwl_scd_txq_disable_agg(trans, txq_id);
1336 ssn = txq->read_ptr;
1340 * If we need to move the SCD write pointer by steps of
1341 * 0x40, 0x80 or 0xc0, it gets stuck. Avoids this and let
1342 * the op_mode know by returning true later.
1343 * Do this only in case cfg is NULL since this trick can
1344 * be done only if we have DQA enabled which is true for mvm
1345 * only. And mvm never sets a cfg pointer.
1346 * This is really ugly, but this is the easiest way out for
1347 * this sad hardware issue.
1348 * This bug has been fixed on devices 9000 and up.
1350 scd_bug = !trans->cfg->mq_rx_supported &&
1351 !((ssn - txq->write_ptr) & 0x3f) &&
1352 (ssn != txq->write_ptr);
1357 /* Place first TFD at index corresponding to start sequence number.
1358 * Assumes that ssn_idx is valid (!= 0xFFF) */
1359 txq->read_ptr = (ssn & 0xff);
1360 txq->write_ptr = (ssn & 0xff);
1361 iwl_write_direct32(trans, HBUS_TARG_WRPTR,
1362 (ssn & 0xff) | (txq_id << 8));
1365 u8 frame_limit = cfg->frame_limit;
1367 iwl_write_prph(trans, SCD_QUEUE_RDPTR(txq_id), ssn);
1369 /* Set up Tx window size and frame limit for this queue */
1370 iwl_trans_write_mem32(trans, trans_pcie->scd_base_addr +
1371 SCD_CONTEXT_QUEUE_OFFSET(txq_id), 0);
1372 iwl_trans_write_mem32(trans,
1373 trans_pcie->scd_base_addr +
1374 SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
1375 SCD_QUEUE_CTX_REG2_VAL(WIN_SIZE, frame_limit) |
1376 SCD_QUEUE_CTX_REG2_VAL(FRAME_LIMIT, frame_limit));
1378 /* Set up status area in SRAM, map to Tx DMA/FIFO, activate */
1379 iwl_write_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id),
1380 (1 << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1381 (cfg->fifo << SCD_QUEUE_STTS_REG_POS_TXF) |
1382 (1 << SCD_QUEUE_STTS_REG_POS_WSL) |
1383 SCD_QUEUE_STTS_REG_MSK);
1385 /* enable the scheduler for this queue (only) */
1386 if (txq_id == trans_pcie->cmd_queue &&
1387 trans_pcie->scd_set_active)
1388 iwl_scd_enable_set_active(trans, BIT(txq_id));
1390 IWL_DEBUG_TX_QUEUES(trans,
1391 "Activate queue %d on FIFO %d WrPtr: %d\n",
1392 txq_id, fifo, ssn & 0xff);
1394 IWL_DEBUG_TX_QUEUES(trans,
1395 "Activate queue %d WrPtr: %d\n",
1396 txq_id, ssn & 0xff);
1402 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id,
1405 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1406 struct iwl_txq *txq = trans_pcie->txq[txq_id];
1408 txq->ampdu = !shared_mode;
1411 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id,
1414 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1415 u32 stts_addr = trans_pcie->scd_base_addr +
1416 SCD_TX_STTS_QUEUE_OFFSET(txq_id);
1417 static const u32 zero_val[4] = {};
1419 trans_pcie->txq[txq_id]->frozen_expiry_remainder = 0;
1420 trans_pcie->txq[txq_id]->frozen = false;
1423 * Upon HW Rfkill - we stop the device, and then stop the queues
1424 * in the op_mode. Just for the sake of the simplicity of the op_mode,
1425 * allow the op_mode to call txq_disable after it already called
1428 if (!test_and_clear_bit(txq_id, trans_pcie->queue_used)) {
1429 WARN_ONCE(test_bit(STATUS_DEVICE_ENABLED, &trans->status),
1430 "queue %d not used", txq_id);
1434 if (configure_scd) {
1435 iwl_scd_txq_set_inactive(trans, txq_id);
1437 iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
1438 ARRAY_SIZE(zero_val));
1441 iwl_pcie_txq_unmap(trans, txq_id);
1442 trans_pcie->txq[txq_id]->ampdu = false;
1444 IWL_DEBUG_TX_QUEUES(trans, "Deactivate queue %d\n", txq_id);
1447 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
1450 * iwl_pcie_enqueue_hcmd - enqueue a uCode command
1451 * @priv: device private data point
1452 * @cmd: a pointer to the ucode command structure
1454 * The function returns < 0 values to indicate the operation
1455 * failed. On success, it returns the index (>= 0) of command in the
1458 static int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans,
1459 struct iwl_host_cmd *cmd)
1461 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1462 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1463 struct iwl_device_cmd *out_cmd;
1464 struct iwl_cmd_meta *out_meta;
1465 unsigned long flags;
1466 void *dup_buf = NULL;
1467 dma_addr_t phys_addr;
1469 u16 copy_size, cmd_size, tb0_size;
1470 bool had_nocopy = false;
1471 u8 group_id = iwl_cmd_groupid(cmd->id);
1474 const u8 *cmddata[IWL_MAX_CMD_TBS_PER_TFD];
1475 u16 cmdlen[IWL_MAX_CMD_TBS_PER_TFD];
1476 unsigned long flags2;
1478 if (WARN(!trans->wide_cmd_header &&
1479 group_id > IWL_ALWAYS_LONG_GROUP,
1480 "unsupported wide command %#x\n", cmd->id))
1483 if (group_id != 0) {
1484 copy_size = sizeof(struct iwl_cmd_header_wide);
1485 cmd_size = sizeof(struct iwl_cmd_header_wide);
1487 copy_size = sizeof(struct iwl_cmd_header);
1488 cmd_size = sizeof(struct iwl_cmd_header);
1491 /* need one for the header if the first is NOCOPY */
1492 BUILD_BUG_ON(IWL_MAX_CMD_TBS_PER_TFD > IWL_NUM_OF_TBS - 1);
1494 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1495 cmddata[i] = cmd->data[i];
1496 cmdlen[i] = cmd->len[i];
1501 /* need at least IWL_FIRST_TB_SIZE copied */
1502 if (copy_size < IWL_FIRST_TB_SIZE) {
1503 int copy = IWL_FIRST_TB_SIZE - copy_size;
1505 if (copy > cmdlen[i])
1512 if (cmd->dataflags[i] & IWL_HCMD_DFL_NOCOPY) {
1514 if (WARN_ON(cmd->dataflags[i] & IWL_HCMD_DFL_DUP)) {
1518 } else if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP) {
1520 * This is also a chunk that isn't copied
1521 * to the static buffer so set had_nocopy.
1525 /* only allowed once */
1526 if (WARN_ON(dup_buf)) {
1531 dup_buf = kmemdup(cmddata[i], cmdlen[i],
1536 /* NOCOPY must not be followed by normal! */
1537 if (WARN_ON(had_nocopy)) {
1541 copy_size += cmdlen[i];
1543 cmd_size += cmd->len[i];
1547 * If any of the command structures end up being larger than
1548 * the TFD_MAX_PAYLOAD_SIZE and they aren't dynamically
1549 * allocated into separate TFDs, then we will need to
1550 * increase the size of the buffers.
1552 if (WARN(copy_size > TFD_MAX_PAYLOAD_SIZE,
1553 "Command %s (%#x) is too large (%d bytes)\n",
1554 iwl_get_cmd_string(trans, cmd->id),
1555 cmd->id, copy_size)) {
1560 spin_lock_irqsave(&txq->lock, flags2);
1562 if (iwl_queue_space(txq) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1563 spin_unlock_irqrestore(&txq->lock, flags2);
1565 IWL_ERR(trans, "No space in command queue\n");
1566 iwl_op_mode_cmd_queue_full(trans->op_mode);
1571 idx = iwl_pcie_get_cmd_index(txq, txq->write_ptr);
1572 out_cmd = txq->entries[idx].cmd;
1573 out_meta = &txq->entries[idx].meta;
1575 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1576 if (cmd->flags & CMD_WANT_SKB)
1577 out_meta->source = cmd;
1579 /* set up the header */
1580 if (group_id != 0) {
1581 out_cmd->hdr_wide.cmd = iwl_cmd_opcode(cmd->id);
1582 out_cmd->hdr_wide.group_id = group_id;
1583 out_cmd->hdr_wide.version = iwl_cmd_version(cmd->id);
1584 out_cmd->hdr_wide.length =
1585 cpu_to_le16(cmd_size -
1586 sizeof(struct iwl_cmd_header_wide));
1587 out_cmd->hdr_wide.reserved = 0;
1588 out_cmd->hdr_wide.sequence =
1589 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1590 INDEX_TO_SEQ(txq->write_ptr));
1592 cmd_pos = sizeof(struct iwl_cmd_header_wide);
1593 copy_size = sizeof(struct iwl_cmd_header_wide);
1595 out_cmd->hdr.cmd = iwl_cmd_opcode(cmd->id);
1596 out_cmd->hdr.sequence =
1597 cpu_to_le16(QUEUE_TO_SEQ(trans_pcie->cmd_queue) |
1598 INDEX_TO_SEQ(txq->write_ptr));
1599 out_cmd->hdr.group_id = 0;
1601 cmd_pos = sizeof(struct iwl_cmd_header);
1602 copy_size = sizeof(struct iwl_cmd_header);
1605 /* and copy the data that needs to be copied */
1606 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1612 /* copy everything if not nocopy/dup */
1613 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1614 IWL_HCMD_DFL_DUP))) {
1617 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1624 * Otherwise we need at least IWL_FIRST_TB_SIZE copied
1625 * in total (for bi-directional DMA), but copy up to what
1626 * we can fit into the payload for debug dump purposes.
1628 copy = min_t(int, TFD_MAX_PAYLOAD_SIZE - cmd_pos, cmd->len[i]);
1630 memcpy((u8 *)out_cmd + cmd_pos, cmd->data[i], copy);
1633 /* However, treat copy_size the proper way, we need it below */
1634 if (copy_size < IWL_FIRST_TB_SIZE) {
1635 copy = IWL_FIRST_TB_SIZE - copy_size;
1637 if (copy > cmd->len[i])
1644 "Sending command %s (%.2x.%.2x), seq: 0x%04X, %d bytes at %d[%d]:%d\n",
1645 iwl_get_cmd_string(trans, cmd->id),
1646 group_id, out_cmd->hdr.cmd,
1647 le16_to_cpu(out_cmd->hdr.sequence),
1648 cmd_size, txq->write_ptr, idx, trans_pcie->cmd_queue);
1650 /* start the TFD with the minimum copy bytes */
1651 tb0_size = min_t(int, copy_size, IWL_FIRST_TB_SIZE);
1652 memcpy(&txq->first_tb_bufs[idx], &out_cmd->hdr, tb0_size);
1653 iwl_pcie_txq_build_tfd(trans, txq,
1654 iwl_pcie_get_first_tb_dma(txq, idx),
1657 /* map first command fragment, if any remains */
1658 if (copy_size > tb0_size) {
1659 phys_addr = dma_map_single(trans->dev,
1660 ((u8 *)&out_cmd->hdr) + tb0_size,
1661 copy_size - tb0_size,
1663 if (dma_mapping_error(trans->dev, phys_addr)) {
1664 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1670 iwl_pcie_txq_build_tfd(trans, txq, phys_addr,
1671 copy_size - tb0_size, false);
1674 /* map the remaining (adjusted) nocopy/dup fragments */
1675 for (i = 0; i < IWL_MAX_CMD_TBS_PER_TFD; i++) {
1676 const void *data = cmddata[i];
1680 if (!(cmd->dataflags[i] & (IWL_HCMD_DFL_NOCOPY |
1683 if (cmd->dataflags[i] & IWL_HCMD_DFL_DUP)
1685 phys_addr = dma_map_single(trans->dev, (void *)data,
1686 cmdlen[i], DMA_TO_DEVICE);
1687 if (dma_mapping_error(trans->dev, phys_addr)) {
1688 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1694 iwl_pcie_txq_build_tfd(trans, txq, phys_addr, cmdlen[i], false);
1697 BUILD_BUG_ON(IWL_TFH_NUM_TBS > sizeof(out_meta->tbs) * BITS_PER_BYTE);
1698 out_meta->flags = cmd->flags;
1699 if (WARN_ON_ONCE(txq->entries[idx].free_buf))
1700 kzfree(txq->entries[idx].free_buf);
1701 txq->entries[idx].free_buf = dup_buf;
1703 trace_iwlwifi_dev_hcmd(trans->dev, cmd, cmd_size, &out_cmd->hdr_wide);
1705 /* start timer if queue currently empty */
1706 if (txq->read_ptr == txq->write_ptr && txq->wd_timeout)
1707 mod_timer(&txq->stuck_timer, jiffies + txq->wd_timeout);
1709 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1710 ret = iwl_pcie_set_cmd_in_flight(trans, cmd);
1713 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1717 /* Increment and update queue's write index */
1718 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
1719 iwl_pcie_txq_inc_wr_ptr(trans, txq);
1721 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1724 spin_unlock_irqrestore(&txq->lock, flags2);
1732 * iwl_pcie_hcmd_complete - Pull unused buffers off the queue and reclaim them
1733 * @rxb: Rx buffer to reclaim
1735 void iwl_pcie_hcmd_complete(struct iwl_trans *trans,
1736 struct iwl_rx_cmd_buffer *rxb)
1738 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1739 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1742 int txq_id = SEQ_TO_QUEUE(sequence);
1743 int index = SEQ_TO_INDEX(sequence);
1745 struct iwl_device_cmd *cmd;
1746 struct iwl_cmd_meta *meta;
1747 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1748 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1750 /* If a Tx command is being handled and it isn't in the actual
1751 * command queue then there a command routing bug has been introduced
1752 * in the queue management code. */
1753 if (WARN(txq_id != trans_pcie->cmd_queue,
1754 "wrong command queue %d (should be %d), sequence 0x%X readp=%d writep=%d\n",
1755 txq_id, trans_pcie->cmd_queue, sequence, txq->read_ptr,
1757 iwl_print_hex_error(trans, pkt, 32);
1761 spin_lock_bh(&txq->lock);
1763 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1764 cmd = txq->entries[cmd_index].cmd;
1765 meta = &txq->entries[cmd_index].meta;
1766 group_id = cmd->hdr.group_id;
1767 cmd_id = iwl_cmd_id(cmd->hdr.cmd, group_id, 0);
1769 iwl_pcie_tfd_unmap(trans, meta, txq, index);
1771 /* Input error checking is done when commands are added to queue. */
1772 if (meta->flags & CMD_WANT_SKB) {
1773 struct page *p = rxb_steal_page(rxb);
1775 meta->source->resp_pkt = pkt;
1776 meta->source->_rx_page_addr = (unsigned long)page_address(p);
1777 meta->source->_rx_page_order = trans_pcie->rx_page_order;
1780 if (meta->flags & CMD_WANT_ASYNC_CALLBACK)
1781 iwl_op_mode_async_cb(trans->op_mode, cmd);
1783 iwl_pcie_cmdq_reclaim(trans, txq_id, index);
1785 if (!(meta->flags & CMD_ASYNC)) {
1786 if (!test_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status)) {
1788 "HCMD_ACTIVE already clear for command %s\n",
1789 iwl_get_cmd_string(trans, cmd_id));
1791 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1792 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1793 iwl_get_cmd_string(trans, cmd_id));
1794 wake_up(&trans_pcie->wait_command_queue);
1797 if (meta->flags & CMD_MAKE_TRANS_IDLE) {
1798 IWL_DEBUG_INFO(trans, "complete %s - mark trans as idle\n",
1799 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1800 set_bit(STATUS_TRANS_IDLE, &trans->status);
1801 wake_up(&trans_pcie->d0i3_waitq);
1804 if (meta->flags & CMD_WAKE_UP_TRANS) {
1805 IWL_DEBUG_INFO(trans, "complete %s - clear trans idle flag\n",
1806 iwl_get_cmd_string(trans, cmd->hdr.cmd));
1807 clear_bit(STATUS_TRANS_IDLE, &trans->status);
1808 wake_up(&trans_pcie->d0i3_waitq);
1813 spin_unlock_bh(&txq->lock);
1816 #define HOST_COMPLETE_TIMEOUT (2 * HZ)
1818 static int iwl_pcie_send_hcmd_async(struct iwl_trans *trans,
1819 struct iwl_host_cmd *cmd)
1823 /* An asynchronous command can not expect an SKB to be set. */
1824 if (WARN_ON(cmd->flags & CMD_WANT_SKB))
1827 ret = iwl_pcie_enqueue_hcmd(trans, cmd);
1830 "Error sending %s: enqueue_hcmd failed: %d\n",
1831 iwl_get_cmd_string(trans, cmd->id), ret);
1837 static int iwl_pcie_send_hcmd_sync(struct iwl_trans *trans,
1838 struct iwl_host_cmd *cmd)
1840 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1841 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1845 IWL_DEBUG_INFO(trans, "Attempting to send sync command %s\n",
1846 iwl_get_cmd_string(trans, cmd->id));
1848 if (WARN(test_and_set_bit(STATUS_SYNC_HCMD_ACTIVE,
1850 "Command %s: a command is already active!\n",
1851 iwl_get_cmd_string(trans, cmd->id)))
1854 IWL_DEBUG_INFO(trans, "Setting HCMD_ACTIVE for command %s\n",
1855 iwl_get_cmd_string(trans, cmd->id));
1857 if (pm_runtime_suspended(&trans_pcie->pci_dev->dev)) {
1858 ret = wait_event_timeout(trans_pcie->d0i3_waitq,
1859 pm_runtime_active(&trans_pcie->pci_dev->dev),
1860 msecs_to_jiffies(IWL_TRANS_IDLE_TIMEOUT));
1862 IWL_ERR(trans, "Timeout exiting D0i3 before hcmd\n");
1867 cmd_idx = iwl_pcie_enqueue_hcmd(trans, cmd);
1870 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1872 "Error sending %s: enqueue_hcmd failed: %d\n",
1873 iwl_get_cmd_string(trans, cmd->id), ret);
1877 ret = wait_event_timeout(trans_pcie->wait_command_queue,
1878 !test_bit(STATUS_SYNC_HCMD_ACTIVE,
1880 HOST_COMPLETE_TIMEOUT);
1882 IWL_ERR(trans, "Error sending %s: time out after %dms.\n",
1883 iwl_get_cmd_string(trans, cmd->id),
1884 jiffies_to_msecs(HOST_COMPLETE_TIMEOUT));
1886 IWL_ERR(trans, "Current CMD queue read_ptr %d write_ptr %d\n",
1887 txq->read_ptr, txq->write_ptr);
1889 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1890 IWL_DEBUG_INFO(trans, "Clearing HCMD_ACTIVE for command %s\n",
1891 iwl_get_cmd_string(trans, cmd->id));
1894 iwl_force_nmi(trans);
1895 iwl_trans_fw_error(trans);
1900 if (test_bit(STATUS_FW_ERROR, &trans->status)) {
1901 IWL_ERR(trans, "FW error in SYNC CMD %s\n",
1902 iwl_get_cmd_string(trans, cmd->id));
1908 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1909 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1910 IWL_DEBUG_RF_KILL(trans, "RFKILL in SYNC CMD... no rsp\n");
1915 if ((cmd->flags & CMD_WANT_SKB) && !cmd->resp_pkt) {
1916 IWL_ERR(trans, "Error: Response NULL in '%s'\n",
1917 iwl_get_cmd_string(trans, cmd->id));
1925 if (cmd->flags & CMD_WANT_SKB) {
1927 * Cancel the CMD_WANT_SKB flag for the cmd in the
1928 * TX cmd queue. Otherwise in case the cmd comes
1929 * in later, it will possibly set an invalid
1930 * address (cmd->meta.source).
1932 txq->entries[cmd_idx].meta.flags &= ~CMD_WANT_SKB;
1935 if (cmd->resp_pkt) {
1937 cmd->resp_pkt = NULL;
1943 int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd)
1945 if (!(cmd->flags & CMD_SEND_IN_RFKILL) &&
1946 test_bit(STATUS_RFKILL_OPMODE, &trans->status)) {
1947 IWL_DEBUG_RF_KILL(trans, "Dropping CMD 0x%x: RF KILL\n",
1952 if (cmd->flags & CMD_ASYNC)
1953 return iwl_pcie_send_hcmd_async(trans, cmd);
1955 /* We still can fail on RFKILL that can be asserted while we wait */
1956 return iwl_pcie_send_hcmd_sync(trans, cmd);
1959 static int iwl_fill_data_tbs(struct iwl_trans *trans, struct sk_buff *skb,
1960 struct iwl_txq *txq, u8 hdr_len,
1961 struct iwl_cmd_meta *out_meta,
1962 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
1964 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1969 * Set up TFD's third entry to point directly to remainder
1970 * of skb's head, if any
1972 tb2_len = skb_headlen(skb) - hdr_len;
1975 dma_addr_t tb2_phys = dma_map_single(trans->dev,
1976 skb->data + hdr_len,
1977 tb2_len, DMA_TO_DEVICE);
1978 if (unlikely(dma_mapping_error(trans->dev, tb2_phys))) {
1979 iwl_pcie_tfd_unmap(trans, out_meta, txq,
1983 iwl_pcie_txq_build_tfd(trans, txq, tb2_phys, tb2_len, false);
1986 /* set up the remaining entries to point to the data */
1987 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1988 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1992 if (!skb_frag_size(frag))
1995 tb_phys = skb_frag_dma_map(trans->dev, frag, 0,
1996 skb_frag_size(frag), DMA_TO_DEVICE);
1998 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
1999 iwl_pcie_tfd_unmap(trans, out_meta, txq,
2003 tb_idx = iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2004 skb_frag_size(frag), false);
2006 out_meta->tbs |= BIT(tb_idx);
2009 trace_iwlwifi_dev_tx(trans->dev, skb,
2010 iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2011 trans_pcie->tfd_size,
2012 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len,
2014 trace_iwlwifi_dev_tx_data(trans->dev, skb, hdr_len);
2019 struct iwl_tso_hdr_page *get_page_hdr(struct iwl_trans *trans, size_t len)
2021 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2022 struct iwl_tso_hdr_page *p = this_cpu_ptr(trans_pcie->tso_hdr_page);
2027 /* enough room on this page */
2028 if (p->pos + len < (u8 *)page_address(p->page) + PAGE_SIZE)
2031 /* We don't have enough room on this page, get a new one. */
2032 __free_page(p->page);
2035 p->page = alloc_page(GFP_ATOMIC);
2038 p->pos = page_address(p->page);
2042 static void iwl_compute_pseudo_hdr_csum(void *iph, struct tcphdr *tcph,
2043 bool ipv6, unsigned int len)
2046 struct ipv6hdr *iphv6 = iph;
2048 tcph->check = ~csum_ipv6_magic(&iphv6->saddr, &iphv6->daddr,
2049 len + tcph->doff * 4,
2052 struct iphdr *iphv4 = iph;
2054 ip_send_check(iphv4);
2055 tcph->check = ~csum_tcpudp_magic(iphv4->saddr, iphv4->daddr,
2056 len + tcph->doff * 4,
2061 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2062 struct iwl_txq *txq, u8 hdr_len,
2063 struct iwl_cmd_meta *out_meta,
2064 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2066 struct iwl_tx_cmd *tx_cmd = (void *)dev_cmd->payload;
2067 struct iwl_trans_pcie *trans_pcie = txq->trans_pcie;
2068 struct ieee80211_hdr *hdr = (void *)skb->data;
2069 unsigned int snap_ip_tcp_hdrlen, ip_hdrlen, total_len, hdr_room;
2070 unsigned int mss = skb_shinfo(skb)->gso_size;
2071 u16 length, iv_len, amsdu_pad;
2073 struct iwl_tso_hdr_page *hdr_page;
2074 struct page **page_ptr;
2078 /* if the packet is protected, then it must be CCMP or GCMP */
2079 BUILD_BUG_ON(IEEE80211_CCMP_HDR_LEN != IEEE80211_GCMP_HDR_LEN);
2080 iv_len = ieee80211_has_protected(hdr->frame_control) ?
2081 IEEE80211_CCMP_HDR_LEN : 0;
2083 trace_iwlwifi_dev_tx(trans->dev, skb,
2084 iwl_pcie_get_tfd(trans, txq, txq->write_ptr),
2085 trans_pcie->tfd_size,
2086 &dev_cmd->hdr, IWL_FIRST_TB_SIZE + tb1_len, 0);
2088 ip_hdrlen = skb_transport_header(skb) - skb_network_header(skb);
2089 snap_ip_tcp_hdrlen = 8 + ip_hdrlen + tcp_hdrlen(skb);
2090 total_len = skb->len - snap_ip_tcp_hdrlen - hdr_len - iv_len;
2093 /* total amount of header we may need for this A-MSDU */
2094 hdr_room = DIV_ROUND_UP(total_len, mss) *
2095 (3 + snap_ip_tcp_hdrlen + sizeof(struct ethhdr)) + iv_len;
2097 /* Our device supports 9 segments at most, it will fit in 1 page */
2098 hdr_page = get_page_hdr(trans, hdr_room);
2102 get_page(hdr_page->page);
2103 start_hdr = hdr_page->pos;
2104 page_ptr = (void *)((u8 *)skb->cb + trans_pcie->page_offs);
2105 *page_ptr = hdr_page->page;
2106 memcpy(hdr_page->pos, skb->data + hdr_len, iv_len);
2107 hdr_page->pos += iv_len;
2110 * Pull the ieee80211 header + IV to be able to use TSO core,
2111 * we will restore it for the tx_status flow.
2113 skb_pull(skb, hdr_len + iv_len);
2116 * Remove the length of all the headers that we don't actually
2117 * have in the MPDU by themselves, but that we duplicate into
2118 * all the different MSDUs inside the A-MSDU.
2120 le16_add_cpu(&tx_cmd->len, -snap_ip_tcp_hdrlen);
2122 tso_start(skb, &tso);
2125 /* this is the data left for this subframe */
2126 unsigned int data_left =
2127 min_t(unsigned int, mss, total_len);
2128 struct sk_buff *csum_skb = NULL;
2129 unsigned int hdr_tb_len;
2130 dma_addr_t hdr_tb_phys;
2131 struct tcphdr *tcph;
2132 u8 *iph, *subf_hdrs_start = hdr_page->pos;
2134 total_len -= data_left;
2136 memset(hdr_page->pos, 0, amsdu_pad);
2137 hdr_page->pos += amsdu_pad;
2138 amsdu_pad = (4 - (sizeof(struct ethhdr) + snap_ip_tcp_hdrlen +
2140 ether_addr_copy(hdr_page->pos, ieee80211_get_DA(hdr));
2141 hdr_page->pos += ETH_ALEN;
2142 ether_addr_copy(hdr_page->pos, ieee80211_get_SA(hdr));
2143 hdr_page->pos += ETH_ALEN;
2145 length = snap_ip_tcp_hdrlen + data_left;
2146 *((__be16 *)hdr_page->pos) = cpu_to_be16(length);
2147 hdr_page->pos += sizeof(length);
2150 * This will copy the SNAP as well which will be considered
2153 tso_build_hdr(skb, hdr_page->pos, &tso, data_left, !total_len);
2154 iph = hdr_page->pos + 8;
2155 tcph = (void *)(iph + ip_hdrlen);
2157 /* For testing on current hardware only */
2158 if (trans_pcie->sw_csum_tx) {
2159 csum_skb = alloc_skb(data_left + tcp_hdrlen(skb),
2166 iwl_compute_pseudo_hdr_csum(iph, tcph,
2171 skb_put_data(csum_skb, tcph, tcp_hdrlen(skb));
2172 skb_reset_transport_header(csum_skb);
2173 csum_skb->csum_start =
2174 (unsigned char *)tcp_hdr(csum_skb) -
2178 hdr_page->pos += snap_ip_tcp_hdrlen;
2180 hdr_tb_len = hdr_page->pos - start_hdr;
2181 hdr_tb_phys = dma_map_single(trans->dev, start_hdr,
2182 hdr_tb_len, DMA_TO_DEVICE);
2183 if (unlikely(dma_mapping_error(trans->dev, hdr_tb_phys))) {
2184 dev_kfree_skb(csum_skb);
2188 iwl_pcie_txq_build_tfd(trans, txq, hdr_tb_phys,
2190 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, start_hdr,
2192 /* add this subframe's headers' length to the tx_cmd */
2193 le16_add_cpu(&tx_cmd->len, hdr_page->pos - subf_hdrs_start);
2195 /* prepare the start_hdr for the next subframe */
2196 start_hdr = hdr_page->pos;
2198 /* put the payload */
2200 unsigned int size = min_t(unsigned int, tso.size,
2204 if (trans_pcie->sw_csum_tx)
2205 skb_put_data(csum_skb, tso.data, size);
2207 tb_phys = dma_map_single(trans->dev, tso.data,
2208 size, DMA_TO_DEVICE);
2209 if (unlikely(dma_mapping_error(trans->dev, tb_phys))) {
2210 dev_kfree_skb(csum_skb);
2215 iwl_pcie_txq_build_tfd(trans, txq, tb_phys,
2217 trace_iwlwifi_dev_tx_tso_chunk(trans->dev, tso.data,
2221 tso_build_data(skb, &tso, size);
2224 /* For testing on early hardware only */
2225 if (trans_pcie->sw_csum_tx) {
2228 csum = skb_checksum(csum_skb,
2229 skb_checksum_start_offset(csum_skb),
2231 skb_checksum_start_offset(csum_skb),
2233 dev_kfree_skb(csum_skb);
2234 dma_sync_single_for_cpu(trans->dev, hdr_tb_phys,
2235 hdr_tb_len, DMA_TO_DEVICE);
2236 tcph->check = csum_fold(csum);
2237 dma_sync_single_for_device(trans->dev, hdr_tb_phys,
2238 hdr_tb_len, DMA_TO_DEVICE);
2242 /* re -add the WiFi header and IV */
2243 skb_push(skb, hdr_len + iv_len);
2248 iwl_pcie_tfd_unmap(trans, out_meta, txq, txq->write_ptr);
2251 #else /* CONFIG_INET */
2252 static int iwl_fill_data_tbs_amsdu(struct iwl_trans *trans, struct sk_buff *skb,
2253 struct iwl_txq *txq, u8 hdr_len,
2254 struct iwl_cmd_meta *out_meta,
2255 struct iwl_device_cmd *dev_cmd, u16 tb1_len)
2257 /* No A-MSDU without CONFIG_INET */
2262 #endif /* CONFIG_INET */
2264 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb,
2265 struct iwl_device_cmd *dev_cmd, int txq_id)
2267 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2268 struct ieee80211_hdr *hdr;
2269 struct iwl_tx_cmd *tx_cmd = (struct iwl_tx_cmd *)dev_cmd->payload;
2270 struct iwl_cmd_meta *out_meta;
2271 struct iwl_txq *txq;
2272 dma_addr_t tb0_phys, tb1_phys, scratch_phys;
2276 bool wait_write_ptr;
2282 txq = trans_pcie->txq[txq_id];
2284 if (WARN_ONCE(!test_bit(txq_id, trans_pcie->queue_used),
2285 "TX on unused queue %d\n", txq_id))
2288 if (unlikely(trans_pcie->sw_csum_tx &&
2289 skb->ip_summed == CHECKSUM_PARTIAL)) {
2290 int offs = skb_checksum_start_offset(skb);
2291 int csum_offs = offs + skb->csum_offset;
2294 if (skb_ensure_writable(skb, csum_offs + sizeof(__sum16)))
2297 csum = skb_checksum(skb, offs, skb->len - offs, 0);
2298 *(__sum16 *)(skb->data + csum_offs) = csum_fold(csum);
2300 skb->ip_summed = CHECKSUM_UNNECESSARY;
2303 if (skb_is_nonlinear(skb) &&
2304 skb_shinfo(skb)->nr_frags > IWL_PCIE_MAX_FRAGS(trans_pcie) &&
2305 __skb_linearize(skb))
2308 /* mac80211 always puts the full header into the SKB's head,
2309 * so there's no need to check if it's readable there
2311 hdr = (struct ieee80211_hdr *)skb->data;
2312 fc = hdr->frame_control;
2313 hdr_len = ieee80211_hdrlen(fc);
2315 spin_lock(&txq->lock);
2317 if (iwl_queue_space(txq) < txq->high_mark) {
2318 iwl_stop_queue(trans, txq);
2320 /* don't put the packet on the ring, if there is no room */
2321 if (unlikely(iwl_queue_space(txq) < 3)) {
2322 struct iwl_device_cmd **dev_cmd_ptr;
2324 dev_cmd_ptr = (void *)((u8 *)skb->cb +
2325 trans_pcie->dev_cmd_offs);
2327 *dev_cmd_ptr = dev_cmd;
2328 __skb_queue_tail(&txq->overflow_q, skb);
2330 spin_unlock(&txq->lock);
2335 /* In AGG mode, the index in the ring must correspond to the WiFi
2336 * sequence number. This is a HW requirements to help the SCD to parse
2338 * Check here that the packets are in the right place on the ring.
2340 wifi_seq = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
2341 WARN_ONCE(txq->ampdu &&
2342 (wifi_seq & 0xff) != txq->write_ptr,
2343 "Q: %d WiFi Seq %d tfdNum %d",
2344 txq_id, wifi_seq, txq->write_ptr);
2346 /* Set up driver data for this TFD */
2347 txq->entries[txq->write_ptr].skb = skb;
2348 txq->entries[txq->write_ptr].cmd = dev_cmd;
2350 dev_cmd->hdr.sequence =
2351 cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
2352 INDEX_TO_SEQ(txq->write_ptr)));
2354 tb0_phys = iwl_pcie_get_first_tb_dma(txq, txq->write_ptr);
2355 scratch_phys = tb0_phys + sizeof(struct iwl_cmd_header) +
2356 offsetof(struct iwl_tx_cmd, scratch);
2358 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
2359 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
2361 /* Set up first empty entry in queue's array of Tx/cmd buffers */
2362 out_meta = &txq->entries[txq->write_ptr].meta;
2363 out_meta->flags = 0;
2366 * The second TB (tb1) points to the remainder of the TX command
2367 * and the 802.11 header - dword aligned size
2368 * (This calculation modifies the TX command, so do it before the
2369 * setup of the first TB)
2371 len = sizeof(struct iwl_tx_cmd) + sizeof(struct iwl_cmd_header) +
2372 hdr_len - IWL_FIRST_TB_SIZE;
2373 /* do not align A-MSDU to dword as the subframe header aligns it */
2374 amsdu = ieee80211_is_data_qos(fc) &&
2375 (*ieee80211_get_qos_ctl(hdr) &
2376 IEEE80211_QOS_CTL_A_MSDU_PRESENT);
2377 if (trans_pcie->sw_csum_tx || !amsdu) {
2378 tb1_len = ALIGN(len, 4);
2379 /* Tell NIC about any 2-byte padding after MAC header */
2381 tx_cmd->tx_flags |= cpu_to_le32(TX_CMD_FLG_MH_PAD);
2387 * The first TB points to bi-directional DMA data, we'll
2388 * memcpy the data into it later.
2390 iwl_pcie_txq_build_tfd(trans, txq, tb0_phys,
2391 IWL_FIRST_TB_SIZE, true);
2393 /* there must be data left over for TB1 or this code must be changed */
2394 BUILD_BUG_ON(sizeof(struct iwl_tx_cmd) < IWL_FIRST_TB_SIZE);
2396 /* map the data for TB1 */
2397 tb1_addr = ((u8 *)&dev_cmd->hdr) + IWL_FIRST_TB_SIZE;
2398 tb1_phys = dma_map_single(trans->dev, tb1_addr, tb1_len, DMA_TO_DEVICE);
2399 if (unlikely(dma_mapping_error(trans->dev, tb1_phys)))
2401 iwl_pcie_txq_build_tfd(trans, txq, tb1_phys, tb1_len, false);
2404 if (unlikely(iwl_fill_data_tbs_amsdu(trans, skb, txq, hdr_len,
2408 } else if (unlikely(iwl_fill_data_tbs(trans, skb, txq, hdr_len,
2409 out_meta, dev_cmd, tb1_len))) {
2413 /* building the A-MSDU might have changed this data, so memcpy it now */
2414 memcpy(&txq->first_tb_bufs[txq->write_ptr], &dev_cmd->hdr,
2417 tfd = iwl_pcie_get_tfd(trans, txq, txq->write_ptr);
2418 /* Set up entry for this TFD in Tx byte-count array */
2419 iwl_pcie_txq_update_byte_cnt_tbl(trans, txq, le16_to_cpu(tx_cmd->len),
2420 iwl_pcie_tfd_get_num_tbs(trans, tfd));
2422 wait_write_ptr = ieee80211_has_morefrags(fc);
2424 /* start timer if queue currently empty */
2425 if (txq->read_ptr == txq->write_ptr) {
2426 if (txq->wd_timeout) {
2428 * If the TXQ is active, then set the timer, if not,
2429 * set the timer in remainder so that the timer will
2430 * be armed with the right value when the station will
2434 mod_timer(&txq->stuck_timer,
2435 jiffies + txq->wd_timeout);
2437 txq->frozen_expiry_remainder = txq->wd_timeout;
2439 IWL_DEBUG_RPM(trans, "Q: %d first tx - take ref\n", txq->id);
2440 iwl_trans_ref(trans);
2443 /* Tell device the write index *just past* this latest filled TFD */
2444 txq->write_ptr = iwl_queue_inc_wrap(txq->write_ptr);
2445 if (!wait_write_ptr)
2446 iwl_pcie_txq_inc_wr_ptr(trans, txq);
2449 * At this point the frame is "transmitted" successfully
2450 * and we will get a TX status notification eventually.
2452 spin_unlock(&txq->lock);
2455 spin_unlock(&txq->lock);