drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   4  * redistributing this file, you may do so under either license.
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  * Copyright(c) 2018 Intel Corporation
  12  *
  13  * This program is free software; you can redistribute it and/or modify
  14  * it under the terms of version 2 of the GNU General Public License as
  15  * published by the Free Software Foundation.
  16  *
  17  * This program is distributed in the hope that it will be useful, but
  18  * WITHOUT ANY WARRANTY; without even the implied warranty of
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  28  * in the file called COPYING.
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  30  * Contact Information:
  31  *  Intel Linux Wireless <linuxwifi@intel.com>
  32  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  34  * BSD LICENSE
  35  *
  36  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  37  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  38  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  39  * Copyright(c) 2018 Intel Corporation
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  43  * modification, are permitted provided that the following conditions
  44  * are met:
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  47  *    notice, this list of conditions and the following disclaimer.
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  50  *    the documentation and/or other materials provided with the
  51  *    distribution.
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  53  *    contributors may be used to endorse or promote products derived
  54  *    from this software without specific prior written permission.
  55  *
  56  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  57  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  58  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  59  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  60  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  62  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  64  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  65  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  66  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  67  *
  68  *****************************************************************************/
  69 #include <linux/pci.h>
  70 #include <linux/pci-aspm.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/debugfs.h>
  73 #include <linux/sched.h>
  74 #include <linux/bitops.h>
  75 #include <linux/gfp.h>
  76 #include <linux/vmalloc.h>
  77 #include <linux/pm_runtime.h>
  78 #include <linux/module.h>
  79
  80 #include "iwl-drv.h"
  81 #include "iwl-trans.h"
  82 #include "iwl-csr.h"
  83 #include "iwl-prph.h"
  84 #include "iwl-scd.h"
  85 #include "iwl-agn-hw.h"
  86 #include "fw/error-dump.h"
  87 #include "fw/dbg.h"
  88 #include "internal.h"
  89 #include "iwl-fh.h"
  90
  91 /* extended range in FW SRAM */
  92 #define IWL_FW_MEM_EXTENDED_START       0x40000
  93 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  94
  95 static void iwl_trans_pcie_dump_regs(struct iwl_trans *trans)
  96 {
  97 #define PCI_DUMP_SIZE   64
  98 #define PREFIX_LEN      32
  99         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 100         struct pci_dev *pdev = trans_pcie->pci_dev;
 101         u32 i, pos, alloc_size, *ptr, *buf;
 102         char *prefix;
 103
 104         if (trans_pcie->pcie_dbg_dumped_once)
 105                 return;
 106
 107         /* Should be a multiple of 4 */
 108         BUILD_BUG_ON(PCI_DUMP_SIZE > 4096 || PCI_DUMP_SIZE & 0x3);
 109         /* Alloc a max size buffer */
 110         if (PCI_ERR_ROOT_ERR_SRC +  4 > PCI_DUMP_SIZE)
 111                 alloc_size = PCI_ERR_ROOT_ERR_SRC +  4 + PREFIX_LEN;
 112         else
 113                 alloc_size = PCI_DUMP_SIZE + PREFIX_LEN;
 114         buf = kmalloc(alloc_size, GFP_ATOMIC);
 115         if (!buf)
 116                 return;
 117         prefix = (char *)buf + alloc_size - PREFIX_LEN;
 118
 119         IWL_ERR(trans, "iwlwifi transaction failed, dumping registers\n");
 120
 121         /* Print wifi device registers */
 122         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 123         IWL_ERR(trans, "iwlwifi device config registers:\n");
 124         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 125                 if (pci_read_config_dword(pdev, i, ptr))
 126                         goto err_read;
 127         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 128
 129         IWL_ERR(trans, "iwlwifi device memory mapped registers:\n");
 130         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 131                 *ptr = iwl_read32(trans, i);
 132         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 133
 134         pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 135         if (pos) {
 136                 IWL_ERR(trans, "iwlwifi device AER capability structure:\n");
 137                 for (i = 0, ptr = buf; i < PCI_ERR_ROOT_COMMAND; i += 4, ptr++)
 138                         if (pci_read_config_dword(pdev, pos + i, ptr))
 139                                 goto err_read;
 140                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET,
 141                                32, 4, buf, i, 0);
 142         }
 143
 144         /* Print parent device registers next */
 145         if (!pdev->bus->self)
 146                 goto out;
 147
 148         pdev = pdev->bus->self;
 149         sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 150
 151         IWL_ERR(trans, "iwlwifi parent port (%s) config registers:\n",
 152                 pci_name(pdev));
 153         for (i = 0, ptr = buf; i < PCI_DUMP_SIZE; i += 4, ptr++)
 154                 if (pci_read_config_dword(pdev, i, ptr))
 155                         goto err_read;
 156         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 157
 158         /* Print root port AER registers */
 159         pos = 0;
 160         pdev = pcie_find_root_port(pdev);
 161         if (pdev)
 162                 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR);
 163         if (pos) {
 164                 IWL_ERR(trans, "iwlwifi root port (%s) AER cap structure:\n",
 165                         pci_name(pdev));
 166                 sprintf(prefix, "iwlwifi %s: ", pci_name(pdev));
 167                 for (i = 0, ptr = buf; i <= PCI_ERR_ROOT_ERR_SRC; i += 4, ptr++)
 168                         if (pci_read_config_dword(pdev, pos + i, ptr))
 169                                 goto err_read;
 170                 print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32,
 171                                4, buf, i, 0);
 172         }
 173         goto out;
 174
 175 err_read:
 176         print_hex_dump(KERN_ERR, prefix, DUMP_PREFIX_OFFSET, 32, 4, buf, i, 0);
 177         IWL_ERR(trans, "Read failed at 0x%X\n", i);
 178 out:
 179         trans_pcie->pcie_dbg_dumped_once = 1;
 180         kfree(buf);
 181 }
 182
 183 static void iwl_trans_pcie_sw_reset(struct iwl_trans *trans)
 184 {
 185         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 186         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 187                     BIT(trans->cfg->csr->flag_sw_reset));
 188         usleep_range(5000, 6000);
 189 }
 190
 191 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
 192 {
 193         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 194
 195         if (!trans_pcie->fw_mon_page)
 196                 return;
 197
 198         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
 199                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 200         __free_pages(trans_pcie->fw_mon_page,
 201                      get_order(trans_pcie->fw_mon_size));
 202         trans_pcie->fw_mon_page = NULL;
 203         trans_pcie->fw_mon_phys = 0;
 204         trans_pcie->fw_mon_size = 0;
 205 }
 206
 207 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 208 {
 209         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 210         struct page *page = NULL;
 211         dma_addr_t phys;
 212         u32 size = 0;
 213         u8 power;
 214
 215         if (!max_power) {
 216                 /* default max_power is maximum */
 217                 max_power = 26;
 218         } else {
 219                 max_power += 11;
 220         }
 221
 222         if (WARN(max_power > 26,
 223                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 224                  max_power))
 225                 return;
 226
 227         if (trans_pcie->fw_mon_page) {
 228                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 229                                            trans_pcie->fw_mon_size,
 230                                            DMA_FROM_DEVICE);
 231                 return;
 232         }
 233
 234         phys = 0;
 235         for (power = max_power; power >= 11; power--) {
 236                 int order;
 237
 238                 size = BIT(power);
 239                 order = get_order(size);
 240                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 241                                    order);
 242                 if (!page)
 243                         continue;
 244
 245                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 246                                     DMA_FROM_DEVICE);
 247                 if (dma_mapping_error(trans->dev, phys)) {
 248                         __free_pages(page, order);
 249                         page = NULL;
 250                         continue;
 251                 }
 252                 IWL_INFO(trans,
 253                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 254                          size, order);
 255                 break;
 256         }
 257
 258         if (WARN_ON_ONCE(!page))
 259                 return;
 260
 261         if (power != max_power)
 262                 IWL_ERR(trans,
 263                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 264                         (unsigned long)BIT(power - 10),
 265                         (unsigned long)BIT(max_power - 10));
 266
 267         trans_pcie->fw_mon_page = page;
 268         trans_pcie->fw_mon_phys = phys;
 269         trans_pcie->fw_mon_size = size;
 270 }
 271
 272 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 273 {
 274         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 275                     ((reg & 0x0000ffff) | (2 << 28)));
 276         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 277 }
 278
 279 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 280 {
 281         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 282         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 283                     ((reg & 0x0000ffff) | (3 << 28)));
 284 }
 285
 286 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 287 {
 288         if (trans->cfg->apmg_not_supported)
 289                 return;
 290
 291         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 292                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 293                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 294                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 295         else
 296                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 297                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 298                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 299 }
 300
 301 /* PCI registers */
 302 #define PCI_CFG_RETRY_TIMEOUT   0x041
 303
 304 void iwl_pcie_apm_config(struct iwl_trans *trans)
 305 {
 306         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 307         u16 lctl;
 308         u16 cap;
 309
 310         /*
 311          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 312          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 313          * If so (likely), disable L0S, so device moves directly L0->L1;
 314          *    costs negligible amount of power savings.
 315          * If not (unlikely), enable L0S, so there is at least some
 316          *    power savings, even without L1.
 317          */
 318         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 319         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 320                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 321         else
 322                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 323         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 324
 325         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 326         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 327         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 328                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 329                         trans->ltr_enabled ? "En" : "Dis");
 330 }
 331
 332 /*
 333  * Start up NIC's basic functionality after it has been reset
 334  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 335  * NOTE:  This does not load uCode nor start the embedded processor
 336  */
 337 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 338 {
 339         int ret;
 340
 341         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 342
 343         /*
 344          * Use "set_bit" below rather than "write", to preserve any hardware
 345          * bits already set by default after reset.
 346          */
 347
 348         /* Disable L0S exit timer (platform NMI Work/Around) */
 349         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 350                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 351                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 352
 353         /*
 354          * Disable L0s without affecting L1;
 355          *  don't wait for ICH L0s (ICH bug W/A)
 356          */
 357         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 358                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 359
 360         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 361         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 362
 363         /*
 364          * Enable HAP INTA (interrupt from management bus) to
 365          * wake device's PCI Express link L1a -> L0s
 366          */
 367         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 368                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 369
 370         iwl_pcie_apm_config(trans);
 371
 372         /* Configure analog phase-lock-loop before activating to D0A */
 373         if (trans->cfg->base_params->pll_cfg)
 374                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 375
 376         /*
 377          * Set "initialization complete" bit to move adapter from
 378          * D0U* --> D0A* (powered-up active) state.
 379          */
 380         iwl_set_bit(trans, CSR_GP_CNTRL,
 381                     BIT(trans->cfg->csr->flag_init_done));
 382
 383         /*
 384          * Wait for clock stabilization; once stabilized, access to
 385          * device-internal resources is supported, e.g. iwl_write_prph()
 386          * and accesses to uCode SRAM.
 387          */
 388         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 389                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 390                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 391                            25000);
 392         if (ret < 0) {
 393                 IWL_ERR(trans, "Failed to init the card\n");
 394                 return ret;
 395         }
 396
 397         if (trans->cfg->host_interrupt_operation_mode) {
 398                 /*
 399                  * This is a bit of an abuse - This is needed for 7260 / 3160
 400                  * only check host_interrupt_operation_mode even if this is
 401                  * not related to host_interrupt_operation_mode.
 402                  *
 403                  * Enable the oscillator to count wake up time for L1 exit. This
 404                  * consumes slightly more power (100uA) - but allows to be sure
 405                  * that we wake up from L1 on time.
 406                  *
 407                  * This looks weird: read twice the same register, discard the
 408                  * value, set a bit, and yet again, read that same register
 409                  * just to discard the value. But that's the way the hardware
 410                  * seems to like it.
 411                  */
 412                 iwl_read_prph(trans, OSC_CLK);
 413                 iwl_read_prph(trans, OSC_CLK);
 414                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 415                 iwl_read_prph(trans, OSC_CLK);
 416                 iwl_read_prph(trans, OSC_CLK);
 417         }
 418
 419         /*
 420          * Enable DMA clock and wait for it to stabilize.
 421          *
 422          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 423          * bits do not disable clocks.  This preserves any hardware
 424          * bits already set by default in "CLK_CTRL_REG" after reset.
 425          */
 426         if (!trans->cfg->apmg_not_supported) {
 427                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 428                                APMG_CLK_VAL_DMA_CLK_RQT);
 429                 udelay(20);
 430
 431                 /* Disable L1-Active */
 432                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 433                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 434
 435                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 436                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 437                                APMG_RTC_INT_STT_RFKILL);
 438         }
 439
 440         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 441
 442         return 0;
 443 }
 444
 445 /*
 446  * Enable LP XTAL to avoid HW bug where device may consume much power if
 447  * FW is not loaded after device reset. LP XTAL is disabled by default
 448  * after device HW reset. Do it only if XTAL is fed by internal source.
 449  * Configure device's "persistence" mode to avoid resetting XTAL again when
 450  * SHRD_HW_RST occurs in S3.
 451  */
 452 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 453 {
 454         int ret;
 455         u32 apmg_gp1_reg;
 456         u32 apmg_xtal_cfg_reg;
 457         u32 dl_cfg_reg;
 458
 459         /* Force XTAL ON */
 460         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 461                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 462
 463         iwl_trans_pcie_sw_reset(trans);
 464
 465         /*
 466          * Set "initialization complete" bit to move adapter from
 467          * D0U* --> D0A* (powered-up active) state.
 468          */
 469         iwl_set_bit(trans, CSR_GP_CNTRL,
 470                     BIT(trans->cfg->csr->flag_init_done));
 471
 472         /*
 473          * Wait for clock stabilization; once stabilized, access to
 474          * device-internal resources is possible.
 475          */
 476         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 477                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 478                            BIT(trans->cfg->csr->flag_mac_clock_ready),
 479                            25000);
 480         if (WARN_ON(ret < 0)) {
 481                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 482                 /* Release XTAL ON request */
 483                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 484                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 485                 return;
 486         }
 487
 488         /*
 489          * Clear "disable persistence" to avoid LP XTAL resetting when
 490          * SHRD_HW_RST is applied in S3.
 491          */
 492         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 493                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 494
 495         /*
 496          * Force APMG XTAL to be active to prevent its disabling by HW
 497          * caused by APMG idle state.
 498          */
 499         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 500                                                     SHR_APMG_XTAL_CFG_REG);
 501         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 502                                  apmg_xtal_cfg_reg |
 503                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 504
 505         iwl_trans_pcie_sw_reset(trans);
 506
 507         /* Enable LP XTAL by indirect access through CSR */
 508         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 509         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 510                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 511                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 512
 513         /* Clear delay line clock power up */
 514         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 515         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 516                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 517
 518         /*
 519          * Enable persistence mode to avoid LP XTAL resetting when
 520          * SHRD_HW_RST is applied in S3.
 521          */
 522         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 523                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 524
 525         /*
 526          * Clear "initialization complete" bit to move adapter from
 527          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 528          */
 529         iwl_clear_bit(trans, CSR_GP_CNTRL,
 530                       BIT(trans->cfg->csr->flag_init_done));
 531
 532         /* Activates XTAL resources monitor */
 533         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 534                                  CSR_MONITOR_XTAL_RESOURCES);
 535
 536         /* Release XTAL ON request */
 537         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 538                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 539         udelay(10);
 540
 541         /* Release APMG XTAL */
 542         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 543                                  apmg_xtal_cfg_reg &
 544                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 545 }
 546
 547 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 548 {
 549         int ret;
 550
 551         /* stop device's busmaster DMA activity */
 552         iwl_set_bit(trans, trans->cfg->csr->addr_sw_reset,
 553                     BIT(trans->cfg->csr->flag_stop_master));
 554
 555         ret = iwl_poll_bit(trans, trans->cfg->csr->addr_sw_reset,
 556                            BIT(trans->cfg->csr->flag_master_dis),
 557                            BIT(trans->cfg->csr->flag_master_dis), 100);
 558         if (ret < 0)
 559                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 560
 561         IWL_DEBUG_INFO(trans, "stop master\n");
 562 }
 563
 564 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 565 {
 566         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 567
 568         if (op_mode_leave) {
 569                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 570                         iwl_pcie_apm_init(trans);
 571
 572                 /* inform ME that we are leaving */
 573                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 574                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 575                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 576                 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
 577                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 578                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 579                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 580                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 581                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 582                         mdelay(1);
 583                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 584                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 585                 }
 586                 mdelay(5);
 587         }
 588
 589         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 590
 591         /* Stop device's DMA activity */
 592         iwl_pcie_apm_stop_master(trans);
 593
 594         if (trans->cfg->lp_xtal_workaround) {
 595                 iwl_pcie_apm_lp_xtal_enable(trans);
 596                 return;
 597         }
 598
 599         iwl_trans_pcie_sw_reset(trans);
 600
 601         /*
 602          * Clear "initialization complete" bit to move adapter from
 603          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 604          */
 605         iwl_clear_bit(trans, CSR_GP_CNTRL,
 606                       BIT(trans->cfg->csr->flag_init_done));
 607 }
 608
 609 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 610 {
 611         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 612         int ret;
 613
 614         /* nic_init */
 615         spin_lock(&trans_pcie->irq_lock);
 616         ret = iwl_pcie_apm_init(trans);
 617         spin_unlock(&trans_pcie->irq_lock);
 618
 619         if (ret)
 620                 return ret;
 621
 622         iwl_pcie_set_pwr(trans, false);
 623
 624         iwl_op_mode_nic_config(trans->op_mode);
 625
 626         /* Allocate the RX queue, or reset if it is already allocated */
 627         iwl_pcie_rx_init(trans);
 628
 629         /* Allocate or reset and init all Tx and Command queues */
 630         if (iwl_pcie_tx_init(trans))
 631                 return -ENOMEM;
 632
 633         if (trans->cfg->base_params->shadow_reg_enable) {
 634                 /* enable shadow regs in HW */
 635                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 636                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 637         }
 638
 639         return 0;
 640 }
 641
 642 #define HW_READY_TIMEOUT (50)
 643
 644 /* Note: returns poll_bit return value, which is >= 0 if success */
 645 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 646 {
 647         int ret;
 648
 649         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 650                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 651
 652         /* See if we got it */
 653         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 654                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 655                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 656                            HW_READY_TIMEOUT);
 657
 658         if (ret >= 0)
 659                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 660
 661         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 662         return ret;
 663 }
 664
 665 /* Note: returns standard 0/-ERROR code */
 666 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 667 {
 668         int ret;
 669         int iter;
 670
 671         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 672
 673         ret = iwl_pcie_set_hw_ready(trans);
 674         /* If the card is ready, exit 0 */
 675         if (ret >= 0)
 676                 return 0;
 677
 678         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 679                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 680         usleep_range(1000, 2000);
 681
 682         for (iter = 0; iter < 10; iter++) {
 683                 int t = 0;
 684
 685                 /* If HW is not ready, prepare the conditions to check again */
 686                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 687                             CSR_HW_IF_CONFIG_REG_PREPARE);
 688
 689                 do {
 690                         ret = iwl_pcie_set_hw_ready(trans);
 691                         if (ret >= 0)
 692                                 return 0;
 693
 694                         usleep_range(200, 1000);
 695                         t += 200;
 696                 } while (t < 150000);
 697                 msleep(25);
 698         }
 699
 700         IWL_ERR(trans, "Couldn't prepare the card\n");
 701
 702         return ret;
 703 }
 704
 705 /*
 706  * ucode
 707  */
 708 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 709                                             u32 dst_addr, dma_addr_t phy_addr,
 710                                             u32 byte_cnt)
 711 {
 712         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 713                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 714
 715         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 716                     dst_addr);
 717
 718         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 719                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 720
 721         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 722                     (iwl_get_dma_hi_addr(phy_addr)
 723                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 724
 725         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 726                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 727                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 728                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 729
 730         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 731                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 732                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 733                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 734 }
 735
 736 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 737                                         u32 dst_addr, dma_addr_t phy_addr,
 738                                         u32 byte_cnt)
 739 {
 740         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 741         unsigned long flags;
 742         int ret;
 743
 744         trans_pcie->ucode_write_complete = false;
 745
 746         if (!iwl_trans_grab_nic_access(trans, &flags))
 747                 return -EIO;
 748
 749         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 750                                         byte_cnt);
 751         iwl_trans_release_nic_access(trans, &flags);
 752
 753         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 754                                  trans_pcie->ucode_write_complete, 5 * HZ);
 755         if (!ret) {
 756                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 757                 iwl_trans_pcie_dump_regs(trans);
 758                 return -ETIMEDOUT;
 759         }
 760
 761         return 0;
 762 }
 763
 764 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 765                             const struct fw_desc *section)
 766 {
 767         u8 *v_addr;
 768         dma_addr_t p_addr;
 769         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 770         int ret = 0;
 771
 772         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 773                      section_num);
 774
 775         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 776                                     GFP_KERNEL | __GFP_NOWARN);
 777         if (!v_addr) {
 778                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 779                 chunk_sz = PAGE_SIZE;
 780                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 781                                             &p_addr, GFP_KERNEL);
 782                 if (!v_addr)
 783                         return -ENOMEM;
 784         }
 785
 786         for (offset = 0; offset < section->len; offset += chunk_sz) {
 787                 u32 copy_size, dst_addr;
 788                 bool extended_addr = false;
 789
 790                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 791                 dst_addr = section->offset + offset;
 792
 793                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 794                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 795                         extended_addr = true;
 796
 797                 if (extended_addr)
 798                         iwl_set_bits_prph(trans, LMPM_CHICK,
 799                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 800
 801                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 802                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 803                                                    copy_size);
 804
 805                 if (extended_addr)
 806                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 807                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 808
 809                 if (ret) {
 810                         IWL_ERR(trans,
 811                                 "Could not load the [%d] uCode section\n",
 812                                 section_num);
 813                         break;
 814                 }
 815         }
 816
 817         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 818         return ret;
 819 }
 820
 821 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 822                                            const struct fw_img *image,
 823                                            int cpu,
 824                                            int *first_ucode_section)
 825 {
 826         int shift_param;
 827         int i, ret = 0, sec_num = 0x1;
 828         u32 val, last_read_idx = 0;
 829
 830         if (cpu == 1) {
 831                 shift_param = 0;
 832                 *first_ucode_section = 0;
 833         } else {
 834                 shift_param = 16;
 835                 (*first_ucode_section)++;
 836         }
 837
 838         for (i = *first_ucode_section; i < image->num_sec; i++) {
 839                 last_read_idx = i;
 840
 841                 /*
 842                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 843                  * CPU1 to CPU2.
 844                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 845                  * CPU2 non paged to CPU2 paging sec.
 846                  */
 847                 if (!image->sec[i].data ||
 848                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 849                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 850                         IWL_DEBUG_FW(trans,
 851                                      "Break since Data not valid or Empty section, sec = %d\n",
 852                                      i);
 853                         break;
 854                 }
 855
 856                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 857                 if (ret)
 858                         return ret;
 859
 860                 /* Notify ucode of loaded section number and status */
 861                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 862                 val = val | (sec_num << shift_param);
 863                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 864
 865                 sec_num = (sec_num << 1) | 0x1;
 866         }
 867
 868         *first_ucode_section = last_read_idx;
 869
 870         iwl_enable_interrupts(trans);
 871
 872         if (trans->cfg->use_tfh) {
 873                 if (cpu == 1)
 874                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 875                                        0xFFFF);
 876                 else
 877                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 878                                        0xFFFFFFFF);
 879         } else {
 880                 if (cpu == 1)
 881                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 882                                            0xFFFF);
 883                 else
 884                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 885                                            0xFFFFFFFF);
 886         }
 887
 888         return 0;
 889 }
 890
 891 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 892                                       const struct fw_img *image,
 893                                       int cpu,
 894                                       int *first_ucode_section)
 895 {
 896         int i, ret = 0;
 897         u32 last_read_idx = 0;
 898
 899         if (cpu == 1)
 900                 *first_ucode_section = 0;
 901         else
 902                 (*first_ucode_section)++;
 903
 904         for (i = *first_ucode_section; i < image->num_sec; i++) {
 905                 last_read_idx = i;
 906
 907                 /*
 908                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 909                  * CPU1 to CPU2.
 910                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 911                  * CPU2 non paged to CPU2 paging sec.
 912                  */
 913                 if (!image->sec[i].data ||
 914                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 915                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 916                         IWL_DEBUG_FW(trans,
 917                                      "Break since Data not valid or Empty section, sec = %d\n",
 918                                      i);
 919                         break;
 920                 }
 921
 922                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 923                 if (ret)
 924                         return ret;
 925         }
 926
 927         *first_ucode_section = last_read_idx;
 928
 929         return 0;
 930 }
 931
 932 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 933 {
 934         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 935         const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg_dest_tlv;
 936         int i;
 937
 938         IWL_INFO(trans, "Applying debug destination %s\n",
 939                  get_fw_dbg_mode_string(dest->monitor_mode));
 940
 941         if (dest->monitor_mode == EXTERNAL_MODE)
 942                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 943         else
 944                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 945
 946         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 947                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 948                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 949
 950                 switch (dest->reg_ops[i].op) {
 951                 case CSR_ASSIGN:
 952                         iwl_write32(trans, addr, val);
 953                         break;
 954                 case CSR_SETBIT:
 955                         iwl_set_bit(trans, addr, BIT(val));
 956                         break;
 957                 case CSR_CLEARBIT:
 958                         iwl_clear_bit(trans, addr, BIT(val));
 959                         break;
 960                 case PRPH_ASSIGN:
 961                         iwl_write_prph(trans, addr, val);
 962                         break;
 963                 case PRPH_SETBIT:
 964                         iwl_set_bits_prph(trans, addr, BIT(val));
 965                         break;
 966                 case PRPH_CLEARBIT:
 967                         iwl_clear_bits_prph(trans, addr, BIT(val));
 968                         break;
 969                 case PRPH_BLOCKBIT:
 970                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 971                                 IWL_ERR(trans,
 972                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 973                                         val, addr);
 974                                 goto monitor;
 975                         }
 976                         break;
 977                 default:
 978                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 979                                 dest->reg_ops[i].op);
 980                         break;
 981                 }
 982         }
 983
 984 monitor:
 985         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 986                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 987                                trans_pcie->fw_mon_phys >> dest->base_shift);
 988                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 989                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 990                                        (trans_pcie->fw_mon_phys +
 991                                         trans_pcie->fw_mon_size - 256) >>
 992                                                 dest->end_shift);
 993                 else
 994                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 995                                        (trans_pcie->fw_mon_phys +
 996                                         trans_pcie->fw_mon_size) >>
 997                                                 dest->end_shift);
 998         }
 999 }
1000
1001 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
1002                                 const struct fw_img *image)
1003 {
1004         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1005         int ret = 0;
1006         int first_ucode_section;
1007
1008         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1009                      image->is_dual_cpus ? "Dual" : "Single");
1010
1011         /* load to FW the binary non secured sections of CPU1 */
1012         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
1013         if (ret)
1014                 return ret;
1015
1016         if (image->is_dual_cpus) {
1017                 /* set CPU2 header address */
1018                 iwl_write_prph(trans,
1019                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1020                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1021
1022                 /* load to FW the binary sections of CPU2 */
1023                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1024                                                  &first_ucode_section);
1025                 if (ret)
1026                         return ret;
1027         }
1028
1029         /* supported for 7000 only for the moment */
1030         if (iwlwifi_mod_params.fw_monitor &&
1031             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1032                 iwl_pcie_alloc_fw_monitor(trans, 0);
1033
1034                 if (trans_pcie->fw_mon_size) {
1035                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1036                                        trans_pcie->fw_mon_phys >> 4);
1037                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1038                                        (trans_pcie->fw_mon_phys +
1039                                         trans_pcie->fw_mon_size) >> 4);
1040                 }
1041         } else if (trans->dbg_dest_tlv) {
1042                 iwl_pcie_apply_destination(trans);
1043         }
1044
1045         iwl_enable_interrupts(trans);
1046
1047         /* release CPU reset */
1048         iwl_write32(trans, CSR_RESET, 0);
1049
1050         return 0;
1051 }
1052
1053 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1054                                           const struct fw_img *image)
1055 {
1056         int ret = 0;
1057         int first_ucode_section;
1058
1059         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1060                      image->is_dual_cpus ? "Dual" : "Single");
1061
1062         if (trans->dbg_dest_tlv)
1063                 iwl_pcie_apply_destination(trans);
1064
1065         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
1066                         iwl_read_prph(trans, WFPM_GP2));
1067
1068         /*
1069          * Set default value. On resume reading the values that were
1070          * zeored can provide debug data on the resume flow.
1071          * This is for debugging only and has no functional impact.
1072          */
1073         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
1074
1075         /* configure the ucode to be ready to get the secured image */
1076         /* release CPU reset */
1077         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1078
1079         /* load to FW the binary Secured sections of CPU1 */
1080         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1081                                               &first_ucode_section);
1082         if (ret)
1083                 return ret;
1084
1085         /* load to FW the binary sections of CPU2 */
1086         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1087                                                &first_ucode_section);
1088 }
1089
1090 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
1091 {
1092         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1093         bool hw_rfkill = iwl_is_rfkill_set(trans);
1094         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1095         bool report;
1096
1097         if (hw_rfkill) {
1098                 set_bit(STATUS_RFKILL_HW, &trans->status);
1099                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1100         } else {
1101                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1102                 if (trans_pcie->opmode_down)
1103                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1104         }
1105
1106         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1107
1108         if (prev != report)
1109                 iwl_trans_pcie_rf_kill(trans, report);
1110
1111         return hw_rfkill;
1112 }
1113
1114 struct iwl_causes_list {
1115         u32 cause_num;
1116         u32 mask_reg;
1117         u8 addr;
1118 };
1119
1120 static struct iwl_causes_list causes_list[] = {
1121         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1122         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1123         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1124         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1125         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1126         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1127         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1128         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1129         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1130         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1131         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1132         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1133         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1134         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1135 };
1136
1137 static struct iwl_causes_list causes_list_v2[] = {
1138         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1139         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1140         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1141         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1142         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1143         {MSIX_HW_INT_CAUSES_REG_IPC,            CSR_MSIX_HW_INT_MASK_AD, 0x11},
1144         {MSIX_HW_INT_CAUSES_REG_SW_ERR_V2,      CSR_MSIX_HW_INT_MASK_AD, 0x15},
1145         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1146         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1147         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1148         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1149         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1150         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1151         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1152 };
1153
1154 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1155 {
1156         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1157         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1158         int i, arr_size =
1159                 (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1160                 ARRAY_SIZE(causes_list) : ARRAY_SIZE(causes_list_v2);
1161
1162         /*
1163          * Access all non RX causes and map them to the default irq.
1164          * In case we are missing at least one interrupt vector,
1165          * the first interrupt vector will serve non-RX and FBQ causes.
1166          */
1167         for (i = 0; i < arr_size; i++) {
1168                 struct iwl_causes_list *causes =
1169                         (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560) ?
1170                         causes_list : causes_list_v2;
1171
1172                 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val);
1173                 iwl_clear_bit(trans, causes[i].mask_reg,
1174                               causes[i].cause_num);
1175         }
1176 }
1177
1178 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1179 {
1180         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1181         u32 offset =
1182                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1183         u32 val, idx;
1184
1185         /*
1186          * The first RX queue - fallback queue, which is designated for
1187          * management frame, command responses etc, is always mapped to the
1188          * first interrupt vector. The other RX queues are mapped to
1189          * the other (N - 2) interrupt vectors.
1190          */
1191         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1192         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1193                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1194                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1195                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1196         }
1197         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1198
1199         val = MSIX_FH_INT_CAUSES_Q(0);
1200         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1201                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1202         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1203
1204         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1205                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1206 }
1207
1208 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1209 {
1210         struct iwl_trans *trans = trans_pcie->trans;
1211
1212         if (!trans_pcie->msix_enabled) {
1213                 if (trans->cfg->mq_rx_supported &&
1214                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1215                         iwl_write_prph(trans, UREG_CHICK,
1216                                        UREG_CHICK_MSI_ENABLE);
1217                 return;
1218         }
1219         /*
1220          * The IVAR table needs to be configured again after reset,
1221          * but if the device is disabled, we can't write to
1222          * prph.
1223          */
1224         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1225                 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1226
1227         /*
1228          * Each cause from the causes list above and the RX causes is
1229          * represented as a byte in the IVAR table. The first nibble
1230          * represents the bound interrupt vector of the cause, the second
1231          * represents no auto clear for this cause. This will be set if its
1232          * interrupt vector is bound to serve other causes.
1233          */
1234         iwl_pcie_map_rx_causes(trans);
1235
1236         iwl_pcie_map_non_rx_causes(trans);
1237 }
1238
1239 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1240 {
1241         struct iwl_trans *trans = trans_pcie->trans;
1242
1243         iwl_pcie_conf_msix_hw(trans_pcie);
1244
1245         if (!trans_pcie->msix_enabled)
1246                 return;
1247
1248         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1249         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1250         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1251         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1252 }
1253
1254 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1255 {
1256         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1257
1258         lockdep_assert_held(&trans_pcie->mutex);
1259
1260         if (trans_pcie->is_down)
1261                 return;
1262
1263         trans_pcie->is_down = true;
1264
1265         /* Stop dbgc before stopping device */
1266         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1267                 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1268         } else {
1269                 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1270                 udelay(100);
1271                 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1272         }
1273
1274         /* tell the device to stop sending interrupts */
1275         iwl_disable_interrupts(trans);
1276
1277         /* device going down, Stop using ICT table */
1278         iwl_pcie_disable_ict(trans);
1279
1280         /*
1281          * If a HW restart happens during firmware loading,
1282          * then the firmware loading might call this function
1283          * and later it might be called again due to the
1284          * restart. So don't process again if the device is
1285          * already dead.
1286          */
1287         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1288                 IWL_DEBUG_INFO(trans,
1289                                "DEVICE_ENABLED bit was set and is now cleared\n");
1290                 iwl_pcie_tx_stop(trans);
1291                 iwl_pcie_rx_stop(trans);
1292
1293                 /* Power-down device's busmaster DMA clocks */
1294                 if (!trans->cfg->apmg_not_supported) {
1295                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1296                                        APMG_CLK_VAL_DMA_CLK_RQT);
1297                         udelay(5);
1298                 }
1299         }
1300
1301         /* Make sure (redundant) we've released our request to stay awake */
1302         iwl_clear_bit(trans, CSR_GP_CNTRL,
1303                       BIT(trans->cfg->csr->flag_mac_access_req));
1304
1305         /* Stop the device, and put it in low power state */
1306         iwl_pcie_apm_stop(trans, false);
1307
1308         iwl_trans_pcie_sw_reset(trans);
1309
1310         /*
1311          * Upon stop, the IVAR table gets erased, so msi-x won't
1312          * work. This causes a bug in RF-KILL flows, since the interrupt
1313          * that enables radio won't fire on the correct irq, and the
1314          * driver won't be able to handle the interrupt.
1315          * Configure the IVAR table again after reset.
1316          */
1317         iwl_pcie_conf_msix_hw(trans_pcie);
1318
1319         /*
1320          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1321          * This is a bug in certain verions of the hardware.
1322          * Certain devices also keep sending HW RF kill interrupt all
1323          * the time, unless the interrupt is ACKed even if the interrupt
1324          * should be masked. Re-ACK all the interrupts here.
1325          */
1326         iwl_disable_interrupts(trans);
1327
1328         /* clear all status bits */
1329         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1330         clear_bit(STATUS_INT_ENABLED, &trans->status);
1331         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1332
1333         /*
1334          * Even if we stop the HW, we still want the RF kill
1335          * interrupt
1336          */
1337         iwl_enable_rfkill_int(trans);
1338
1339         /* re-take ownership to prevent other users from stealing the device */
1340         iwl_pcie_prepare_card_hw(trans);
1341 }
1342
1343 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1344 {
1345         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1346
1347         if (trans_pcie->msix_enabled) {
1348                 int i;
1349
1350                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1351                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1352         } else {
1353                 synchronize_irq(trans_pcie->pci_dev->irq);
1354         }
1355 }
1356
1357 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1358                                    const struct fw_img *fw, bool run_in_rfkill)
1359 {
1360         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1361         bool hw_rfkill;
1362         int ret;
1363
1364         /* This may fail if AMT took ownership of the device */
1365         if (iwl_pcie_prepare_card_hw(trans)) {
1366                 IWL_WARN(trans, "Exit HW not ready\n");
1367                 return -EIO;
1368         }
1369
1370         iwl_enable_rfkill_int(trans);
1371
1372         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1373
1374         /*
1375          * We enabled the RF-Kill interrupt and the handler may very
1376          * well be running. Disable the interrupts to make sure no other
1377          * interrupt can be fired.
1378          */
1379         iwl_disable_interrupts(trans);
1380
1381         /* Make sure it finished running */
1382         iwl_pcie_synchronize_irqs(trans);
1383
1384         mutex_lock(&trans_pcie->mutex);
1385
1386         /* If platform's RF_KILL switch is NOT set to KILL */
1387         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1388         if (hw_rfkill && !run_in_rfkill) {
1389                 ret = -ERFKILL;
1390                 goto out;
1391         }
1392
1393         /* Someone called stop_device, don't try to start_fw */
1394         if (trans_pcie->is_down) {
1395                 IWL_WARN(trans,
1396                          "Can't start_fw since the HW hasn't been started\n");
1397                 ret = -EIO;
1398                 goto out;
1399         }
1400
1401         /* make sure rfkill handshake bits are cleared */
1402         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1403         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1404                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1405
1406         /* clear (again), then enable host interrupts */
1407         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1408
1409         ret = iwl_pcie_nic_init(trans);
1410         if (ret) {
1411                 IWL_ERR(trans, "Unable to init nic\n");
1412                 goto out;
1413         }
1414
1415         /*
1416          * Now, we load the firmware and don't want to be interrupted, even
1417          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1418          * FH_TX interrupt which is needed to load the firmware). If the
1419          * RF-Kill switch is toggled, we will find out after having loaded
1420          * the firmware and return the proper value to the caller.
1421          */
1422         iwl_enable_fw_load_int(trans);
1423
1424         /* really make sure rfkill handshake bits are cleared */
1425         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1426         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1427
1428         /* Load the given image to the HW */
1429         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1430                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1431         else
1432                 ret = iwl_pcie_load_given_ucode(trans, fw);
1433
1434         /* re-check RF-Kill state since we may have missed the interrupt */
1435         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1436         if (hw_rfkill && !run_in_rfkill)
1437                 ret = -ERFKILL;
1438
1439 out:
1440         mutex_unlock(&trans_pcie->mutex);
1441         return ret;
1442 }
1443
1444 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1445 {
1446         iwl_pcie_reset_ict(trans);
1447         iwl_pcie_tx_start(trans, scd_addr);
1448 }
1449
1450 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1451                                        bool was_in_rfkill)
1452 {
1453         bool hw_rfkill;
1454
1455         /*
1456          * Check again since the RF kill state may have changed while
1457          * all the interrupts were disabled, in this case we couldn't
1458          * receive the RF kill interrupt and update the state in the
1459          * op_mode.
1460          * Don't call the op_mode if the rkfill state hasn't changed.
1461          * This allows the op_mode to call stop_device from the rfkill
1462          * notification without endless recursion. Under very rare
1463          * circumstances, we might have a small recursion if the rfkill
1464          * state changed exactly now while we were called from stop_device.
1465          * This is very unlikely but can happen and is supported.
1466          */
1467         hw_rfkill = iwl_is_rfkill_set(trans);
1468         if (hw_rfkill) {
1469                 set_bit(STATUS_RFKILL_HW, &trans->status);
1470                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1471         } else {
1472                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1473                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1474         }
1475         if (hw_rfkill != was_in_rfkill)
1476                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1477 }
1478
1479 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1480 {
1481         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1482         bool was_in_rfkill;
1483
1484         mutex_lock(&trans_pcie->mutex);
1485         trans_pcie->opmode_down = true;
1486         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1487         _iwl_trans_pcie_stop_device(trans, low_power);
1488         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1489         mutex_unlock(&trans_pcie->mutex);
1490 }
1491
1492 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1493 {
1494         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1495                 IWL_TRANS_GET_PCIE_TRANS(trans);
1496
1497         lockdep_assert_held(&trans_pcie->mutex);
1498
1499         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1500                  state ? "disabled" : "enabled");
1501         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1502                 if (trans->cfg->gen2)
1503                         _iwl_trans_pcie_gen2_stop_device(trans, true);
1504                 else
1505                         _iwl_trans_pcie_stop_device(trans, true);
1506         }
1507 }
1508
1509 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1510                                       bool reset)
1511 {
1512         if (!reset) {
1513                 /* Enable persistence mode to avoid reset */
1514                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1515                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1516         }
1517
1518         iwl_disable_interrupts(trans);
1519
1520         /*
1521          * in testing mode, the host stays awake and the
1522          * hardware won't be reset (not even partially)
1523          */
1524         if (test)
1525                 return;
1526
1527         iwl_pcie_disable_ict(trans);
1528
1529         iwl_pcie_synchronize_irqs(trans);
1530
1531         iwl_clear_bit(trans, CSR_GP_CNTRL,
1532                       BIT(trans->cfg->csr->flag_mac_access_req));
1533         iwl_clear_bit(trans, CSR_GP_CNTRL,
1534                       BIT(trans->cfg->csr->flag_init_done));
1535
1536         iwl_pcie_enable_rx_wake(trans, false);
1537
1538         if (reset) {
1539                 /*
1540                  * reset TX queues -- some of their registers reset during S3
1541                  * so if we don't reset everything here the D3 image would try
1542                  * to execute some invalid memory upon resume
1543                  */
1544                 iwl_trans_pcie_tx_reset(trans);
1545         }
1546
1547         iwl_pcie_set_pwr(trans, true);
1548 }
1549
1550 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1551                                     enum iwl_d3_status *status,
1552                                     bool test,  bool reset)
1553 {
1554         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1555         u32 val;
1556         int ret;
1557
1558         if (test) {
1559                 iwl_enable_interrupts(trans);
1560                 *status = IWL_D3_STATUS_ALIVE;
1561                 return 0;
1562         }
1563
1564         iwl_pcie_enable_rx_wake(trans, true);
1565
1566         iwl_set_bit(trans, CSR_GP_CNTRL,
1567                     BIT(trans->cfg->csr->flag_mac_access_req));
1568         iwl_set_bit(trans, CSR_GP_CNTRL,
1569                     BIT(trans->cfg->csr->flag_init_done));
1570
1571         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1572                 udelay(2);
1573
1574         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1575                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1576                            BIT(trans->cfg->csr->flag_mac_clock_ready),
1577                            25000);
1578         if (ret < 0) {
1579                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1580                 return ret;
1581         }
1582
1583         /*
1584          * Reconfigure IVAR table in case of MSIX or reset ict table in
1585          * MSI mode since HW reset erased it.
1586          * Also enables interrupts - none will happen as
1587          * the device doesn't know we're waking it up, only when
1588          * the opmode actually tells it after this call.
1589          */
1590         iwl_pcie_conf_msix_hw(trans_pcie);
1591         if (!trans_pcie->msix_enabled)
1592                 iwl_pcie_reset_ict(trans);
1593         iwl_enable_interrupts(trans);
1594
1595         iwl_pcie_set_pwr(trans, false);
1596
1597         if (!reset) {
1598                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1599                               BIT(trans->cfg->csr->flag_mac_access_req));
1600         } else {
1601                 iwl_trans_pcie_tx_reset(trans);
1602
1603                 ret = iwl_pcie_rx_init(trans);
1604                 if (ret) {
1605                         IWL_ERR(trans,
1606                                 "Failed to resume the device (RX reset)\n");
1607                         return ret;
1608                 }
1609         }
1610
1611         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1612                         iwl_read_prph(trans, WFPM_GP2));
1613
1614         val = iwl_read32(trans, CSR_RESET);
1615         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1616                 *status = IWL_D3_STATUS_RESET;
1617         else
1618                 *status = IWL_D3_STATUS_ALIVE;
1619
1620         return 0;
1621 }
1622
1623 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1624                                         struct iwl_trans *trans)
1625 {
1626         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1627         int max_irqs, num_irqs, i, ret;
1628         u16 pci_cmd;
1629
1630         if (!trans->cfg->mq_rx_supported)
1631                 goto enable_msi;
1632
1633         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1634         for (i = 0; i < max_irqs; i++)
1635                 trans_pcie->msix_entries[i].entry = i;
1636
1637         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1638                                          MSIX_MIN_INTERRUPT_VECTORS,
1639                                          max_irqs);
1640         if (num_irqs < 0) {
1641                 IWL_DEBUG_INFO(trans,
1642                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1643                                num_irqs);
1644                 goto enable_msi;
1645         }
1646         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1647
1648         IWL_DEBUG_INFO(trans,
1649                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1650                        num_irqs);
1651
1652         /*
1653          * In case the OS provides fewer interrupts than requested, different
1654          * causes will share the same interrupt vector as follows:
1655          * One interrupt less: non rx causes shared with FBQ.
1656          * Two interrupts less: non rx causes shared with FBQ and RSS.
1657          * More than two interrupts: we will use fewer RSS queues.
1658          */
1659         if (num_irqs <= max_irqs - 2) {
1660                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1661                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1662                         IWL_SHARED_IRQ_FIRST_RSS;
1663         } else if (num_irqs == max_irqs - 1) {
1664                 trans_pcie->trans->num_rx_queues = num_irqs;
1665                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1666         } else {
1667                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1668         }
1669         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1670
1671         trans_pcie->alloc_vecs = num_irqs;
1672         trans_pcie->msix_enabled = true;
1673         return;
1674
1675 enable_msi:
1676         ret = pci_enable_msi(pdev);
1677         if (ret) {
1678                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1679                 /* enable rfkill interrupt: hw bug w/a */
1680                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1681                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1682                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1683                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1684                 }
1685         }
1686 }
1687
1688 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1689 {
1690         int iter_rx_q, i, ret, cpu, offset;
1691         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1692
1693         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1694         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1695         offset = 1 + i;
1696         for (; i < iter_rx_q ; i++) {
1697                 /*
1698                  * Get the cpu prior to the place to search
1699                  * (i.e. return will be > i - 1).
1700                  */
1701                 cpu = cpumask_next(i - offset, cpu_online_mask);
1702                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1703                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1704                                             &trans_pcie->affinity_mask[i]);
1705                 if (ret)
1706                         IWL_ERR(trans_pcie->trans,
1707                                 "Failed to set affinity mask for IRQ %d\n",
1708                                 i);
1709         }
1710 }
1711
1712 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1713                                       struct iwl_trans_pcie *trans_pcie)
1714 {
1715         int i;
1716
1717         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1718                 int ret;
1719                 struct msix_entry *msix_entry;
1720                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1721
1722                 if (!qname)
1723                         return -ENOMEM;
1724
1725                 msix_entry = &trans_pcie->msix_entries[i];
1726                 ret = devm_request_threaded_irq(&pdev->dev,
1727                                                 msix_entry->vector,
1728                                                 iwl_pcie_msix_isr,
1729                                                 (i == trans_pcie->def_irq) ?
1730                                                 iwl_pcie_irq_msix_handler :
1731                                                 iwl_pcie_irq_rx_msix_handler,
1732                                                 IRQF_SHARED,
1733                                                 qname,
1734                                                 msix_entry);
1735                 if (ret) {
1736                         IWL_ERR(trans_pcie->trans,
1737                                 "Error allocating IRQ %d\n", i);
1738
1739                         return ret;
1740                 }
1741         }
1742         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1743
1744         return 0;
1745 }
1746
1747 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1748 {
1749         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1750         u32 hpm;
1751         int err;
1752
1753         lockdep_assert_held(&trans_pcie->mutex);
1754
1755         err = iwl_pcie_prepare_card_hw(trans);
1756         if (err) {
1757                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1758                 return err;
1759         }
1760
1761         hpm = iwl_trans_read_prph(trans, HPM_DEBUG);
1762         if (hpm != 0xa5a5a5a0 && (hpm & PERSISTENCE_BIT)) {
1763                 if (iwl_trans_read_prph(trans, PREG_PRPH_WPROT_0) &
1764                     PREG_WFPM_ACCESS) {
1765                         IWL_ERR(trans,
1766                                 "Error, can not clear persistence bit\n");
1767                         return -EPERM;
1768                 }
1769                 iwl_trans_write_prph(trans, HPM_DEBUG, hpm & ~PERSISTENCE_BIT);
1770         }
1771
1772         iwl_trans_pcie_sw_reset(trans);
1773
1774         err = iwl_pcie_apm_init(trans);
1775         if (err)
1776                 return err;
1777
1778         iwl_pcie_init_msix(trans_pcie);
1779
1780         /* From now on, the op_mode will be kept updated about RF kill state */
1781         iwl_enable_rfkill_int(trans);
1782
1783         trans_pcie->opmode_down = false;
1784
1785         /* Set is_down to false here so that...*/
1786         trans_pcie->is_down = false;
1787
1788         /* ...rfkill can call stop_device and set it false if needed */
1789         iwl_pcie_check_hw_rf_kill(trans);
1790
1791         /* Make sure we sync here, because we'll need full access later */
1792         if (low_power)
1793                 pm_runtime_resume(trans->dev);
1794
1795         return 0;
1796 }
1797
1798 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1799 {
1800         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1801         int ret;
1802
1803         mutex_lock(&trans_pcie->mutex);
1804         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1805         mutex_unlock(&trans_pcie->mutex);
1806
1807         return ret;
1808 }
1809
1810 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1811 {
1812         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1813
1814         mutex_lock(&trans_pcie->mutex);
1815
1816         /* disable interrupts - don't enable HW RF kill interrupt */
1817         iwl_disable_interrupts(trans);
1818
1819         iwl_pcie_apm_stop(trans, true);
1820
1821         iwl_disable_interrupts(trans);
1822
1823         iwl_pcie_disable_ict(trans);
1824
1825         mutex_unlock(&trans_pcie->mutex);
1826
1827         iwl_pcie_synchronize_irqs(trans);
1828 }
1829
1830 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1831 {
1832         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1833 }
1834
1835 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1836 {
1837         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1838 }
1839
1840 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1841 {
1842         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1843 }
1844
1845 static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans)
1846 {
1847         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1848                 return 0x00FFFFFF;
1849         else
1850                 return 0x000FFFFF;
1851 }
1852
1853 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1854 {
1855         u32 mask = iwl_trans_pcie_prph_msk(trans);
1856
1857         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1858                                ((reg & mask) | (3 << 24)));
1859         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1860 }
1861
1862 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1863                                       u32 val)
1864 {
1865         u32 mask = iwl_trans_pcie_prph_msk(trans);
1866
1867         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1868                                ((addr & mask) | (3 << 24)));
1869         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1870 }
1871
1872 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1873                                      const struct iwl_trans_config *trans_cfg)
1874 {
1875         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1876
1877         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1878         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1879         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1880         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1881                 trans_pcie->n_no_reclaim_cmds = 0;
1882         else
1883                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1884         if (trans_pcie->n_no_reclaim_cmds)
1885                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1886                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1887
1888         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1889         trans_pcie->rx_page_order =
1890                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1891
1892         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1893         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1894         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1895
1896         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1897         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1898
1899         trans->command_groups = trans_cfg->command_groups;
1900         trans->command_groups_size = trans_cfg->command_groups_size;
1901
1902         /* Initialize NAPI here - it should be before registering to mac80211
1903          * in the opmode but after the HW struct is allocated.
1904          * As this function may be called again in some corner cases don't
1905          * do anything if NAPI was already initialized.
1906          */
1907         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1908                 init_dummy_netdev(&trans_pcie->napi_dev);
1909 }
1910
1911 void iwl_trans_pcie_free(struct iwl_trans *trans)
1912 {
1913         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1914         int i;
1915
1916         iwl_pcie_synchronize_irqs(trans);
1917
1918         if (trans->cfg->gen2)
1919                 iwl_pcie_gen2_tx_free(trans);
1920         else
1921                 iwl_pcie_tx_free(trans);
1922         iwl_pcie_rx_free(trans);
1923
1924         if (trans_pcie->rba.alloc_wq) {
1925                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1926                 trans_pcie->rba.alloc_wq = NULL;
1927         }
1928
1929         if (trans_pcie->msix_enabled) {
1930                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1931                         irq_set_affinity_hint(
1932                                 trans_pcie->msix_entries[i].vector,
1933                                 NULL);
1934                 }
1935
1936                 trans_pcie->msix_enabled = false;
1937         } else {
1938                 iwl_pcie_free_ict(trans);
1939         }
1940
1941         iwl_pcie_free_fw_monitor(trans);
1942
1943         for_each_possible_cpu(i) {
1944                 struct iwl_tso_hdr_page *p =
1945                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1946
1947                 if (p->page)
1948                         __free_page(p->page);
1949         }
1950
1951         free_percpu(trans_pcie->tso_hdr_page);
1952         mutex_destroy(&trans_pcie->mutex);
1953         iwl_trans_free(trans);
1954 }
1955
1956 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1957 {
1958         if (state)
1959                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1960         else
1961                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1962 }
1963
1964 struct iwl_trans_pcie_removal {
1965         struct pci_dev *pdev;
1966         struct work_struct work;
1967 };
1968
1969 static void iwl_trans_pcie_removal_wk(struct work_struct *wk)
1970 {
1971         struct iwl_trans_pcie_removal *removal =
1972                 container_of(wk, struct iwl_trans_pcie_removal, work);
1973         struct pci_dev *pdev = removal->pdev;
1974         char *prop[] = {"EVENT=INACCESSIBLE", NULL};
1975
1976         dev_err(&pdev->dev, "Device gone - attempting removal\n");
1977         kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop);
1978         pci_lock_rescan_remove();
1979         pci_dev_put(pdev);
1980         pci_stop_and_remove_bus_device(pdev);
1981         pci_unlock_rescan_remove();
1982
1983         kfree(removal);
1984         module_put(THIS_MODULE);
1985 }
1986
1987 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1988                                            unsigned long *flags)
1989 {
1990         int ret;
1991         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1992
1993         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1994
1995         if (trans_pcie->cmd_hold_nic_awake)
1996                 goto out;
1997
1998         /* this bit wakes up the NIC */
1999         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
2000                                  BIT(trans->cfg->csr->flag_mac_access_req));
2001         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
2002                 udelay(2);
2003
2004         /*
2005          * These bits say the device is running, and should keep running for
2006          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
2007          * but they do not indicate that embedded SRAM is restored yet;
2008          * HW with volatile SRAM must save/restore contents to/from
2009          * host DRAM when sleeping/waking for power-saving.
2010          * Each direction takes approximately 1/4 millisecond; with this
2011          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
2012          * series of register accesses are expected (e.g. reading Event Log),
2013          * to keep device from sleeping.
2014          *
2015          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
2016          * SRAM is okay/restored.  We don't check that here because this call
2017          * is just for hardware register access; but GP1 MAC_SLEEP
2018          * check is a good idea before accessing the SRAM of HW with
2019          * volatile SRAM (e.g. reading Event Log).
2020          *
2021          * 5000 series and later (including 1000 series) have non-volatile SRAM,
2022          * and do not save/restore SRAM when power cycling.
2023          */
2024         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
2025                            BIT(trans->cfg->csr->flag_val_mac_access_en),
2026                            (BIT(trans->cfg->csr->flag_mac_clock_ready) |
2027                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
2028         if (unlikely(ret < 0)) {
2029                 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL);
2030
2031                 WARN_ONCE(1,
2032                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
2033                           cntrl);
2034
2035                 iwl_trans_pcie_dump_regs(trans);
2036
2037                 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) {
2038                         struct iwl_trans_pcie_removal *removal;
2039
2040                         if (trans_pcie->scheduled_for_removal)
2041                                 goto err;
2042
2043                         IWL_ERR(trans, "Device gone - scheduling removal!\n");
2044
2045                         /*
2046                          * get a module reference to avoid doing this
2047                          * while unloading anyway and to avoid
2048                          * scheduling a work with code that's being
2049                          * removed.
2050                          */
2051                         if (!try_module_get(THIS_MODULE)) {
2052                                 IWL_ERR(trans,
2053                                         "Module is being unloaded - abort\n");
2054                                 goto err;
2055                         }
2056
2057                         removal = kzalloc(sizeof(*removal), GFP_ATOMIC);
2058                         if (!removal) {
2059                                 module_put(THIS_MODULE);
2060                                 goto err;
2061                         }
2062                         /*
2063                          * we don't need to clear this flag, because
2064                          * the trans will be freed and reallocated.
2065                         */
2066                         trans_pcie->scheduled_for_removal = true;
2067
2068                         removal->pdev = to_pci_dev(trans->dev);
2069                         INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk);
2070                         pci_dev_get(removal->pdev);
2071                         schedule_work(&removal->work);
2072                 } else {
2073                         iwl_write32(trans, CSR_RESET,
2074                                     CSR_RESET_REG_FLAG_FORCE_NMI);
2075                 }
2076
2077 err:
2078                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2079                 return false;
2080         }
2081
2082 out:
2083         /*
2084          * Fool sparse by faking we release the lock - sparse will
2085          * track nic_access anyway.
2086          */
2087         __release(&trans_pcie->reg_lock);
2088         return true;
2089 }
2090
2091 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
2092                                               unsigned long *flags)
2093 {
2094         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2095
2096         lockdep_assert_held(&trans_pcie->reg_lock);
2097
2098         /*
2099          * Fool sparse by faking we acquiring the lock - sparse will
2100          * track nic_access anyway.
2101          */
2102         __acquire(&trans_pcie->reg_lock);
2103
2104         if (trans_pcie->cmd_hold_nic_awake)
2105                 goto out;
2106
2107         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
2108                                    BIT(trans->cfg->csr->flag_mac_access_req));
2109         /*
2110          * Above we read the CSR_GP_CNTRL register, which will flush
2111          * any previous writes, but we need the write that clears the
2112          * MAC_ACCESS_REQ bit to be performed before any other writes
2113          * scheduled on different CPUs (after we drop reg_lock).
2114          */
2115         mmiowb();
2116 out:
2117         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
2118 }
2119
2120 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
2121                                    void *buf, int dwords)
2122 {
2123         unsigned long flags;
2124         int offs = 0;
2125         u32 *vals = buf;
2126
2127         while (offs < dwords) {
2128                 /* limit the time we spin here under lock to 1/2s */
2129                 unsigned long end = jiffies + HZ / 2;
2130                 bool resched = false;
2131
2132                 if (iwl_trans_grab_nic_access(trans, &flags)) {
2133                         iwl_write32(trans, HBUS_TARG_MEM_RADDR,
2134                                     addr + 4 * offs);
2135
2136                         while (offs < dwords) {
2137                                 vals[offs] = iwl_read32(trans,
2138                                                         HBUS_TARG_MEM_RDAT);
2139                                 offs++;
2140
2141                                 if (time_after(jiffies, end)) {
2142                                         resched = true;
2143                                         break;
2144                                 }
2145                         }
2146                         iwl_trans_release_nic_access(trans, &flags);
2147
2148                         if (resched)
2149                                 cond_resched();
2150                 } else {
2151                         return -EBUSY;
2152                 }
2153         }
2154
2155         return 0;
2156 }
2157
2158 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
2159                                     const void *buf, int dwords)
2160 {
2161         unsigned long flags;
2162         int offs, ret = 0;
2163         const u32 *vals = buf;
2164
2165         if (iwl_trans_grab_nic_access(trans, &flags)) {
2166                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
2167                 for (offs = 0; offs < dwords; offs++)
2168                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
2169                                     vals ? vals[offs] : 0);
2170                 iwl_trans_release_nic_access(trans, &flags);
2171         } else {
2172                 ret = -EBUSY;
2173         }
2174         return ret;
2175 }
2176
2177 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
2178                                             unsigned long txqs,
2179                                             bool freeze)
2180 {
2181         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2182         int queue;
2183
2184         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
2185                 struct iwl_txq *txq = trans_pcie->txq[queue];
2186                 unsigned long now;
2187
2188                 spin_lock_bh(&txq->lock);
2189
2190                 now = jiffies;
2191
2192                 if (txq->frozen == freeze)
2193                         goto next_queue;
2194
2195                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2196                                     freeze ? "Freezing" : "Waking", queue);
2197
2198                 txq->frozen = freeze;
2199
2200                 if (txq->read_ptr == txq->write_ptr)
2201                         goto next_queue;
2202
2203                 if (freeze) {
2204                         if (unlikely(time_after(now,
2205                                                 txq->stuck_timer.expires))) {
2206                                 /*
2207                                  * The timer should have fired, maybe it is
2208                                  * spinning right now on the lock.
2209                                  */
2210                                 goto next_queue;
2211                         }
2212                         /* remember how long until the timer fires */
2213                         txq->frozen_expiry_remainder =
2214                                 txq->stuck_timer.expires - now;
2215                         del_timer(&txq->stuck_timer);
2216                         goto next_queue;
2217                 }
2218
2219                 /*
2220                  * Wake a non-empty queue -> arm timer with the
2221                  * remainder before it froze
2222                  */
2223                 mod_timer(&txq->stuck_timer,
2224                           now + txq->frozen_expiry_remainder);
2225
2226 next_queue:
2227                 spin_unlock_bh(&txq->lock);
2228         }
2229 }
2230
2231 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2232 {
2233         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2234         int i;
2235
2236         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2237                 struct iwl_txq *txq = trans_pcie->txq[i];
2238
2239                 if (i == trans_pcie->cmd_queue)
2240                         continue;
2241
2242                 spin_lock_bh(&txq->lock);
2243
2244                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2245                         txq->block--;
2246                         if (!txq->block) {
2247                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2248                                             txq->write_ptr | (i << 8));
2249                         }
2250                 } else if (block) {
2251                         txq->block++;
2252                 }
2253
2254                 spin_unlock_bh(&txq->lock);
2255         }
2256 }
2257
2258 #define IWL_FLUSH_WAIT_MS       2000
2259
2260 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2261 {
2262         u32 txq_id = txq->id;
2263         u32 status;
2264         bool active;
2265         u8 fifo;
2266
2267         if (trans->cfg->use_tfh) {
2268                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2269                         txq->read_ptr, txq->write_ptr);
2270                 /* TODO: access new SCD registers and dump them */
2271                 return;
2272         }
2273
2274         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2275         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2276         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2277
2278         IWL_ERR(trans,
2279                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2280                 txq_id, active ? "" : "in", fifo,
2281                 jiffies_to_msecs(txq->wd_timeout),
2282                 txq->read_ptr, txq->write_ptr,
2283                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2284                         (trans->cfg->base_params->max_tfd_queue_size - 1),
2285                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2286                         (trans->cfg->base_params->max_tfd_queue_size - 1),
2287                 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2288 }
2289
2290 static int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue,
2291                                        struct iwl_trans_rxq_dma_data *data)
2292 {
2293         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2294
2295         if (queue >= trans->num_rx_queues || !trans_pcie->rxq)
2296                 return -EINVAL;
2297
2298         data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma;
2299         data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma;
2300         data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma;
2301         data->fr_bd_wid = 0;
2302
2303         return 0;
2304 }
2305
2306 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2307 {
2308         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2309         struct iwl_txq *txq;
2310         unsigned long now = jiffies;
2311         u8 wr_ptr;
2312
2313         if (!test_bit(txq_idx, trans_pcie->queue_used))
2314                 return -EINVAL;
2315
2316         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2317         txq = trans_pcie->txq[txq_idx];
2318         wr_ptr = READ_ONCE(txq->write_ptr);
2319
2320         while (txq->read_ptr != READ_ONCE(txq->write_ptr) &&
2321                !time_after(jiffies,
2322                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2323                 u8 write_ptr = READ_ONCE(txq->write_ptr);
2324
2325                 if (WARN_ONCE(wr_ptr != write_ptr,
2326                               "WR pointer moved while flushing %d -> %d\n",
2327                               wr_ptr, write_ptr))
2328                         return -ETIMEDOUT;
2329                 usleep_range(1000, 2000);
2330         }
2331
2332         if (txq->read_ptr != txq->write_ptr) {
2333                 IWL_ERR(trans,
2334                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2335                 iwl_trans_pcie_log_scd_error(trans, txq);
2336                 return -ETIMEDOUT;
2337         }
2338
2339         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2340
2341         return 0;
2342 }
2343
2344 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2345 {
2346         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2347         int cnt;
2348         int ret = 0;
2349
2350         /* waiting for all the tx frames complete might take a while */
2351         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2352
2353                 if (cnt == trans_pcie->cmd_queue)
2354                         continue;
2355                 if (!test_bit(cnt, trans_pcie->queue_used))
2356                         continue;
2357                 if (!(BIT(cnt) & txq_bm))
2358                         continue;
2359
2360                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2361                 if (ret)
2362                         break;
2363         }
2364
2365         return ret;
2366 }
2367
2368 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2369                                          u32 mask, u32 value)
2370 {
2371         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2372         unsigned long flags;
2373
2374         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2375         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2376         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2377 }
2378
2379 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2380 {
2381         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2382
2383         if (iwlwifi_mod_params.d0i3_disable)
2384                 return;
2385
2386         pm_runtime_get(&trans_pcie->pci_dev->dev);
2387
2388 #ifdef CONFIG_PM
2389         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2390                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2391 #endif /* CONFIG_PM */
2392 }
2393
2394 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2395 {
2396         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2397
2398         if (iwlwifi_mod_params.d0i3_disable)
2399                 return;
2400
2401         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2402         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2403
2404 #ifdef CONFIG_PM
2405         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2406                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2407 #endif /* CONFIG_PM */
2408 }
2409
2410 static const char *get_csr_string(int cmd)
2411 {
2412 #define IWL_CMD(x) case x: return #x
2413         switch (cmd) {
2414         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2415         IWL_CMD(CSR_INT_COALESCING);
2416         IWL_CMD(CSR_INT);
2417         IWL_CMD(CSR_INT_MASK);
2418         IWL_CMD(CSR_FH_INT_STATUS);
2419         IWL_CMD(CSR_GPIO_IN);
2420         IWL_CMD(CSR_RESET);
2421         IWL_CMD(CSR_GP_CNTRL);
2422         IWL_CMD(CSR_HW_REV);
2423         IWL_CMD(CSR_EEPROM_REG);
2424         IWL_CMD(CSR_EEPROM_GP);
2425         IWL_CMD(CSR_OTP_GP_REG);
2426         IWL_CMD(CSR_GIO_REG);
2427         IWL_CMD(CSR_GP_UCODE_REG);
2428         IWL_CMD(CSR_GP_DRIVER_REG);
2429         IWL_CMD(CSR_UCODE_DRV_GP1);
2430         IWL_CMD(CSR_UCODE_DRV_GP2);
2431         IWL_CMD(CSR_LED_REG);
2432         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2433         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2434         IWL_CMD(CSR_ANA_PLL_CFG);
2435         IWL_CMD(CSR_HW_REV_WA_REG);
2436         IWL_CMD(CSR_MONITOR_STATUS_REG);
2437         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2438         default:
2439                 return "UNKNOWN";
2440         }
2441 #undef IWL_CMD
2442 }
2443
2444 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2445 {
2446         int i;
2447         static const u32 csr_tbl[] = {
2448                 CSR_HW_IF_CONFIG_REG,
2449                 CSR_INT_COALESCING,
2450                 CSR_INT,
2451                 CSR_INT_MASK,
2452                 CSR_FH_INT_STATUS,
2453                 CSR_GPIO_IN,
2454                 CSR_RESET,
2455                 CSR_GP_CNTRL,
2456                 CSR_HW_REV,
2457                 CSR_EEPROM_REG,
2458                 CSR_EEPROM_GP,
2459                 CSR_OTP_GP_REG,
2460                 CSR_GIO_REG,
2461                 CSR_GP_UCODE_REG,
2462                 CSR_GP_DRIVER_REG,
2463                 CSR_UCODE_DRV_GP1,
2464                 CSR_UCODE_DRV_GP2,
2465                 CSR_LED_REG,
2466                 CSR_DRAM_INT_TBL_REG,
2467                 CSR_GIO_CHICKEN_BITS,
2468                 CSR_ANA_PLL_CFG,
2469                 CSR_MONITOR_STATUS_REG,
2470                 CSR_HW_REV_WA_REG,
2471                 CSR_DBG_HPET_MEM_REG
2472         };
2473         IWL_ERR(trans, "CSR values:\n");
2474         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2475                 "CSR_INT_PERIODIC_REG)\n");
2476         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2477                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2478                         get_csr_string(csr_tbl[i]),
2479                         iwl_read32(trans, csr_tbl[i]));
2480         }
2481 }
2482
2483 #ifdef CONFIG_IWLWIFI_DEBUGFS
2484 /* create and remove of files */
2485 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2486         if (!debugfs_create_file(#name, mode, parent, trans,            \
2487                                  &iwl_dbgfs_##name##_ops))              \
2488                 goto err;                                               \
2489 } while (0)
2490
2491 /* file operation */
2492 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2493 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2494         .read = iwl_dbgfs_##name##_read,                                \
2495         .open = simple_open,                                            \
2496         .llseek = generic_file_llseek,                                  \
2497 };
2498
2499 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2500 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2501         .write = iwl_dbgfs_##name##_write,                              \
2502         .open = simple_open,                                            \
2503         .llseek = generic_file_llseek,                                  \
2504 };
2505
2506 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2507 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2508         .write = iwl_dbgfs_##name##_write,                              \
2509         .read = iwl_dbgfs_##name##_read,                                \
2510         .open = simple_open,                                            \
2511         .llseek = generic_file_llseek,                                  \
2512 };
2513
2514 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2515                                        char __user *user_buf,
2516                                        size_t count, loff_t *ppos)
2517 {
2518         struct iwl_trans *trans = file->private_data;
2519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2520         struct iwl_txq *txq;
2521         char *buf;
2522         int pos = 0;
2523         int cnt;
2524         int ret;
2525         size_t bufsz;
2526
2527         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2528
2529         if (!trans_pcie->txq_memory)
2530                 return -EAGAIN;
2531
2532         buf = kzalloc(bufsz, GFP_KERNEL);
2533         if (!buf)
2534                 return -ENOMEM;
2535
2536         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2537                 txq = trans_pcie->txq[cnt];
2538                 pos += scnprintf(buf + pos, bufsz - pos,
2539                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2540                                 cnt, txq->read_ptr, txq->write_ptr,
2541                                 !!test_bit(cnt, trans_pcie->queue_used),
2542                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2543                                  txq->need_update, txq->frozen,
2544                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2545         }
2546         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2547         kfree(buf);
2548         return ret;
2549 }
2550
2551 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2552                                        char __user *user_buf,
2553                                        size_t count, loff_t *ppos)
2554 {
2555         struct iwl_trans *trans = file->private_data;
2556         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2557         char *buf;
2558         int pos = 0, i, ret;
2559         size_t bufsz = sizeof(buf);
2560
2561         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2562
2563         if (!trans_pcie->rxq)
2564                 return -EAGAIN;
2565
2566         buf = kzalloc(bufsz, GFP_KERNEL);
2567         if (!buf)
2568                 return -ENOMEM;
2569
2570         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2571                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2572
2573                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2574                                  i);
2575                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2576                                  rxq->read);
2577                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2578                                  rxq->write);
2579                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2580                                  rxq->write_actual);
2581                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2582                                  rxq->need_update);
2583                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2584                                  rxq->free_count);
2585                 if (rxq->rb_stts) {
2586                         u32 r = __le16_to_cpu(iwl_get_closed_rb_stts(trans,
2587                                                                      rxq));
2588                         pos += scnprintf(buf + pos, bufsz - pos,
2589                                          "\tclosed_rb_num: %u\n",
2590                                          r & 0x0FFF);
2591                 } else {
2592                         pos += scnprintf(buf + pos, bufsz - pos,
2593                                          "\tclosed_rb_num: Not Allocated\n");
2594                 }
2595         }
2596         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2597         kfree(buf);
2598
2599         return ret;
2600 }
2601
2602 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2603                                         char __user *user_buf,
2604                                         size_t count, loff_t *ppos)
2605 {
2606         struct iwl_trans *trans = file->private_data;
2607         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2608         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2609
2610         int pos = 0;
2611         char *buf;
2612         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2613         ssize_t ret;
2614
2615         buf = kzalloc(bufsz, GFP_KERNEL);
2616         if (!buf)
2617                 return -ENOMEM;
2618
2619         pos += scnprintf(buf + pos, bufsz - pos,
2620                         "Interrupt Statistics Report:\n");
2621
2622         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2623                 isr_stats->hw);
2624         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2625                 isr_stats->sw);
2626         if (isr_stats->sw || isr_stats->hw) {
2627                 pos += scnprintf(buf + pos, bufsz - pos,
2628                         "\tLast Restarting Code:  0x%X\n",
2629                         isr_stats->err_code);
2630         }
2631 #ifdef CONFIG_IWLWIFI_DEBUG
2632         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2633                 isr_stats->sch);
2634         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2635                 isr_stats->alive);
2636 #endif
2637         pos += scnprintf(buf + pos, bufsz - pos,
2638                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2639
2640         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2641                 isr_stats->ctkill);
2642
2643         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2644                 isr_stats->wakeup);
2645
2646         pos += scnprintf(buf + pos, bufsz - pos,
2647                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2648
2649         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2650                 isr_stats->tx);
2651
2652         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2653                 isr_stats->unhandled);
2654
2655         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2656         kfree(buf);
2657         return ret;
2658 }
2659
2660 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2661                                          const char __user *user_buf,
2662                                          size_t count, loff_t *ppos)
2663 {
2664         struct iwl_trans *trans = file->private_data;
2665         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2666         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2667         u32 reset_flag;
2668         int ret;
2669
2670         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2671         if (ret)
2672                 return ret;
2673         if (reset_flag == 0)
2674                 memset(isr_stats, 0, sizeof(*isr_stats));
2675
2676         return count;
2677 }
2678
2679 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2680                                    const char __user *user_buf,
2681                                    size_t count, loff_t *ppos)
2682 {
2683         struct iwl_trans *trans = file->private_data;
2684
2685         iwl_pcie_dump_csr(trans);
2686
2687         return count;
2688 }
2689
2690 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2691                                      char __user *user_buf,
2692                                      size_t count, loff_t *ppos)
2693 {
2694         struct iwl_trans *trans = file->private_data;
2695         char *buf = NULL;
2696         ssize_t ret;
2697
2698         ret = iwl_dump_fh(trans, &buf);
2699         if (ret < 0)
2700                 return ret;
2701         if (!buf)
2702                 return -EINVAL;
2703         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2704         kfree(buf);
2705         return ret;
2706 }
2707
2708 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2709                                      char __user *user_buf,
2710                                      size_t count, loff_t *ppos)
2711 {
2712         struct iwl_trans *trans = file->private_data;
2713         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2714         char buf[100];
2715         int pos;
2716
2717         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2718                         trans_pcie->debug_rfkill,
2719                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2720                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2721
2722         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2723 }
2724
2725 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2726                                       const char __user *user_buf,
2727                                       size_t count, loff_t *ppos)
2728 {
2729         struct iwl_trans *trans = file->private_data;
2730         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2731         bool old = trans_pcie->debug_rfkill;
2732         int ret;
2733
2734         ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2735         if (ret)
2736                 return ret;
2737         if (old == trans_pcie->debug_rfkill)
2738                 return count;
2739         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2740                  old, trans_pcie->debug_rfkill);
2741         iwl_pcie_handle_rfkill_irq(trans);
2742
2743         return count;
2744 }
2745
2746 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2747 DEBUGFS_READ_FILE_OPS(fh_reg);
2748 DEBUGFS_READ_FILE_OPS(rx_queue);
2749 DEBUGFS_READ_FILE_OPS(tx_queue);
2750 DEBUGFS_WRITE_FILE_OPS(csr);
2751 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2752
2753 /* Create the debugfs files and directories */
2754 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2755 {
2756         struct dentry *dir = trans->dbgfs_dir;
2757
2758         DEBUGFS_ADD_FILE(rx_queue, dir, 0400);
2759         DEBUGFS_ADD_FILE(tx_queue, dir, 0400);
2760         DEBUGFS_ADD_FILE(interrupt, dir, 0600);
2761         DEBUGFS_ADD_FILE(csr, dir, 0200);
2762         DEBUGFS_ADD_FILE(fh_reg, dir, 0400);
2763         DEBUGFS_ADD_FILE(rfkill, dir, 0600);
2764         return 0;
2765
2766 err:
2767         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2768         return -ENOMEM;
2769 }
2770 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2771
2772 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2773 {
2774         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2775         u32 cmdlen = 0;
2776         int i;
2777
2778         for (i = 0; i < trans_pcie->max_tbs; i++)
2779                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2780
2781         return cmdlen;
2782 }
2783
2784 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2785                                    struct iwl_fw_error_dump_data **data,
2786                                    int allocated_rb_nums)
2787 {
2788         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2789         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2790         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2791         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2792         u32 i, r, j, rb_len = 0;
2793
2794         spin_lock(&rxq->lock);
2795
2796         r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
2797
2798         for (i = rxq->read, j = 0;
2799              i != r && j < allocated_rb_nums;
2800              i = (i + 1) & RX_QUEUE_MASK, j++) {
2801                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2802                 struct iwl_fw_error_dump_rb *rb;
2803
2804                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2805                                DMA_FROM_DEVICE);
2806
2807                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2808
2809                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2810                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2811                 rb = (void *)(*data)->data;
2812                 rb->index = cpu_to_le32(i);
2813                 memcpy(rb->data, page_address(rxb->page), max_len);
2814                 /* remap the page for the free benefit */
2815                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2816                                                      max_len,
2817                                                      DMA_FROM_DEVICE);
2818
2819                 *data = iwl_fw_error_next_data(*data);
2820         }
2821
2822         spin_unlock(&rxq->lock);
2823
2824         return rb_len;
2825 }
2826 #define IWL_CSR_TO_DUMP (0x250)
2827
2828 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2829                                    struct iwl_fw_error_dump_data **data)
2830 {
2831         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2832         __le32 *val;
2833         int i;
2834
2835         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2836         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2837         val = (void *)(*data)->data;
2838
2839         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2840                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2841
2842         *data = iwl_fw_error_next_data(*data);
2843
2844         return csr_len;
2845 }
2846
2847 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2848                                        struct iwl_fw_error_dump_data **data)
2849 {
2850         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2851         unsigned long flags;
2852         __le32 *val;
2853         int i;
2854
2855         if (!iwl_trans_grab_nic_access(trans, &flags))
2856                 return 0;
2857
2858         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2859         (*data)->len = cpu_to_le32(fh_regs_len);
2860         val = (void *)(*data)->data;
2861
2862         if (!trans->cfg->gen2)
2863                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2864                      i += sizeof(u32))
2865                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2866         else
2867                 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2868                      i += sizeof(u32))
2869                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2870                                                                       i));
2871
2872         iwl_trans_release_nic_access(trans, &flags);
2873
2874         *data = iwl_fw_error_next_data(*data);
2875
2876         return sizeof(**data) + fh_regs_len;
2877 }
2878
2879 static u32
2880 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2881                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2882                                  u32 monitor_len)
2883 {
2884         u32 buf_size_in_dwords = (monitor_len >> 2);
2885         u32 *buffer = (u32 *)fw_mon_data->data;
2886         unsigned long flags;
2887         u32 i;
2888
2889         if (!iwl_trans_grab_nic_access(trans, &flags))
2890                 return 0;
2891
2892         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2893         for (i = 0; i < buf_size_in_dwords; i++)
2894                 buffer[i] = iwl_read_prph_no_grab(trans,
2895                                 MON_DMARB_RD_DATA_ADDR);
2896         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2897
2898         iwl_trans_release_nic_access(trans, &flags);
2899
2900         return monitor_len;
2901 }
2902
2903 static u32
2904 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2905                             struct iwl_fw_error_dump_data **data,
2906                             u32 monitor_len)
2907 {
2908         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2909         u32 len = 0;
2910
2911         if ((trans_pcie->fw_mon_page &&
2912              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2913             trans->dbg_dest_tlv) {
2914                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2915                 u32 base, write_ptr, wrap_cnt;
2916
2917                 /* If there was a dest TLV - use the values from there */
2918                 if (trans->dbg_dest_tlv) {
2919                         write_ptr =
2920                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2921                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2922                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2923                 } else {
2924                         base = MON_BUFF_BASE_ADDR;
2925                         write_ptr = MON_BUFF_WRPTR;
2926                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2927                 }
2928
2929                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2930                 fw_mon_data = (void *)(*data)->data;
2931                 fw_mon_data->fw_mon_wr_ptr =
2932                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2933                 fw_mon_data->fw_mon_cycle_cnt =
2934                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2935                 fw_mon_data->fw_mon_base_ptr =
2936                         cpu_to_le32(iwl_read_prph(trans, base));
2937
2938                 len += sizeof(**data) + sizeof(*fw_mon_data);
2939                 if (trans_pcie->fw_mon_page) {
2940                         /*
2941                          * The firmware is now asserted, it won't write anything
2942                          * to the buffer. CPU can take ownership to fetch the
2943                          * data. The buffer will be handed back to the device
2944                          * before the firmware will be restarted.
2945                          */
2946                         dma_sync_single_for_cpu(trans->dev,
2947                                                 trans_pcie->fw_mon_phys,
2948                                                 trans_pcie->fw_mon_size,
2949                                                 DMA_FROM_DEVICE);
2950                         memcpy(fw_mon_data->data,
2951                                page_address(trans_pcie->fw_mon_page),
2952                                trans_pcie->fw_mon_size);
2953
2954                         monitor_len = trans_pcie->fw_mon_size;
2955                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2956                         /*
2957                          * Update pointers to reflect actual values after
2958                          * shifting
2959                          */
2960                         if (trans->dbg_dest_tlv->version) {
2961                                 base = (iwl_read_prph(trans, base) &
2962                                         IWL_LDBG_M2S_BUF_BA_MSK) <<
2963                                        trans->dbg_dest_tlv->base_shift;
2964                                 base *= IWL_M2S_UNIT_SIZE;
2965                                 base += trans->cfg->smem_offset;
2966                         } else {
2967                                 base = iwl_read_prph(trans, base) <<
2968                                        trans->dbg_dest_tlv->base_shift;
2969                         }
2970
2971                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2972                                            monitor_len / sizeof(u32));
2973                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2974                         monitor_len =
2975                                 iwl_trans_pci_dump_marbh_monitor(trans,
2976                                                                  fw_mon_data,
2977                                                                  monitor_len);
2978                 } else {
2979                         /* Didn't match anything - output no monitor data */
2980                         monitor_len = 0;
2981                 }
2982
2983                 len += monitor_len;
2984                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2985         }
2986
2987         return len;
2988 }
2989
2990 static struct iwl_trans_dump_data
2991 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2992                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2993 {
2994         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2995         struct iwl_fw_error_dump_data *data;
2996         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2997         struct iwl_fw_error_dump_txcmd *txcmd;
2998         struct iwl_trans_dump_data *dump_data;
2999         u32 len, num_rbs = 0;
3000         u32 monitor_len;
3001         int i, ptr;
3002         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
3003                         !trans->cfg->mq_rx_supported &&
3004                         trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_RB);
3005
3006         /* transport dump header */
3007         len = sizeof(*dump_data);
3008
3009         /* host commands */
3010         len += sizeof(*data) +
3011                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
3012
3013         /* FW monitor */
3014         if (trans_pcie->fw_mon_page) {
3015                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3016                        trans_pcie->fw_mon_size;
3017                 monitor_len = trans_pcie->fw_mon_size;
3018         } else if (trans->dbg_dest_tlv) {
3019                 u32 base, end, cfg_reg;
3020
3021                 if (trans->dbg_dest_tlv->version == 1) {
3022                         cfg_reg = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3023                         cfg_reg = iwl_read_prph(trans, cfg_reg);
3024                         base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) <<
3025                                 trans->dbg_dest_tlv->base_shift;
3026                         base *= IWL_M2S_UNIT_SIZE;
3027                         base += trans->cfg->smem_offset;
3028
3029                         monitor_len =
3030                                 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >>
3031                                 trans->dbg_dest_tlv->end_shift;
3032                         monitor_len *= IWL_M2S_UNIT_SIZE;
3033                 } else {
3034                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
3035                         end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
3036
3037                         base = iwl_read_prph(trans, base) <<
3038                                trans->dbg_dest_tlv->base_shift;
3039                         end = iwl_read_prph(trans, end) <<
3040                               trans->dbg_dest_tlv->end_shift;
3041
3042                         /* Make "end" point to the actual end */
3043                         if (trans->cfg->device_family >=
3044                             IWL_DEVICE_FAMILY_8000 ||
3045                             trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
3046                                 end += (1 << trans->dbg_dest_tlv->end_shift);
3047                         monitor_len = end - base;
3048                 }
3049                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
3050                        monitor_len;
3051         } else {
3052                 monitor_len = 0;
3053         }
3054
3055         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
3056                 if (!(trans->dbg_dump_mask &
3057                       BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)))
3058                         return NULL;
3059
3060                 dump_data = vzalloc(len);
3061                 if (!dump_data)
3062                         return NULL;
3063
3064                 data = (void *)dump_data->data;
3065                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3066                 dump_data->len = len;
3067
3068                 return dump_data;
3069         }
3070
3071         /* CSR registers */
3072         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3073                 len += sizeof(*data) + IWL_CSR_TO_DUMP;
3074
3075         /* FH registers */
3076         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) {
3077                 if (trans->cfg->gen2)
3078                         len += sizeof(*data) +
3079                                (FH_MEM_UPPER_BOUND_GEN2 -
3080                                 FH_MEM_LOWER_BOUND_GEN2);
3081                 else
3082                         len += sizeof(*data) +
3083                                (FH_MEM_UPPER_BOUND -
3084                                 FH_MEM_LOWER_BOUND);
3085         }
3086
3087         if (dump_rbs) {
3088                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
3089                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
3090                 /* RBs */
3091                 num_rbs =
3092                         le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq))
3093                         & 0x0FFF;
3094                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
3095                 len += num_rbs * (sizeof(*data) +
3096                                   sizeof(struct iwl_fw_error_dump_rb) +
3097                                   (PAGE_SIZE << trans_pcie->rx_page_order));
3098         }
3099
3100         /* Paged memory for gen2 HW */
3101         if (trans->cfg->gen2 &&
3102             trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING))
3103                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
3104                         len += sizeof(*data) +
3105                                sizeof(struct iwl_fw_error_dump_paging) +
3106                                trans_pcie->init_dram.paging[i].size;
3107
3108         dump_data = vzalloc(len);
3109         if (!dump_data)
3110                 return NULL;
3111
3112         len = 0;
3113         data = (void *)dump_data->data;
3114
3115         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD)) {
3116                 u16 tfd_size = trans_pcie->tfd_size;
3117
3118                 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
3119                 txcmd = (void *)data->data;
3120                 spin_lock_bh(&cmdq->lock);
3121                 ptr = cmdq->write_ptr;
3122                 for (i = 0; i < cmdq->n_window; i++) {
3123                         u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
3124                         u32 caplen, cmdlen;
3125
3126                         cmdlen = iwl_trans_pcie_get_cmdlen(trans,
3127                                                            cmdq->tfds +
3128                                                            tfd_size * ptr);
3129                         caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
3130
3131                         if (cmdlen) {
3132                                 len += sizeof(*txcmd) + caplen;
3133                                 txcmd->cmdlen = cpu_to_le32(cmdlen);
3134                                 txcmd->caplen = cpu_to_le32(caplen);
3135                                 memcpy(txcmd->data, cmdq->entries[idx].cmd,
3136                                        caplen);
3137                                 txcmd = (void *)((u8 *)txcmd->data + caplen);
3138                         }
3139
3140                         ptr = iwl_queue_dec_wrap(trans, ptr);
3141                 }
3142                 spin_unlock_bh(&cmdq->lock);
3143
3144                 data->len = cpu_to_le32(len);
3145                 len += sizeof(*data);
3146                 data = iwl_fw_error_next_data(data);
3147         }
3148
3149         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR))
3150                 len += iwl_trans_pcie_dump_csr(trans, &data);
3151         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS))
3152                 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
3153         if (dump_rbs)
3154                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
3155
3156         /* Paged memory for gen2 HW */
3157         if (trans->cfg->gen2 &&
3158             trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) {
3159                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
3160                         struct iwl_fw_error_dump_paging *paging;
3161                         dma_addr_t addr =
3162                                 trans_pcie->init_dram.paging[i].physical;
3163                         u32 page_len = trans_pcie->init_dram.paging[i].size;
3164
3165                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
3166                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
3167                         paging = (void *)data->data;
3168                         paging->index = cpu_to_le32(i);
3169                         dma_sync_single_for_cpu(trans->dev, addr, page_len,
3170                                                 DMA_BIDIRECTIONAL);
3171                         memcpy(paging->data,
3172                                trans_pcie->init_dram.paging[i].block, page_len);
3173                         data = iwl_fw_error_next_data(data);
3174
3175                         len += sizeof(*data) + sizeof(*paging) + page_len;
3176                 }
3177         }
3178         if (trans->dbg_dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR))
3179                 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
3180
3181         dump_data->len = len;
3182
3183         return dump_data;
3184 }
3185
3186 #ifdef CONFIG_PM_SLEEP
3187 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
3188 {
3189         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3190             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3191                 return iwl_pci_fw_enter_d0i3(trans);
3192
3193         return 0;
3194 }
3195
3196 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
3197 {
3198         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
3199             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
3200                 iwl_pci_fw_exit_d0i3(trans);
3201 }
3202 #endif /* CONFIG_PM_SLEEP */
3203
3204 #define IWL_TRANS_COMMON_OPS                                            \
3205         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
3206         .write8 = iwl_trans_pcie_write8,                                \
3207         .write32 = iwl_trans_pcie_write32,                              \
3208         .read32 = iwl_trans_pcie_read32,                                \
3209         .read_prph = iwl_trans_pcie_read_prph,                          \
3210         .write_prph = iwl_trans_pcie_write_prph,                        \
3211         .read_mem = iwl_trans_pcie_read_mem,                            \
3212         .write_mem = iwl_trans_pcie_write_mem,                          \
3213         .configure = iwl_trans_pcie_configure,                          \
3214         .set_pmi = iwl_trans_pcie_set_pmi,                              \
3215         .sw_reset = iwl_trans_pcie_sw_reset,                            \
3216         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
3217         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
3218         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
3219         .ref = iwl_trans_pcie_ref,                                      \
3220         .unref = iwl_trans_pcie_unref,                                  \
3221         .dump_data = iwl_trans_pcie_dump_data,                          \
3222         .dump_regs = iwl_trans_pcie_dump_regs,                          \
3223         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
3224         .d3_resume = iwl_trans_pcie_d3_resume
3225
3226 #ifdef CONFIG_PM_SLEEP
3227 #define IWL_TRANS_PM_OPS                                                \
3228         .suspend = iwl_trans_pcie_suspend,                              \
3229         .resume = iwl_trans_pcie_resume,
3230 #else
3231 #define IWL_TRANS_PM_OPS
3232 #endif /* CONFIG_PM_SLEEP */
3233
3234 static const struct iwl_trans_ops trans_ops_pcie = {
3235         IWL_TRANS_COMMON_OPS,
3236         IWL_TRANS_PM_OPS
3237         .start_hw = iwl_trans_pcie_start_hw,
3238         .fw_alive = iwl_trans_pcie_fw_alive,
3239         .start_fw = iwl_trans_pcie_start_fw,
3240         .stop_device = iwl_trans_pcie_stop_device,
3241
3242         .send_cmd = iwl_trans_pcie_send_hcmd,
3243
3244         .tx = iwl_trans_pcie_tx,
3245         .reclaim = iwl_trans_pcie_reclaim,
3246
3247         .txq_disable = iwl_trans_pcie_txq_disable,
3248         .txq_enable = iwl_trans_pcie_txq_enable,
3249
3250         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
3251
3252         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
3253
3254         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
3255         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
3256 };
3257
3258 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3259         IWL_TRANS_COMMON_OPS,
3260         IWL_TRANS_PM_OPS
3261         .start_hw = iwl_trans_pcie_start_hw,
3262         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3263         .start_fw = iwl_trans_pcie_gen2_start_fw,
3264         .stop_device = iwl_trans_pcie_gen2_stop_device,
3265
3266         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3267
3268         .tx = iwl_trans_pcie_gen2_tx,
3269         .reclaim = iwl_trans_pcie_reclaim,
3270
3271         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3272         .txq_free = iwl_trans_pcie_dyn_txq_free,
3273         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3274         .rxq_dma_data = iwl_trans_pcie_rxq_dma_data,
3275 };
3276
3277 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3278                                        const struct pci_device_id *ent,
3279                                        const struct iwl_cfg *cfg)
3280 {
3281         struct iwl_trans_pcie *trans_pcie;
3282         struct iwl_trans *trans;
3283         int ret, addr_size;
3284
3285         ret = pcim_enable_device(pdev);
3286         if (ret)
3287                 return ERR_PTR(ret);
3288
3289         if (cfg->gen2)
3290                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3291                                         &pdev->dev, cfg, &trans_ops_pcie_gen2);
3292         else
3293                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3294                                         &pdev->dev, cfg, &trans_ops_pcie);
3295         if (!trans)
3296                 return ERR_PTR(-ENOMEM);
3297
3298         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3299
3300         trans_pcie->trans = trans;
3301         trans_pcie->opmode_down = true;
3302         spin_lock_init(&trans_pcie->irq_lock);
3303         spin_lock_init(&trans_pcie->reg_lock);
3304         mutex_init(&trans_pcie->mutex);
3305         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3306
3307         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3308                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3309         if (!trans_pcie->rba.alloc_wq) {
3310                 ret = -ENOMEM;
3311                 goto out_free_trans;
3312         }
3313         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3314
3315         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3316         if (!trans_pcie->tso_hdr_page) {
3317                 ret = -ENOMEM;
3318                 goto out_no_pci;
3319         }
3320
3321
3322         if (!cfg->base_params->pcie_l1_allowed) {
3323                 /*
3324                  * W/A - seems to solve weird behavior. We need to remove this
3325                  * if we don't want to stay in L1 all the time. This wastes a
3326                  * lot of power.
3327                  */
3328                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3329                                        PCIE_LINK_STATE_L1 |
3330                                        PCIE_LINK_STATE_CLKPM);
3331         }
3332
3333         if (cfg->use_tfh) {
3334                 addr_size = 64;
3335                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3336                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3337         } else {
3338                 addr_size = 36;
3339                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3340                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3341         }
3342         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3343
3344         pci_set_master(pdev);
3345
3346         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3347         if (!ret)
3348                 ret = pci_set_consistent_dma_mask(pdev,
3349                                                   DMA_BIT_MASK(addr_size));
3350         if (ret) {
3351                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3352                 if (!ret)
3353                         ret = pci_set_consistent_dma_mask(pdev,
3354                                                           DMA_BIT_MASK(32));
3355                 /* both attempts failed: */
3356                 if (ret) {
3357                         dev_err(&pdev->dev, "No suitable DMA available\n");
3358                         goto out_no_pci;
3359                 }
3360         }
3361
3362         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3363         if (ret) {
3364                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3365                 goto out_no_pci;
3366         }
3367
3368         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3369         if (!trans_pcie->hw_base) {
3370                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3371                 ret = -ENODEV;
3372                 goto out_no_pci;
3373         }
3374
3375         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3376          * PCI Tx retries from interfering with C3 CPU state */
3377         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3378
3379         trans_pcie->pci_dev = pdev;
3380         iwl_disable_interrupts(trans);
3381
3382         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3383         /*
3384          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3385          * changed, and now the revision step also includes bit 0-1 (no more
3386          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3387          * in the old format.
3388          */
3389         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3390                 unsigned long flags;
3391
3392                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3393                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3394
3395                 ret = iwl_pcie_prepare_card_hw(trans);
3396                 if (ret) {
3397                         IWL_WARN(trans, "Exit HW not ready\n");
3398                         goto out_no_pci;
3399                 }
3400
3401                 /*
3402                  * in-order to recognize C step driver should read chip version
3403                  * id located at the AUX bus MISC address space.
3404                  */
3405                 iwl_set_bit(trans, CSR_GP_CNTRL,
3406                             BIT(trans->cfg->csr->flag_init_done));
3407                 udelay(2);
3408
3409                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3410                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3411                                    BIT(trans->cfg->csr->flag_mac_clock_ready),
3412                                    25000);
3413                 if (ret < 0) {
3414                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3415                         goto out_no_pci;
3416                 }
3417
3418                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3419                         u32 hw_step;
3420
3421                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3422                         hw_step |= ENABLE_WFPM;
3423                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3424                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3425                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3426                         if (hw_step == 0x3)
3427                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3428                                                 (SILICON_C_STEP << 2);
3429                         iwl_trans_release_nic_access(trans, &flags);
3430                 }
3431         }
3432
3433         /*
3434          * 9000-series integrated A-step has a problem with suspend/resume
3435          * and sometimes even causes the whole platform to get stuck. This
3436          * workaround makes the hardware not go into the problematic state.
3437          */
3438         if (trans->cfg->integrated &&
3439             trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3440             CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3441                 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3442                             CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3443
3444 #if IS_ENABLED(CONFIG_IWLMVM)
3445         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3446
3447         if (cfg == &iwl22000_2ax_cfg_hr) {
3448                 if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3449                     CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3450                         trans->cfg = &iwl22000_2ax_cfg_hr;
3451                 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3452                            CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_JF)) {
3453                         trans->cfg = &iwl22000_2ax_cfg_jf;
3454                 } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3455                            CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HRCDB)) {
3456                         IWL_ERR(trans, "RF ID HRCDB is not supported\n");
3457                         ret = -EINVAL;
3458                         goto out_no_pci;
3459                 } else {
3460                         IWL_ERR(trans, "Unrecognized RF ID 0x%08x\n",
3461                                 CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id));
3462                         ret = -EINVAL;
3463                         goto out_no_pci;
3464                 }
3465         } else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
3466                    CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR)) {
3467                 u32 hw_status;
3468
3469                 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3470                 if (CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_B_STEP)
3471                         /*
3472                         * b step fw is the same for physical card and fpga
3473                         */
3474                         trans->cfg = &iwl22000_2ax_cfg_qnj_hr_b0;
3475                 else if ((hw_status & UMAG_GEN_HW_IS_FPGA) &&
3476                          CSR_HW_RF_STEP(trans->hw_rf_id) == SILICON_A_STEP) {
3477                         trans->cfg = &iwl22000_2ax_cfg_qnj_hr_a0_f0;
3478                 } else {
3479                         /*
3480                         * a step no FPGA
3481                         */
3482                         trans->cfg = &iwl22000_2ac_cfg_hr;
3483                 }
3484         }
3485 #endif
3486
3487         iwl_pcie_set_interrupt_capa(pdev, trans);
3488         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3489         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3490                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3491
3492         /* Initialize the wait queue for commands */
3493         init_waitqueue_head(&trans_pcie->wait_command_queue);
3494
3495         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3496
3497         if (trans_pcie->msix_enabled) {
3498                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3499                 if (ret)
3500                         goto out_no_pci;
3501          } else {
3502                 ret = iwl_pcie_alloc_ict(trans);
3503                 if (ret)
3504                         goto out_no_pci;
3505
3506                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3507                                                 iwl_pcie_isr,
3508                                                 iwl_pcie_irq_handler,
3509                                                 IRQF_SHARED, DRV_NAME, trans);
3510                 if (ret) {
3511                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3512                         goto out_free_ict;
3513                 }
3514                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3515          }
3516
3517 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3518         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3519 #else
3520         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3521 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3522
3523         return trans;
3524
3525 out_free_ict:
3526         iwl_pcie_free_ict(trans);
3527 out_no_pci:
3528         free_percpu(trans_pcie->tso_hdr_page);
3529         destroy_workqueue(trans_pcie->rba.alloc_wq);
3530 out_free_trans:
3531         iwl_trans_free(trans);
3532         return ERR_PTR(ret);
3533 }