drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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  22  * along with this program; if not, write to the Free Software
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  27  * in the file called COPYING.
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  32  *
  33  * BSD LICENSE
  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 Intel Deutschland GmbH
  38  * All rights reserved.
  39  *
  40  * Redistribution and use in source and binary forms, with or without
  41  * modification, are permitted provided that the following conditions
  42  * are met:
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  44  *  * Redistributions of source code must retain the above copyright
  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  61  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  62  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "iwl-fw-error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
 228                  (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                  trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret = 0;
 240         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 241
 242         /*
 243          * Use "set_bit" below rather than "write", to preserve any hardware
 244          * bits already set by default after reset.
 245          */
 246
 247         /* Disable L0S exit timer (platform NMI Work/Around) */
 248         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
 249                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 250                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 251
 252         /*
 253          * Disable L0s without affecting L1;
 254          *  don't wait for ICH L0s (ICH bug W/A)
 255          */
 256         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 257                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 258
 259         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 260         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 261
 262         /*
 263          * Enable HAP INTA (interrupt from management bus) to
 264          * wake device's PCI Express link L1a -> L0s
 265          */
 266         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 267                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 268
 269         iwl_pcie_apm_config(trans);
 270
 271         /* Configure analog phase-lock-loop before activating to D0A */
 272         if (trans->cfg->base_params->pll_cfg)
 273                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 274
 275         /*
 276          * Set "initialization complete" bit to move adapter from
 277          * D0U* --> D0A* (powered-up active) state.
 278          */
 279         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 280
 281         /*
 282          * Wait for clock stabilization; once stabilized, access to
 283          * device-internal resources is supported, e.g. iwl_write_prph()
 284          * and accesses to uCode SRAM.
 285          */
 286         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 287                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 289         if (ret < 0) {
 290                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 291                 goto out;
 292         }
 293
 294         if (trans->cfg->host_interrupt_operation_mode) {
 295                 /*
 296                  * This is a bit of an abuse - This is needed for 7260 / 3160
 297                  * only check host_interrupt_operation_mode even if this is
 298                  * not related to host_interrupt_operation_mode.
 299                  *
 300                  * Enable the oscillator to count wake up time for L1 exit. This
 301                  * consumes slightly more power (100uA) - but allows to be sure
 302                  * that we wake up from L1 on time.
 303                  *
 304                  * This looks weird: read twice the same register, discard the
 305                  * value, set a bit, and yet again, read that same register
 306                  * just to discard the value. But that's the way the hardware
 307                  * seems to like it.
 308                  */
 309                 iwl_read_prph(trans, OSC_CLK);
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 312                 iwl_read_prph(trans, OSC_CLK);
 313                 iwl_read_prph(trans, OSC_CLK);
 314         }
 315
 316         /*
 317          * Enable DMA clock and wait for it to stabilize.
 318          *
 319          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 320          * bits do not disable clocks.  This preserves any hardware
 321          * bits already set by default in "CLK_CTRL_REG" after reset.
 322          */
 323         if (!trans->cfg->apmg_not_supported) {
 324                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 325                                APMG_CLK_VAL_DMA_CLK_RQT);
 326                 udelay(20);
 327
 328                 /* Disable L1-Active */
 329                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 330                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 331
 332                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 333                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 334                                APMG_RTC_INT_STT_RFKILL);
 335         }
 336
 337         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 338
 339 out:
 340         return ret;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
 362         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 363         usleep_range(1000, 2000);
 364
 365         /*
 366          * Set "initialization complete" bit to move adapter from
 367          * D0U* --> D0A* (powered-up active) state.
 368          */
 369         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 370
 371         /*
 372          * Wait for clock stabilization; once stabilized, access to
 373          * device-internal resources is possible.
 374          */
 375         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 378                            25000);
 379         if (WARN_ON(ret < 0)) {
 380                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 381                 /* Release XTAL ON request */
 382                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 383                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 384                 return;
 385         }
 386
 387         /*
 388          * Clear "disable persistence" to avoid LP XTAL resetting when
 389          * SHRD_HW_RST is applied in S3.
 390          */
 391         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 392                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 393
 394         /*
 395          * Force APMG XTAL to be active to prevent its disabling by HW
 396          * caused by APMG idle state.
 397          */
 398         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 399                                                     SHR_APMG_XTAL_CFG_REG);
 400         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 401                                  apmg_xtal_cfg_reg |
 402                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 403
 404         /*
 405          * Reset entire device again - do controller reset (results in
 406          * SHRD_HW_RST). Turn MAC off before proceeding.
 407          */
 408         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 409         usleep_range(1000, 2000);
 410
 411         /* Enable LP XTAL by indirect access through CSR */
 412         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 413         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 414                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 415                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 416
 417         /* Clear delay line clock power up */
 418         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 419         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 420                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 421
 422         /*
 423          * Enable persistence mode to avoid LP XTAL resetting when
 424          * SHRD_HW_RST is applied in S3.
 425          */
 426         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 427                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 428
 429         /*
 430          * Clear "initialization complete" bit to move adapter from
 431          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 432          */
 433         iwl_clear_bit(trans, CSR_GP_CNTRL,
 434                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 435
 436         /* Activates XTAL resources monitor */
 437         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 438                                  CSR_MONITOR_XTAL_RESOURCES);
 439
 440         /* Release XTAL ON request */
 441         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 442                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 443         udelay(10);
 444
 445         /* Release APMG XTAL */
 446         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 447                                  apmg_xtal_cfg_reg &
 448                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 449 }
 450
 451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 452 {
 453         int ret = 0;
 454
 455         /* stop device's busmaster DMA activity */
 456         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 457
 458         ret = iwl_poll_bit(trans, CSR_RESET,
 459                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 460                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 461         if (ret < 0)
 462                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 463
 464         IWL_DEBUG_INFO(trans, "stop master\n");
 465
 466         return ret;
 467 }
 468
 469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 470 {
 471         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 472
 473         if (op_mode_leave) {
 474                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 475                         iwl_pcie_apm_init(trans);
 476
 477                 /* inform ME that we are leaving */
 478                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 479                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 480                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 481                 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
 482                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 483                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 484                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 485                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 486                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 487                         mdelay(1);
 488                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 489                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 490                 }
 491                 mdelay(5);
 492         }
 493
 494         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 495
 496         /* Stop device's DMA activity */
 497         iwl_pcie_apm_stop_master(trans);
 498
 499         if (trans->cfg->lp_xtal_workaround) {
 500                 iwl_pcie_apm_lp_xtal_enable(trans);
 501                 return;
 502         }
 503
 504         /* Reset the entire device */
 505         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 506         usleep_range(1000, 2000);
 507
 508         /*
 509          * Clear "initialization complete" bit to move adapter from
 510          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 511          */
 512         iwl_clear_bit(trans, CSR_GP_CNTRL,
 513                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 514 }
 515
 516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 517 {
 518         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 519
 520         /* nic_init */
 521         spin_lock(&trans_pcie->irq_lock);
 522         iwl_pcie_apm_init(trans);
 523
 524         spin_unlock(&trans_pcie->irq_lock);
 525
 526         iwl_pcie_set_pwr(trans, false);
 527
 528         iwl_op_mode_nic_config(trans->op_mode);
 529
 530         /* Allocate the RX queue, or reset if it is already allocated */
 531         iwl_pcie_rx_init(trans);
 532
 533         /* Allocate or reset and init all Tx and Command queues */
 534         if (iwl_pcie_tx_init(trans))
 535                 return -ENOMEM;
 536
 537         if (trans->cfg->base_params->shadow_reg_enable) {
 538                 /* enable shadow regs in HW */
 539                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 540                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 541         }
 542
 543         return 0;
 544 }
 545
 546 #define HW_READY_TIMEOUT (50)
 547
 548 /* Note: returns poll_bit return value, which is >= 0 if success */
 549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 550 {
 551         int ret;
 552
 553         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 554                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 555
 556         /* See if we got it */
 557         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 558                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 559                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 560                            HW_READY_TIMEOUT);
 561
 562         if (ret >= 0)
 563                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 564
 565         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 566         return ret;
 567 }
 568
 569 /* Note: returns standard 0/-ERROR code */
 570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 571 {
 572         int ret;
 573         int t = 0;
 574         int iter;
 575
 576         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 577
 578         ret = iwl_pcie_set_hw_ready(trans);
 579         /* If the card is ready, exit 0 */
 580         if (ret >= 0)
 581                 return 0;
 582
 583         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 584                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 585         usleep_range(1000, 2000);
 586
 587         for (iter = 0; iter < 10; iter++) {
 588                 /* If HW is not ready, prepare the conditions to check again */
 589                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 590                             CSR_HW_IF_CONFIG_REG_PREPARE);
 591
 592                 do {
 593                         ret = iwl_pcie_set_hw_ready(trans);
 594                         if (ret >= 0)
 595                                 return 0;
 596
 597                         usleep_range(200, 1000);
 598                         t += 200;
 599                 } while (t < 150000);
 600                 msleep(25);
 601         }
 602
 603         IWL_ERR(trans, "Couldn't prepare the card\n");
 604
 605         return ret;
 606 }
 607
 608 /*
 609  * ucode
 610  */
 611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 612                                             u32 dst_addr, dma_addr_t phy_addr,
 613                                             u32 byte_cnt)
 614 {
 615         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 616                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 617
 618         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 619                     dst_addr);
 620
 621         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 622                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 623
 624         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 625                     (iwl_get_dma_hi_addr(phy_addr)
 626                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 627
 628         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 629                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 630                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 631                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 632
 633         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 634                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 635                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 636                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 637 }
 638
 639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
 640                                              u32 dst_addr, dma_addr_t phy_addr,
 641                                              u32 byte_cnt)
 642 {
 643         /* Stop DMA channel */
 644         iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
 645
 646         /* Configure SRAM address */
 647         iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
 648                     dst_addr);
 649
 650         /* Configure DRAM address - 64 bit */
 651         iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
 652
 653         /* Configure byte count to transfer */
 654         iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
 655
 656         /* Enable the DRAM2SRAM to start */
 657         iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
 658                                                    TFH_SRV_DMA_TO_DRIVER |
 659                                                    TFH_SRV_DMA_START);
 660 }
 661
 662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 663                                         u32 dst_addr, dma_addr_t phy_addr,
 664                                         u32 byte_cnt)
 665 {
 666         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 667         unsigned long flags;
 668         int ret;
 669
 670         trans_pcie->ucode_write_complete = false;
 671
 672         if (!iwl_trans_grab_nic_access(trans, &flags))
 673                 return -EIO;
 674
 675         if (trans->cfg->use_tfh)
 676                 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
 677                                                  byte_cnt);
 678         else
 679                 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 680                                                 byte_cnt);
 681         iwl_trans_release_nic_access(trans, &flags);
 682
 683         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 684                                  trans_pcie->ucode_write_complete, 5 * HZ);
 685         if (!ret) {
 686                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 687                 return -ETIMEDOUT;
 688         }
 689
 690         return 0;
 691 }
 692
 693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 694                             const struct fw_desc *section)
 695 {
 696         u8 *v_addr;
 697         dma_addr_t p_addr;
 698         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 699         int ret = 0;
 700
 701         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 702                      section_num);
 703
 704         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 705                                     GFP_KERNEL | __GFP_NOWARN);
 706         if (!v_addr) {
 707                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 708                 chunk_sz = PAGE_SIZE;
 709                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 710                                             &p_addr, GFP_KERNEL);
 711                 if (!v_addr)
 712                         return -ENOMEM;
 713         }
 714
 715         for (offset = 0; offset < section->len; offset += chunk_sz) {
 716                 u32 copy_size, dst_addr;
 717                 bool extended_addr = false;
 718
 719                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 720                 dst_addr = section->offset + offset;
 721
 722                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 723                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 724                         extended_addr = true;
 725
 726                 if (extended_addr)
 727                         iwl_set_bits_prph(trans, LMPM_CHICK,
 728                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 729
 730                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 731                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 732                                                    copy_size);
 733
 734                 if (extended_addr)
 735                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 736                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 737
 738                 if (ret) {
 739                         IWL_ERR(trans,
 740                                 "Could not load the [%d] uCode section\n",
 741                                 section_num);
 742                         break;
 743                 }
 744         }
 745
 746         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 747         return ret;
 748 }
 749
 750 /*
 751  * Driver Takes the ownership on secure machine before FW load
 752  * and prevent race with the BT load.
 753  * W/A for ROM bug. (should be remove in the next Si step)
 754  */
 755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
 756 {
 757         u32 val, loop = 1000;
 758
 759         /*
 760          * Check the RSA semaphore is accessible.
 761          * If the HW isn't locked and the rsa semaphore isn't accessible,
 762          * we are in trouble.
 763          */
 764         val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
 765         if (val & (BIT(1) | BIT(17))) {
 766                 IWL_DEBUG_INFO(trans,
 767                                "can't access the RSA semaphore it is write protected\n");
 768                 return 0;
 769         }
 770
 771         /* take ownership on the AUX IF */
 772         iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
 773         iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
 774
 775         do {
 776                 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
 777                 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
 778                 if (val == 0x1) {
 779                         iwl_write_prph(trans, RSA_ENABLE, 0);
 780                         return 0;
 781                 }
 782
 783                 udelay(10);
 784                 loop--;
 785         } while (loop > 0);
 786
 787         IWL_ERR(trans, "Failed to take ownership on secure machine\n");
 788         return -EIO;
 789 }
 790
 791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 792                                            const struct fw_img *image,
 793                                            int cpu,
 794                                            int *first_ucode_section)
 795 {
 796         int shift_param;
 797         int i, ret = 0, sec_num = 0x1;
 798         u32 val, last_read_idx = 0;
 799
 800         if (cpu == 1) {
 801                 shift_param = 0;
 802                 *first_ucode_section = 0;
 803         } else {
 804                 shift_param = 16;
 805                 (*first_ucode_section)++;
 806         }
 807
 808         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 809                 last_read_idx = i;
 810
 811                 /*
 812                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 813                  * CPU1 to CPU2.
 814                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 815                  * CPU2 non paged to CPU2 paging sec.
 816                  */
 817                 if (!image->sec[i].data ||
 818                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 819                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 820                         IWL_DEBUG_FW(trans,
 821                                      "Break since Data not valid or Empty section, sec = %d\n",
 822                                      i);
 823                         break;
 824                 }
 825
 826                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 827                 if (ret)
 828                         return ret;
 829
 830                 /* Notify ucode of loaded section number and status */
 831                 if (trans->cfg->use_tfh) {
 832                         val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS);
 833                         val = val | (sec_num << shift_param);
 834                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val);
 835                 } else {
 836                         val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 837                         val = val | (sec_num << shift_param);
 838                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 839                 }
 840                 sec_num = (sec_num << 1) | 0x1;
 841         }
 842
 843         *first_ucode_section = last_read_idx;
 844
 845         iwl_enable_interrupts(trans);
 846
 847         if (trans->cfg->use_tfh) {
 848                 if (cpu == 1)
 849                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 850                                        0xFFFF);
 851                 else
 852                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 853                                        0xFFFFFFFF);
 854         } else {
 855                 if (cpu == 1)
 856                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 857                                            0xFFFF);
 858                 else
 859                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 860                                            0xFFFFFFFF);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 867                                       const struct fw_img *image,
 868                                       int cpu,
 869                                       int *first_ucode_section)
 870 {
 871         int shift_param;
 872         int i, ret = 0;
 873         u32 last_read_idx = 0;
 874
 875         if (cpu == 1) {
 876                 shift_param = 0;
 877                 *first_ucode_section = 0;
 878         } else {
 879                 shift_param = 16;
 880                 (*first_ucode_section)++;
 881         }
 882
 883         for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
 884                 last_read_idx = i;
 885
 886                 /*
 887                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 888                  * CPU1 to CPU2.
 889                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 890                  * CPU2 non paged to CPU2 paging sec.
 891                  */
 892                 if (!image->sec[i].data ||
 893                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 894                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 895                         IWL_DEBUG_FW(trans,
 896                                      "Break since Data not valid or Empty section, sec = %d\n",
 897                                      i);
 898                         break;
 899                 }
 900
 901                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 902                 if (ret)
 903                         return ret;
 904         }
 905
 906         *first_ucode_section = last_read_idx;
 907
 908         return 0;
 909 }
 910
 911 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
 912 {
 913         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 914         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 915         int i;
 916
 917         if (dest->version)
 918                 IWL_ERR(trans,
 919                         "DBG DEST version is %d - expect issues\n",
 920                         dest->version);
 921
 922         IWL_INFO(trans, "Applying debug destination %s\n",
 923                  get_fw_dbg_mode_string(dest->monitor_mode));
 924
 925         if (dest->monitor_mode == EXTERNAL_MODE)
 926                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 927         else
 928                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 929
 930         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 931                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 932                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 933
 934                 switch (dest->reg_ops[i].op) {
 935                 case CSR_ASSIGN:
 936                         iwl_write32(trans, addr, val);
 937                         break;
 938                 case CSR_SETBIT:
 939                         iwl_set_bit(trans, addr, BIT(val));
 940                         break;
 941                 case CSR_CLEARBIT:
 942                         iwl_clear_bit(trans, addr, BIT(val));
 943                         break;
 944                 case PRPH_ASSIGN:
 945                         iwl_write_prph(trans, addr, val);
 946                         break;
 947                 case PRPH_SETBIT:
 948                         iwl_set_bits_prph(trans, addr, BIT(val));
 949                         break;
 950                 case PRPH_CLEARBIT:
 951                         iwl_clear_bits_prph(trans, addr, BIT(val));
 952                         break;
 953                 case PRPH_BLOCKBIT:
 954                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 955                                 IWL_ERR(trans,
 956                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 957                                         val, addr);
 958                                 goto monitor;
 959                         }
 960                         break;
 961                 default:
 962                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 963                                 dest->reg_ops[i].op);
 964                         break;
 965                 }
 966         }
 967
 968 monitor:
 969         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 970                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 971                                trans_pcie->fw_mon_phys >> dest->base_shift);
 972                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
 973                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 974                                        (trans_pcie->fw_mon_phys +
 975                                         trans_pcie->fw_mon_size - 256) >>
 976                                                 dest->end_shift);
 977                 else
 978                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 979                                        (trans_pcie->fw_mon_phys +
 980                                         trans_pcie->fw_mon_size) >>
 981                                                 dest->end_shift);
 982         }
 983 }
 984
 985 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 986                                 const struct fw_img *image)
 987 {
 988         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 989         int ret = 0;
 990         int first_ucode_section;
 991
 992         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 993                      image->is_dual_cpus ? "Dual" : "Single");
 994
 995         /* load to FW the binary non secured sections of CPU1 */
 996         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 997         if (ret)
 998                 return ret;
 999
1000         if (image->is_dual_cpus) {
1001                 /* set CPU2 header address */
1002                 iwl_write_prph(trans,
1003                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1004                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1005
1006                 /* load to FW the binary sections of CPU2 */
1007                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1008                                                  &first_ucode_section);
1009                 if (ret)
1010                         return ret;
1011         }
1012
1013         /* supported for 7000 only for the moment */
1014         if (iwlwifi_mod_params.fw_monitor &&
1015             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1016                 iwl_pcie_alloc_fw_monitor(trans, 0);
1017
1018                 if (trans_pcie->fw_mon_size) {
1019                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1020                                        trans_pcie->fw_mon_phys >> 4);
1021                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
1022                                        (trans_pcie->fw_mon_phys +
1023                                         trans_pcie->fw_mon_size) >> 4);
1024                 }
1025         } else if (trans->dbg_dest_tlv) {
1026                 iwl_pcie_apply_destination(trans);
1027         }
1028
1029         iwl_enable_interrupts(trans);
1030
1031         /* release CPU reset */
1032         iwl_write32(trans, CSR_RESET, 0);
1033
1034         return 0;
1035 }
1036
1037 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1038                                           const struct fw_img *image)
1039 {
1040         int ret = 0;
1041         int first_ucode_section;
1042
1043         IWL_DEBUG_FW(trans, "working with %s CPU\n",
1044                      image->is_dual_cpus ? "Dual" : "Single");
1045
1046         if (trans->dbg_dest_tlv)
1047                 iwl_pcie_apply_destination(trans);
1048
1049         /* TODO: remove in the next Si step */
1050         ret = iwl_pcie_rsa_race_bug_wa(trans);
1051         if (ret)
1052                 return ret;
1053
1054         /* configure the ucode to be ready to get the secured image */
1055         /* release CPU reset */
1056         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1057
1058         /* load to FW the binary Secured sections of CPU1 */
1059         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1060                                               &first_ucode_section);
1061         if (ret)
1062                 return ret;
1063
1064         /* load to FW the binary sections of CPU2 */
1065         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1066                                                &first_ucode_section);
1067 }
1068
1069 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1070 {
1071         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1072         bool hw_rfkill, was_hw_rfkill;
1073
1074         lockdep_assert_held(&trans_pcie->mutex);
1075
1076         if (trans_pcie->is_down)
1077                 return;
1078
1079         trans_pcie->is_down = true;
1080
1081         was_hw_rfkill = iwl_is_rfkill_set(trans);
1082
1083         /* tell the device to stop sending interrupts */
1084         iwl_disable_interrupts(trans);
1085
1086         /* device going down, Stop using ICT table */
1087         iwl_pcie_disable_ict(trans);
1088
1089         /*
1090          * If a HW restart happens during firmware loading,
1091          * then the firmware loading might call this function
1092          * and later it might be called again due to the
1093          * restart. So don't process again if the device is
1094          * already dead.
1095          */
1096         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1097                 IWL_DEBUG_INFO(trans,
1098                                "DEVICE_ENABLED bit was set and is now cleared\n");
1099                 iwl_pcie_tx_stop(trans);
1100                 iwl_pcie_rx_stop(trans);
1101
1102                 /* Power-down device's busmaster DMA clocks */
1103                 if (!trans->cfg->apmg_not_supported) {
1104                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1105                                        APMG_CLK_VAL_DMA_CLK_RQT);
1106                         udelay(5);
1107                 }
1108         }
1109
1110         /* Make sure (redundant) we've released our request to stay awake */
1111         iwl_clear_bit(trans, CSR_GP_CNTRL,
1112                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1113
1114         /* Stop the device, and put it in low power state */
1115         iwl_pcie_apm_stop(trans, false);
1116
1117         /* stop and reset the on-board processor */
1118         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1119         usleep_range(1000, 2000);
1120
1121         /*
1122          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1123          * This is a bug in certain verions of the hardware.
1124          * Certain devices also keep sending HW RF kill interrupt all
1125          * the time, unless the interrupt is ACKed even if the interrupt
1126          * should be masked. Re-ACK all the interrupts here.
1127          */
1128         iwl_disable_interrupts(trans);
1129
1130         /* clear all status bits */
1131         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1132         clear_bit(STATUS_INT_ENABLED, &trans->status);
1133         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1134         clear_bit(STATUS_RFKILL, &trans->status);
1135
1136         /*
1137          * Even if we stop the HW, we still want the RF kill
1138          * interrupt
1139          */
1140         iwl_enable_rfkill_int(trans);
1141
1142         /*
1143          * Check again since the RF kill state may have changed while
1144          * all the interrupts were disabled, in this case we couldn't
1145          * receive the RF kill interrupt and update the state in the
1146          * op_mode.
1147          * Don't call the op_mode if the rkfill state hasn't changed.
1148          * This allows the op_mode to call stop_device from the rfkill
1149          * notification without endless recursion. Under very rare
1150          * circumstances, we might have a small recursion if the rfkill
1151          * state changed exactly now while we were called from stop_device.
1152          * This is very unlikely but can happen and is supported.
1153          */
1154         hw_rfkill = iwl_is_rfkill_set(trans);
1155         if (hw_rfkill)
1156                 set_bit(STATUS_RFKILL, &trans->status);
1157         else
1158                 clear_bit(STATUS_RFKILL, &trans->status);
1159         if (hw_rfkill != was_hw_rfkill)
1160                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1161
1162         /* re-take ownership to prevent other users from stealing the device */
1163         iwl_pcie_prepare_card_hw(trans);
1164 }
1165
1166 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1167 {
1168         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1169
1170         if (trans_pcie->msix_enabled) {
1171                 int i;
1172
1173                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1174                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1175         } else {
1176                 synchronize_irq(trans_pcie->pci_dev->irq);
1177         }
1178 }
1179
1180 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1181                                    const struct fw_img *fw, bool run_in_rfkill)
1182 {
1183         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1184         bool hw_rfkill;
1185         int ret;
1186
1187         /* This may fail if AMT took ownership of the device */
1188         if (iwl_pcie_prepare_card_hw(trans)) {
1189                 IWL_WARN(trans, "Exit HW not ready\n");
1190                 ret = -EIO;
1191                 goto out;
1192         }
1193
1194         iwl_enable_rfkill_int(trans);
1195
1196         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1197
1198         /*
1199          * We enabled the RF-Kill interrupt and the handler may very
1200          * well be running. Disable the interrupts to make sure no other
1201          * interrupt can be fired.
1202          */
1203         iwl_disable_interrupts(trans);
1204
1205         /* Make sure it finished running */
1206         iwl_pcie_synchronize_irqs(trans);
1207
1208         mutex_lock(&trans_pcie->mutex);
1209
1210         /* If platform's RF_KILL switch is NOT set to KILL */
1211         hw_rfkill = iwl_is_rfkill_set(trans);
1212         if (hw_rfkill)
1213                 set_bit(STATUS_RFKILL, &trans->status);
1214         else
1215                 clear_bit(STATUS_RFKILL, &trans->status);
1216         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1217         if (hw_rfkill && !run_in_rfkill) {
1218                 ret = -ERFKILL;
1219                 goto out;
1220         }
1221
1222         /* Someone called stop_device, don't try to start_fw */
1223         if (trans_pcie->is_down) {
1224                 IWL_WARN(trans,
1225                          "Can't start_fw since the HW hasn't been started\n");
1226                 ret = -EIO;
1227                 goto out;
1228         }
1229
1230         /* make sure rfkill handshake bits are cleared */
1231         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1232         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1233                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1234
1235         /* clear (again), then enable host interrupts */
1236         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1237
1238         ret = iwl_pcie_nic_init(trans);
1239         if (ret) {
1240                 IWL_ERR(trans, "Unable to init nic\n");
1241                 goto out;
1242         }
1243
1244         /*
1245          * Now, we load the firmware and don't want to be interrupted, even
1246          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1247          * FH_TX interrupt which is needed to load the firmware). If the
1248          * RF-Kill switch is toggled, we will find out after having loaded
1249          * the firmware and return the proper value to the caller.
1250          */
1251         iwl_enable_fw_load_int(trans);
1252
1253         /* really make sure rfkill handshake bits are cleared */
1254         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1255         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1256
1257         /* Load the given image to the HW */
1258         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1259                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1260         else
1261                 ret = iwl_pcie_load_given_ucode(trans, fw);
1262
1263         /* re-check RF-Kill state since we may have missed the interrupt */
1264         hw_rfkill = iwl_is_rfkill_set(trans);
1265         if (hw_rfkill)
1266                 set_bit(STATUS_RFKILL, &trans->status);
1267         else
1268                 clear_bit(STATUS_RFKILL, &trans->status);
1269
1270         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1271         if (hw_rfkill && !run_in_rfkill)
1272                 ret = -ERFKILL;
1273
1274 out:
1275         mutex_unlock(&trans_pcie->mutex);
1276         return ret;
1277 }
1278
1279 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1280 {
1281         iwl_pcie_reset_ict(trans);
1282         iwl_pcie_tx_start(trans, scd_addr);
1283 }
1284
1285 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1286 {
1287         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1288
1289         mutex_lock(&trans_pcie->mutex);
1290         _iwl_trans_pcie_stop_device(trans, low_power);
1291         mutex_unlock(&trans_pcie->mutex);
1292 }
1293
1294 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1295 {
1296         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1297                 IWL_TRANS_GET_PCIE_TRANS(trans);
1298
1299         lockdep_assert_held(&trans_pcie->mutex);
1300
1301         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1302                 _iwl_trans_pcie_stop_device(trans, true);
1303 }
1304
1305 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1306                                       bool reset)
1307 {
1308         if (!reset) {
1309                 /* Enable persistence mode to avoid reset */
1310                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1311                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1312         }
1313
1314         iwl_disable_interrupts(trans);
1315
1316         /*
1317          * in testing mode, the host stays awake and the
1318          * hardware won't be reset (not even partially)
1319          */
1320         if (test)
1321                 return;
1322
1323         iwl_pcie_disable_ict(trans);
1324
1325         iwl_pcie_synchronize_irqs(trans);
1326
1327         iwl_clear_bit(trans, CSR_GP_CNTRL,
1328                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1329         iwl_clear_bit(trans, CSR_GP_CNTRL,
1330                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1331
1332         iwl_pcie_enable_rx_wake(trans, false);
1333
1334         if (reset) {
1335                 /*
1336                  * reset TX queues -- some of their registers reset during S3
1337                  * so if we don't reset everything here the D3 image would try
1338                  * to execute some invalid memory upon resume
1339                  */
1340                 iwl_trans_pcie_tx_reset(trans);
1341         }
1342
1343         iwl_pcie_set_pwr(trans, true);
1344 }
1345
1346 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1347                                     enum iwl_d3_status *status,
1348                                     bool test,  bool reset)
1349 {
1350         u32 val;
1351         int ret;
1352
1353         if (test) {
1354                 iwl_enable_interrupts(trans);
1355                 *status = IWL_D3_STATUS_ALIVE;
1356                 return 0;
1357         }
1358
1359         iwl_pcie_enable_rx_wake(trans, true);
1360
1361         /*
1362          * Also enables interrupts - none will happen as the device doesn't
1363          * know we're waking it up, only when the opmode actually tells it
1364          * after this call.
1365          */
1366         iwl_pcie_reset_ict(trans);
1367         iwl_enable_interrupts(trans);
1368
1369         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1370         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1371
1372         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1373                 udelay(2);
1374
1375         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1376                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1377                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1378                            25000);
1379         if (ret < 0) {
1380                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1381                 return ret;
1382         }
1383
1384         iwl_pcie_set_pwr(trans, false);
1385
1386         if (!reset) {
1387                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1388                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1389         } else {
1390                 iwl_trans_pcie_tx_reset(trans);
1391
1392                 ret = iwl_pcie_rx_init(trans);
1393                 if (ret) {
1394                         IWL_ERR(trans,
1395                                 "Failed to resume the device (RX reset)\n");
1396                         return ret;
1397                 }
1398         }
1399
1400         val = iwl_read32(trans, CSR_RESET);
1401         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1402                 *status = IWL_D3_STATUS_RESET;
1403         else
1404                 *status = IWL_D3_STATUS_ALIVE;
1405
1406         return 0;
1407 }
1408
1409 struct iwl_causes_list {
1410         u32 cause_num;
1411         u32 mask_reg;
1412         u8 addr;
1413 };
1414
1415 static struct iwl_causes_list causes_list[] = {
1416         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1417         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1418         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1419         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1420         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1421         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1422         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1423         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1424         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1425         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1426         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1427         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1428         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1429         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1430 };
1431
1432 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1433 {
1434         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1435         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1436         int i;
1437
1438         /*
1439          * Access all non RX causes and map them to the default irq.
1440          * In case we are missing at least one interrupt vector,
1441          * the first interrupt vector will serve non-RX and FBQ causes.
1442          */
1443         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1444                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1445                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1446                               causes_list[i].cause_num);
1447         }
1448 }
1449
1450 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1451 {
1452         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1453         u32 offset =
1454                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1455         u32 val, idx;
1456
1457         /*
1458          * The first RX queue - fallback queue, which is designated for
1459          * management frame, command responses etc, is always mapped to the
1460          * first interrupt vector. The other RX queues are mapped to
1461          * the other (N - 2) interrupt vectors.
1462          */
1463         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1464         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1465                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1466                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1467                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1468         }
1469         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1470
1471         val = MSIX_FH_INT_CAUSES_Q(0);
1472         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1473                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1474         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1475
1476         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1477                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1478 }
1479
1480 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1481 {
1482         struct iwl_trans *trans = trans_pcie->trans;
1483
1484         if (!trans_pcie->msix_enabled) {
1485                 if (trans->cfg->mq_rx_supported)
1486                         iwl_write_prph(trans, UREG_CHICK,
1487                                        UREG_CHICK_MSI_ENABLE);
1488                 return;
1489         }
1490
1491         iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1492
1493         /*
1494          * Each cause from the causes list above and the RX causes is
1495          * represented as a byte in the IVAR table. The first nibble
1496          * represents the bound interrupt vector of the cause, the second
1497          * represents no auto clear for this cause. This will be set if its
1498          * interrupt vector is bound to serve other causes.
1499          */
1500         iwl_pcie_map_rx_causes(trans);
1501
1502         iwl_pcie_map_non_rx_causes(trans);
1503
1504         trans_pcie->fh_init_mask =
1505                 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1506         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1507         trans_pcie->hw_init_mask =
1508                 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1509         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1510 }
1511
1512 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1513                                         struct iwl_trans *trans)
1514 {
1515         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1516         int max_irqs, num_irqs, i, ret, nr_online_cpus;
1517         u16 pci_cmd;
1518
1519         if (!trans->cfg->mq_rx_supported)
1520                 goto enable_msi;
1521
1522         nr_online_cpus = num_online_cpus();
1523         max_irqs = min_t(u32, nr_online_cpus + 2, IWL_MAX_RX_HW_QUEUES);
1524         for (i = 0; i < max_irqs; i++)
1525                 trans_pcie->msix_entries[i].entry = i;
1526
1527         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1528                                          MSIX_MIN_INTERRUPT_VECTORS,
1529                                          max_irqs);
1530         if (num_irqs < 0) {
1531                 IWL_DEBUG_INFO(trans,
1532                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1533                                num_irqs);
1534                 goto enable_msi;
1535         }
1536         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1537
1538         IWL_DEBUG_INFO(trans,
1539                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1540                        num_irqs);
1541
1542         /*
1543          * In case the OS provides fewer interrupts than requested, different
1544          * causes will share the same interrupt vector as follows:
1545          * One interrupt less: non rx causes shared with FBQ.
1546          * Two interrupts less: non rx causes shared with FBQ and RSS.
1547          * More than two interrupts: we will use fewer RSS queues.
1548          */
1549         if (num_irqs <= nr_online_cpus) {
1550                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1551                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1552                         IWL_SHARED_IRQ_FIRST_RSS;
1553         } else if (num_irqs == nr_online_cpus + 1) {
1554                 trans_pcie->trans->num_rx_queues = num_irqs;
1555                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1556         } else {
1557                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1558         }
1559
1560         trans_pcie->alloc_vecs = num_irqs;
1561         trans_pcie->msix_enabled = true;
1562         return;
1563
1564 enable_msi:
1565         ret = pci_enable_msi(pdev);
1566         if (ret) {
1567                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1568                 /* enable rfkill interrupt: hw bug w/a */
1569                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1570                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1571                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1572                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1573                 }
1574         }
1575 }
1576
1577 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1578 {
1579         int iter_rx_q, i, ret, cpu, offset;
1580         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1581
1582         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1583         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1584         offset = 1 + i;
1585         for (; i < iter_rx_q ; i++) {
1586                 /*
1587                  * Get the cpu prior to the place to search
1588                  * (i.e. return will be > i - 1).
1589                  */
1590                 cpu = cpumask_next(i - offset, cpu_online_mask);
1591                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1592                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1593                                             &trans_pcie->affinity_mask[i]);
1594                 if (ret)
1595                         IWL_ERR(trans_pcie->trans,
1596                                 "Failed to set affinity mask for IRQ %d\n",
1597                                 i);
1598         }
1599 }
1600
1601 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1602                                       struct iwl_trans_pcie *trans_pcie)
1603 {
1604         int i;
1605
1606         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1607                 int ret;
1608                 struct msix_entry *msix_entry;
1609
1610                 msix_entry = &trans_pcie->msix_entries[i];
1611                 ret = devm_request_threaded_irq(&pdev->dev,
1612                                                 msix_entry->vector,
1613                                                 iwl_pcie_msix_isr,
1614                                                 (i == trans_pcie->def_irq) ?
1615                                                 iwl_pcie_irq_msix_handler :
1616                                                 iwl_pcie_irq_rx_msix_handler,
1617                                                 IRQF_SHARED,
1618                                                 DRV_NAME,
1619                                                 msix_entry);
1620                 if (ret) {
1621                         IWL_ERR(trans_pcie->trans,
1622                                 "Error allocating IRQ %d\n", i);
1623
1624                         return ret;
1625                 }
1626         }
1627         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1628
1629         return 0;
1630 }
1631
1632 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1633 {
1634         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1635         bool hw_rfkill;
1636         int err;
1637
1638         lockdep_assert_held(&trans_pcie->mutex);
1639
1640         err = iwl_pcie_prepare_card_hw(trans);
1641         if (err) {
1642                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1643                 return err;
1644         }
1645
1646         /* Reset the entire device */
1647         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1648         usleep_range(1000, 2000);
1649
1650         iwl_pcie_apm_init(trans);
1651
1652         iwl_pcie_init_msix(trans_pcie);
1653         /* From now on, the op_mode will be kept updated about RF kill state */
1654         iwl_enable_rfkill_int(trans);
1655
1656         /* Set is_down to false here so that...*/
1657         trans_pcie->is_down = false;
1658
1659         hw_rfkill = iwl_is_rfkill_set(trans);
1660         if (hw_rfkill)
1661                 set_bit(STATUS_RFKILL, &trans->status);
1662         else
1663                 clear_bit(STATUS_RFKILL, &trans->status);
1664         /* ... rfkill can call stop_device and set it false if needed */
1665         iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1666
1667         /* Make sure we sync here, because we'll need full access later */
1668         if (low_power)
1669                 pm_runtime_resume(trans->dev);
1670
1671         return 0;
1672 }
1673
1674 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1675 {
1676         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1677         int ret;
1678
1679         mutex_lock(&trans_pcie->mutex);
1680         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1681         mutex_unlock(&trans_pcie->mutex);
1682
1683         return ret;
1684 }
1685
1686 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1687 {
1688         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1689
1690         mutex_lock(&trans_pcie->mutex);
1691
1692         /* disable interrupts - don't enable HW RF kill interrupt */
1693         iwl_disable_interrupts(trans);
1694
1695         iwl_pcie_apm_stop(trans, true);
1696
1697         iwl_disable_interrupts(trans);
1698
1699         iwl_pcie_disable_ict(trans);
1700
1701         mutex_unlock(&trans_pcie->mutex);
1702
1703         iwl_pcie_synchronize_irqs(trans);
1704 }
1705
1706 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1707 {
1708         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1709 }
1710
1711 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1712 {
1713         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1714 }
1715
1716 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1717 {
1718         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1719 }
1720
1721 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1722 {
1723         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1724                                ((reg & 0x000FFFFF) | (3 << 24)));
1725         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1726 }
1727
1728 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1729                                       u32 val)
1730 {
1731         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1732                                ((addr & 0x000FFFFF) | (3 << 24)));
1733         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1734 }
1735
1736 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1737                                      const struct iwl_trans_config *trans_cfg)
1738 {
1739         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1740
1741         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1742         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1743         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1744         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1745                 trans_pcie->n_no_reclaim_cmds = 0;
1746         else
1747                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1748         if (trans_pcie->n_no_reclaim_cmds)
1749                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1750                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1751
1752         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1753         trans_pcie->rx_page_order =
1754                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1755
1756         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1757         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1758         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1759
1760         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1761         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1762
1763         trans->command_groups = trans_cfg->command_groups;
1764         trans->command_groups_size = trans_cfg->command_groups_size;
1765
1766         /* Initialize NAPI here - it should be before registering to mac80211
1767          * in the opmode but after the HW struct is allocated.
1768          * As this function may be called again in some corner cases don't
1769          * do anything if NAPI was already initialized.
1770          */
1771         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1772                 init_dummy_netdev(&trans_pcie->napi_dev);
1773 }
1774
1775 void iwl_trans_pcie_free(struct iwl_trans *trans)
1776 {
1777         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1778         int i;
1779
1780         iwl_pcie_synchronize_irqs(trans);
1781
1782         iwl_pcie_tx_free(trans);
1783         iwl_pcie_rx_free(trans);
1784
1785         if (trans_pcie->msix_enabled) {
1786                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1787                         irq_set_affinity_hint(
1788                                 trans_pcie->msix_entries[i].vector,
1789                                 NULL);
1790                 }
1791
1792                 trans_pcie->msix_enabled = false;
1793         } else {
1794                 iwl_pcie_free_ict(trans);
1795         }
1796
1797         iwl_pcie_free_fw_monitor(trans);
1798
1799         for_each_possible_cpu(i) {
1800                 struct iwl_tso_hdr_page *p =
1801                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1802
1803                 if (p->page)
1804                         __free_page(p->page);
1805         }
1806
1807         free_percpu(trans_pcie->tso_hdr_page);
1808         mutex_destroy(&trans_pcie->mutex);
1809         iwl_trans_free(trans);
1810 }
1811
1812 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1813 {
1814         if (state)
1815                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1816         else
1817                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1818 }
1819
1820 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1821                                            unsigned long *flags)
1822 {
1823         int ret;
1824         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1825
1826         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1827
1828         if (trans_pcie->cmd_hold_nic_awake)
1829                 goto out;
1830
1831         /* this bit wakes up the NIC */
1832         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1833                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1834         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1835                 udelay(2);
1836
1837         /*
1838          * These bits say the device is running, and should keep running for
1839          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1840          * but they do not indicate that embedded SRAM is restored yet;
1841          * 3945 and 4965 have volatile SRAM, and must save/restore contents
1842          * to/from host DRAM when sleeping/waking for power-saving.
1843          * Each direction takes approximately 1/4 millisecond; with this
1844          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1845          * series of register accesses are expected (e.g. reading Event Log),
1846          * to keep device from sleeping.
1847          *
1848          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1849          * SRAM is okay/restored.  We don't check that here because this call
1850          * is just for hardware register access; but GP1 MAC_SLEEP check is a
1851          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1852          *
1853          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1854          * and do not save/restore SRAM when power cycling.
1855          */
1856         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1857                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1858                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1859                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1860         if (unlikely(ret < 0)) {
1861                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1862                 WARN_ONCE(1,
1863                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1864                           iwl_read32(trans, CSR_GP_CNTRL));
1865                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1866                 return false;
1867         }
1868
1869 out:
1870         /*
1871          * Fool sparse by faking we release the lock - sparse will
1872          * track nic_access anyway.
1873          */
1874         __release(&trans_pcie->reg_lock);
1875         return true;
1876 }
1877
1878 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1879                                               unsigned long *flags)
1880 {
1881         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1882
1883         lockdep_assert_held(&trans_pcie->reg_lock);
1884
1885         /*
1886          * Fool sparse by faking we acquiring the lock - sparse will
1887          * track nic_access anyway.
1888          */
1889         __acquire(&trans_pcie->reg_lock);
1890
1891         if (trans_pcie->cmd_hold_nic_awake)
1892                 goto out;
1893
1894         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1895                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1896         /*
1897          * Above we read the CSR_GP_CNTRL register, which will flush
1898          * any previous writes, but we need the write that clears the
1899          * MAC_ACCESS_REQ bit to be performed before any other writes
1900          * scheduled on different CPUs (after we drop reg_lock).
1901          */
1902         mmiowb();
1903 out:
1904         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1905 }
1906
1907 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1908                                    void *buf, int dwords)
1909 {
1910         unsigned long flags;
1911         int offs, ret = 0;
1912         u32 *vals = buf;
1913
1914         if (iwl_trans_grab_nic_access(trans, &flags)) {
1915                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
1916                 for (offs = 0; offs < dwords; offs++)
1917                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
1918                 iwl_trans_release_nic_access(trans, &flags);
1919         } else {
1920                 ret = -EBUSY;
1921         }
1922         return ret;
1923 }
1924
1925 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1926                                     const void *buf, int dwords)
1927 {
1928         unsigned long flags;
1929         int offs, ret = 0;
1930         const u32 *vals = buf;
1931
1932         if (iwl_trans_grab_nic_access(trans, &flags)) {
1933                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1934                 for (offs = 0; offs < dwords; offs++)
1935                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1936                                     vals ? vals[offs] : 0);
1937                 iwl_trans_release_nic_access(trans, &flags);
1938         } else {
1939                 ret = -EBUSY;
1940         }
1941         return ret;
1942 }
1943
1944 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1945                                             unsigned long txqs,
1946                                             bool freeze)
1947 {
1948         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1949         int queue;
1950
1951         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1952                 struct iwl_txq *txq = &trans_pcie->txq[queue];
1953                 unsigned long now;
1954
1955                 spin_lock_bh(&txq->lock);
1956
1957                 now = jiffies;
1958
1959                 if (txq->frozen == freeze)
1960                         goto next_queue;
1961
1962                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1963                                     freeze ? "Freezing" : "Waking", queue);
1964
1965                 txq->frozen = freeze;
1966
1967                 if (txq->read_ptr == txq->write_ptr)
1968                         goto next_queue;
1969
1970                 if (freeze) {
1971                         if (unlikely(time_after(now,
1972                                                 txq->stuck_timer.expires))) {
1973                                 /*
1974                                  * The timer should have fired, maybe it is
1975                                  * spinning right now on the lock.
1976                                  */
1977                                 goto next_queue;
1978                         }
1979                         /* remember how long until the timer fires */
1980                         txq->frozen_expiry_remainder =
1981                                 txq->stuck_timer.expires - now;
1982                         del_timer(&txq->stuck_timer);
1983                         goto next_queue;
1984                 }
1985
1986                 /*
1987                  * Wake a non-empty queue -> arm timer with the
1988                  * remainder before it froze
1989                  */
1990                 mod_timer(&txq->stuck_timer,
1991                           now + txq->frozen_expiry_remainder);
1992
1993 next_queue:
1994                 spin_unlock_bh(&txq->lock);
1995         }
1996 }
1997
1998 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
1999 {
2000         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2001         int i;
2002
2003         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2004                 struct iwl_txq *txq = &trans_pcie->txq[i];
2005
2006                 if (i == trans_pcie->cmd_queue)
2007                         continue;
2008
2009                 spin_lock_bh(&txq->lock);
2010
2011                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2012                         txq->block--;
2013                         if (!txq->block) {
2014                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2015                                             txq->write_ptr | (i << 8));
2016                         }
2017                 } else if (block) {
2018                         txq->block++;
2019                 }
2020
2021                 spin_unlock_bh(&txq->lock);
2022         }
2023 }
2024
2025 #define IWL_FLUSH_WAIT_MS       2000
2026
2027 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2028 {
2029         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2030         u32 scd_sram_addr;
2031         u8 buf[16];
2032         int cnt;
2033
2034         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
2035                 txq->read_ptr, txq->write_ptr);
2036
2037         if (trans->cfg->use_tfh)
2038                 /* TODO: access new SCD registers and dump them */
2039                 return;
2040
2041         scd_sram_addr = trans_pcie->scd_base_addr +
2042                         SCD_TX_STTS_QUEUE_OFFSET(txq->id);
2043         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
2044
2045         iwl_print_hex_error(trans, buf, sizeof(buf));
2046
2047         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
2048                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
2049                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
2050
2051         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2052                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
2053                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2054                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2055                 u32 tbl_dw =
2056                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
2057                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
2058
2059                 if (cnt & 0x1)
2060                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2061                 else
2062                         tbl_dw = tbl_dw & 0x0000FFFF;
2063
2064                 IWL_ERR(trans,
2065                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2066                         cnt, active ? "" : "in", fifo, tbl_dw,
2067                         iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2068                                 (TFD_QUEUE_SIZE_MAX - 1),
2069                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2070         }
2071 }
2072
2073 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
2074 {
2075         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2076         struct iwl_txq *txq;
2077         int cnt;
2078         unsigned long now = jiffies;
2079         int ret = 0;
2080
2081         /* waiting for all the tx frames complete might take a while */
2082         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2083                 u8 wr_ptr;
2084
2085                 if (cnt == trans_pcie->cmd_queue)
2086                         continue;
2087                 if (!test_bit(cnt, trans_pcie->queue_used))
2088                         continue;
2089                 if (!(BIT(cnt) & txq_bm))
2090                         continue;
2091
2092                 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
2093                 txq = &trans_pcie->txq[cnt];
2094                 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2095
2096                 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2097                        !time_after(jiffies,
2098                                    now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2099                         u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2100
2101                         if (WARN_ONCE(wr_ptr != write_ptr,
2102                                       "WR pointer moved while flushing %d -> %d\n",
2103                                       wr_ptr, write_ptr))
2104                                 return -ETIMEDOUT;
2105                         usleep_range(1000, 2000);
2106                 }
2107
2108                 if (txq->read_ptr != txq->write_ptr) {
2109                         IWL_ERR(trans,
2110                                 "fail to flush all tx fifo queues Q %d\n", cnt);
2111                         ret = -ETIMEDOUT;
2112                         break;
2113                 }
2114                 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
2115         }
2116
2117         if (ret)
2118                 iwl_trans_pcie_log_scd_error(trans, txq);
2119
2120         return ret;
2121 }
2122
2123 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2124                                          u32 mask, u32 value)
2125 {
2126         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2127         unsigned long flags;
2128
2129         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2130         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2131         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2132 }
2133
2134 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2135 {
2136         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2137
2138         if (iwlwifi_mod_params.d0i3_disable)
2139                 return;
2140
2141         pm_runtime_get(&trans_pcie->pci_dev->dev);
2142
2143 #ifdef CONFIG_PM
2144         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2145                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2146 #endif /* CONFIG_PM */
2147 }
2148
2149 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2150 {
2151         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2152
2153         if (iwlwifi_mod_params.d0i3_disable)
2154                 return;
2155
2156         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2157         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2158
2159 #ifdef CONFIG_PM
2160         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2161                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2162 #endif /* CONFIG_PM */
2163 }
2164
2165 static const char *get_csr_string(int cmd)
2166 {
2167 #define IWL_CMD(x) case x: return #x
2168         switch (cmd) {
2169         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2170         IWL_CMD(CSR_INT_COALESCING);
2171         IWL_CMD(CSR_INT);
2172         IWL_CMD(CSR_INT_MASK);
2173         IWL_CMD(CSR_FH_INT_STATUS);
2174         IWL_CMD(CSR_GPIO_IN);
2175         IWL_CMD(CSR_RESET);
2176         IWL_CMD(CSR_GP_CNTRL);
2177         IWL_CMD(CSR_HW_REV);
2178         IWL_CMD(CSR_EEPROM_REG);
2179         IWL_CMD(CSR_EEPROM_GP);
2180         IWL_CMD(CSR_OTP_GP_REG);
2181         IWL_CMD(CSR_GIO_REG);
2182         IWL_CMD(CSR_GP_UCODE_REG);
2183         IWL_CMD(CSR_GP_DRIVER_REG);
2184         IWL_CMD(CSR_UCODE_DRV_GP1);
2185         IWL_CMD(CSR_UCODE_DRV_GP2);
2186         IWL_CMD(CSR_LED_REG);
2187         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2188         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2189         IWL_CMD(CSR_ANA_PLL_CFG);
2190         IWL_CMD(CSR_HW_REV_WA_REG);
2191         IWL_CMD(CSR_MONITOR_STATUS_REG);
2192         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2193         default:
2194                 return "UNKNOWN";
2195         }
2196 #undef IWL_CMD
2197 }
2198
2199 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2200 {
2201         int i;
2202         static const u32 csr_tbl[] = {
2203                 CSR_HW_IF_CONFIG_REG,
2204                 CSR_INT_COALESCING,
2205                 CSR_INT,
2206                 CSR_INT_MASK,
2207                 CSR_FH_INT_STATUS,
2208                 CSR_GPIO_IN,
2209                 CSR_RESET,
2210                 CSR_GP_CNTRL,
2211                 CSR_HW_REV,
2212                 CSR_EEPROM_REG,
2213                 CSR_EEPROM_GP,
2214                 CSR_OTP_GP_REG,
2215                 CSR_GIO_REG,
2216                 CSR_GP_UCODE_REG,
2217                 CSR_GP_DRIVER_REG,
2218                 CSR_UCODE_DRV_GP1,
2219                 CSR_UCODE_DRV_GP2,
2220                 CSR_LED_REG,
2221                 CSR_DRAM_INT_TBL_REG,
2222                 CSR_GIO_CHICKEN_BITS,
2223                 CSR_ANA_PLL_CFG,
2224                 CSR_MONITOR_STATUS_REG,
2225                 CSR_HW_REV_WA_REG,
2226                 CSR_DBG_HPET_MEM_REG
2227         };
2228         IWL_ERR(trans, "CSR values:\n");
2229         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2230                 "CSR_INT_PERIODIC_REG)\n");
2231         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2232                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2233                         get_csr_string(csr_tbl[i]),
2234                         iwl_read32(trans, csr_tbl[i]));
2235         }
2236 }
2237
2238 #ifdef CONFIG_IWLWIFI_DEBUGFS
2239 /* create and remove of files */
2240 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2241         if (!debugfs_create_file(#name, mode, parent, trans,            \
2242                                  &iwl_dbgfs_##name##_ops))              \
2243                 goto err;                                               \
2244 } while (0)
2245
2246 /* file operation */
2247 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2248 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2249         .read = iwl_dbgfs_##name##_read,                                \
2250         .open = simple_open,                                            \
2251         .llseek = generic_file_llseek,                                  \
2252 };
2253
2254 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2255 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2256         .write = iwl_dbgfs_##name##_write,                              \
2257         .open = simple_open,                                            \
2258         .llseek = generic_file_llseek,                                  \
2259 };
2260
2261 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2262 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2263         .write = iwl_dbgfs_##name##_write,                              \
2264         .read = iwl_dbgfs_##name##_read,                                \
2265         .open = simple_open,                                            \
2266         .llseek = generic_file_llseek,                                  \
2267 };
2268
2269 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2270                                        char __user *user_buf,
2271                                        size_t count, loff_t *ppos)
2272 {
2273         struct iwl_trans *trans = file->private_data;
2274         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2275         struct iwl_txq *txq;
2276         char *buf;
2277         int pos = 0;
2278         int cnt;
2279         int ret;
2280         size_t bufsz;
2281
2282         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2283
2284         if (!trans_pcie->txq)
2285                 return -EAGAIN;
2286
2287         buf = kzalloc(bufsz, GFP_KERNEL);
2288         if (!buf)
2289                 return -ENOMEM;
2290
2291         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2292                 txq = &trans_pcie->txq[cnt];
2293                 pos += scnprintf(buf + pos, bufsz - pos,
2294                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2295                                 cnt, txq->read_ptr, txq->write_ptr,
2296                                 !!test_bit(cnt, trans_pcie->queue_used),
2297                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2298                                  txq->need_update, txq->frozen,
2299                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2300         }
2301         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2302         kfree(buf);
2303         return ret;
2304 }
2305
2306 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2307                                        char __user *user_buf,
2308                                        size_t count, loff_t *ppos)
2309 {
2310         struct iwl_trans *trans = file->private_data;
2311         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2312         char *buf;
2313         int pos = 0, i, ret;
2314         size_t bufsz = sizeof(buf);
2315
2316         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2317
2318         if (!trans_pcie->rxq)
2319                 return -EAGAIN;
2320
2321         buf = kzalloc(bufsz, GFP_KERNEL);
2322         if (!buf)
2323                 return -ENOMEM;
2324
2325         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2326                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2327
2328                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2329                                  i);
2330                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2331                                  rxq->read);
2332                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2333                                  rxq->write);
2334                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2335                                  rxq->write_actual);
2336                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2337                                  rxq->need_update);
2338                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2339                                  rxq->free_count);
2340                 if (rxq->rb_stts) {
2341                         pos += scnprintf(buf + pos, bufsz - pos,
2342                                          "\tclosed_rb_num: %u\n",
2343                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2344                                          0x0FFF);
2345                 } else {
2346                         pos += scnprintf(buf + pos, bufsz - pos,
2347                                          "\tclosed_rb_num: Not Allocated\n");
2348                 }
2349         }
2350         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2351         kfree(buf);
2352
2353         return ret;
2354 }
2355
2356 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2357                                         char __user *user_buf,
2358                                         size_t count, loff_t *ppos)
2359 {
2360         struct iwl_trans *trans = file->private_data;
2361         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2362         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2363
2364         int pos = 0;
2365         char *buf;
2366         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2367         ssize_t ret;
2368
2369         buf = kzalloc(bufsz, GFP_KERNEL);
2370         if (!buf)
2371                 return -ENOMEM;
2372
2373         pos += scnprintf(buf + pos, bufsz - pos,
2374                         "Interrupt Statistics Report:\n");
2375
2376         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2377                 isr_stats->hw);
2378         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2379                 isr_stats->sw);
2380         if (isr_stats->sw || isr_stats->hw) {
2381                 pos += scnprintf(buf + pos, bufsz - pos,
2382                         "\tLast Restarting Code:  0x%X\n",
2383                         isr_stats->err_code);
2384         }
2385 #ifdef CONFIG_IWLWIFI_DEBUG
2386         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2387                 isr_stats->sch);
2388         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2389                 isr_stats->alive);
2390 #endif
2391         pos += scnprintf(buf + pos, bufsz - pos,
2392                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2393
2394         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2395                 isr_stats->ctkill);
2396
2397         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2398                 isr_stats->wakeup);
2399
2400         pos += scnprintf(buf + pos, bufsz - pos,
2401                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2402
2403         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2404                 isr_stats->tx);
2405
2406         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2407                 isr_stats->unhandled);
2408
2409         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2410         kfree(buf);
2411         return ret;
2412 }
2413
2414 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2415                                          const char __user *user_buf,
2416                                          size_t count, loff_t *ppos)
2417 {
2418         struct iwl_trans *trans = file->private_data;
2419         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2420         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2421
2422         char buf[8];
2423         int buf_size;
2424         u32 reset_flag;
2425
2426         memset(buf, 0, sizeof(buf));
2427         buf_size = min(count, sizeof(buf) -  1);
2428         if (copy_from_user(buf, user_buf, buf_size))
2429                 return -EFAULT;
2430         if (sscanf(buf, "%x", &reset_flag) != 1)
2431                 return -EFAULT;
2432         if (reset_flag == 0)
2433                 memset(isr_stats, 0, sizeof(*isr_stats));
2434
2435         return count;
2436 }
2437
2438 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2439                                    const char __user *user_buf,
2440                                    size_t count, loff_t *ppos)
2441 {
2442         struct iwl_trans *trans = file->private_data;
2443         char buf[8];
2444         int buf_size;
2445         int csr;
2446
2447         memset(buf, 0, sizeof(buf));
2448         buf_size = min(count, sizeof(buf) -  1);
2449         if (copy_from_user(buf, user_buf, buf_size))
2450                 return -EFAULT;
2451         if (sscanf(buf, "%d", &csr) != 1)
2452                 return -EFAULT;
2453
2454         iwl_pcie_dump_csr(trans);
2455
2456         return count;
2457 }
2458
2459 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2460                                      char __user *user_buf,
2461                                      size_t count, loff_t *ppos)
2462 {
2463         struct iwl_trans *trans = file->private_data;
2464         char *buf = NULL;
2465         ssize_t ret;
2466
2467         ret = iwl_dump_fh(trans, &buf);
2468         if (ret < 0)
2469                 return ret;
2470         if (!buf)
2471                 return -EINVAL;
2472         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2473         kfree(buf);
2474         return ret;
2475 }
2476
2477 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2478 DEBUGFS_READ_FILE_OPS(fh_reg);
2479 DEBUGFS_READ_FILE_OPS(rx_queue);
2480 DEBUGFS_READ_FILE_OPS(tx_queue);
2481 DEBUGFS_WRITE_FILE_OPS(csr);
2482
2483 /* Create the debugfs files and directories */
2484 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2485 {
2486         struct dentry *dir = trans->dbgfs_dir;
2487
2488         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2489         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2490         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2491         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2492         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2493         return 0;
2494
2495 err:
2496         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2497         return -ENOMEM;
2498 }
2499 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2500
2501 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2502 {
2503         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2504         u32 cmdlen = 0;
2505         int i;
2506
2507         for (i = 0; i < trans_pcie->max_tbs; i++)
2508                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2509
2510         return cmdlen;
2511 }
2512
2513 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2514                                    struct iwl_fw_error_dump_data **data,
2515                                    int allocated_rb_nums)
2516 {
2517         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2518         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2519         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2520         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2521         u32 i, r, j, rb_len = 0;
2522
2523         spin_lock(&rxq->lock);
2524
2525         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2526
2527         for (i = rxq->read, j = 0;
2528              i != r && j < allocated_rb_nums;
2529              i = (i + 1) & RX_QUEUE_MASK, j++) {
2530                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2531                 struct iwl_fw_error_dump_rb *rb;
2532
2533                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2534                                DMA_FROM_DEVICE);
2535
2536                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2537
2538                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2539                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2540                 rb = (void *)(*data)->data;
2541                 rb->index = cpu_to_le32(i);
2542                 memcpy(rb->data, page_address(rxb->page), max_len);
2543                 /* remap the page for the free benefit */
2544                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2545                                                      max_len,
2546                                                      DMA_FROM_DEVICE);
2547
2548                 *data = iwl_fw_error_next_data(*data);
2549         }
2550
2551         spin_unlock(&rxq->lock);
2552
2553         return rb_len;
2554 }
2555 #define IWL_CSR_TO_DUMP (0x250)
2556
2557 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2558                                    struct iwl_fw_error_dump_data **data)
2559 {
2560         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2561         __le32 *val;
2562         int i;
2563
2564         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2565         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2566         val = (void *)(*data)->data;
2567
2568         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2569                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2570
2571         *data = iwl_fw_error_next_data(*data);
2572
2573         return csr_len;
2574 }
2575
2576 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2577                                        struct iwl_fw_error_dump_data **data)
2578 {
2579         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2580         unsigned long flags;
2581         __le32 *val;
2582         int i;
2583
2584         if (!iwl_trans_grab_nic_access(trans, &flags))
2585                 return 0;
2586
2587         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2588         (*data)->len = cpu_to_le32(fh_regs_len);
2589         val = (void *)(*data)->data;
2590
2591         for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2592                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2593
2594         iwl_trans_release_nic_access(trans, &flags);
2595
2596         *data = iwl_fw_error_next_data(*data);
2597
2598         return sizeof(**data) + fh_regs_len;
2599 }
2600
2601 static u32
2602 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2603                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2604                                  u32 monitor_len)
2605 {
2606         u32 buf_size_in_dwords = (monitor_len >> 2);
2607         u32 *buffer = (u32 *)fw_mon_data->data;
2608         unsigned long flags;
2609         u32 i;
2610
2611         if (!iwl_trans_grab_nic_access(trans, &flags))
2612                 return 0;
2613
2614         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2615         for (i = 0; i < buf_size_in_dwords; i++)
2616                 buffer[i] = iwl_read_prph_no_grab(trans,
2617                                 MON_DMARB_RD_DATA_ADDR);
2618         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2619
2620         iwl_trans_release_nic_access(trans, &flags);
2621
2622         return monitor_len;
2623 }
2624
2625 static u32
2626 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2627                             struct iwl_fw_error_dump_data **data,
2628                             u32 monitor_len)
2629 {
2630         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2631         u32 len = 0;
2632
2633         if ((trans_pcie->fw_mon_page &&
2634              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2635             trans->dbg_dest_tlv) {
2636                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2637                 u32 base, write_ptr, wrap_cnt;
2638
2639                 /* If there was a dest TLV - use the values from there */
2640                 if (trans->dbg_dest_tlv) {
2641                         write_ptr =
2642                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2643                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2644                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2645                 } else {
2646                         base = MON_BUFF_BASE_ADDR;
2647                         write_ptr = MON_BUFF_WRPTR;
2648                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2649                 }
2650
2651                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2652                 fw_mon_data = (void *)(*data)->data;
2653                 fw_mon_data->fw_mon_wr_ptr =
2654                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2655                 fw_mon_data->fw_mon_cycle_cnt =
2656                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2657                 fw_mon_data->fw_mon_base_ptr =
2658                         cpu_to_le32(iwl_read_prph(trans, base));
2659
2660                 len += sizeof(**data) + sizeof(*fw_mon_data);
2661                 if (trans_pcie->fw_mon_page) {
2662                         /*
2663                          * The firmware is now asserted, it won't write anything
2664                          * to the buffer. CPU can take ownership to fetch the
2665                          * data. The buffer will be handed back to the device
2666                          * before the firmware will be restarted.
2667                          */
2668                         dma_sync_single_for_cpu(trans->dev,
2669                                                 trans_pcie->fw_mon_phys,
2670                                                 trans_pcie->fw_mon_size,
2671                                                 DMA_FROM_DEVICE);
2672                         memcpy(fw_mon_data->data,
2673                                page_address(trans_pcie->fw_mon_page),
2674                                trans_pcie->fw_mon_size);
2675
2676                         monitor_len = trans_pcie->fw_mon_size;
2677                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2678                         /*
2679                          * Update pointers to reflect actual values after
2680                          * shifting
2681                          */
2682                         base = iwl_read_prph(trans, base) <<
2683                                trans->dbg_dest_tlv->base_shift;
2684                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2685                                            monitor_len / sizeof(u32));
2686                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2687                         monitor_len =
2688                                 iwl_trans_pci_dump_marbh_monitor(trans,
2689                                                                  fw_mon_data,
2690                                                                  monitor_len);
2691                 } else {
2692                         /* Didn't match anything - output no monitor data */
2693                         monitor_len = 0;
2694                 }
2695
2696                 len += monitor_len;
2697                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2698         }
2699
2700         return len;
2701 }
2702
2703 static struct iwl_trans_dump_data
2704 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2705                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2706 {
2707         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2708         struct iwl_fw_error_dump_data *data;
2709         struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2710         struct iwl_fw_error_dump_txcmd *txcmd;
2711         struct iwl_trans_dump_data *dump_data;
2712         u32 len, num_rbs;
2713         u32 monitor_len;
2714         int i, ptr;
2715         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2716                         !trans->cfg->mq_rx_supported;
2717
2718         /* transport dump header */
2719         len = sizeof(*dump_data);
2720
2721         /* host commands */
2722         len += sizeof(*data) +
2723                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2724
2725         /* FW monitor */
2726         if (trans_pcie->fw_mon_page) {
2727                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2728                        trans_pcie->fw_mon_size;
2729                 monitor_len = trans_pcie->fw_mon_size;
2730         } else if (trans->dbg_dest_tlv) {
2731                 u32 base, end;
2732
2733                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2734                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2735
2736                 base = iwl_read_prph(trans, base) <<
2737                        trans->dbg_dest_tlv->base_shift;
2738                 end = iwl_read_prph(trans, end) <<
2739                       trans->dbg_dest_tlv->end_shift;
2740
2741                 /* Make "end" point to the actual end */
2742                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2743                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2744                         end += (1 << trans->dbg_dest_tlv->end_shift);
2745                 monitor_len = end - base;
2746                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2747                        monitor_len;
2748         } else {
2749                 monitor_len = 0;
2750         }
2751
2752         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2753                 dump_data = vzalloc(len);
2754                 if (!dump_data)
2755                         return NULL;
2756
2757                 data = (void *)dump_data->data;
2758                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2759                 dump_data->len = len;
2760
2761                 return dump_data;
2762         }
2763
2764         /* CSR registers */
2765         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2766
2767         /* FH registers */
2768         len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2769
2770         if (dump_rbs) {
2771                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2772                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2773                 /* RBs */
2774                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2775                                       & 0x0FFF;
2776                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2777                 len += num_rbs * (sizeof(*data) +
2778                                   sizeof(struct iwl_fw_error_dump_rb) +
2779                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2780         }
2781
2782         dump_data = vzalloc(len);
2783         if (!dump_data)
2784                 return NULL;
2785
2786         len = 0;
2787         data = (void *)dump_data->data;
2788         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2789         txcmd = (void *)data->data;
2790         spin_lock_bh(&cmdq->lock);
2791         ptr = cmdq->write_ptr;
2792         for (i = 0; i < cmdq->n_window; i++) {
2793                 u8 idx = get_cmd_index(cmdq, ptr);
2794                 u32 caplen, cmdlen;
2795
2796                 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2797                                                    trans_pcie->tfd_size * ptr);
2798                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2799
2800                 if (cmdlen) {
2801                         len += sizeof(*txcmd) + caplen;
2802                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2803                         txcmd->caplen = cpu_to_le32(caplen);
2804                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2805                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2806                 }
2807
2808                 ptr = iwl_queue_dec_wrap(ptr);
2809         }
2810         spin_unlock_bh(&cmdq->lock);
2811
2812         data->len = cpu_to_le32(len);
2813         len += sizeof(*data);
2814         data = iwl_fw_error_next_data(data);
2815
2816         len += iwl_trans_pcie_dump_csr(trans, &data);
2817         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2818         if (dump_rbs)
2819                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2820
2821         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2822
2823         dump_data->len = len;
2824
2825         return dump_data;
2826 }
2827
2828 #ifdef CONFIG_PM_SLEEP
2829 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2830 {
2831         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2832                 return iwl_pci_fw_enter_d0i3(trans);
2833
2834         return 0;
2835 }
2836
2837 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2838 {
2839         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3)
2840                 iwl_pci_fw_exit_d0i3(trans);
2841 }
2842 #endif /* CONFIG_PM_SLEEP */
2843
2844 static const struct iwl_trans_ops trans_ops_pcie = {
2845         .start_hw = iwl_trans_pcie_start_hw,
2846         .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2847         .fw_alive = iwl_trans_pcie_fw_alive,
2848         .start_fw = iwl_trans_pcie_start_fw,
2849         .stop_device = iwl_trans_pcie_stop_device,
2850
2851         .d3_suspend = iwl_trans_pcie_d3_suspend,
2852         .d3_resume = iwl_trans_pcie_d3_resume,
2853
2854 #ifdef CONFIG_PM_SLEEP
2855         .suspend = iwl_trans_pcie_suspend,
2856         .resume = iwl_trans_pcie_resume,
2857 #endif /* CONFIG_PM_SLEEP */
2858
2859         .send_cmd = iwl_trans_pcie_send_hcmd,
2860
2861         .tx = iwl_trans_pcie_tx,
2862         .reclaim = iwl_trans_pcie_reclaim,
2863
2864         .txq_disable = iwl_trans_pcie_txq_disable,
2865         .txq_enable = iwl_trans_pcie_txq_enable,
2866
2867         .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table,
2868
2869         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2870
2871         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2872         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2873         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2874
2875         .write8 = iwl_trans_pcie_write8,
2876         .write32 = iwl_trans_pcie_write32,
2877         .read32 = iwl_trans_pcie_read32,
2878         .read_prph = iwl_trans_pcie_read_prph,
2879         .write_prph = iwl_trans_pcie_write_prph,
2880         .read_mem = iwl_trans_pcie_read_mem,
2881         .write_mem = iwl_trans_pcie_write_mem,
2882         .configure = iwl_trans_pcie_configure,
2883         .set_pmi = iwl_trans_pcie_set_pmi,
2884         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2885         .release_nic_access = iwl_trans_pcie_release_nic_access,
2886         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2887
2888         .ref = iwl_trans_pcie_ref,
2889         .unref = iwl_trans_pcie_unref,
2890
2891         .dump_data = iwl_trans_pcie_dump_data,
2892 };
2893
2894 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2895                                        const struct pci_device_id *ent,
2896                                        const struct iwl_cfg *cfg)
2897 {
2898         struct iwl_trans_pcie *trans_pcie;
2899         struct iwl_trans *trans;
2900         int ret, addr_size;
2901
2902         ret = pcim_enable_device(pdev);
2903         if (ret)
2904                 return ERR_PTR(ret);
2905
2906         trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2907                                 &pdev->dev, cfg, &trans_ops_pcie, 0);
2908         if (!trans)
2909                 return ERR_PTR(-ENOMEM);
2910
2911         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2912
2913         trans_pcie->trans = trans;
2914         spin_lock_init(&trans_pcie->irq_lock);
2915         spin_lock_init(&trans_pcie->reg_lock);
2916         mutex_init(&trans_pcie->mutex);
2917         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2918         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2919         if (!trans_pcie->tso_hdr_page) {
2920                 ret = -ENOMEM;
2921                 goto out_no_pci;
2922         }
2923
2924
2925         if (!cfg->base_params->pcie_l1_allowed) {
2926                 /*
2927                  * W/A - seems to solve weird behavior. We need to remove this
2928                  * if we don't want to stay in L1 all the time. This wastes a
2929                  * lot of power.
2930                  */
2931                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2932                                        PCIE_LINK_STATE_L1 |
2933                                        PCIE_LINK_STATE_CLKPM);
2934         }
2935
2936         if (cfg->mq_rx_supported)
2937                 addr_size = 64;
2938         else
2939                 addr_size = 36;
2940
2941         if (cfg->use_tfh) {
2942                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
2943                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
2944
2945         } else {
2946                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
2947                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2948         }
2949         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2950
2951         pci_set_master(pdev);
2952
2953         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2954         if (!ret)
2955                 ret = pci_set_consistent_dma_mask(pdev,
2956                                                   DMA_BIT_MASK(addr_size));
2957         if (ret) {
2958                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2959                 if (!ret)
2960                         ret = pci_set_consistent_dma_mask(pdev,
2961                                                           DMA_BIT_MASK(32));
2962                 /* both attempts failed: */
2963                 if (ret) {
2964                         dev_err(&pdev->dev, "No suitable DMA available\n");
2965                         goto out_no_pci;
2966                 }
2967         }
2968
2969         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
2970         if (ret) {
2971                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
2972                 goto out_no_pci;
2973         }
2974
2975         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
2976         if (!trans_pcie->hw_base) {
2977                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
2978                 ret = -ENODEV;
2979                 goto out_no_pci;
2980         }
2981
2982         /* We disable the RETRY_TIMEOUT register (0x41) to keep
2983          * PCI Tx retries from interfering with C3 CPU state */
2984         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2985
2986         trans->dev = &pdev->dev;
2987         trans_pcie->pci_dev = pdev;
2988         iwl_disable_interrupts(trans);
2989
2990         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
2991         /*
2992          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
2993          * changed, and now the revision step also includes bit 0-1 (no more
2994          * "dash" value). To keep hw_rev backwards compatible - we'll store it
2995          * in the old format.
2996          */
2997         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
2998                 unsigned long flags;
2999
3000                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3001                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3002
3003                 ret = iwl_pcie_prepare_card_hw(trans);
3004                 if (ret) {
3005                         IWL_WARN(trans, "Exit HW not ready\n");
3006                         goto out_no_pci;
3007                 }
3008
3009                 /*
3010                  * in-order to recognize C step driver should read chip version
3011                  * id located at the AUX bus MISC address space.
3012                  */
3013                 iwl_set_bit(trans, CSR_GP_CNTRL,
3014                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3015                 udelay(2);
3016
3017                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3018                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3019                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3020                                    25000);
3021                 if (ret < 0) {
3022                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3023                         goto out_no_pci;
3024                 }
3025
3026                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3027                         u32 hw_step;
3028
3029                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3030                         hw_step |= ENABLE_WFPM;
3031                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3032                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3033                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3034                         if (hw_step == 0x3)
3035                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3036                                                 (SILICON_C_STEP << 2);
3037                         iwl_trans_release_nic_access(trans, &flags);
3038                 }
3039         }
3040
3041         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3042
3043         iwl_pcie_set_interrupt_capa(pdev, trans);
3044         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3045         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3046                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3047
3048         /* Initialize the wait queue for commands */
3049         init_waitqueue_head(&trans_pcie->wait_command_queue);
3050
3051         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3052
3053         if (trans_pcie->msix_enabled) {
3054                 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
3055                         goto out_no_pci;
3056          } else {
3057                 ret = iwl_pcie_alloc_ict(trans);
3058                 if (ret)
3059                         goto out_no_pci;
3060
3061                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3062                                                 iwl_pcie_isr,
3063                                                 iwl_pcie_irq_handler,
3064                                                 IRQF_SHARED, DRV_NAME, trans);
3065                 if (ret) {
3066                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3067                         goto out_free_ict;
3068                 }
3069                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3070          }
3071
3072 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3073         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3074 #else
3075         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3076 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3077
3078         return trans;
3079
3080 out_free_ict:
3081         iwl_pcie_free_ict(trans);
3082 out_no_pci:
3083         free_percpu(trans_pcie->tso_hdr_page);
3084         iwl_trans_free(trans);
3085         return ERR_PTR(ret);
3086 }