drivers/net/wireless/intel/iwlwifi/pcie/trans.c

   1 /******************************************************************************
   2  *
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   6  * GPL LICENSE SUMMARY
   7  *
   8  * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
   9  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  10  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of version 2 of the GNU General Public License as
  14  * published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope that it will be useful, but
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  29  * Contact Information:
  30  *  Intel Linux Wireless <linuxwifi@intel.com>
  31  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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  34  *
  35  * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
  36  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
  37  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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  41  * modification, are permitted provided that the following conditions
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  45  *    notice, this list of conditions and the following disclaimer.
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  49  *    distribution.
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  51  *    contributors may be used to endorse or promote products derived
  52  *    from this software without specific prior written permission.
  53  *
  54  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  55  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  56  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  57  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  58  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  63  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  64  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  65  *
  66  *****************************************************************************/
  67 #include <linux/pci.h>
  68 #include <linux/pci-aspm.h>
  69 #include <linux/interrupt.h>
  70 #include <linux/debugfs.h>
  71 #include <linux/sched.h>
  72 #include <linux/bitops.h>
  73 #include <linux/gfp.h>
  74 #include <linux/vmalloc.h>
  75 #include <linux/pm_runtime.h>
  76
  77 #include "iwl-drv.h"
  78 #include "iwl-trans.h"
  79 #include "iwl-csr.h"
  80 #include "iwl-prph.h"
  81 #include "iwl-scd.h"
  82 #include "iwl-agn-hw.h"
  83 #include "fw/error-dump.h"
  84 #include "internal.h"
  85 #include "iwl-fh.h"
  86
  87 /* extended range in FW SRAM */
  88 #define IWL_FW_MEM_EXTENDED_START       0x40000
  89 #define IWL_FW_MEM_EXTENDED_END         0x57FFF
  90
  91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
  92 {
  93         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
  94
  95         if (!trans_pcie->fw_mon_page)
  96                 return;
  97
  98         dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
  99                        trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
 100         __free_pages(trans_pcie->fw_mon_page,
 101                      get_order(trans_pcie->fw_mon_size));
 102         trans_pcie->fw_mon_page = NULL;
 103         trans_pcie->fw_mon_phys = 0;
 104         trans_pcie->fw_mon_size = 0;
 105 }
 106
 107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
 108 {
 109         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 110         struct page *page = NULL;
 111         dma_addr_t phys;
 112         u32 size = 0;
 113         u8 power;
 114
 115         if (!max_power) {
 116                 /* default max_power is maximum */
 117                 max_power = 26;
 118         } else {
 119                 max_power += 11;
 120         }
 121
 122         if (WARN(max_power > 26,
 123                  "External buffer size for monitor is too big %d, check the FW TLV\n",
 124                  max_power))
 125                 return;
 126
 127         if (trans_pcie->fw_mon_page) {
 128                 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
 129                                            trans_pcie->fw_mon_size,
 130                                            DMA_FROM_DEVICE);
 131                 return;
 132         }
 133
 134         phys = 0;
 135         for (power = max_power; power >= 11; power--) {
 136                 int order;
 137
 138                 size = BIT(power);
 139                 order = get_order(size);
 140                 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
 141                                    order);
 142                 if (!page)
 143                         continue;
 144
 145                 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
 146                                     DMA_FROM_DEVICE);
 147                 if (dma_mapping_error(trans->dev, phys)) {
 148                         __free_pages(page, order);
 149                         page = NULL;
 150                         continue;
 151                 }
 152                 IWL_INFO(trans,
 153                          "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
 154                          size, order);
 155                 break;
 156         }
 157
 158         if (WARN_ON_ONCE(!page))
 159                 return;
 160
 161         if (power != max_power)
 162                 IWL_ERR(trans,
 163                         "Sorry - debug buffer is only %luK while you requested %luK\n",
 164                         (unsigned long)BIT(power - 10),
 165                         (unsigned long)BIT(max_power - 10));
 166
 167         trans_pcie->fw_mon_page = page;
 168         trans_pcie->fw_mon_phys = phys;
 169         trans_pcie->fw_mon_size = size;
 170 }
 171
 172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
 173 {
 174         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 175                     ((reg & 0x0000ffff) | (2 << 28)));
 176         return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
 177 }
 178
 179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
 180 {
 181         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
 182         iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
 183                     ((reg & 0x0000ffff) | (3 << 28)));
 184 }
 185
 186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 187 {
 188         if (trans->cfg->apmg_not_supported)
 189                 return;
 190
 191         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 192                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 193                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 194                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 195         else
 196                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 197                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 198                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 199 }
 200
 201 /* PCI registers */
 202 #define PCI_CFG_RETRY_TIMEOUT   0x041
 203
 204 void iwl_pcie_apm_config(struct iwl_trans *trans)
 205 {
 206         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 207         u16 lctl;
 208         u16 cap;
 209
 210         /*
 211          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 212          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 213          * If so (likely), disable L0S, so device moves directly L0->L1;
 214          *    costs negligible amount of power savings.
 215          * If not (unlikely), enable L0S, so there is at least some
 216          *    power savings, even without L1.
 217          */
 218         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 219         if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
 220                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221         else
 222                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 223         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 224
 225         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
 226         trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
 227         IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n",
 228                         (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
 229                         trans->ltr_enabled ? "En" : "Dis");
 230 }
 231
 232 /*
 233  * Start up NIC's basic functionality after it has been reset
 234  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 235  * NOTE:  This does not load uCode nor start the embedded processor
 236  */
 237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 238 {
 239         int ret;
 240
 241         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 242
 243         /*
 244          * Use "set_bit" below rather than "write", to preserve any hardware
 245          * bits already set by default after reset.
 246          */
 247
 248         /* Disable L0S exit timer (platform NMI Work/Around) */
 249         if (trans->cfg->device_family < IWL_DEVICE_FAMILY_8000)
 250                 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 251                             CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 252
 253         /*
 254          * Disable L0s without affecting L1;
 255          *  don't wait for ICH L0s (ICH bug W/A)
 256          */
 257         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 258                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 259
 260         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 261         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 262
 263         /*
 264          * Enable HAP INTA (interrupt from management bus) to
 265          * wake device's PCI Express link L1a -> L0s
 266          */
 267         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 268                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 269
 270         iwl_pcie_apm_config(trans);
 271
 272         /* Configure analog phase-lock-loop before activating to D0A */
 273         if (trans->cfg->base_params->pll_cfg)
 274                 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 275
 276         /*
 277          * Set "initialization complete" bit to move adapter from
 278          * D0U* --> D0A* (powered-up active) state.
 279          */
 280         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 281
 282         /*
 283          * Wait for clock stabilization; once stabilized, access to
 284          * device-internal resources is supported, e.g. iwl_write_prph()
 285          * and accesses to uCode SRAM.
 286          */
 287         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 288                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 289                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 290         if (ret < 0) {
 291                 IWL_ERR(trans, "Failed to init the card\n");
 292                 return ret;
 293         }
 294
 295         if (trans->cfg->host_interrupt_operation_mode) {
 296                 /*
 297                  * This is a bit of an abuse - This is needed for 7260 / 3160
 298                  * only check host_interrupt_operation_mode even if this is
 299                  * not related to host_interrupt_operation_mode.
 300                  *
 301                  * Enable the oscillator to count wake up time for L1 exit. This
 302                  * consumes slightly more power (100uA) - but allows to be sure
 303                  * that we wake up from L1 on time.
 304                  *
 305                  * This looks weird: read twice the same register, discard the
 306                  * value, set a bit, and yet again, read that same register
 307                  * just to discard the value. But that's the way the hardware
 308                  * seems to like it.
 309                  */
 310                 iwl_read_prph(trans, OSC_CLK);
 311                 iwl_read_prph(trans, OSC_CLK);
 312                 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
 313                 iwl_read_prph(trans, OSC_CLK);
 314                 iwl_read_prph(trans, OSC_CLK);
 315         }
 316
 317         /*
 318          * Enable DMA clock and wait for it to stabilize.
 319          *
 320          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
 321          * bits do not disable clocks.  This preserves any hardware
 322          * bits already set by default in "CLK_CTRL_REG" after reset.
 323          */
 324         if (!trans->cfg->apmg_not_supported) {
 325                 iwl_write_prph(trans, APMG_CLK_EN_REG,
 326                                APMG_CLK_VAL_DMA_CLK_RQT);
 327                 udelay(20);
 328
 329                 /* Disable L1-Active */
 330                 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 331                                   APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 332
 333                 /* Clear the interrupt in APMG if the NIC is in RFKILL */
 334                 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
 335                                APMG_RTC_INT_STT_RFKILL);
 336         }
 337
 338         set_bit(STATUS_DEVICE_ENABLED, &trans->status);
 339
 340         return 0;
 341 }
 342
 343 /*
 344  * Enable LP XTAL to avoid HW bug where device may consume much power if
 345  * FW is not loaded after device reset. LP XTAL is disabled by default
 346  * after device HW reset. Do it only if XTAL is fed by internal source.
 347  * Configure device's "persistence" mode to avoid resetting XTAL again when
 348  * SHRD_HW_RST occurs in S3.
 349  */
 350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
 351 {
 352         int ret;
 353         u32 apmg_gp1_reg;
 354         u32 apmg_xtal_cfg_reg;
 355         u32 dl_cfg_reg;
 356
 357         /* Force XTAL ON */
 358         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 359                                  CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 360
 361         iwl_pcie_sw_reset(trans);
 362
 363         /*
 364          * Set "initialization complete" bit to move adapter from
 365          * D0U* --> D0A* (powered-up active) state.
 366          */
 367         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 368
 369         /*
 370          * Wait for clock stabilization; once stabilized, access to
 371          * device-internal resources is possible.
 372          */
 373         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 374                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 375                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 376                            25000);
 377         if (WARN_ON(ret < 0)) {
 378                 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
 379                 /* Release XTAL ON request */
 380                 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 381                                            CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 382                 return;
 383         }
 384
 385         /*
 386          * Clear "disable persistence" to avoid LP XTAL resetting when
 387          * SHRD_HW_RST is applied in S3.
 388          */
 389         iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
 390                                     APMG_PCIDEV_STT_VAL_PERSIST_DIS);
 391
 392         /*
 393          * Force APMG XTAL to be active to prevent its disabling by HW
 394          * caused by APMG idle state.
 395          */
 396         apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
 397                                                     SHR_APMG_XTAL_CFG_REG);
 398         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 399                                  apmg_xtal_cfg_reg |
 400                                  SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 401
 402         iwl_pcie_sw_reset(trans);
 403
 404         /* Enable LP XTAL by indirect access through CSR */
 405         apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
 406         iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
 407                                  SHR_APMG_GP1_WF_XTAL_LP_EN |
 408                                  SHR_APMG_GP1_CHICKEN_BIT_SELECT);
 409
 410         /* Clear delay line clock power up */
 411         dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
 412         iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
 413                                  ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
 414
 415         /*
 416          * Enable persistence mode to avoid LP XTAL resetting when
 417          * SHRD_HW_RST is applied in S3.
 418          */
 419         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 420                     CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
 421
 422         /*
 423          * Clear "initialization complete" bit to move adapter from
 424          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 425          */
 426         iwl_clear_bit(trans, CSR_GP_CNTRL,
 427                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 428
 429         /* Activates XTAL resources monitor */
 430         __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
 431                                  CSR_MONITOR_XTAL_RESOURCES);
 432
 433         /* Release XTAL ON request */
 434         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 435                                    CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
 436         udelay(10);
 437
 438         /* Release APMG XTAL */
 439         iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
 440                                  apmg_xtal_cfg_reg &
 441                                  ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
 442 }
 443
 444 void iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 445 {
 446         int ret;
 447
 448         /* stop device's busmaster DMA activity */
 449         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 450
 451         ret = iwl_poll_bit(trans, CSR_RESET,
 452                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 453                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 454         if (ret < 0)
 455                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 456
 457         IWL_DEBUG_INFO(trans, "stop master\n");
 458 }
 459
 460 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
 461 {
 462         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 463
 464         if (op_mode_leave) {
 465                 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 466                         iwl_pcie_apm_init(trans);
 467
 468                 /* inform ME that we are leaving */
 469                 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
 470                         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 471                                           APMG_PCIDEV_STT_VAL_WAKE_ME);
 472                 else if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
 473                         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 474                                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 475                         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 476                                     CSR_HW_IF_CONFIG_REG_PREPARE |
 477                                     CSR_HW_IF_CONFIG_REG_ENABLE_PME);
 478                         mdelay(1);
 479                         iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 480                                       CSR_RESET_LINK_PWR_MGMT_DISABLED);
 481                 }
 482                 mdelay(5);
 483         }
 484
 485         clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
 486
 487         /* Stop device's DMA activity */
 488         iwl_pcie_apm_stop_master(trans);
 489
 490         if (trans->cfg->lp_xtal_workaround) {
 491                 iwl_pcie_apm_lp_xtal_enable(trans);
 492                 return;
 493         }
 494
 495         iwl_pcie_sw_reset(trans);
 496
 497         /*
 498          * Clear "initialization complete" bit to move adapter from
 499          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 500          */
 501         iwl_clear_bit(trans, CSR_GP_CNTRL,
 502                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 503 }
 504
 505 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 506 {
 507         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 508         int ret;
 509
 510         /* nic_init */
 511         spin_lock(&trans_pcie->irq_lock);
 512         ret = iwl_pcie_apm_init(trans);
 513         spin_unlock(&trans_pcie->irq_lock);
 514
 515         if (ret)
 516                 return ret;
 517
 518         iwl_pcie_set_pwr(trans, false);
 519
 520         iwl_op_mode_nic_config(trans->op_mode);
 521
 522         /* Allocate the RX queue, or reset if it is already allocated */
 523         iwl_pcie_rx_init(trans);
 524
 525         /* Allocate or reset and init all Tx and Command queues */
 526         if (iwl_pcie_tx_init(trans))
 527                 return -ENOMEM;
 528
 529         if (trans->cfg->base_params->shadow_reg_enable) {
 530                 /* enable shadow regs in HW */
 531                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 532                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 533         }
 534
 535         return 0;
 536 }
 537
 538 #define HW_READY_TIMEOUT (50)
 539
 540 /* Note: returns poll_bit return value, which is >= 0 if success */
 541 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 542 {
 543         int ret;
 544
 545         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 546                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 547
 548         /* See if we got it */
 549         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 550                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 551                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 552                            HW_READY_TIMEOUT);
 553
 554         if (ret >= 0)
 555                 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
 556
 557         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 558         return ret;
 559 }
 560
 561 /* Note: returns standard 0/-ERROR code */
 562 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 563 {
 564         int ret;
 565         int t = 0;
 566         int iter;
 567
 568         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 569
 570         ret = iwl_pcie_set_hw_ready(trans);
 571         /* If the card is ready, exit 0 */
 572         if (ret >= 0)
 573                 return 0;
 574
 575         iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
 576                     CSR_RESET_LINK_PWR_MGMT_DISABLED);
 577         usleep_range(1000, 2000);
 578
 579         for (iter = 0; iter < 10; iter++) {
 580                 /* If HW is not ready, prepare the conditions to check again */
 581                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 582                             CSR_HW_IF_CONFIG_REG_PREPARE);
 583
 584                 do {
 585                         ret = iwl_pcie_set_hw_ready(trans);
 586                         if (ret >= 0)
 587                                 return 0;
 588
 589                         usleep_range(200, 1000);
 590                         t += 200;
 591                 } while (t < 150000);
 592                 msleep(25);
 593         }
 594
 595         IWL_ERR(trans, "Couldn't prepare the card\n");
 596
 597         return ret;
 598 }
 599
 600 /*
 601  * ucode
 602  */
 603 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
 604                                             u32 dst_addr, dma_addr_t phy_addr,
 605                                             u32 byte_cnt)
 606 {
 607         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 608                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 609
 610         iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 611                     dst_addr);
 612
 613         iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 614                     phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 615
 616         iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 617                     (iwl_get_dma_hi_addr(phy_addr)
 618                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 619
 620         iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 621                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
 622                     BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
 623                     FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 624
 625         iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 626                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 627                     FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 628                     FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 629 }
 630
 631 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
 632                                         u32 dst_addr, dma_addr_t phy_addr,
 633                                         u32 byte_cnt)
 634 {
 635         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 636         unsigned long flags;
 637         int ret;
 638
 639         trans_pcie->ucode_write_complete = false;
 640
 641         if (!iwl_trans_grab_nic_access(trans, &flags))
 642                 return -EIO;
 643
 644         iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
 645                                         byte_cnt);
 646         iwl_trans_release_nic_access(trans, &flags);
 647
 648         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 649                                  trans_pcie->ucode_write_complete, 5 * HZ);
 650         if (!ret) {
 651                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 652                 return -ETIMEDOUT;
 653         }
 654
 655         return 0;
 656 }
 657
 658 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 659                             const struct fw_desc *section)
 660 {
 661         u8 *v_addr;
 662         dma_addr_t p_addr;
 663         u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
 664         int ret = 0;
 665
 666         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 667                      section_num);
 668
 669         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 670                                     GFP_KERNEL | __GFP_NOWARN);
 671         if (!v_addr) {
 672                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 673                 chunk_sz = PAGE_SIZE;
 674                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 675                                             &p_addr, GFP_KERNEL);
 676                 if (!v_addr)
 677                         return -ENOMEM;
 678         }
 679
 680         for (offset = 0; offset < section->len; offset += chunk_sz) {
 681                 u32 copy_size, dst_addr;
 682                 bool extended_addr = false;
 683
 684                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 685                 dst_addr = section->offset + offset;
 686
 687                 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
 688                     dst_addr <= IWL_FW_MEM_EXTENDED_END)
 689                         extended_addr = true;
 690
 691                 if (extended_addr)
 692                         iwl_set_bits_prph(trans, LMPM_CHICK,
 693                                           LMPM_CHICK_EXTENDED_ADDR_SPACE);
 694
 695                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 696                 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
 697                                                    copy_size);
 698
 699                 if (extended_addr)
 700                         iwl_clear_bits_prph(trans, LMPM_CHICK,
 701                                             LMPM_CHICK_EXTENDED_ADDR_SPACE);
 702
 703                 if (ret) {
 704                         IWL_ERR(trans,
 705                                 "Could not load the [%d] uCode section\n",
 706                                 section_num);
 707                         break;
 708                 }
 709         }
 710
 711         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 712         return ret;
 713 }
 714
 715 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
 716                                            const struct fw_img *image,
 717                                            int cpu,
 718                                            int *first_ucode_section)
 719 {
 720         int shift_param;
 721         int i, ret = 0, sec_num = 0x1;
 722         u32 val, last_read_idx = 0;
 723
 724         if (cpu == 1) {
 725                 shift_param = 0;
 726                 *first_ucode_section = 0;
 727         } else {
 728                 shift_param = 16;
 729                 (*first_ucode_section)++;
 730         }
 731
 732         for (i = *first_ucode_section; i < image->num_sec; i++) {
 733                 last_read_idx = i;
 734
 735                 /*
 736                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 737                  * CPU1 to CPU2.
 738                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 739                  * CPU2 non paged to CPU2 paging sec.
 740                  */
 741                 if (!image->sec[i].data ||
 742                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 743                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 744                         IWL_DEBUG_FW(trans,
 745                                      "Break since Data not valid or Empty section, sec = %d\n",
 746                                      i);
 747                         break;
 748                 }
 749
 750                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 751                 if (ret)
 752                         return ret;
 753
 754                 /* Notify ucode of loaded section number and status */
 755                 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
 756                 val = val | (sec_num << shift_param);
 757                 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
 758
 759                 sec_num = (sec_num << 1) | 0x1;
 760         }
 761
 762         *first_ucode_section = last_read_idx;
 763
 764         iwl_enable_interrupts(trans);
 765
 766         if (trans->cfg->use_tfh) {
 767                 if (cpu == 1)
 768                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 769                                        0xFFFF);
 770                 else
 771                         iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
 772                                        0xFFFFFFFF);
 773         } else {
 774                 if (cpu == 1)
 775                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 776                                            0xFFFF);
 777                 else
 778                         iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
 779                                            0xFFFFFFFF);
 780         }
 781
 782         return 0;
 783 }
 784
 785 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
 786                                       const struct fw_img *image,
 787                                       int cpu,
 788                                       int *first_ucode_section)
 789 {
 790         int i, ret = 0;
 791         u32 last_read_idx = 0;
 792
 793         if (cpu == 1)
 794                 *first_ucode_section = 0;
 795         else
 796                 (*first_ucode_section)++;
 797
 798         for (i = *first_ucode_section; i < image->num_sec; i++) {
 799                 last_read_idx = i;
 800
 801                 /*
 802                  * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
 803                  * CPU1 to CPU2.
 804                  * PAGING_SEPARATOR_SECTION delimiter - separate between
 805                  * CPU2 non paged to CPU2 paging sec.
 806                  */
 807                 if (!image->sec[i].data ||
 808                     image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
 809                     image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
 810                         IWL_DEBUG_FW(trans,
 811                                      "Break since Data not valid or Empty section, sec = %d\n",
 812                                      i);
 813                         break;
 814                 }
 815
 816                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 817                 if (ret)
 818                         return ret;
 819         }
 820
 821         *first_ucode_section = last_read_idx;
 822
 823         return 0;
 824 }
 825
 826 void iwl_pcie_apply_destination(struct iwl_trans *trans)
 827 {
 828         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 829         const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
 830         int i;
 831
 832         if (dest->version)
 833                 IWL_ERR(trans,
 834                         "DBG DEST version is %d - expect issues\n",
 835                         dest->version);
 836
 837         IWL_INFO(trans, "Applying debug destination %s\n",
 838                  get_fw_dbg_mode_string(dest->monitor_mode));
 839
 840         if (dest->monitor_mode == EXTERNAL_MODE)
 841                 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
 842         else
 843                 IWL_WARN(trans, "PCI should have external buffer debug\n");
 844
 845         for (i = 0; i < trans->dbg_dest_reg_num; i++) {
 846                 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
 847                 u32 val = le32_to_cpu(dest->reg_ops[i].val);
 848
 849                 switch (dest->reg_ops[i].op) {
 850                 case CSR_ASSIGN:
 851                         iwl_write32(trans, addr, val);
 852                         break;
 853                 case CSR_SETBIT:
 854                         iwl_set_bit(trans, addr, BIT(val));
 855                         break;
 856                 case CSR_CLEARBIT:
 857                         iwl_clear_bit(trans, addr, BIT(val));
 858                         break;
 859                 case PRPH_ASSIGN:
 860                         iwl_write_prph(trans, addr, val);
 861                         break;
 862                 case PRPH_SETBIT:
 863                         iwl_set_bits_prph(trans, addr, BIT(val));
 864                         break;
 865                 case PRPH_CLEARBIT:
 866                         iwl_clear_bits_prph(trans, addr, BIT(val));
 867                         break;
 868                 case PRPH_BLOCKBIT:
 869                         if (iwl_read_prph(trans, addr) & BIT(val)) {
 870                                 IWL_ERR(trans,
 871                                         "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
 872                                         val, addr);
 873                                 goto monitor;
 874                         }
 875                         break;
 876                 default:
 877                         IWL_ERR(trans, "FW debug - unknown OP %d\n",
 878                                 dest->reg_ops[i].op);
 879                         break;
 880                 }
 881         }
 882
 883 monitor:
 884         if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
 885                 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
 886                                trans_pcie->fw_mon_phys >> dest->base_shift);
 887                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
 888                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 889                                        (trans_pcie->fw_mon_phys +
 890                                         trans_pcie->fw_mon_size - 256) >>
 891                                                 dest->end_shift);
 892                 else
 893                         iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
 894                                        (trans_pcie->fw_mon_phys +
 895                                         trans_pcie->fw_mon_size) >>
 896                                                 dest->end_shift);
 897         }
 898 }
 899
 900 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 901                                 const struct fw_img *image)
 902 {
 903         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 904         int ret = 0;
 905         int first_ucode_section;
 906
 907         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 908                      image->is_dual_cpus ? "Dual" : "Single");
 909
 910         /* load to FW the binary non secured sections of CPU1 */
 911         ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
 912         if (ret)
 913                 return ret;
 914
 915         if (image->is_dual_cpus) {
 916                 /* set CPU2 header address */
 917                 iwl_write_prph(trans,
 918                                LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
 919                                LMPM_SECURE_CPU2_HDR_MEM_SPACE);
 920
 921                 /* load to FW the binary sections of CPU2 */
 922                 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
 923                                                  &first_ucode_section);
 924                 if (ret)
 925                         return ret;
 926         }
 927
 928         /* supported for 7000 only for the moment */
 929         if (iwlwifi_mod_params.fw_monitor &&
 930             trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
 931                 iwl_pcie_alloc_fw_monitor(trans, 0);
 932
 933                 if (trans_pcie->fw_mon_size) {
 934                         iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
 935                                        trans_pcie->fw_mon_phys >> 4);
 936                         iwl_write_prph(trans, MON_BUFF_END_ADDR,
 937                                        (trans_pcie->fw_mon_phys +
 938                                         trans_pcie->fw_mon_size) >> 4);
 939                 }
 940         } else if (trans->dbg_dest_tlv) {
 941                 iwl_pcie_apply_destination(trans);
 942         }
 943
 944         iwl_enable_interrupts(trans);
 945
 946         /* release CPU reset */
 947         iwl_write32(trans, CSR_RESET, 0);
 948
 949         return 0;
 950 }
 951
 952 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
 953                                           const struct fw_img *image)
 954 {
 955         int ret = 0;
 956         int first_ucode_section;
 957
 958         IWL_DEBUG_FW(trans, "working with %s CPU\n",
 959                      image->is_dual_cpus ? "Dual" : "Single");
 960
 961         if (trans->dbg_dest_tlv)
 962                 iwl_pcie_apply_destination(trans);
 963
 964         IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n",
 965                         iwl_read_prph(trans, WFPM_GP2));
 966
 967         /*
 968          * Set default value. On resume reading the values that were
 969          * zeored can provide debug data on the resume flow.
 970          * This is for debugging only and has no functional impact.
 971          */
 972         iwl_write_prph(trans, WFPM_GP2, 0x01010101);
 973
 974         /* configure the ucode to be ready to get the secured image */
 975         /* release CPU reset */
 976         iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
 977
 978         /* load to FW the binary Secured sections of CPU1 */
 979         ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
 980                                               &first_ucode_section);
 981         if (ret)
 982                 return ret;
 983
 984         /* load to FW the binary sections of CPU2 */
 985         return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
 986                                                &first_ucode_section);
 987 }
 988
 989 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans)
 990 {
 991         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
 992         bool hw_rfkill = iwl_is_rfkill_set(trans);
 993         bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
 994         bool report;
 995
 996         if (hw_rfkill) {
 997                 set_bit(STATUS_RFKILL_HW, &trans->status);
 998                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
 999         } else {
1000                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1001                 if (trans_pcie->opmode_down)
1002                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1003         }
1004
1005         report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1006
1007         if (prev != report)
1008                 iwl_trans_pcie_rf_kill(trans, report);
1009
1010         return hw_rfkill;
1011 }
1012
1013 struct iwl_causes_list {
1014         u32 cause_num;
1015         u32 mask_reg;
1016         u8 addr;
1017 };
1018
1019 static struct iwl_causes_list causes_list[] = {
1020         {MSIX_FH_INT_CAUSES_D2S_CH0_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0},
1021         {MSIX_FH_INT_CAUSES_D2S_CH1_NUM,        CSR_MSIX_FH_INT_MASK_AD, 0x1},
1022         {MSIX_FH_INT_CAUSES_S2D,                CSR_MSIX_FH_INT_MASK_AD, 0x3},
1023         {MSIX_FH_INT_CAUSES_FH_ERR,             CSR_MSIX_FH_INT_MASK_AD, 0x5},
1024         {MSIX_HW_INT_CAUSES_REG_ALIVE,          CSR_MSIX_HW_INT_MASK_AD, 0x10},
1025         {MSIX_HW_INT_CAUSES_REG_WAKEUP,         CSR_MSIX_HW_INT_MASK_AD, 0x11},
1026         {MSIX_HW_INT_CAUSES_REG_CT_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x16},
1027         {MSIX_HW_INT_CAUSES_REG_RF_KILL,        CSR_MSIX_HW_INT_MASK_AD, 0x17},
1028         {MSIX_HW_INT_CAUSES_REG_PERIODIC,       CSR_MSIX_HW_INT_MASK_AD, 0x18},
1029         {MSIX_HW_INT_CAUSES_REG_SW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x29},
1030         {MSIX_HW_INT_CAUSES_REG_SCD,            CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1031         {MSIX_HW_INT_CAUSES_REG_FH_TX,          CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1032         {MSIX_HW_INT_CAUSES_REG_HW_ERR,         CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1033         {MSIX_HW_INT_CAUSES_REG_HAP,            CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1034 };
1035
1036 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1037 {
1038         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1039         int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1040         int i;
1041
1042         /*
1043          * Access all non RX causes and map them to the default irq.
1044          * In case we are missing at least one interrupt vector,
1045          * the first interrupt vector will serve non-RX and FBQ causes.
1046          */
1047         for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1048                 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1049                 iwl_clear_bit(trans, causes_list[i].mask_reg,
1050                               causes_list[i].cause_num);
1051         }
1052 }
1053
1054 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1055 {
1056         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1057         u32 offset =
1058                 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1059         u32 val, idx;
1060
1061         /*
1062          * The first RX queue - fallback queue, which is designated for
1063          * management frame, command responses etc, is always mapped to the
1064          * first interrupt vector. The other RX queues are mapped to
1065          * the other (N - 2) interrupt vectors.
1066          */
1067         val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1068         for (idx = 1; idx < trans->num_rx_queues; idx++) {
1069                 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1070                            MSIX_FH_INT_CAUSES_Q(idx - offset));
1071                 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1072         }
1073         iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1074
1075         val = MSIX_FH_INT_CAUSES_Q(0);
1076         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1077                 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1078         iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1079
1080         if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1081                 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1082 }
1083
1084 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie)
1085 {
1086         struct iwl_trans *trans = trans_pcie->trans;
1087
1088         if (!trans_pcie->msix_enabled) {
1089                 if (trans->cfg->mq_rx_supported &&
1090                     test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1091                         iwl_write_prph(trans, UREG_CHICK,
1092                                        UREG_CHICK_MSI_ENABLE);
1093                 return;
1094         }
1095         /*
1096          * The IVAR table needs to be configured again after reset,
1097          * but if the device is disabled, we can't write to
1098          * prph.
1099          */
1100         if (test_bit(STATUS_DEVICE_ENABLED, &trans->status))
1101                 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1102
1103         /*
1104          * Each cause from the causes list above and the RX causes is
1105          * represented as a byte in the IVAR table. The first nibble
1106          * represents the bound interrupt vector of the cause, the second
1107          * represents no auto clear for this cause. This will be set if its
1108          * interrupt vector is bound to serve other causes.
1109          */
1110         iwl_pcie_map_rx_causes(trans);
1111
1112         iwl_pcie_map_non_rx_causes(trans);
1113 }
1114
1115 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1116 {
1117         struct iwl_trans *trans = trans_pcie->trans;
1118
1119         iwl_pcie_conf_msix_hw(trans_pcie);
1120
1121         if (!trans_pcie->msix_enabled)
1122                 return;
1123
1124         trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1125         trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1126         trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1127         trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1128 }
1129
1130 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1131 {
1132         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1133
1134         lockdep_assert_held(&trans_pcie->mutex);
1135
1136         if (trans_pcie->is_down)
1137                 return;
1138
1139         trans_pcie->is_down = true;
1140
1141         /* Stop dbgc before stopping device */
1142         if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1143                 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100);
1144         } else {
1145                 iwl_write_prph(trans, DBGC_IN_SAMPLE, 0);
1146                 udelay(100);
1147                 iwl_write_prph(trans, DBGC_OUT_CTRL, 0);
1148         }
1149
1150         /* tell the device to stop sending interrupts */
1151         iwl_disable_interrupts(trans);
1152
1153         /* device going down, Stop using ICT table */
1154         iwl_pcie_disable_ict(trans);
1155
1156         /*
1157          * If a HW restart happens during firmware loading,
1158          * then the firmware loading might call this function
1159          * and later it might be called again due to the
1160          * restart. So don't process again if the device is
1161          * already dead.
1162          */
1163         if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1164                 IWL_DEBUG_INFO(trans,
1165                                "DEVICE_ENABLED bit was set and is now cleared\n");
1166                 iwl_pcie_tx_stop(trans);
1167                 iwl_pcie_rx_stop(trans);
1168
1169                 /* Power-down device's busmaster DMA clocks */
1170                 if (!trans->cfg->apmg_not_supported) {
1171                         iwl_write_prph(trans, APMG_CLK_DIS_REG,
1172                                        APMG_CLK_VAL_DMA_CLK_RQT);
1173                         udelay(5);
1174                 }
1175         }
1176
1177         /* Make sure (redundant) we've released our request to stay awake */
1178         iwl_clear_bit(trans, CSR_GP_CNTRL,
1179                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1180
1181         /* Stop the device, and put it in low power state */
1182         iwl_pcie_apm_stop(trans, false);
1183
1184         iwl_pcie_sw_reset(trans);
1185
1186         /*
1187          * Upon stop, the IVAR table gets erased, so msi-x won't
1188          * work. This causes a bug in RF-KILL flows, since the interrupt
1189          * that enables radio won't fire on the correct irq, and the
1190          * driver won't be able to handle the interrupt.
1191          * Configure the IVAR table again after reset.
1192          */
1193         iwl_pcie_conf_msix_hw(trans_pcie);
1194
1195         /*
1196          * Upon stop, the APM issues an interrupt if HW RF kill is set.
1197          * This is a bug in certain verions of the hardware.
1198          * Certain devices also keep sending HW RF kill interrupt all
1199          * the time, unless the interrupt is ACKed even if the interrupt
1200          * should be masked. Re-ACK all the interrupts here.
1201          */
1202         iwl_disable_interrupts(trans);
1203
1204         /* clear all status bits */
1205         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1206         clear_bit(STATUS_INT_ENABLED, &trans->status);
1207         clear_bit(STATUS_TPOWER_PMI, &trans->status);
1208
1209         /*
1210          * Even if we stop the HW, we still want the RF kill
1211          * interrupt
1212          */
1213         iwl_enable_rfkill_int(trans);
1214
1215         /* re-take ownership to prevent other users from stealing the device */
1216         iwl_pcie_prepare_card_hw(trans);
1217 }
1218
1219 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1220 {
1221         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1222
1223         if (trans_pcie->msix_enabled) {
1224                 int i;
1225
1226                 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1227                         synchronize_irq(trans_pcie->msix_entries[i].vector);
1228         } else {
1229                 synchronize_irq(trans_pcie->pci_dev->irq);
1230         }
1231 }
1232
1233 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1234                                    const struct fw_img *fw, bool run_in_rfkill)
1235 {
1236         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1237         bool hw_rfkill;
1238         int ret;
1239
1240         /* This may fail if AMT took ownership of the device */
1241         if (iwl_pcie_prepare_card_hw(trans)) {
1242                 IWL_WARN(trans, "Exit HW not ready\n");
1243                 ret = -EIO;
1244                 goto out;
1245         }
1246
1247         iwl_enable_rfkill_int(trans);
1248
1249         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1250
1251         /*
1252          * We enabled the RF-Kill interrupt and the handler may very
1253          * well be running. Disable the interrupts to make sure no other
1254          * interrupt can be fired.
1255          */
1256         iwl_disable_interrupts(trans);
1257
1258         /* Make sure it finished running */
1259         iwl_pcie_synchronize_irqs(trans);
1260
1261         mutex_lock(&trans_pcie->mutex);
1262
1263         /* If platform's RF_KILL switch is NOT set to KILL */
1264         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1265         if (hw_rfkill && !run_in_rfkill) {
1266                 ret = -ERFKILL;
1267                 goto out;
1268         }
1269
1270         /* Someone called stop_device, don't try to start_fw */
1271         if (trans_pcie->is_down) {
1272                 IWL_WARN(trans,
1273                          "Can't start_fw since the HW hasn't been started\n");
1274                 ret = -EIO;
1275                 goto out;
1276         }
1277
1278         /* make sure rfkill handshake bits are cleared */
1279         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1280         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1281                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1282
1283         /* clear (again), then enable host interrupts */
1284         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1285
1286         ret = iwl_pcie_nic_init(trans);
1287         if (ret) {
1288                 IWL_ERR(trans, "Unable to init nic\n");
1289                 goto out;
1290         }
1291
1292         /*
1293          * Now, we load the firmware and don't want to be interrupted, even
1294          * by the RF-Kill interrupt (hence mask all the interrupt besides the
1295          * FH_TX interrupt which is needed to load the firmware). If the
1296          * RF-Kill switch is toggled, we will find out after having loaded
1297          * the firmware and return the proper value to the caller.
1298          */
1299         iwl_enable_fw_load_int(trans);
1300
1301         /* really make sure rfkill handshake bits are cleared */
1302         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1303         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1304
1305         /* Load the given image to the HW */
1306         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1307                 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1308         else
1309                 ret = iwl_pcie_load_given_ucode(trans, fw);
1310
1311         /* re-check RF-Kill state since we may have missed the interrupt */
1312         hw_rfkill = iwl_pcie_check_hw_rf_kill(trans);
1313         if (hw_rfkill && !run_in_rfkill)
1314                 ret = -ERFKILL;
1315
1316 out:
1317         mutex_unlock(&trans_pcie->mutex);
1318         return ret;
1319 }
1320
1321 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1322 {
1323         iwl_pcie_reset_ict(trans);
1324         iwl_pcie_tx_start(trans, scd_addr);
1325 }
1326
1327 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans,
1328                                        bool was_in_rfkill)
1329 {
1330         bool hw_rfkill;
1331
1332         /*
1333          * Check again since the RF kill state may have changed while
1334          * all the interrupts were disabled, in this case we couldn't
1335          * receive the RF kill interrupt and update the state in the
1336          * op_mode.
1337          * Don't call the op_mode if the rkfill state hasn't changed.
1338          * This allows the op_mode to call stop_device from the rfkill
1339          * notification without endless recursion. Under very rare
1340          * circumstances, we might have a small recursion if the rfkill
1341          * state changed exactly now while we were called from stop_device.
1342          * This is very unlikely but can happen and is supported.
1343          */
1344         hw_rfkill = iwl_is_rfkill_set(trans);
1345         if (hw_rfkill) {
1346                 set_bit(STATUS_RFKILL_HW, &trans->status);
1347                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1348         } else {
1349                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1350                 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1351         }
1352         if (hw_rfkill != was_in_rfkill)
1353                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1354 }
1355
1356 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1357 {
1358         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1359         bool was_in_rfkill;
1360
1361         mutex_lock(&trans_pcie->mutex);
1362         trans_pcie->opmode_down = true;
1363         was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1364         _iwl_trans_pcie_stop_device(trans, low_power);
1365         iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill);
1366         mutex_unlock(&trans_pcie->mutex);
1367 }
1368
1369 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1370 {
1371         struct iwl_trans_pcie __maybe_unused *trans_pcie =
1372                 IWL_TRANS_GET_PCIE_TRANS(trans);
1373
1374         lockdep_assert_held(&trans_pcie->mutex);
1375
1376         IWL_WARN(trans, "reporting RF_KILL (radio %s)\n",
1377                  state ? "disabled" : "enabled");
1378         if (iwl_op_mode_hw_rf_kill(trans->op_mode, state)) {
1379                 if (trans->cfg->gen2)
1380                         _iwl_trans_pcie_gen2_stop_device(trans, true);
1381                 else
1382                         _iwl_trans_pcie_stop_device(trans, true);
1383         }
1384 }
1385
1386 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1387                                       bool reset)
1388 {
1389         if (!reset) {
1390                 /* Enable persistence mode to avoid reset */
1391                 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1392                             CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1393         }
1394
1395         iwl_disable_interrupts(trans);
1396
1397         /*
1398          * in testing mode, the host stays awake and the
1399          * hardware won't be reset (not even partially)
1400          */
1401         if (test)
1402                 return;
1403
1404         iwl_pcie_disable_ict(trans);
1405
1406         iwl_pcie_synchronize_irqs(trans);
1407
1408         iwl_clear_bit(trans, CSR_GP_CNTRL,
1409                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1410         iwl_clear_bit(trans, CSR_GP_CNTRL,
1411                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1412
1413         iwl_pcie_enable_rx_wake(trans, false);
1414
1415         if (reset) {
1416                 /*
1417                  * reset TX queues -- some of their registers reset during S3
1418                  * so if we don't reset everything here the D3 image would try
1419                  * to execute some invalid memory upon resume
1420                  */
1421                 iwl_trans_pcie_tx_reset(trans);
1422         }
1423
1424         iwl_pcie_set_pwr(trans, true);
1425 }
1426
1427 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1428                                     enum iwl_d3_status *status,
1429                                     bool test,  bool reset)
1430 {
1431         struct iwl_trans_pcie *trans_pcie =  IWL_TRANS_GET_PCIE_TRANS(trans);
1432         u32 val;
1433         int ret;
1434
1435         if (test) {
1436                 iwl_enable_interrupts(trans);
1437                 *status = IWL_D3_STATUS_ALIVE;
1438                 return 0;
1439         }
1440
1441         iwl_pcie_enable_rx_wake(trans, true);
1442
1443         /*
1444          * Reconfigure IVAR table in case of MSIX or reset ict table in
1445          * MSI mode since HW reset erased it.
1446          * Also enables interrupts - none will happen as
1447          * the device doesn't know we're waking it up, only when
1448          * the opmode actually tells it after this call.
1449          */
1450         iwl_pcie_conf_msix_hw(trans_pcie);
1451         if (!trans_pcie->msix_enabled)
1452                 iwl_pcie_reset_ict(trans);
1453         iwl_enable_interrupts(trans);
1454
1455         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1456         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1457
1458         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1459                 udelay(2);
1460
1461         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1462                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1463                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1464                            25000);
1465         if (ret < 0) {
1466                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1467                 return ret;
1468         }
1469
1470         iwl_pcie_set_pwr(trans, false);
1471
1472         if (!reset) {
1473                 iwl_clear_bit(trans, CSR_GP_CNTRL,
1474                               CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1475         } else {
1476                 iwl_trans_pcie_tx_reset(trans);
1477
1478                 ret = iwl_pcie_rx_init(trans);
1479                 if (ret) {
1480                         IWL_ERR(trans,
1481                                 "Failed to resume the device (RX reset)\n");
1482                         return ret;
1483                 }
1484         }
1485
1486         IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n",
1487                         iwl_read_prph(trans, WFPM_GP2));
1488
1489         val = iwl_read32(trans, CSR_RESET);
1490         if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1491                 *status = IWL_D3_STATUS_RESET;
1492         else
1493                 *status = IWL_D3_STATUS_ALIVE;
1494
1495         return 0;
1496 }
1497
1498 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1499                                         struct iwl_trans *trans)
1500 {
1501         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1502         int max_irqs, num_irqs, i, ret;
1503         u16 pci_cmd;
1504
1505         if (!trans->cfg->mq_rx_supported)
1506                 goto enable_msi;
1507
1508         max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1509         for (i = 0; i < max_irqs; i++)
1510                 trans_pcie->msix_entries[i].entry = i;
1511
1512         num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1513                                          MSIX_MIN_INTERRUPT_VECTORS,
1514                                          max_irqs);
1515         if (num_irqs < 0) {
1516                 IWL_DEBUG_INFO(trans,
1517                                "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1518                                num_irqs);
1519                 goto enable_msi;
1520         }
1521         trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1522
1523         IWL_DEBUG_INFO(trans,
1524                        "MSI-X enabled. %d interrupt vectors were allocated\n",
1525                        num_irqs);
1526
1527         /*
1528          * In case the OS provides fewer interrupts than requested, different
1529          * causes will share the same interrupt vector as follows:
1530          * One interrupt less: non rx causes shared with FBQ.
1531          * Two interrupts less: non rx causes shared with FBQ and RSS.
1532          * More than two interrupts: we will use fewer RSS queues.
1533          */
1534         if (num_irqs <= max_irqs - 2) {
1535                 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1536                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1537                         IWL_SHARED_IRQ_FIRST_RSS;
1538         } else if (num_irqs == max_irqs - 1) {
1539                 trans_pcie->trans->num_rx_queues = num_irqs;
1540                 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1541         } else {
1542                 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1543         }
1544         WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1545
1546         trans_pcie->alloc_vecs = num_irqs;
1547         trans_pcie->msix_enabled = true;
1548         return;
1549
1550 enable_msi:
1551         ret = pci_enable_msi(pdev);
1552         if (ret) {
1553                 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1554                 /* enable rfkill interrupt: hw bug w/a */
1555                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1556                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1557                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1558                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1559                 }
1560         }
1561 }
1562
1563 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1564 {
1565         int iter_rx_q, i, ret, cpu, offset;
1566         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1567
1568         i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1569         iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1570         offset = 1 + i;
1571         for (; i < iter_rx_q ; i++) {
1572                 /*
1573                  * Get the cpu prior to the place to search
1574                  * (i.e. return will be > i - 1).
1575                  */
1576                 cpu = cpumask_next(i - offset, cpu_online_mask);
1577                 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1578                 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1579                                             &trans_pcie->affinity_mask[i]);
1580                 if (ret)
1581                         IWL_ERR(trans_pcie->trans,
1582                                 "Failed to set affinity mask for IRQ %d\n",
1583                                 i);
1584         }
1585 }
1586
1587 static const char *queue_name(struct device *dev,
1588                               struct iwl_trans_pcie *trans_p, int i)
1589 {
1590         if (trans_p->shared_vec_mask) {
1591                 int vec = trans_p->shared_vec_mask &
1592                           IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1593
1594                 if (i == 0)
1595                         return DRV_NAME ": shared IRQ";
1596
1597                 return devm_kasprintf(dev, GFP_KERNEL,
1598                                       DRV_NAME ": queue %d", i + vec);
1599         }
1600         if (i == 0)
1601                 return DRV_NAME ": default queue";
1602
1603         if (i == trans_p->alloc_vecs - 1)
1604                 return DRV_NAME ": exception";
1605
1606         return devm_kasprintf(dev, GFP_KERNEL,
1607                               DRV_NAME  ": queue %d", i);
1608 }
1609
1610 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1611                                       struct iwl_trans_pcie *trans_pcie)
1612 {
1613         int i;
1614
1615         for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1616                 int ret;
1617                 struct msix_entry *msix_entry;
1618                 const char *qname = queue_name(&pdev->dev, trans_pcie, i);
1619
1620                 if (!qname)
1621                         return -ENOMEM;
1622
1623                 msix_entry = &trans_pcie->msix_entries[i];
1624                 ret = devm_request_threaded_irq(&pdev->dev,
1625                                                 msix_entry->vector,
1626                                                 iwl_pcie_msix_isr,
1627                                                 (i == trans_pcie->def_irq) ?
1628                                                 iwl_pcie_irq_msix_handler :
1629                                                 iwl_pcie_irq_rx_msix_handler,
1630                                                 IRQF_SHARED,
1631                                                 qname,
1632                                                 msix_entry);
1633                 if (ret) {
1634                         IWL_ERR(trans_pcie->trans,
1635                                 "Error allocating IRQ %d\n", i);
1636
1637                         return ret;
1638                 }
1639         }
1640         iwl_pcie_irq_set_affinity(trans_pcie->trans);
1641
1642         return 0;
1643 }
1644
1645 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1646 {
1647         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1648         int err;
1649
1650         lockdep_assert_held(&trans_pcie->mutex);
1651
1652         err = iwl_pcie_prepare_card_hw(trans);
1653         if (err) {
1654                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1655                 return err;
1656         }
1657
1658         iwl_pcie_sw_reset(trans);
1659
1660         err = iwl_pcie_apm_init(trans);
1661         if (err)
1662                 return err;
1663
1664         iwl_pcie_init_msix(trans_pcie);
1665
1666         /* From now on, the op_mode will be kept updated about RF kill state */
1667         iwl_enable_rfkill_int(trans);
1668
1669         trans_pcie->opmode_down = false;
1670
1671         /* Set is_down to false here so that...*/
1672         trans_pcie->is_down = false;
1673
1674         /* ...rfkill can call stop_device and set it false if needed */
1675         iwl_pcie_check_hw_rf_kill(trans);
1676
1677         /* Make sure we sync here, because we'll need full access later */
1678         if (low_power)
1679                 pm_runtime_resume(trans->dev);
1680
1681         return 0;
1682 }
1683
1684 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1685 {
1686         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1687         int ret;
1688
1689         mutex_lock(&trans_pcie->mutex);
1690         ret = _iwl_trans_pcie_start_hw(trans, low_power);
1691         mutex_unlock(&trans_pcie->mutex);
1692
1693         return ret;
1694 }
1695
1696 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1697 {
1698         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1699
1700         mutex_lock(&trans_pcie->mutex);
1701
1702         /* disable interrupts - don't enable HW RF kill interrupt */
1703         iwl_disable_interrupts(trans);
1704
1705         iwl_pcie_apm_stop(trans, true);
1706
1707         iwl_disable_interrupts(trans);
1708
1709         iwl_pcie_disable_ict(trans);
1710
1711         mutex_unlock(&trans_pcie->mutex);
1712
1713         iwl_pcie_synchronize_irqs(trans);
1714 }
1715
1716 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1717 {
1718         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1719 }
1720
1721 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1722 {
1723         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1724 }
1725
1726 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1727 {
1728         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1729 }
1730
1731 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1732 {
1733         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1734                                ((reg & 0x000FFFFF) | (3 << 24)));
1735         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1736 }
1737
1738 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1739                                       u32 val)
1740 {
1741         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1742                                ((addr & 0x000FFFFF) | (3 << 24)));
1743         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1744 }
1745
1746 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1747                                      const struct iwl_trans_config *trans_cfg)
1748 {
1749         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1750
1751         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1752         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1753         trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1754         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1755                 trans_pcie->n_no_reclaim_cmds = 0;
1756         else
1757                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1758         if (trans_pcie->n_no_reclaim_cmds)
1759                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1760                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1761
1762         trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1763         trans_pcie->rx_page_order =
1764                 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1765
1766         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1767         trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1768         trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1769
1770         trans_pcie->page_offs = trans_cfg->cb_data_offs;
1771         trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1772
1773         trans->command_groups = trans_cfg->command_groups;
1774         trans->command_groups_size = trans_cfg->command_groups_size;
1775
1776         /* Initialize NAPI here - it should be before registering to mac80211
1777          * in the opmode but after the HW struct is allocated.
1778          * As this function may be called again in some corner cases don't
1779          * do anything if NAPI was already initialized.
1780          */
1781         if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1782                 init_dummy_netdev(&trans_pcie->napi_dev);
1783 }
1784
1785 void iwl_trans_pcie_free(struct iwl_trans *trans)
1786 {
1787         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1788         int i;
1789
1790         iwl_pcie_synchronize_irqs(trans);
1791
1792         if (trans->cfg->gen2)
1793                 iwl_pcie_gen2_tx_free(trans);
1794         else
1795                 iwl_pcie_tx_free(trans);
1796         iwl_pcie_rx_free(trans);
1797
1798         if (trans_pcie->rba.alloc_wq) {
1799                 destroy_workqueue(trans_pcie->rba.alloc_wq);
1800                 trans_pcie->rba.alloc_wq = NULL;
1801         }
1802
1803         if (trans_pcie->msix_enabled) {
1804                 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1805                         irq_set_affinity_hint(
1806                                 trans_pcie->msix_entries[i].vector,
1807                                 NULL);
1808                 }
1809
1810                 trans_pcie->msix_enabled = false;
1811         } else {
1812                 iwl_pcie_free_ict(trans);
1813         }
1814
1815         iwl_pcie_free_fw_monitor(trans);
1816
1817         for_each_possible_cpu(i) {
1818                 struct iwl_tso_hdr_page *p =
1819                         per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1820
1821                 if (p->page)
1822                         __free_page(p->page);
1823         }
1824
1825         free_percpu(trans_pcie->tso_hdr_page);
1826         mutex_destroy(&trans_pcie->mutex);
1827         iwl_trans_free(trans);
1828 }
1829
1830 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1831 {
1832         if (state)
1833                 set_bit(STATUS_TPOWER_PMI, &trans->status);
1834         else
1835                 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1836 }
1837
1838 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1839                                            unsigned long *flags)
1840 {
1841         int ret;
1842         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1843
1844         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1845
1846         if (trans_pcie->cmd_hold_nic_awake)
1847                 goto out;
1848
1849         /* this bit wakes up the NIC */
1850         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1851                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1852         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000)
1853                 udelay(2);
1854
1855         /*
1856          * These bits say the device is running, and should keep running for
1857          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1858          * but they do not indicate that embedded SRAM is restored yet;
1859          * HW with volatile SRAM must save/restore contents to/from
1860          * host DRAM when sleeping/waking for power-saving.
1861          * Each direction takes approximately 1/4 millisecond; with this
1862          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1863          * series of register accesses are expected (e.g. reading Event Log),
1864          * to keep device from sleeping.
1865          *
1866          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1867          * SRAM is okay/restored.  We don't check that here because this call
1868          * is just for hardware register access; but GP1 MAC_SLEEP
1869          * check is a good idea before accessing the SRAM of HW with
1870          * volatile SRAM (e.g. reading Event Log).
1871          *
1872          * 5000 series and later (including 1000 series) have non-volatile SRAM,
1873          * and do not save/restore SRAM when power cycling.
1874          */
1875         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1876                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1877                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1878                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1879         if (unlikely(ret < 0)) {
1880                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1881                 WARN_ONCE(1,
1882                           "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1883                           iwl_read32(trans, CSR_GP_CNTRL));
1884                 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1885                 return false;
1886         }
1887
1888 out:
1889         /*
1890          * Fool sparse by faking we release the lock - sparse will
1891          * track nic_access anyway.
1892          */
1893         __release(&trans_pcie->reg_lock);
1894         return true;
1895 }
1896
1897 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1898                                               unsigned long *flags)
1899 {
1900         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1901
1902         lockdep_assert_held(&trans_pcie->reg_lock);
1903
1904         /*
1905          * Fool sparse by faking we acquiring the lock - sparse will
1906          * track nic_access anyway.
1907          */
1908         __acquire(&trans_pcie->reg_lock);
1909
1910         if (trans_pcie->cmd_hold_nic_awake)
1911                 goto out;
1912
1913         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1914                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1915         /*
1916          * Above we read the CSR_GP_CNTRL register, which will flush
1917          * any previous writes, but we need the write that clears the
1918          * MAC_ACCESS_REQ bit to be performed before any other writes
1919          * scheduled on different CPUs (after we drop reg_lock).
1920          */
1921         mmiowb();
1922 out:
1923         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1924 }
1925
1926 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1927                                    void *buf, int dwords)
1928 {
1929         unsigned long flags;
1930         int offs = 0;
1931         u32 *vals = buf;
1932
1933         while (offs < dwords) {
1934                 /* limit the time we spin here under lock to 1/2s */
1935                 unsigned long end = jiffies + HZ / 2;
1936                 bool resched = false;
1937
1938                 if (iwl_trans_grab_nic_access(trans, &flags)) {
1939                         iwl_write32(trans, HBUS_TARG_MEM_RADDR,
1940                                     addr + 4 * offs);
1941
1942                         while (offs < dwords) {
1943                                 vals[offs] = iwl_read32(trans,
1944                                                         HBUS_TARG_MEM_RDAT);
1945                                 offs++;
1946
1947                                 if (time_after(jiffies, end)) {
1948                                         resched = true;
1949                                         break;
1950                                 }
1951                         }
1952                         iwl_trans_release_nic_access(trans, &flags);
1953
1954                         if (resched)
1955                                 cond_resched();
1956                 } else {
1957                         return -EBUSY;
1958                 }
1959         }
1960
1961         return 0;
1962 }
1963
1964 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1965                                     const void *buf, int dwords)
1966 {
1967         unsigned long flags;
1968         int offs, ret = 0;
1969         const u32 *vals = buf;
1970
1971         if (iwl_trans_grab_nic_access(trans, &flags)) {
1972                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1973                 for (offs = 0; offs < dwords; offs++)
1974                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1975                                     vals ? vals[offs] : 0);
1976                 iwl_trans_release_nic_access(trans, &flags);
1977         } else {
1978                 ret = -EBUSY;
1979         }
1980         return ret;
1981 }
1982
1983 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1984                                             unsigned long txqs,
1985                                             bool freeze)
1986 {
1987         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1988         int queue;
1989
1990         for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1991                 struct iwl_txq *txq = trans_pcie->txq[queue];
1992                 unsigned long now;
1993
1994                 spin_lock_bh(&txq->lock);
1995
1996                 now = jiffies;
1997
1998                 if (txq->frozen == freeze)
1999                         goto next_queue;
2000
2001                 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
2002                                     freeze ? "Freezing" : "Waking", queue);
2003
2004                 txq->frozen = freeze;
2005
2006                 if (txq->read_ptr == txq->write_ptr)
2007                         goto next_queue;
2008
2009                 if (freeze) {
2010                         if (unlikely(time_after(now,
2011                                                 txq->stuck_timer.expires))) {
2012                                 /*
2013                                  * The timer should have fired, maybe it is
2014                                  * spinning right now on the lock.
2015                                  */
2016                                 goto next_queue;
2017                         }
2018                         /* remember how long until the timer fires */
2019                         txq->frozen_expiry_remainder =
2020                                 txq->stuck_timer.expires - now;
2021                         del_timer(&txq->stuck_timer);
2022                         goto next_queue;
2023                 }
2024
2025                 /*
2026                  * Wake a non-empty queue -> arm timer with the
2027                  * remainder before it froze
2028                  */
2029                 mod_timer(&txq->stuck_timer,
2030                           now + txq->frozen_expiry_remainder);
2031
2032 next_queue:
2033                 spin_unlock_bh(&txq->lock);
2034         }
2035 }
2036
2037 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2038 {
2039         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2040         int i;
2041
2042         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2043                 struct iwl_txq *txq = trans_pcie->txq[i];
2044
2045                 if (i == trans_pcie->cmd_queue)
2046                         continue;
2047
2048                 spin_lock_bh(&txq->lock);
2049
2050                 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2051                         txq->block--;
2052                         if (!txq->block) {
2053                                 iwl_write32(trans, HBUS_TARG_WRPTR,
2054                                             txq->write_ptr | (i << 8));
2055                         }
2056                 } else if (block) {
2057                         txq->block++;
2058                 }
2059
2060                 spin_unlock_bh(&txq->lock);
2061         }
2062 }
2063
2064 #define IWL_FLUSH_WAIT_MS       2000
2065
2066 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2067 {
2068         u32 txq_id = txq->id;
2069         u32 status;
2070         bool active;
2071         u8 fifo;
2072
2073         if (trans->cfg->use_tfh) {
2074                 IWL_ERR(trans, "Queue %d is stuck %d %d\n", txq_id,
2075                         txq->read_ptr, txq->write_ptr);
2076                 /* TODO: access new SCD registers and dump them */
2077                 return;
2078         }
2079
2080         status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(txq_id));
2081         fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2082         active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2083
2084         IWL_ERR(trans,
2085                 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2086                 txq_id, active ? "" : "in", fifo,
2087                 jiffies_to_msecs(txq->wd_timeout),
2088                 txq->read_ptr, txq->write_ptr,
2089                 iwl_read_prph(trans, SCD_QUEUE_RDPTR(txq_id)) &
2090                         (TFD_QUEUE_SIZE_MAX - 1),
2091                 iwl_read_prph(trans, SCD_QUEUE_WRPTR(txq_id)) &
2092                         (TFD_QUEUE_SIZE_MAX - 1),
2093                 iwl_read_direct32(trans, FH_TX_TRB_REG(fifo)));
2094 }
2095
2096 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx)
2097 {
2098         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2099         struct iwl_txq *txq;
2100         unsigned long now = jiffies;
2101         u8 wr_ptr;
2102
2103         if (!test_bit(txq_idx, trans_pcie->queue_used))
2104                 return -EINVAL;
2105
2106         IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx);
2107         txq = trans_pcie->txq[txq_idx];
2108         wr_ptr = ACCESS_ONCE(txq->write_ptr);
2109
2110         while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2111                !time_after(jiffies,
2112                            now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2113                 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2114
2115                 if (WARN_ONCE(wr_ptr != write_ptr,
2116                               "WR pointer moved while flushing %d -> %d\n",
2117                               wr_ptr, write_ptr))
2118                         return -ETIMEDOUT;
2119                 usleep_range(1000, 2000);
2120         }
2121
2122         if (txq->read_ptr != txq->write_ptr) {
2123                 IWL_ERR(trans,
2124                         "fail to flush all tx fifo queues Q %d\n", txq_idx);
2125                 iwl_trans_pcie_log_scd_error(trans, txq);
2126                 return -ETIMEDOUT;
2127         }
2128
2129         IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx);
2130
2131         return 0;
2132 }
2133
2134 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm)
2135 {
2136         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2137         int cnt;
2138         int ret = 0;
2139
2140         /* waiting for all the tx frames complete might take a while */
2141         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2142
2143                 if (cnt == trans_pcie->cmd_queue)
2144                         continue;
2145                 if (!test_bit(cnt, trans_pcie->queue_used))
2146                         continue;
2147                 if (!(BIT(cnt) & txq_bm))
2148                         continue;
2149
2150                 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt);
2151                 if (ret)
2152                         break;
2153         }
2154
2155         return ret;
2156 }
2157
2158 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2159                                          u32 mask, u32 value)
2160 {
2161         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2162         unsigned long flags;
2163
2164         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2165         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2166         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2167 }
2168
2169 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2170 {
2171         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2172
2173         if (iwlwifi_mod_params.d0i3_disable)
2174                 return;
2175
2176         pm_runtime_get(&trans_pcie->pci_dev->dev);
2177
2178 #ifdef CONFIG_PM
2179         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2180                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2181 #endif /* CONFIG_PM */
2182 }
2183
2184 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2185 {
2186         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2187
2188         if (iwlwifi_mod_params.d0i3_disable)
2189                 return;
2190
2191         pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2192         pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2193
2194 #ifdef CONFIG_PM
2195         IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2196                       atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2197 #endif /* CONFIG_PM */
2198 }
2199
2200 static const char *get_csr_string(int cmd)
2201 {
2202 #define IWL_CMD(x) case x: return #x
2203         switch (cmd) {
2204         IWL_CMD(CSR_HW_IF_CONFIG_REG);
2205         IWL_CMD(CSR_INT_COALESCING);
2206         IWL_CMD(CSR_INT);
2207         IWL_CMD(CSR_INT_MASK);
2208         IWL_CMD(CSR_FH_INT_STATUS);
2209         IWL_CMD(CSR_GPIO_IN);
2210         IWL_CMD(CSR_RESET);
2211         IWL_CMD(CSR_GP_CNTRL);
2212         IWL_CMD(CSR_HW_REV);
2213         IWL_CMD(CSR_EEPROM_REG);
2214         IWL_CMD(CSR_EEPROM_GP);
2215         IWL_CMD(CSR_OTP_GP_REG);
2216         IWL_CMD(CSR_GIO_REG);
2217         IWL_CMD(CSR_GP_UCODE_REG);
2218         IWL_CMD(CSR_GP_DRIVER_REG);
2219         IWL_CMD(CSR_UCODE_DRV_GP1);
2220         IWL_CMD(CSR_UCODE_DRV_GP2);
2221         IWL_CMD(CSR_LED_REG);
2222         IWL_CMD(CSR_DRAM_INT_TBL_REG);
2223         IWL_CMD(CSR_GIO_CHICKEN_BITS);
2224         IWL_CMD(CSR_ANA_PLL_CFG);
2225         IWL_CMD(CSR_HW_REV_WA_REG);
2226         IWL_CMD(CSR_MONITOR_STATUS_REG);
2227         IWL_CMD(CSR_DBG_HPET_MEM_REG);
2228         default:
2229                 return "UNKNOWN";
2230         }
2231 #undef IWL_CMD
2232 }
2233
2234 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2235 {
2236         int i;
2237         static const u32 csr_tbl[] = {
2238                 CSR_HW_IF_CONFIG_REG,
2239                 CSR_INT_COALESCING,
2240                 CSR_INT,
2241                 CSR_INT_MASK,
2242                 CSR_FH_INT_STATUS,
2243                 CSR_GPIO_IN,
2244                 CSR_RESET,
2245                 CSR_GP_CNTRL,
2246                 CSR_HW_REV,
2247                 CSR_EEPROM_REG,
2248                 CSR_EEPROM_GP,
2249                 CSR_OTP_GP_REG,
2250                 CSR_GIO_REG,
2251                 CSR_GP_UCODE_REG,
2252                 CSR_GP_DRIVER_REG,
2253                 CSR_UCODE_DRV_GP1,
2254                 CSR_UCODE_DRV_GP2,
2255                 CSR_LED_REG,
2256                 CSR_DRAM_INT_TBL_REG,
2257                 CSR_GIO_CHICKEN_BITS,
2258                 CSR_ANA_PLL_CFG,
2259                 CSR_MONITOR_STATUS_REG,
2260                 CSR_HW_REV_WA_REG,
2261                 CSR_DBG_HPET_MEM_REG
2262         };
2263         IWL_ERR(trans, "CSR values:\n");
2264         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2265                 "CSR_INT_PERIODIC_REG)\n");
2266         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
2267                 IWL_ERR(trans, "  %25s: 0X%08x\n",
2268                         get_csr_string(csr_tbl[i]),
2269                         iwl_read32(trans, csr_tbl[i]));
2270         }
2271 }
2272
2273 #ifdef CONFIG_IWLWIFI_DEBUGFS
2274 /* create and remove of files */
2275 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
2276         if (!debugfs_create_file(#name, mode, parent, trans,            \
2277                                  &iwl_dbgfs_##name##_ops))              \
2278                 goto err;                                               \
2279 } while (0)
2280
2281 /* file operation */
2282 #define DEBUGFS_READ_FILE_OPS(name)                                     \
2283 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2284         .read = iwl_dbgfs_##name##_read,                                \
2285         .open = simple_open,                                            \
2286         .llseek = generic_file_llseek,                                  \
2287 };
2288
2289 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
2290 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2291         .write = iwl_dbgfs_##name##_write,                              \
2292         .open = simple_open,                                            \
2293         .llseek = generic_file_llseek,                                  \
2294 };
2295
2296 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
2297 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
2298         .write = iwl_dbgfs_##name##_write,                              \
2299         .read = iwl_dbgfs_##name##_read,                                \
2300         .open = simple_open,                                            \
2301         .llseek = generic_file_llseek,                                  \
2302 };
2303
2304 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2305                                        char __user *user_buf,
2306                                        size_t count, loff_t *ppos)
2307 {
2308         struct iwl_trans *trans = file->private_data;
2309         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2310         struct iwl_txq *txq;
2311         char *buf;
2312         int pos = 0;
2313         int cnt;
2314         int ret;
2315         size_t bufsz;
2316
2317         bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2318
2319         if (!trans_pcie->txq_memory)
2320                 return -EAGAIN;
2321
2322         buf = kzalloc(bufsz, GFP_KERNEL);
2323         if (!buf)
2324                 return -ENOMEM;
2325
2326         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2327                 txq = trans_pcie->txq[cnt];
2328                 pos += scnprintf(buf + pos, bufsz - pos,
2329                                 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2330                                 cnt, txq->read_ptr, txq->write_ptr,
2331                                 !!test_bit(cnt, trans_pcie->queue_used),
2332                                  !!test_bit(cnt, trans_pcie->queue_stopped),
2333                                  txq->need_update, txq->frozen,
2334                                  (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2335         }
2336         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2337         kfree(buf);
2338         return ret;
2339 }
2340
2341 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2342                                        char __user *user_buf,
2343                                        size_t count, loff_t *ppos)
2344 {
2345         struct iwl_trans *trans = file->private_data;
2346         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2347         char *buf;
2348         int pos = 0, i, ret;
2349         size_t bufsz = sizeof(buf);
2350
2351         bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2352
2353         if (!trans_pcie->rxq)
2354                 return -EAGAIN;
2355
2356         buf = kzalloc(bufsz, GFP_KERNEL);
2357         if (!buf)
2358                 return -ENOMEM;
2359
2360         for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2361                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2362
2363                 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2364                                  i);
2365                 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2366                                  rxq->read);
2367                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2368                                  rxq->write);
2369                 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2370                                  rxq->write_actual);
2371                 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2372                                  rxq->need_update);
2373                 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2374                                  rxq->free_count);
2375                 if (rxq->rb_stts) {
2376                         pos += scnprintf(buf + pos, bufsz - pos,
2377                                          "\tclosed_rb_num: %u\n",
2378                                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2379                                          0x0FFF);
2380                 } else {
2381                         pos += scnprintf(buf + pos, bufsz - pos,
2382                                          "\tclosed_rb_num: Not Allocated\n");
2383                 }
2384         }
2385         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2386         kfree(buf);
2387
2388         return ret;
2389 }
2390
2391 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2392                                         char __user *user_buf,
2393                                         size_t count, loff_t *ppos)
2394 {
2395         struct iwl_trans *trans = file->private_data;
2396         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2397         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2398
2399         int pos = 0;
2400         char *buf;
2401         int bufsz = 24 * 64; /* 24 items * 64 char per item */
2402         ssize_t ret;
2403
2404         buf = kzalloc(bufsz, GFP_KERNEL);
2405         if (!buf)
2406                 return -ENOMEM;
2407
2408         pos += scnprintf(buf + pos, bufsz - pos,
2409                         "Interrupt Statistics Report:\n");
2410
2411         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2412                 isr_stats->hw);
2413         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2414                 isr_stats->sw);
2415         if (isr_stats->sw || isr_stats->hw) {
2416                 pos += scnprintf(buf + pos, bufsz - pos,
2417                         "\tLast Restarting Code:  0x%X\n",
2418                         isr_stats->err_code);
2419         }
2420 #ifdef CONFIG_IWLWIFI_DEBUG
2421         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2422                 isr_stats->sch);
2423         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2424                 isr_stats->alive);
2425 #endif
2426         pos += scnprintf(buf + pos, bufsz - pos,
2427                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2428
2429         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2430                 isr_stats->ctkill);
2431
2432         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2433                 isr_stats->wakeup);
2434
2435         pos += scnprintf(buf + pos, bufsz - pos,
2436                 "Rx command responses:\t\t %u\n", isr_stats->rx);
2437
2438         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2439                 isr_stats->tx);
2440
2441         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2442                 isr_stats->unhandled);
2443
2444         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2445         kfree(buf);
2446         return ret;
2447 }
2448
2449 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2450                                          const char __user *user_buf,
2451                                          size_t count, loff_t *ppos)
2452 {
2453         struct iwl_trans *trans = file->private_data;
2454         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2455         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2456         u32 reset_flag;
2457         int ret;
2458
2459         ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag);
2460         if (ret)
2461                 return ret;
2462         if (reset_flag == 0)
2463                 memset(isr_stats, 0, sizeof(*isr_stats));
2464
2465         return count;
2466 }
2467
2468 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2469                                    const char __user *user_buf,
2470                                    size_t count, loff_t *ppos)
2471 {
2472         struct iwl_trans *trans = file->private_data;
2473
2474         iwl_pcie_dump_csr(trans);
2475
2476         return count;
2477 }
2478
2479 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2480                                      char __user *user_buf,
2481                                      size_t count, loff_t *ppos)
2482 {
2483         struct iwl_trans *trans = file->private_data;
2484         char *buf = NULL;
2485         ssize_t ret;
2486
2487         ret = iwl_dump_fh(trans, &buf);
2488         if (ret < 0)
2489                 return ret;
2490         if (!buf)
2491                 return -EINVAL;
2492         ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2493         kfree(buf);
2494         return ret;
2495 }
2496
2497 static ssize_t iwl_dbgfs_rfkill_read(struct file *file,
2498                                      char __user *user_buf,
2499                                      size_t count, loff_t *ppos)
2500 {
2501         struct iwl_trans *trans = file->private_data;
2502         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2503         char buf[100];
2504         int pos;
2505
2506         pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n",
2507                         trans_pcie->debug_rfkill,
2508                         !(iwl_read32(trans, CSR_GP_CNTRL) &
2509                                 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW));
2510
2511         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2512 }
2513
2514 static ssize_t iwl_dbgfs_rfkill_write(struct file *file,
2515                                       const char __user *user_buf,
2516                                       size_t count, loff_t *ppos)
2517 {
2518         struct iwl_trans *trans = file->private_data;
2519         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2520         bool old = trans_pcie->debug_rfkill;
2521         int ret;
2522
2523         ret = kstrtobool_from_user(user_buf, count, &trans_pcie->debug_rfkill);
2524         if (ret)
2525                 return ret;
2526         if (old == trans_pcie->debug_rfkill)
2527                 return count;
2528         IWL_WARN(trans, "changing debug rfkill %d->%d\n",
2529                  old, trans_pcie->debug_rfkill);
2530         iwl_pcie_handle_rfkill_irq(trans);
2531
2532         return count;
2533 }
2534
2535 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2536 DEBUGFS_READ_FILE_OPS(fh_reg);
2537 DEBUGFS_READ_FILE_OPS(rx_queue);
2538 DEBUGFS_READ_FILE_OPS(tx_queue);
2539 DEBUGFS_WRITE_FILE_OPS(csr);
2540 DEBUGFS_READ_WRITE_FILE_OPS(rfkill);
2541
2542 /* Create the debugfs files and directories */
2543 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2544 {
2545         struct dentry *dir = trans->dbgfs_dir;
2546
2547         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2548         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2549         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2550         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2551         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2552         DEBUGFS_ADD_FILE(rfkill, dir, S_IWUSR | S_IRUSR);
2553         return 0;
2554
2555 err:
2556         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2557         return -ENOMEM;
2558 }
2559 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2560
2561 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2562 {
2563         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2564         u32 cmdlen = 0;
2565         int i;
2566
2567         for (i = 0; i < trans_pcie->max_tbs; i++)
2568                 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2569
2570         return cmdlen;
2571 }
2572
2573 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2574                                    struct iwl_fw_error_dump_data **data,
2575                                    int allocated_rb_nums)
2576 {
2577         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2578         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2579         /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2580         struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2581         u32 i, r, j, rb_len = 0;
2582
2583         spin_lock(&rxq->lock);
2584
2585         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2586
2587         for (i = rxq->read, j = 0;
2588              i != r && j < allocated_rb_nums;
2589              i = (i + 1) & RX_QUEUE_MASK, j++) {
2590                 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2591                 struct iwl_fw_error_dump_rb *rb;
2592
2593                 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2594                                DMA_FROM_DEVICE);
2595
2596                 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2597
2598                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2599                 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2600                 rb = (void *)(*data)->data;
2601                 rb->index = cpu_to_le32(i);
2602                 memcpy(rb->data, page_address(rxb->page), max_len);
2603                 /* remap the page for the free benefit */
2604                 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2605                                                      max_len,
2606                                                      DMA_FROM_DEVICE);
2607
2608                 *data = iwl_fw_error_next_data(*data);
2609         }
2610
2611         spin_unlock(&rxq->lock);
2612
2613         return rb_len;
2614 }
2615 #define IWL_CSR_TO_DUMP (0x250)
2616
2617 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2618                                    struct iwl_fw_error_dump_data **data)
2619 {
2620         u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2621         __le32 *val;
2622         int i;
2623
2624         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2625         (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2626         val = (void *)(*data)->data;
2627
2628         for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2629                 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2630
2631         *data = iwl_fw_error_next_data(*data);
2632
2633         return csr_len;
2634 }
2635
2636 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2637                                        struct iwl_fw_error_dump_data **data)
2638 {
2639         u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2640         unsigned long flags;
2641         __le32 *val;
2642         int i;
2643
2644         if (!iwl_trans_grab_nic_access(trans, &flags))
2645                 return 0;
2646
2647         (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2648         (*data)->len = cpu_to_le32(fh_regs_len);
2649         val = (void *)(*data)->data;
2650
2651         if (!trans->cfg->gen2)
2652                 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND;
2653                      i += sizeof(u32))
2654                         *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2655         else
2656                 for (i = FH_MEM_LOWER_BOUND_GEN2; i < FH_MEM_UPPER_BOUND_GEN2;
2657                      i += sizeof(u32))
2658                         *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans,
2659                                                                       i));
2660
2661         iwl_trans_release_nic_access(trans, &flags);
2662
2663         *data = iwl_fw_error_next_data(*data);
2664
2665         return sizeof(**data) + fh_regs_len;
2666 }
2667
2668 static u32
2669 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2670                                  struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2671                                  u32 monitor_len)
2672 {
2673         u32 buf_size_in_dwords = (monitor_len >> 2);
2674         u32 *buffer = (u32 *)fw_mon_data->data;
2675         unsigned long flags;
2676         u32 i;
2677
2678         if (!iwl_trans_grab_nic_access(trans, &flags))
2679                 return 0;
2680
2681         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2682         for (i = 0; i < buf_size_in_dwords; i++)
2683                 buffer[i] = iwl_read_prph_no_grab(trans,
2684                                 MON_DMARB_RD_DATA_ADDR);
2685         iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2686
2687         iwl_trans_release_nic_access(trans, &flags);
2688
2689         return monitor_len;
2690 }
2691
2692 static u32
2693 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2694                             struct iwl_fw_error_dump_data **data,
2695                             u32 monitor_len)
2696 {
2697         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2698         u32 len = 0;
2699
2700         if ((trans_pcie->fw_mon_page &&
2701              trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2702             trans->dbg_dest_tlv) {
2703                 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2704                 u32 base, write_ptr, wrap_cnt;
2705
2706                 /* If there was a dest TLV - use the values from there */
2707                 if (trans->dbg_dest_tlv) {
2708                         write_ptr =
2709                                 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2710                         wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2711                         base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2712                 } else {
2713                         base = MON_BUFF_BASE_ADDR;
2714                         write_ptr = MON_BUFF_WRPTR;
2715                         wrap_cnt = MON_BUFF_CYCLE_CNT;
2716                 }
2717
2718                 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2719                 fw_mon_data = (void *)(*data)->data;
2720                 fw_mon_data->fw_mon_wr_ptr =
2721                         cpu_to_le32(iwl_read_prph(trans, write_ptr));
2722                 fw_mon_data->fw_mon_cycle_cnt =
2723                         cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2724                 fw_mon_data->fw_mon_base_ptr =
2725                         cpu_to_le32(iwl_read_prph(trans, base));
2726
2727                 len += sizeof(**data) + sizeof(*fw_mon_data);
2728                 if (trans_pcie->fw_mon_page) {
2729                         /*
2730                          * The firmware is now asserted, it won't write anything
2731                          * to the buffer. CPU can take ownership to fetch the
2732                          * data. The buffer will be handed back to the device
2733                          * before the firmware will be restarted.
2734                          */
2735                         dma_sync_single_for_cpu(trans->dev,
2736                                                 trans_pcie->fw_mon_phys,
2737                                                 trans_pcie->fw_mon_size,
2738                                                 DMA_FROM_DEVICE);
2739                         memcpy(fw_mon_data->data,
2740                                page_address(trans_pcie->fw_mon_page),
2741                                trans_pcie->fw_mon_size);
2742
2743                         monitor_len = trans_pcie->fw_mon_size;
2744                 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2745                         /*
2746                          * Update pointers to reflect actual values after
2747                          * shifting
2748                          */
2749                         base = iwl_read_prph(trans, base) <<
2750                                trans->dbg_dest_tlv->base_shift;
2751                         iwl_trans_read_mem(trans, base, fw_mon_data->data,
2752                                            monitor_len / sizeof(u32));
2753                 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2754                         monitor_len =
2755                                 iwl_trans_pci_dump_marbh_monitor(trans,
2756                                                                  fw_mon_data,
2757                                                                  monitor_len);
2758                 } else {
2759                         /* Didn't match anything - output no monitor data */
2760                         monitor_len = 0;
2761                 }
2762
2763                 len += monitor_len;
2764                 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2765         }
2766
2767         return len;
2768 }
2769
2770 static struct iwl_trans_dump_data
2771 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2772                           const struct iwl_fw_dbg_trigger_tlv *trigger)
2773 {
2774         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2775         struct iwl_fw_error_dump_data *data;
2776         struct iwl_txq *cmdq = trans_pcie->txq[trans_pcie->cmd_queue];
2777         struct iwl_fw_error_dump_txcmd *txcmd;
2778         struct iwl_trans_dump_data *dump_data;
2779         u32 len, num_rbs;
2780         u32 monitor_len;
2781         int i, ptr;
2782         bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2783                         !trans->cfg->mq_rx_supported;
2784
2785         /* transport dump header */
2786         len = sizeof(*dump_data);
2787
2788         /* host commands */
2789         len += sizeof(*data) +
2790                 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2791
2792         /* FW monitor */
2793         if (trans_pcie->fw_mon_page) {
2794                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2795                        trans_pcie->fw_mon_size;
2796                 monitor_len = trans_pcie->fw_mon_size;
2797         } else if (trans->dbg_dest_tlv) {
2798                 u32 base, end;
2799
2800                 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2801                 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2802
2803                 base = iwl_read_prph(trans, base) <<
2804                        trans->dbg_dest_tlv->base_shift;
2805                 end = iwl_read_prph(trans, end) <<
2806                       trans->dbg_dest_tlv->end_shift;
2807
2808                 /* Make "end" point to the actual end */
2809                 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000 ||
2810                     trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2811                         end += (1 << trans->dbg_dest_tlv->end_shift);
2812                 monitor_len = end - base;
2813                 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2814                        monitor_len;
2815         } else {
2816                 monitor_len = 0;
2817         }
2818
2819         if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2820                 dump_data = vzalloc(len);
2821                 if (!dump_data)
2822                         return NULL;
2823
2824                 data = (void *)dump_data->data;
2825                 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2826                 dump_data->len = len;
2827
2828                 return dump_data;
2829         }
2830
2831         /* CSR registers */
2832         len += sizeof(*data) + IWL_CSR_TO_DUMP;
2833
2834         /* FH registers */
2835         if (trans->cfg->gen2)
2836                 len += sizeof(*data) +
2837                        (FH_MEM_UPPER_BOUND_GEN2 - FH_MEM_LOWER_BOUND_GEN2);
2838         else
2839                 len += sizeof(*data) +
2840                        (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2841
2842         if (dump_rbs) {
2843                 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2844                 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2845                 /* RBs */
2846                 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2847                                       & 0x0FFF;
2848                 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2849                 len += num_rbs * (sizeof(*data) +
2850                                   sizeof(struct iwl_fw_error_dump_rb) +
2851                                   (PAGE_SIZE << trans_pcie->rx_page_order));
2852         }
2853
2854         /* Paged memory for gen2 HW */
2855         if (trans->cfg->gen2)
2856                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++)
2857                         len += sizeof(*data) +
2858                                sizeof(struct iwl_fw_error_dump_paging) +
2859                                trans_pcie->init_dram.paging[i].size;
2860
2861         dump_data = vzalloc(len);
2862         if (!dump_data)
2863                 return NULL;
2864
2865         len = 0;
2866         data = (void *)dump_data->data;
2867         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2868         txcmd = (void *)data->data;
2869         spin_lock_bh(&cmdq->lock);
2870         ptr = cmdq->write_ptr;
2871         for (i = 0; i < cmdq->n_window; i++) {
2872                 u8 idx = iwl_pcie_get_cmd_index(cmdq, ptr);
2873                 u32 caplen, cmdlen;
2874
2875                 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2876                                                    trans_pcie->tfd_size * ptr);
2877                 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2878
2879                 if (cmdlen) {
2880                         len += sizeof(*txcmd) + caplen;
2881                         txcmd->cmdlen = cpu_to_le32(cmdlen);
2882                         txcmd->caplen = cpu_to_le32(caplen);
2883                         memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2884                         txcmd = (void *)((u8 *)txcmd->data + caplen);
2885                 }
2886
2887                 ptr = iwl_queue_dec_wrap(ptr);
2888         }
2889         spin_unlock_bh(&cmdq->lock);
2890
2891         data->len = cpu_to_le32(len);
2892         len += sizeof(*data);
2893         data = iwl_fw_error_next_data(data);
2894
2895         len += iwl_trans_pcie_dump_csr(trans, &data);
2896         len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2897         if (dump_rbs)
2898                 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2899
2900         /* Paged memory for gen2 HW */
2901         if (trans->cfg->gen2) {
2902                 for (i = 0; i < trans_pcie->init_dram.paging_cnt; i++) {
2903                         struct iwl_fw_error_dump_paging *paging;
2904                         dma_addr_t addr =
2905                                 trans_pcie->init_dram.paging[i].physical;
2906                         u32 page_len = trans_pcie->init_dram.paging[i].size;
2907
2908                         data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING);
2909                         data->len = cpu_to_le32(sizeof(*paging) + page_len);
2910                         paging = (void *)data->data;
2911                         paging->index = cpu_to_le32(i);
2912                         dma_sync_single_for_cpu(trans->dev, addr, page_len,
2913                                                 DMA_BIDIRECTIONAL);
2914                         memcpy(paging->data,
2915                                trans_pcie->init_dram.paging[i].block, page_len);
2916                         data = iwl_fw_error_next_data(data);
2917
2918                         len += sizeof(*data) + sizeof(*paging) + page_len;
2919                 }
2920         }
2921
2922         len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2923
2924         dump_data->len = len;
2925
2926         return dump_data;
2927 }
2928
2929 #ifdef CONFIG_PM_SLEEP
2930 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2931 {
2932         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2933             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2934                 return iwl_pci_fw_enter_d0i3(trans);
2935
2936         return 0;
2937 }
2938
2939 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2940 {
2941         if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2942             (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2943                 iwl_pci_fw_exit_d0i3(trans);
2944 }
2945 #endif /* CONFIG_PM_SLEEP */
2946
2947 #define IWL_TRANS_COMMON_OPS                                            \
2948         .op_mode_leave = iwl_trans_pcie_op_mode_leave,                  \
2949         .write8 = iwl_trans_pcie_write8,                                \
2950         .write32 = iwl_trans_pcie_write32,                              \
2951         .read32 = iwl_trans_pcie_read32,                                \
2952         .read_prph = iwl_trans_pcie_read_prph,                          \
2953         .write_prph = iwl_trans_pcie_write_prph,                        \
2954         .read_mem = iwl_trans_pcie_read_mem,                            \
2955         .write_mem = iwl_trans_pcie_write_mem,                          \
2956         .configure = iwl_trans_pcie_configure,                          \
2957         .set_pmi = iwl_trans_pcie_set_pmi,                              \
2958         .grab_nic_access = iwl_trans_pcie_grab_nic_access,              \
2959         .release_nic_access = iwl_trans_pcie_release_nic_access,        \
2960         .set_bits_mask = iwl_trans_pcie_set_bits_mask,                  \
2961         .ref = iwl_trans_pcie_ref,                                      \
2962         .unref = iwl_trans_pcie_unref,                                  \
2963         .dump_data = iwl_trans_pcie_dump_data,                          \
2964         .d3_suspend = iwl_trans_pcie_d3_suspend,                        \
2965         .d3_resume = iwl_trans_pcie_d3_resume
2966
2967 #ifdef CONFIG_PM_SLEEP
2968 #define IWL_TRANS_PM_OPS                                                \
2969         .suspend = iwl_trans_pcie_suspend,                              \
2970         .resume = iwl_trans_pcie_resume,
2971 #else
2972 #define IWL_TRANS_PM_OPS
2973 #endif /* CONFIG_PM_SLEEP */
2974
2975 static const struct iwl_trans_ops trans_ops_pcie = {
2976         IWL_TRANS_COMMON_OPS,
2977         IWL_TRANS_PM_OPS
2978         .start_hw = iwl_trans_pcie_start_hw,
2979         .fw_alive = iwl_trans_pcie_fw_alive,
2980         .start_fw = iwl_trans_pcie_start_fw,
2981         .stop_device = iwl_trans_pcie_stop_device,
2982
2983         .send_cmd = iwl_trans_pcie_send_hcmd,
2984
2985         .tx = iwl_trans_pcie_tx,
2986         .reclaim = iwl_trans_pcie_reclaim,
2987
2988         .txq_disable = iwl_trans_pcie_txq_disable,
2989         .txq_enable = iwl_trans_pcie_txq_enable,
2990
2991         .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2992
2993         .wait_tx_queues_empty = iwl_trans_pcie_wait_txqs_empty,
2994
2995         .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2996         .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2997 };
2998
2999 static const struct iwl_trans_ops trans_ops_pcie_gen2 = {
3000         IWL_TRANS_COMMON_OPS,
3001         IWL_TRANS_PM_OPS
3002         .start_hw = iwl_trans_pcie_start_hw,
3003         .fw_alive = iwl_trans_pcie_gen2_fw_alive,
3004         .start_fw = iwl_trans_pcie_gen2_start_fw,
3005         .stop_device = iwl_trans_pcie_gen2_stop_device,
3006
3007         .send_cmd = iwl_trans_pcie_gen2_send_hcmd,
3008
3009         .tx = iwl_trans_pcie_gen2_tx,
3010         .reclaim = iwl_trans_pcie_reclaim,
3011
3012         .txq_alloc = iwl_trans_pcie_dyn_txq_alloc,
3013         .txq_free = iwl_trans_pcie_dyn_txq_free,
3014         .wait_txq_empty = iwl_trans_pcie_wait_txq_empty,
3015 };
3016
3017 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
3018                                        const struct pci_device_id *ent,
3019                                        const struct iwl_cfg *cfg)
3020 {
3021         struct iwl_trans_pcie *trans_pcie;
3022         struct iwl_trans *trans;
3023         int ret, addr_size;
3024
3025         ret = pcim_enable_device(pdev);
3026         if (ret)
3027                 return ERR_PTR(ret);
3028
3029         if (cfg->gen2)
3030                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3031                                         &pdev->dev, cfg, &trans_ops_pcie_gen2);
3032         else
3033                 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
3034                                         &pdev->dev, cfg, &trans_ops_pcie);
3035         if (!trans)
3036                 return ERR_PTR(-ENOMEM);
3037
3038         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
3039
3040         trans_pcie->trans = trans;
3041         trans_pcie->opmode_down = true;
3042         spin_lock_init(&trans_pcie->irq_lock);
3043         spin_lock_init(&trans_pcie->reg_lock);
3044         mutex_init(&trans_pcie->mutex);
3045         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
3046
3047         trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator",
3048                                                    WQ_HIGHPRI | WQ_UNBOUND, 1);
3049         if (!trans_pcie->rba.alloc_wq) {
3050                 ret = -ENOMEM;
3051                 goto out_free_trans;
3052         }
3053         INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work);
3054
3055         trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
3056         if (!trans_pcie->tso_hdr_page) {
3057                 ret = -ENOMEM;
3058                 goto out_no_pci;
3059         }
3060
3061
3062         if (!cfg->base_params->pcie_l1_allowed) {
3063                 /*
3064                  * W/A - seems to solve weird behavior. We need to remove this
3065                  * if we don't want to stay in L1 all the time. This wastes a
3066                  * lot of power.
3067                  */
3068                 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
3069                                        PCIE_LINK_STATE_L1 |
3070                                        PCIE_LINK_STATE_CLKPM);
3071         }
3072
3073         if (cfg->use_tfh) {
3074                 addr_size = 64;
3075                 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
3076                 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
3077         } else {
3078                 addr_size = 36;
3079                 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
3080                 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
3081         }
3082         trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
3083
3084         pci_set_master(pdev);
3085
3086         ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
3087         if (!ret)
3088                 ret = pci_set_consistent_dma_mask(pdev,
3089                                                   DMA_BIT_MASK(addr_size));
3090         if (ret) {
3091                 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3092                 if (!ret)
3093                         ret = pci_set_consistent_dma_mask(pdev,
3094                                                           DMA_BIT_MASK(32));
3095                 /* both attempts failed: */
3096                 if (ret) {
3097                         dev_err(&pdev->dev, "No suitable DMA available\n");
3098                         goto out_no_pci;
3099                 }
3100         }
3101
3102         ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
3103         if (ret) {
3104                 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
3105                 goto out_no_pci;
3106         }
3107
3108         trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
3109         if (!trans_pcie->hw_base) {
3110                 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
3111                 ret = -ENODEV;
3112                 goto out_no_pci;
3113         }
3114
3115         /* We disable the RETRY_TIMEOUT register (0x41) to keep
3116          * PCI Tx retries from interfering with C3 CPU state */
3117         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3118
3119         trans_pcie->pci_dev = pdev;
3120         iwl_disable_interrupts(trans);
3121
3122         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3123         /*
3124          * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3125          * changed, and now the revision step also includes bit 0-1 (no more
3126          * "dash" value). To keep hw_rev backwards compatible - we'll store it
3127          * in the old format.
3128          */
3129         if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_8000) {
3130                 unsigned long flags;
3131
3132                 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3133                                 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3134
3135                 ret = iwl_pcie_prepare_card_hw(trans);
3136                 if (ret) {
3137                         IWL_WARN(trans, "Exit HW not ready\n");
3138                         goto out_no_pci;
3139                 }
3140
3141                 /*
3142                  * in-order to recognize C step driver should read chip version
3143                  * id located at the AUX bus MISC address space.
3144                  */
3145                 iwl_set_bit(trans, CSR_GP_CNTRL,
3146                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3147                 udelay(2);
3148
3149                 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3150                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3151                                    CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3152                                    25000);
3153                 if (ret < 0) {
3154                         IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3155                         goto out_no_pci;
3156                 }
3157
3158                 if (iwl_trans_grab_nic_access(trans, &flags)) {
3159                         u32 hw_step;
3160
3161                         hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3162                         hw_step |= ENABLE_WFPM;
3163                         iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3164                         hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3165                         hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3166                         if (hw_step == 0x3)
3167                                 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3168                                                 (SILICON_C_STEP << 2);
3169                         iwl_trans_release_nic_access(trans, &flags);
3170                 }
3171         }
3172
3173         /*
3174          * 9000-series integrated A-step has a problem with suspend/resume
3175          * and sometimes even causes the whole platform to get stuck. This
3176          * workaround makes the hardware not go into the problematic state.
3177          */
3178         if (trans->cfg->integrated &&
3179             trans->cfg->device_family == IWL_DEVICE_FAMILY_9000 &&
3180             CSR_HW_REV_STEP(trans->hw_rev) == SILICON_A_STEP)
3181                 iwl_set_bit(trans, CSR_HOST_CHICKEN,
3182                             CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
3183
3184 #if IS_ENABLED(CONFIG_IWLMVM)
3185         trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3186         if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
3187                 u32 hw_status;
3188
3189                 hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
3190                 if (hw_status & UMAG_GEN_HW_IS_FPGA)
3191                         trans->cfg = &iwla000_2ax_cfg_qnj_hr_f0;
3192                 else
3193                         trans->cfg = &iwla000_2ac_cfg_hr;
3194         }
3195 #endif
3196
3197         iwl_pcie_set_interrupt_capa(pdev, trans);
3198         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3199         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3200                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3201
3202         /* Initialize the wait queue for commands */
3203         init_waitqueue_head(&trans_pcie->wait_command_queue);
3204
3205         init_waitqueue_head(&trans_pcie->d0i3_waitq);
3206
3207         if (trans_pcie->msix_enabled) {
3208                 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie);
3209                 if (ret)
3210                         goto out_no_pci;
3211          } else {
3212                 ret = iwl_pcie_alloc_ict(trans);
3213                 if (ret)
3214                         goto out_no_pci;
3215
3216                 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3217                                                 iwl_pcie_isr,
3218                                                 iwl_pcie_irq_handler,
3219                                                 IRQF_SHARED, DRV_NAME, trans);
3220                 if (ret) {
3221                         IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3222                         goto out_free_ict;
3223                 }
3224                 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3225          }
3226
3227 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3228         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3229 #else
3230         trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3231 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3232
3233         return trans;
3234
3235 out_free_ict:
3236         iwl_pcie_free_ict(trans);
3237 out_no_pci:
3238         free_percpu(trans_pcie->tso_hdr_page);
3239         destroy_workqueue(trans_pcie->rba.alloc_wq);
3240 out_free_trans:
3241         iwl_trans_free(trans);
3242         return ERR_PTR(ret);
3243 }