1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
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47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
78 #include "iwl-trans.h"
82 #include "iwl-agn-hw.h"
83 #include "iwl-fw-error-dump.h"
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
91 static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans)
93 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
95 if (!trans_pcie->fw_mon_page)
98 dma_unmap_page(trans->dev, trans_pcie->fw_mon_phys,
99 trans_pcie->fw_mon_size, DMA_FROM_DEVICE);
100 __free_pages(trans_pcie->fw_mon_page,
101 get_order(trans_pcie->fw_mon_size));
102 trans_pcie->fw_mon_page = NULL;
103 trans_pcie->fw_mon_phys = 0;
104 trans_pcie->fw_mon_size = 0;
107 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power)
109 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
110 struct page *page = NULL;
116 /* default max_power is maximum */
122 if (WARN(max_power > 26,
123 "External buffer size for monitor is too big %d, check the FW TLV\n",
127 if (trans_pcie->fw_mon_page) {
128 dma_sync_single_for_device(trans->dev, trans_pcie->fw_mon_phys,
129 trans_pcie->fw_mon_size,
135 for (power = max_power; power >= 11; power--) {
139 order = get_order(size);
140 page = alloc_pages(__GFP_COMP | __GFP_NOWARN | __GFP_ZERO,
145 phys = dma_map_page(trans->dev, page, 0, PAGE_SIZE << order,
147 if (dma_mapping_error(trans->dev, phys)) {
148 __free_pages(page, order);
153 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
158 if (WARN_ON_ONCE(!page))
161 if (power != max_power)
163 "Sorry - debug buffer is only %luK while you requested %luK\n",
164 (unsigned long)BIT(power - 10),
165 (unsigned long)BIT(max_power - 10));
167 trans_pcie->fw_mon_page = page;
168 trans_pcie->fw_mon_phys = phys;
169 trans_pcie->fw_mon_size = size;
172 static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg)
174 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
175 ((reg & 0x0000ffff) | (2 << 28)));
176 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG);
179 static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val)
181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val);
182 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG,
183 ((reg & 0x0000ffff) | (3 << 28)));
186 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
188 if (trans->cfg->apmg_not_supported)
191 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
192 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
193 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
194 ~APMG_PS_CTRL_MSK_PWR_SRC);
196 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
197 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
198 ~APMG_PS_CTRL_MSK_PWR_SRC);
202 #define PCI_CFG_RETRY_TIMEOUT 0x041
204 static void iwl_pcie_apm_config(struct iwl_trans *trans)
206 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
211 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
212 * Check if BIOS (or OS) enabled L1-ASPM on this device.
213 * If so (likely), disable L0S, so device moves directly L0->L1;
214 * costs negligible amount of power savings.
215 * If not (unlikely), enable L0S, so there is at least some
216 * power savings, even without L1.
218 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
219 if (lctl & PCI_EXP_LNKCTL_ASPM_L1)
220 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
222 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
223 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
225 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap);
226 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN;
227 dev_info(trans->dev, "L1 %sabled - LTR %sabled\n",
228 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis",
229 trans->ltr_enabled ? "En" : "Dis");
233 * Start up NIC's basic functionality after it has been reset
234 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
235 * NOTE: This does not load uCode nor start the embedded processor
237 static int iwl_pcie_apm_init(struct iwl_trans *trans)
240 IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
243 * Use "set_bit" below rather than "write", to preserve any hardware
244 * bits already set by default after reset.
247 /* Disable L0S exit timer (platform NMI Work/Around) */
248 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_8000)
249 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
250 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
253 * Disable L0s without affecting L1;
254 * don't wait for ICH L0s (ICH bug W/A)
256 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
257 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
259 /* Set FH wait threshold to maximum (HW error during stress W/A) */
260 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
263 * Enable HAP INTA (interrupt from management bus) to
264 * wake device's PCI Express link L1a -> L0s
266 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
267 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
269 iwl_pcie_apm_config(trans);
271 /* Configure analog phase-lock-loop before activating to D0A */
272 if (trans->cfg->base_params->pll_cfg)
273 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
276 * Set "initialization complete" bit to move adapter from
277 * D0U* --> D0A* (powered-up active) state.
279 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
282 * Wait for clock stabilization; once stabilized, access to
283 * device-internal resources is supported, e.g. iwl_write_prph()
284 * and accesses to uCode SRAM.
286 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
287 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
288 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
290 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
294 if (trans->cfg->host_interrupt_operation_mode) {
296 * This is a bit of an abuse - This is needed for 7260 / 3160
297 * only check host_interrupt_operation_mode even if this is
298 * not related to host_interrupt_operation_mode.
300 * Enable the oscillator to count wake up time for L1 exit. This
301 * consumes slightly more power (100uA) - but allows to be sure
302 * that we wake up from L1 on time.
304 * This looks weird: read twice the same register, discard the
305 * value, set a bit, and yet again, read that same register
306 * just to discard the value. But that's the way the hardware
309 iwl_read_prph(trans, OSC_CLK);
310 iwl_read_prph(trans, OSC_CLK);
311 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL);
312 iwl_read_prph(trans, OSC_CLK);
313 iwl_read_prph(trans, OSC_CLK);
317 * Enable DMA clock and wait for it to stabilize.
319 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
320 * bits do not disable clocks. This preserves any hardware
321 * bits already set by default in "CLK_CTRL_REG" after reset.
323 if (!trans->cfg->apmg_not_supported) {
324 iwl_write_prph(trans, APMG_CLK_EN_REG,
325 APMG_CLK_VAL_DMA_CLK_RQT);
328 /* Disable L1-Active */
329 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
330 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
332 /* Clear the interrupt in APMG if the NIC is in RFKILL */
333 iwl_write_prph(trans, APMG_RTC_INT_STT_REG,
334 APMG_RTC_INT_STT_RFKILL);
337 set_bit(STATUS_DEVICE_ENABLED, &trans->status);
344 * Enable LP XTAL to avoid HW bug where device may consume much power if
345 * FW is not loaded after device reset. LP XTAL is disabled by default
346 * after device HW reset. Do it only if XTAL is fed by internal source.
347 * Configure device's "persistence" mode to avoid resetting XTAL again when
348 * SHRD_HW_RST occurs in S3.
350 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans)
354 u32 apmg_xtal_cfg_reg;
358 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
359 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
361 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */
362 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
363 usleep_range(1000, 2000);
366 * Set "initialization complete" bit to move adapter from
367 * D0U* --> D0A* (powered-up active) state.
369 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
372 * Wait for clock stabilization; once stabilized, access to
373 * device-internal resources is possible.
375 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
379 if (WARN_ON(ret < 0)) {
380 IWL_ERR(trans, "Access time out - failed to enable LP XTAL\n");
381 /* Release XTAL ON request */
382 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
383 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
388 * Clear "disable persistence" to avoid LP XTAL resetting when
389 * SHRD_HW_RST is applied in S3.
391 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG,
392 APMG_PCIDEV_STT_VAL_PERSIST_DIS);
395 * Force APMG XTAL to be active to prevent its disabling by HW
396 * caused by APMG idle state.
398 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans,
399 SHR_APMG_XTAL_CFG_REG);
400 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
402 SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
405 * Reset entire device again - do controller reset (results in
406 * SHRD_HW_RST). Turn MAC off before proceeding.
408 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
409 usleep_range(1000, 2000);
411 /* Enable LP XTAL by indirect access through CSR */
412 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG);
413 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg |
414 SHR_APMG_GP1_WF_XTAL_LP_EN |
415 SHR_APMG_GP1_CHICKEN_BIT_SELECT);
417 /* Clear delay line clock power up */
418 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG);
419 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg &
420 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP);
423 * Enable persistence mode to avoid LP XTAL resetting when
424 * SHRD_HW_RST is applied in S3.
426 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
427 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
430 * Clear "initialization complete" bit to move adapter from
431 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
433 iwl_clear_bit(trans, CSR_GP_CNTRL,
434 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
436 /* Activates XTAL resources monitor */
437 __iwl_trans_pcie_set_bit(trans, CSR_MONITOR_CFG_REG,
438 CSR_MONITOR_XTAL_RESOURCES);
440 /* Release XTAL ON request */
441 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
442 CSR_GP_CNTRL_REG_FLAG_XTAL_ON);
445 /* Release APMG XTAL */
446 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG,
448 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ);
451 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
455 /* stop device's busmaster DMA activity */
456 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
458 ret = iwl_poll_bit(trans, CSR_RESET,
459 CSR_RESET_REG_FLAG_MASTER_DISABLED,
460 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
462 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
464 IWL_DEBUG_INFO(trans, "stop master\n");
469 static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave)
471 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
474 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
475 iwl_pcie_apm_init(trans);
477 /* inform ME that we are leaving */
478 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_7000)
479 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
480 APMG_PCIDEV_STT_VAL_WAKE_ME);
481 else if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
482 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
483 CSR_RESET_LINK_PWR_MGMT_DISABLED);
484 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
485 CSR_HW_IF_CONFIG_REG_PREPARE |
486 CSR_HW_IF_CONFIG_REG_ENABLE_PME);
488 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
489 CSR_RESET_LINK_PWR_MGMT_DISABLED);
494 clear_bit(STATUS_DEVICE_ENABLED, &trans->status);
496 /* Stop device's DMA activity */
497 iwl_pcie_apm_stop_master(trans);
499 if (trans->cfg->lp_xtal_workaround) {
500 iwl_pcie_apm_lp_xtal_enable(trans);
504 /* Reset the entire device */
505 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
506 usleep_range(1000, 2000);
509 * Clear "initialization complete" bit to move adapter from
510 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
512 iwl_clear_bit(trans, CSR_GP_CNTRL,
513 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
516 static int iwl_pcie_nic_init(struct iwl_trans *trans)
518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
521 spin_lock(&trans_pcie->irq_lock);
522 iwl_pcie_apm_init(trans);
524 spin_unlock(&trans_pcie->irq_lock);
526 iwl_pcie_set_pwr(trans, false);
528 iwl_op_mode_nic_config(trans->op_mode);
530 /* Allocate the RX queue, or reset if it is already allocated */
531 iwl_pcie_rx_init(trans);
533 /* Allocate or reset and init all Tx and Command queues */
534 if (iwl_pcie_tx_init(trans))
537 if (trans->cfg->base_params->shadow_reg_enable) {
538 /* enable shadow regs in HW */
539 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
540 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
546 #define HW_READY_TIMEOUT (50)
548 /* Note: returns poll_bit return value, which is >= 0 if success */
549 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
553 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
554 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
556 /* See if we got it */
557 ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
558 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
559 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
563 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE);
565 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
569 /* Note: returns standard 0/-ERROR code */
570 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
576 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
578 ret = iwl_pcie_set_hw_ready(trans);
579 /* If the card is ready, exit 0 */
583 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG,
584 CSR_RESET_LINK_PWR_MGMT_DISABLED);
585 usleep_range(1000, 2000);
587 for (iter = 0; iter < 10; iter++) {
588 /* If HW is not ready, prepare the conditions to check again */
589 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
590 CSR_HW_IF_CONFIG_REG_PREPARE);
593 ret = iwl_pcie_set_hw_ready(trans);
597 usleep_range(200, 1000);
599 } while (t < 150000);
603 IWL_ERR(trans, "Couldn't prepare the card\n");
611 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans,
612 u32 dst_addr, dma_addr_t phy_addr,
615 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
616 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
618 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
621 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
622 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
624 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
625 (iwl_get_dma_hi_addr(phy_addr)
626 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
628 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
629 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) |
630 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) |
631 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
633 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
634 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
635 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
636 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
639 static void iwl_pcie_load_firmware_chunk_tfh(struct iwl_trans *trans,
640 u32 dst_addr, dma_addr_t phy_addr,
643 /* Stop DMA channel */
644 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, 0);
646 /* Configure SRAM address */
647 iwl_write32(trans, TFH_SRV_DMA_CHNL0_SRAM_ADDR,
650 /* Configure DRAM address - 64 bit */
651 iwl_write64(trans, TFH_SRV_DMA_CHNL0_DRAM_ADDR, phy_addr);
653 /* Configure byte count to transfer */
654 iwl_write32(trans, TFH_SRV_DMA_CHNL0_BC, byte_cnt);
656 /* Enable the DRAM2SRAM to start */
657 iwl_write32(trans, TFH_SRV_DMA_CHNL0_CTRL, TFH_SRV_DMA_SNOOP |
658 TFH_SRV_DMA_TO_DRIVER |
662 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans,
663 u32 dst_addr, dma_addr_t phy_addr,
666 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
670 trans_pcie->ucode_write_complete = false;
672 if (!iwl_trans_grab_nic_access(trans, &flags))
675 if (trans->cfg->use_tfh)
676 iwl_pcie_load_firmware_chunk_tfh(trans, dst_addr, phy_addr,
679 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr,
681 iwl_trans_release_nic_access(trans, &flags);
683 ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
684 trans_pcie->ucode_write_complete, 5 * HZ);
686 IWL_ERR(trans, "Failed to load firmware chunk!\n");
693 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
694 const struct fw_desc *section)
698 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len);
701 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
704 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
705 GFP_KERNEL | __GFP_NOWARN);
707 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
708 chunk_sz = PAGE_SIZE;
709 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
710 &p_addr, GFP_KERNEL);
715 for (offset = 0; offset < section->len; offset += chunk_sz) {
716 u32 copy_size, dst_addr;
717 bool extended_addr = false;
719 copy_size = min_t(u32, chunk_sz, section->len - offset);
720 dst_addr = section->offset + offset;
722 if (dst_addr >= IWL_FW_MEM_EXTENDED_START &&
723 dst_addr <= IWL_FW_MEM_EXTENDED_END)
724 extended_addr = true;
727 iwl_set_bits_prph(trans, LMPM_CHICK,
728 LMPM_CHICK_EXTENDED_ADDR_SPACE);
730 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
731 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr,
735 iwl_clear_bits_prph(trans, LMPM_CHICK,
736 LMPM_CHICK_EXTENDED_ADDR_SPACE);
740 "Could not load the [%d] uCode section\n",
746 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
751 * Driver Takes the ownership on secure machine before FW load
752 * and prevent race with the BT load.
753 * W/A for ROM bug. (should be remove in the next Si step)
755 static int iwl_pcie_rsa_race_bug_wa(struct iwl_trans *trans)
757 u32 val, loop = 1000;
760 * Check the RSA semaphore is accessible.
761 * If the HW isn't locked and the rsa semaphore isn't accessible,
764 val = iwl_read_prph(trans, PREG_AUX_BUS_WPROT_0);
765 if (val & (BIT(1) | BIT(17))) {
766 IWL_DEBUG_INFO(trans,
767 "can't access the RSA semaphore it is write protected\n");
771 /* take ownership on the AUX IF */
772 iwl_write_prph(trans, WFPM_CTRL_REG, WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK);
773 iwl_write_prph(trans, AUX_MISC_MASTER1_EN, AUX_MISC_MASTER1_EN_SBE_MSK);
776 iwl_write_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS, 0x1);
777 val = iwl_read_prph(trans, AUX_MISC_MASTER1_SMPHR_STATUS);
779 iwl_write_prph(trans, RSA_ENABLE, 0);
787 IWL_ERR(trans, "Failed to take ownership on secure machine\n");
791 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans,
792 const struct fw_img *image,
794 int *first_ucode_section)
797 int i, ret = 0, sec_num = 0x1;
798 u32 val, last_read_idx = 0;
802 *first_ucode_section = 0;
805 (*first_ucode_section)++;
808 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
812 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
814 * PAGING_SEPARATOR_SECTION delimiter - separate between
815 * CPU2 non paged to CPU2 paging sec.
817 if (!image->sec[i].data ||
818 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
819 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
821 "Break since Data not valid or Empty section, sec = %d\n",
826 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
830 /* Notify ucode of loaded section number and status */
831 if (trans->cfg->use_tfh) {
832 val = iwl_read_prph(trans, UREG_UCODE_LOAD_STATUS);
833 val = val | (sec_num << shift_param);
834 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, val);
836 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS);
837 val = val | (sec_num << shift_param);
838 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val);
840 sec_num = (sec_num << 1) | 0x1;
843 *first_ucode_section = last_read_idx;
845 iwl_enable_interrupts(trans);
847 if (trans->cfg->use_tfh) {
849 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
852 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS,
856 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
859 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS,
866 static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans,
867 const struct fw_img *image,
869 int *first_ucode_section)
872 u32 last_read_idx = 0;
875 *first_ucode_section = 0;
877 (*first_ucode_section)++;
879 for (i = *first_ucode_section; i < IWL_UCODE_SECTION_MAX; i++) {
883 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
885 * PAGING_SEPARATOR_SECTION delimiter - separate between
886 * CPU2 non paged to CPU2 paging sec.
888 if (!image->sec[i].data ||
889 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION ||
890 image->sec[i].offset == PAGING_SEPARATOR_SECTION) {
892 "Break since Data not valid or Empty section, sec = %d\n",
897 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
902 *first_ucode_section = last_read_idx;
907 static void iwl_pcie_apply_destination(struct iwl_trans *trans)
909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
910 const struct iwl_fw_dbg_dest_tlv *dest = trans->dbg_dest_tlv;
915 "DBG DEST version is %d - expect issues\n",
918 IWL_INFO(trans, "Applying debug destination %s\n",
919 get_fw_dbg_mode_string(dest->monitor_mode));
921 if (dest->monitor_mode == EXTERNAL_MODE)
922 iwl_pcie_alloc_fw_monitor(trans, dest->size_power);
924 IWL_WARN(trans, "PCI should have external buffer debug\n");
926 for (i = 0; i < trans->dbg_dest_reg_num; i++) {
927 u32 addr = le32_to_cpu(dest->reg_ops[i].addr);
928 u32 val = le32_to_cpu(dest->reg_ops[i].val);
930 switch (dest->reg_ops[i].op) {
932 iwl_write32(trans, addr, val);
935 iwl_set_bit(trans, addr, BIT(val));
938 iwl_clear_bit(trans, addr, BIT(val));
941 iwl_write_prph(trans, addr, val);
944 iwl_set_bits_prph(trans, addr, BIT(val));
947 iwl_clear_bits_prph(trans, addr, BIT(val));
950 if (iwl_read_prph(trans, addr) & BIT(val)) {
952 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
958 IWL_ERR(trans, "FW debug - unknown OP %d\n",
959 dest->reg_ops[i].op);
965 if (dest->monitor_mode == EXTERNAL_MODE && trans_pcie->fw_mon_size) {
966 iwl_write_prph(trans, le32_to_cpu(dest->base_reg),
967 trans_pcie->fw_mon_phys >> dest->base_shift);
968 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
969 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
970 (trans_pcie->fw_mon_phys +
971 trans_pcie->fw_mon_size - 256) >>
974 iwl_write_prph(trans, le32_to_cpu(dest->end_reg),
975 (trans_pcie->fw_mon_phys +
976 trans_pcie->fw_mon_size) >>
981 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
982 const struct fw_img *image)
984 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
986 int first_ucode_section;
988 IWL_DEBUG_FW(trans, "working with %s CPU\n",
989 image->is_dual_cpus ? "Dual" : "Single");
991 /* load to FW the binary non secured sections of CPU1 */
992 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section);
996 if (image->is_dual_cpus) {
997 /* set CPU2 header address */
998 iwl_write_prph(trans,
999 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR,
1000 LMPM_SECURE_CPU2_HDR_MEM_SPACE);
1002 /* load to FW the binary sections of CPU2 */
1003 ret = iwl_pcie_load_cpu_sections(trans, image, 2,
1004 &first_ucode_section);
1009 /* supported for 7000 only for the moment */
1010 if (iwlwifi_mod_params.fw_monitor &&
1011 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1012 iwl_pcie_alloc_fw_monitor(trans, 0);
1014 if (trans_pcie->fw_mon_size) {
1015 iwl_write_prph(trans, MON_BUFF_BASE_ADDR,
1016 trans_pcie->fw_mon_phys >> 4);
1017 iwl_write_prph(trans, MON_BUFF_END_ADDR,
1018 (trans_pcie->fw_mon_phys +
1019 trans_pcie->fw_mon_size) >> 4);
1021 } else if (trans->dbg_dest_tlv) {
1022 iwl_pcie_apply_destination(trans);
1025 iwl_enable_interrupts(trans);
1027 /* release CPU reset */
1028 iwl_write32(trans, CSR_RESET, 0);
1033 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans,
1034 const struct fw_img *image)
1037 int first_ucode_section;
1039 IWL_DEBUG_FW(trans, "working with %s CPU\n",
1040 image->is_dual_cpus ? "Dual" : "Single");
1042 if (trans->dbg_dest_tlv)
1043 iwl_pcie_apply_destination(trans);
1045 /* TODO: remove in the next Si step */
1046 ret = iwl_pcie_rsa_race_bug_wa(trans);
1050 /* configure the ucode to be ready to get the secured image */
1051 /* release CPU reset */
1052 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT);
1054 /* load to FW the binary Secured sections of CPU1 */
1055 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1,
1056 &first_ucode_section);
1060 /* load to FW the binary sections of CPU2 */
1061 return iwl_pcie_load_cpu_sections_8000(trans, image, 2,
1062 &first_ucode_section);
1065 static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1067 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1068 bool hw_rfkill, was_hw_rfkill;
1070 lockdep_assert_held(&trans_pcie->mutex);
1072 if (trans_pcie->is_down)
1075 trans_pcie->is_down = true;
1077 was_hw_rfkill = iwl_is_rfkill_set(trans);
1079 /* tell the device to stop sending interrupts */
1080 iwl_disable_interrupts(trans);
1082 /* device going down, Stop using ICT table */
1083 iwl_pcie_disable_ict(trans);
1086 * If a HW restart happens during firmware loading,
1087 * then the firmware loading might call this function
1088 * and later it might be called again due to the
1089 * restart. So don't process again if the device is
1092 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) {
1093 IWL_DEBUG_INFO(trans,
1094 "DEVICE_ENABLED bit was set and is now cleared\n");
1095 iwl_pcie_tx_stop(trans);
1096 iwl_pcie_rx_stop(trans);
1098 /* Power-down device's busmaster DMA clocks */
1099 if (!trans->cfg->apmg_not_supported) {
1100 iwl_write_prph(trans, APMG_CLK_DIS_REG,
1101 APMG_CLK_VAL_DMA_CLK_RQT);
1106 /* Make sure (redundant) we've released our request to stay awake */
1107 iwl_clear_bit(trans, CSR_GP_CNTRL,
1108 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1110 /* Stop the device, and put it in low power state */
1111 iwl_pcie_apm_stop(trans, false);
1113 /* stop and reset the on-board processor */
1114 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1115 usleep_range(1000, 2000);
1118 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1119 * This is a bug in certain verions of the hardware.
1120 * Certain devices also keep sending HW RF kill interrupt all
1121 * the time, unless the interrupt is ACKed even if the interrupt
1122 * should be masked. Re-ACK all the interrupts here.
1124 iwl_disable_interrupts(trans);
1126 /* clear all status bits */
1127 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1128 clear_bit(STATUS_INT_ENABLED, &trans->status);
1129 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1130 clear_bit(STATUS_RFKILL, &trans->status);
1133 * Even if we stop the HW, we still want the RF kill
1136 iwl_enable_rfkill_int(trans);
1139 * Check again since the RF kill state may have changed while
1140 * all the interrupts were disabled, in this case we couldn't
1141 * receive the RF kill interrupt and update the state in the
1143 * Don't call the op_mode if the rkfill state hasn't changed.
1144 * This allows the op_mode to call stop_device from the rfkill
1145 * notification without endless recursion. Under very rare
1146 * circumstances, we might have a small recursion if the rfkill
1147 * state changed exactly now while we were called from stop_device.
1148 * This is very unlikely but can happen and is supported.
1150 hw_rfkill = iwl_is_rfkill_set(trans);
1152 set_bit(STATUS_RFKILL, &trans->status);
1154 clear_bit(STATUS_RFKILL, &trans->status);
1155 if (hw_rfkill != was_hw_rfkill)
1156 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1158 /* re-take ownership to prevent other users from stealing the device */
1159 iwl_pcie_prepare_card_hw(trans);
1162 static void iwl_pcie_synchronize_irqs(struct iwl_trans *trans)
1164 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1166 if (trans_pcie->msix_enabled) {
1169 for (i = 0; i < trans_pcie->alloc_vecs; i++)
1170 synchronize_irq(trans_pcie->msix_entries[i].vector);
1172 synchronize_irq(trans_pcie->pci_dev->irq);
1176 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
1177 const struct fw_img *fw, bool run_in_rfkill)
1179 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1183 /* This may fail if AMT took ownership of the device */
1184 if (iwl_pcie_prepare_card_hw(trans)) {
1185 IWL_WARN(trans, "Exit HW not ready\n");
1189 iwl_enable_rfkill_int(trans);
1191 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1194 * We enabled the RF-Kill interrupt and the handler may very
1195 * well be running. Disable the interrupts to make sure no other
1196 * interrupt can be fired.
1198 iwl_disable_interrupts(trans);
1200 /* Make sure it finished running */
1201 iwl_pcie_synchronize_irqs(trans);
1203 mutex_lock(&trans_pcie->mutex);
1205 /* If platform's RF_KILL switch is NOT set to KILL */
1206 hw_rfkill = iwl_is_rfkill_set(trans);
1208 set_bit(STATUS_RFKILL, &trans->status);
1210 clear_bit(STATUS_RFKILL, &trans->status);
1211 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1212 if (hw_rfkill && !run_in_rfkill) {
1217 /* Someone called stop_device, don't try to start_fw */
1218 if (trans_pcie->is_down) {
1220 "Can't start_fw since the HW hasn't been started\n");
1225 /* make sure rfkill handshake bits are cleared */
1226 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1227 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
1228 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
1230 /* clear (again), then enable host interrupts */
1231 iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
1233 ret = iwl_pcie_nic_init(trans);
1235 IWL_ERR(trans, "Unable to init nic\n");
1240 * Now, we load the firmware and don't want to be interrupted, even
1241 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1242 * FH_TX interrupt which is needed to load the firmware). If the
1243 * RF-Kill switch is toggled, we will find out after having loaded
1244 * the firmware and return the proper value to the caller.
1246 iwl_enable_fw_load_int(trans);
1248 /* really make sure rfkill handshake bits are cleared */
1249 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1250 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
1252 /* Load the given image to the HW */
1253 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1254 ret = iwl_pcie_load_given_ucode_8000(trans, fw);
1256 ret = iwl_pcie_load_given_ucode(trans, fw);
1258 /* re-check RF-Kill state since we may have missed the interrupt */
1259 hw_rfkill = iwl_is_rfkill_set(trans);
1261 set_bit(STATUS_RFKILL, &trans->status);
1263 clear_bit(STATUS_RFKILL, &trans->status);
1265 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1266 if (hw_rfkill && !run_in_rfkill)
1270 mutex_unlock(&trans_pcie->mutex);
1274 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
1276 iwl_pcie_reset_ict(trans);
1277 iwl_pcie_tx_start(trans, scd_addr);
1280 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool low_power)
1282 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1284 mutex_lock(&trans_pcie->mutex);
1285 _iwl_trans_pcie_stop_device(trans, low_power);
1286 mutex_unlock(&trans_pcie->mutex);
1289 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state)
1291 struct iwl_trans_pcie __maybe_unused *trans_pcie =
1292 IWL_TRANS_GET_PCIE_TRANS(trans);
1294 lockdep_assert_held(&trans_pcie->mutex);
1296 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state))
1297 _iwl_trans_pcie_stop_device(trans, true);
1300 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test,
1304 /* Enable persistence mode to avoid reset */
1305 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
1306 CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
1309 iwl_disable_interrupts(trans);
1312 * in testing mode, the host stays awake and the
1313 * hardware won't be reset (not even partially)
1318 iwl_pcie_disable_ict(trans);
1320 iwl_pcie_synchronize_irqs(trans);
1322 iwl_clear_bit(trans, CSR_GP_CNTRL,
1323 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1324 iwl_clear_bit(trans, CSR_GP_CNTRL,
1325 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1327 iwl_pcie_enable_rx_wake(trans, false);
1331 * reset TX queues -- some of their registers reset during S3
1332 * so if we don't reset everything here the D3 image would try
1333 * to execute some invalid memory upon resume
1335 iwl_trans_pcie_tx_reset(trans);
1338 iwl_pcie_set_pwr(trans, true);
1341 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
1342 enum iwl_d3_status *status,
1343 bool test, bool reset)
1349 iwl_enable_interrupts(trans);
1350 *status = IWL_D3_STATUS_ALIVE;
1354 iwl_pcie_enable_rx_wake(trans, true);
1357 * Also enables interrupts - none will happen as the device doesn't
1358 * know we're waking it up, only when the opmode actually tells it
1361 iwl_pcie_reset_ict(trans);
1362 iwl_enable_interrupts(trans);
1364 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1365 iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1367 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1370 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1371 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1372 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1375 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
1379 iwl_pcie_set_pwr(trans, false);
1382 iwl_clear_bit(trans, CSR_GP_CNTRL,
1383 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1385 iwl_trans_pcie_tx_reset(trans);
1387 ret = iwl_pcie_rx_init(trans);
1390 "Failed to resume the device (RX reset)\n");
1395 val = iwl_read32(trans, CSR_RESET);
1396 if (val & CSR_RESET_REG_FLAG_NEVO_RESET)
1397 *status = IWL_D3_STATUS_RESET;
1399 *status = IWL_D3_STATUS_ALIVE;
1404 struct iwl_causes_list {
1410 static struct iwl_causes_list causes_list[] = {
1411 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM, CSR_MSIX_FH_INT_MASK_AD, 0},
1412 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM, CSR_MSIX_FH_INT_MASK_AD, 0x1},
1413 {MSIX_FH_INT_CAUSES_S2D, CSR_MSIX_FH_INT_MASK_AD, 0x3},
1414 {MSIX_FH_INT_CAUSES_FH_ERR, CSR_MSIX_FH_INT_MASK_AD, 0x5},
1415 {MSIX_HW_INT_CAUSES_REG_ALIVE, CSR_MSIX_HW_INT_MASK_AD, 0x10},
1416 {MSIX_HW_INT_CAUSES_REG_WAKEUP, CSR_MSIX_HW_INT_MASK_AD, 0x11},
1417 {MSIX_HW_INT_CAUSES_REG_CT_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x16},
1418 {MSIX_HW_INT_CAUSES_REG_RF_KILL, CSR_MSIX_HW_INT_MASK_AD, 0x17},
1419 {MSIX_HW_INT_CAUSES_REG_PERIODIC, CSR_MSIX_HW_INT_MASK_AD, 0x18},
1420 {MSIX_HW_INT_CAUSES_REG_SW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x29},
1421 {MSIX_HW_INT_CAUSES_REG_SCD, CSR_MSIX_HW_INT_MASK_AD, 0x2A},
1422 {MSIX_HW_INT_CAUSES_REG_FH_TX, CSR_MSIX_HW_INT_MASK_AD, 0x2B},
1423 {MSIX_HW_INT_CAUSES_REG_HW_ERR, CSR_MSIX_HW_INT_MASK_AD, 0x2D},
1424 {MSIX_HW_INT_CAUSES_REG_HAP, CSR_MSIX_HW_INT_MASK_AD, 0x2E},
1427 static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans)
1429 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1430 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE;
1434 * Access all non RX causes and map them to the default irq.
1435 * In case we are missing at least one interrupt vector,
1436 * the first interrupt vector will serve non-RX and FBQ causes.
1438 for (i = 0; i < ARRAY_SIZE(causes_list); i++) {
1439 iwl_write8(trans, CSR_MSIX_IVAR(causes_list[i].addr), val);
1440 iwl_clear_bit(trans, causes_list[i].mask_reg,
1441 causes_list[i].cause_num);
1445 static void iwl_pcie_map_rx_causes(struct iwl_trans *trans)
1447 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1449 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0;
1453 * The first RX queue - fallback queue, which is designated for
1454 * management frame, command responses etc, is always mapped to the
1455 * first interrupt vector. The other RX queues are mapped to
1456 * the other (N - 2) interrupt vectors.
1458 val = BIT(MSIX_FH_INT_CAUSES_Q(0));
1459 for (idx = 1; idx < trans->num_rx_queues; idx++) {
1460 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx),
1461 MSIX_FH_INT_CAUSES_Q(idx - offset));
1462 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx));
1464 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val);
1466 val = MSIX_FH_INT_CAUSES_Q(0);
1467 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX)
1468 val |= MSIX_NON_AUTO_CLEAR_CAUSE;
1469 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val);
1471 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS)
1472 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val);
1475 static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie)
1477 struct iwl_trans *trans = trans_pcie->trans;
1479 if (!trans_pcie->msix_enabled) {
1480 if (trans->cfg->mq_rx_supported)
1481 iwl_write_prph(trans, UREG_CHICK,
1482 UREG_CHICK_MSI_ENABLE);
1486 iwl_write_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE);
1489 * Each cause from the causes list above and the RX causes is
1490 * represented as a byte in the IVAR table. The first nibble
1491 * represents the bound interrupt vector of the cause, the second
1492 * represents no auto clear for this cause. This will be set if its
1493 * interrupt vector is bound to serve other causes.
1495 iwl_pcie_map_rx_causes(trans);
1497 iwl_pcie_map_non_rx_causes(trans);
1499 trans_pcie->fh_init_mask =
1500 ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD);
1501 trans_pcie->fh_mask = trans_pcie->fh_init_mask;
1502 trans_pcie->hw_init_mask =
1503 ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD);
1504 trans_pcie->hw_mask = trans_pcie->hw_init_mask;
1507 static void iwl_pcie_set_interrupt_capa(struct pci_dev *pdev,
1508 struct iwl_trans *trans)
1510 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1511 int max_irqs, num_irqs, i, ret;
1514 if (!trans->cfg->mq_rx_supported)
1517 max_irqs = min_t(u32, num_online_cpus() + 2, IWL_MAX_RX_HW_QUEUES);
1518 for (i = 0; i < max_irqs; i++)
1519 trans_pcie->msix_entries[i].entry = i;
1521 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries,
1522 MSIX_MIN_INTERRUPT_VECTORS,
1525 IWL_DEBUG_INFO(trans,
1526 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1530 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0;
1532 IWL_DEBUG_INFO(trans,
1533 "MSI-X enabled. %d interrupt vectors were allocated\n",
1537 * In case the OS provides fewer interrupts than requested, different
1538 * causes will share the same interrupt vector as follows:
1539 * One interrupt less: non rx causes shared with FBQ.
1540 * Two interrupts less: non rx causes shared with FBQ and RSS.
1541 * More than two interrupts: we will use fewer RSS queues.
1543 if (num_irqs <= max_irqs - 2) {
1544 trans_pcie->trans->num_rx_queues = num_irqs + 1;
1545 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX |
1546 IWL_SHARED_IRQ_FIRST_RSS;
1547 } else if (num_irqs == max_irqs - 1) {
1548 trans_pcie->trans->num_rx_queues = num_irqs;
1549 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX;
1551 trans_pcie->trans->num_rx_queues = num_irqs - 1;
1553 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES);
1555 trans_pcie->alloc_vecs = num_irqs;
1556 trans_pcie->msix_enabled = true;
1560 ret = pci_enable_msi(pdev);
1562 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret);
1563 /* enable rfkill interrupt: hw bug w/a */
1564 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1565 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1566 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1567 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1572 static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans)
1574 int iter_rx_q, i, ret, cpu, offset;
1575 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1577 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1;
1578 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i;
1580 for (; i < iter_rx_q ; i++) {
1582 * Get the cpu prior to the place to search
1583 * (i.e. return will be > i - 1).
1585 cpu = cpumask_next(i - offset, cpu_online_mask);
1586 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]);
1587 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector,
1588 &trans_pcie->affinity_mask[i]);
1590 IWL_ERR(trans_pcie->trans,
1591 "Failed to set affinity mask for IRQ %d\n",
1596 static int iwl_pcie_init_msix_handler(struct pci_dev *pdev,
1597 struct iwl_trans_pcie *trans_pcie)
1601 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1603 struct msix_entry *msix_entry;
1605 msix_entry = &trans_pcie->msix_entries[i];
1606 ret = devm_request_threaded_irq(&pdev->dev,
1609 (i == trans_pcie->def_irq) ?
1610 iwl_pcie_irq_msix_handler :
1611 iwl_pcie_irq_rx_msix_handler,
1616 IWL_ERR(trans_pcie->trans,
1617 "Error allocating IRQ %d\n", i);
1622 iwl_pcie_irq_set_affinity(trans_pcie->trans);
1627 static int _iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1629 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1633 lockdep_assert_held(&trans_pcie->mutex);
1635 err = iwl_pcie_prepare_card_hw(trans);
1637 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
1641 /* Reset the entire device */
1642 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1643 usleep_range(1000, 2000);
1645 iwl_pcie_apm_init(trans);
1647 iwl_pcie_init_msix(trans_pcie);
1648 /* From now on, the op_mode will be kept updated about RF kill state */
1649 iwl_enable_rfkill_int(trans);
1651 /* Set is_down to false here so that...*/
1652 trans_pcie->is_down = false;
1654 hw_rfkill = iwl_is_rfkill_set(trans);
1656 set_bit(STATUS_RFKILL, &trans->status);
1658 clear_bit(STATUS_RFKILL, &trans->status);
1659 /* ... rfkill can call stop_device and set it false if needed */
1660 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1662 /* Make sure we sync here, because we'll need full access later */
1664 pm_runtime_resume(trans->dev);
1669 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans, bool low_power)
1671 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1674 mutex_lock(&trans_pcie->mutex);
1675 ret = _iwl_trans_pcie_start_hw(trans, low_power);
1676 mutex_unlock(&trans_pcie->mutex);
1681 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans)
1683 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1685 mutex_lock(&trans_pcie->mutex);
1687 /* disable interrupts - don't enable HW RF kill interrupt */
1688 iwl_disable_interrupts(trans);
1690 iwl_pcie_apm_stop(trans, true);
1692 iwl_disable_interrupts(trans);
1694 iwl_pcie_disable_ict(trans);
1696 mutex_unlock(&trans_pcie->mutex);
1698 iwl_pcie_synchronize_irqs(trans);
1701 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
1703 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1706 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
1708 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1711 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
1713 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
1716 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
1718 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
1719 ((reg & 0x000FFFFF) | (3 << 24)));
1720 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
1723 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
1726 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
1727 ((addr & 0x000FFFFF) | (3 << 24)));
1728 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
1731 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
1732 const struct iwl_trans_config *trans_cfg)
1734 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1736 trans_pcie->cmd_queue = trans_cfg->cmd_queue;
1737 trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
1738 trans_pcie->cmd_q_wdg_timeout = trans_cfg->cmd_q_wdg_timeout;
1739 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
1740 trans_pcie->n_no_reclaim_cmds = 0;
1742 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
1743 if (trans_pcie->n_no_reclaim_cmds)
1744 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
1745 trans_pcie->n_no_reclaim_cmds * sizeof(u8));
1747 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size;
1748 trans_pcie->rx_page_order =
1749 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size);
1751 trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
1752 trans_pcie->scd_set_active = trans_cfg->scd_set_active;
1753 trans_pcie->sw_csum_tx = trans_cfg->sw_csum_tx;
1755 trans_pcie->page_offs = trans_cfg->cb_data_offs;
1756 trans_pcie->dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *);
1758 trans->command_groups = trans_cfg->command_groups;
1759 trans->command_groups_size = trans_cfg->command_groups_size;
1761 /* Initialize NAPI here - it should be before registering to mac80211
1762 * in the opmode but after the HW struct is allocated.
1763 * As this function may be called again in some corner cases don't
1764 * do anything if NAPI was already initialized.
1766 if (trans_pcie->napi_dev.reg_state != NETREG_DUMMY)
1767 init_dummy_netdev(&trans_pcie->napi_dev);
1770 void iwl_trans_pcie_free(struct iwl_trans *trans)
1772 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1775 iwl_pcie_synchronize_irqs(trans);
1777 iwl_pcie_tx_free(trans);
1778 iwl_pcie_rx_free(trans);
1780 if (trans_pcie->msix_enabled) {
1781 for (i = 0; i < trans_pcie->alloc_vecs; i++) {
1782 irq_set_affinity_hint(
1783 trans_pcie->msix_entries[i].vector,
1787 trans_pcie->msix_enabled = false;
1789 iwl_pcie_free_ict(trans);
1792 iwl_pcie_free_fw_monitor(trans);
1794 for_each_possible_cpu(i) {
1795 struct iwl_tso_hdr_page *p =
1796 per_cpu_ptr(trans_pcie->tso_hdr_page, i);
1799 __free_page(p->page);
1802 free_percpu(trans_pcie->tso_hdr_page);
1803 mutex_destroy(&trans_pcie->mutex);
1804 iwl_trans_free(trans);
1807 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
1810 set_bit(STATUS_TPOWER_PMI, &trans->status);
1812 clear_bit(STATUS_TPOWER_PMI, &trans->status);
1815 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans,
1816 unsigned long *flags)
1819 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1821 spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
1823 if (trans_pcie->cmd_hold_nic_awake)
1826 /* this bit wakes up the NIC */
1827 __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
1828 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1829 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000)
1833 * These bits say the device is running, and should keep running for
1834 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1835 * but they do not indicate that embedded SRAM is restored yet;
1836 * 3945 and 4965 have volatile SRAM, and must save/restore contents
1837 * to/from host DRAM when sleeping/waking for power-saving.
1838 * Each direction takes approximately 1/4 millisecond; with this
1839 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1840 * series of register accesses are expected (e.g. reading Event Log),
1841 * to keep device from sleeping.
1843 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1844 * SRAM is okay/restored. We don't check that here because this call
1845 * is just for hardware register access; but GP1 MAC_SLEEP check is a
1846 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
1848 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1849 * and do not save/restore SRAM when power cycling.
1851 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
1852 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
1853 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
1854 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
1855 if (unlikely(ret < 0)) {
1856 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
1858 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1859 iwl_read32(trans, CSR_GP_CNTRL));
1860 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1866 * Fool sparse by faking we release the lock - sparse will
1867 * track nic_access anyway.
1869 __release(&trans_pcie->reg_lock);
1873 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
1874 unsigned long *flags)
1876 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1878 lockdep_assert_held(&trans_pcie->reg_lock);
1881 * Fool sparse by faking we acquiring the lock - sparse will
1882 * track nic_access anyway.
1884 __acquire(&trans_pcie->reg_lock);
1886 if (trans_pcie->cmd_hold_nic_awake)
1889 __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
1890 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1892 * Above we read the CSR_GP_CNTRL register, which will flush
1893 * any previous writes, but we need the write that clears the
1894 * MAC_ACCESS_REQ bit to be performed before any other writes
1895 * scheduled on different CPUs (after we drop reg_lock).
1899 spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
1902 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
1903 void *buf, int dwords)
1905 unsigned long flags;
1909 while (offs < dwords) {
1910 /* limit the time we spin here under lock to 1/2s */
1911 unsigned long end = jiffies + HZ / 2;
1912 bool resched = false;
1914 if (iwl_trans_grab_nic_access(trans, &flags)) {
1915 iwl_write32(trans, HBUS_TARG_MEM_RADDR,
1918 while (offs < dwords) {
1919 vals[offs] = iwl_read32(trans,
1920 HBUS_TARG_MEM_RDAT);
1923 if (time_after(jiffies, end)) {
1928 iwl_trans_release_nic_access(trans, &flags);
1940 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
1941 const void *buf, int dwords)
1943 unsigned long flags;
1945 const u32 *vals = buf;
1947 if (iwl_trans_grab_nic_access(trans, &flags)) {
1948 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
1949 for (offs = 0; offs < dwords; offs++)
1950 iwl_write32(trans, HBUS_TARG_MEM_WDAT,
1951 vals ? vals[offs] : 0);
1952 iwl_trans_release_nic_access(trans, &flags);
1959 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans *trans,
1963 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1966 for_each_set_bit(queue, &txqs, BITS_PER_LONG) {
1967 struct iwl_txq *txq = &trans_pcie->txq[queue];
1970 spin_lock_bh(&txq->lock);
1974 if (txq->frozen == freeze)
1977 IWL_DEBUG_TX_QUEUES(trans, "%s TXQ %d\n",
1978 freeze ? "Freezing" : "Waking", queue);
1980 txq->frozen = freeze;
1982 if (txq->read_ptr == txq->write_ptr)
1986 if (unlikely(time_after(now,
1987 txq->stuck_timer.expires))) {
1989 * The timer should have fired, maybe it is
1990 * spinning right now on the lock.
1994 /* remember how long until the timer fires */
1995 txq->frozen_expiry_remainder =
1996 txq->stuck_timer.expires - now;
1997 del_timer(&txq->stuck_timer);
2002 * Wake a non-empty queue -> arm timer with the
2003 * remainder before it froze
2005 mod_timer(&txq->stuck_timer,
2006 now + txq->frozen_expiry_remainder);
2009 spin_unlock_bh(&txq->lock);
2013 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans *trans, bool block)
2015 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2018 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
2019 struct iwl_txq *txq = &trans_pcie->txq[i];
2021 if (i == trans_pcie->cmd_queue)
2024 spin_lock_bh(&txq->lock);
2026 if (!block && !(WARN_ON_ONCE(!txq->block))) {
2029 iwl_write32(trans, HBUS_TARG_WRPTR,
2030 txq->write_ptr | (i << 8));
2036 spin_unlock_bh(&txq->lock);
2040 #define IWL_FLUSH_WAIT_MS 2000
2042 void iwl_trans_pcie_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq)
2044 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2049 IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
2050 txq->read_ptr, txq->write_ptr);
2052 if (trans->cfg->use_tfh)
2053 /* TODO: access new SCD registers and dump them */
2056 scd_sram_addr = trans_pcie->scd_base_addr +
2057 SCD_TX_STTS_QUEUE_OFFSET(txq->id);
2058 iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
2060 iwl_print_hex_error(trans, buf, sizeof(buf));
2062 for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
2063 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
2064 iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
2066 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2067 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
2068 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
2069 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
2071 iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
2072 SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
2075 tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
2077 tbl_dw = tbl_dw & 0x0000FFFF;
2080 "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
2081 cnt, active ? "" : "in", fifo, tbl_dw,
2082 iwl_read_prph(trans, SCD_QUEUE_RDPTR(cnt)) &
2083 (TFD_QUEUE_SIZE_MAX - 1),
2084 iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
2088 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, u32 txq_bm)
2090 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2091 struct iwl_txq *txq;
2093 unsigned long now = jiffies;
2096 /* waiting for all the tx frames complete might take a while */
2097 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2100 if (cnt == trans_pcie->cmd_queue)
2102 if (!test_bit(cnt, trans_pcie->queue_used))
2104 if (!(BIT(cnt) & txq_bm))
2107 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", cnt);
2108 txq = &trans_pcie->txq[cnt];
2109 wr_ptr = ACCESS_ONCE(txq->write_ptr);
2111 while (txq->read_ptr != ACCESS_ONCE(txq->write_ptr) &&
2112 !time_after(jiffies,
2113 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) {
2114 u8 write_ptr = ACCESS_ONCE(txq->write_ptr);
2116 if (WARN_ONCE(wr_ptr != write_ptr,
2117 "WR pointer moved while flushing %d -> %d\n",
2120 usleep_range(1000, 2000);
2123 if (txq->read_ptr != txq->write_ptr) {
2125 "fail to flush all tx fifo queues Q %d\n", cnt);
2129 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", cnt);
2133 iwl_trans_pcie_log_scd_error(trans, txq);
2138 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
2139 u32 mask, u32 value)
2141 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2142 unsigned long flags;
2144 spin_lock_irqsave(&trans_pcie->reg_lock, flags);
2145 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
2146 spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
2149 static void iwl_trans_pcie_ref(struct iwl_trans *trans)
2151 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2153 if (iwlwifi_mod_params.d0i3_disable)
2156 pm_runtime_get(&trans_pcie->pci_dev->dev);
2159 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2160 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2161 #endif /* CONFIG_PM */
2164 static void iwl_trans_pcie_unref(struct iwl_trans *trans)
2166 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2168 if (iwlwifi_mod_params.d0i3_disable)
2171 pm_runtime_mark_last_busy(&trans_pcie->pci_dev->dev);
2172 pm_runtime_put_autosuspend(&trans_pcie->pci_dev->dev);
2175 IWL_DEBUG_RPM(trans, "runtime usage count: %d\n",
2176 atomic_read(&trans_pcie->pci_dev->dev.power.usage_count));
2177 #endif /* CONFIG_PM */
2180 static const char *get_csr_string(int cmd)
2182 #define IWL_CMD(x) case x: return #x
2184 IWL_CMD(CSR_HW_IF_CONFIG_REG);
2185 IWL_CMD(CSR_INT_COALESCING);
2187 IWL_CMD(CSR_INT_MASK);
2188 IWL_CMD(CSR_FH_INT_STATUS);
2189 IWL_CMD(CSR_GPIO_IN);
2191 IWL_CMD(CSR_GP_CNTRL);
2192 IWL_CMD(CSR_HW_REV);
2193 IWL_CMD(CSR_EEPROM_REG);
2194 IWL_CMD(CSR_EEPROM_GP);
2195 IWL_CMD(CSR_OTP_GP_REG);
2196 IWL_CMD(CSR_GIO_REG);
2197 IWL_CMD(CSR_GP_UCODE_REG);
2198 IWL_CMD(CSR_GP_DRIVER_REG);
2199 IWL_CMD(CSR_UCODE_DRV_GP1);
2200 IWL_CMD(CSR_UCODE_DRV_GP2);
2201 IWL_CMD(CSR_LED_REG);
2202 IWL_CMD(CSR_DRAM_INT_TBL_REG);
2203 IWL_CMD(CSR_GIO_CHICKEN_BITS);
2204 IWL_CMD(CSR_ANA_PLL_CFG);
2205 IWL_CMD(CSR_HW_REV_WA_REG);
2206 IWL_CMD(CSR_MONITOR_STATUS_REG);
2207 IWL_CMD(CSR_DBG_HPET_MEM_REG);
2214 void iwl_pcie_dump_csr(struct iwl_trans *trans)
2217 static const u32 csr_tbl[] = {
2218 CSR_HW_IF_CONFIG_REG,
2236 CSR_DRAM_INT_TBL_REG,
2237 CSR_GIO_CHICKEN_BITS,
2239 CSR_MONITOR_STATUS_REG,
2241 CSR_DBG_HPET_MEM_REG
2243 IWL_ERR(trans, "CSR values:\n");
2244 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
2245 "CSR_INT_PERIODIC_REG)\n");
2246 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) {
2247 IWL_ERR(trans, " %25s: 0X%08x\n",
2248 get_csr_string(csr_tbl[i]),
2249 iwl_read32(trans, csr_tbl[i]));
2253 #ifdef CONFIG_IWLWIFI_DEBUGFS
2254 /* create and remove of files */
2255 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2256 if (!debugfs_create_file(#name, mode, parent, trans, \
2257 &iwl_dbgfs_##name##_ops)) \
2261 /* file operation */
2262 #define DEBUGFS_READ_FILE_OPS(name) \
2263 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2264 .read = iwl_dbgfs_##name##_read, \
2265 .open = simple_open, \
2266 .llseek = generic_file_llseek, \
2269 #define DEBUGFS_WRITE_FILE_OPS(name) \
2270 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2271 .write = iwl_dbgfs_##name##_write, \
2272 .open = simple_open, \
2273 .llseek = generic_file_llseek, \
2276 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2277 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2278 .write = iwl_dbgfs_##name##_write, \
2279 .read = iwl_dbgfs_##name##_read, \
2280 .open = simple_open, \
2281 .llseek = generic_file_llseek, \
2284 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
2285 char __user *user_buf,
2286 size_t count, loff_t *ppos)
2288 struct iwl_trans *trans = file->private_data;
2289 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2290 struct iwl_txq *txq;
2297 bufsz = sizeof(char) * 75 * trans->cfg->base_params->num_of_queues;
2299 if (!trans_pcie->txq)
2302 buf = kzalloc(bufsz, GFP_KERNEL);
2306 for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
2307 txq = &trans_pcie->txq[cnt];
2308 pos += scnprintf(buf + pos, bufsz - pos,
2309 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2310 cnt, txq->read_ptr, txq->write_ptr,
2311 !!test_bit(cnt, trans_pcie->queue_used),
2312 !!test_bit(cnt, trans_pcie->queue_stopped),
2313 txq->need_update, txq->frozen,
2314 (cnt == trans_pcie->cmd_queue ? " HCMD" : ""));
2316 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2321 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
2322 char __user *user_buf,
2323 size_t count, loff_t *ppos)
2325 struct iwl_trans *trans = file->private_data;
2326 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2328 int pos = 0, i, ret;
2329 size_t bufsz = sizeof(buf);
2331 bufsz = sizeof(char) * 121 * trans->num_rx_queues;
2333 if (!trans_pcie->rxq)
2336 buf = kzalloc(bufsz, GFP_KERNEL);
2340 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) {
2341 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
2343 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n",
2345 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n",
2347 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n",
2349 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n",
2351 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n",
2353 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n",
2356 pos += scnprintf(buf + pos, bufsz - pos,
2357 "\tclosed_rb_num: %u\n",
2358 le16_to_cpu(rxq->rb_stts->closed_rb_num) &
2361 pos += scnprintf(buf + pos, bufsz - pos,
2362 "\tclosed_rb_num: Not Allocated\n");
2365 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2371 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
2372 char __user *user_buf,
2373 size_t count, loff_t *ppos)
2375 struct iwl_trans *trans = file->private_data;
2376 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2377 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2381 int bufsz = 24 * 64; /* 24 items * 64 char per item */
2384 buf = kzalloc(bufsz, GFP_KERNEL);
2388 pos += scnprintf(buf + pos, bufsz - pos,
2389 "Interrupt Statistics Report:\n");
2391 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
2393 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
2395 if (isr_stats->sw || isr_stats->hw) {
2396 pos += scnprintf(buf + pos, bufsz - pos,
2397 "\tLast Restarting Code: 0x%X\n",
2398 isr_stats->err_code);
2400 #ifdef CONFIG_IWLWIFI_DEBUG
2401 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
2403 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
2406 pos += scnprintf(buf + pos, bufsz - pos,
2407 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
2409 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
2412 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
2415 pos += scnprintf(buf + pos, bufsz - pos,
2416 "Rx command responses:\t\t %u\n", isr_stats->rx);
2418 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
2421 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
2422 isr_stats->unhandled);
2424 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
2429 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
2430 const char __user *user_buf,
2431 size_t count, loff_t *ppos)
2433 struct iwl_trans *trans = file->private_data;
2434 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2435 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2441 memset(buf, 0, sizeof(buf));
2442 buf_size = min(count, sizeof(buf) - 1);
2443 if (copy_from_user(buf, user_buf, buf_size))
2445 if (sscanf(buf, "%x", &reset_flag) != 1)
2447 if (reset_flag == 0)
2448 memset(isr_stats, 0, sizeof(*isr_stats));
2453 static ssize_t iwl_dbgfs_csr_write(struct file *file,
2454 const char __user *user_buf,
2455 size_t count, loff_t *ppos)
2457 struct iwl_trans *trans = file->private_data;
2462 memset(buf, 0, sizeof(buf));
2463 buf_size = min(count, sizeof(buf) - 1);
2464 if (copy_from_user(buf, user_buf, buf_size))
2466 if (sscanf(buf, "%d", &csr) != 1)
2469 iwl_pcie_dump_csr(trans);
2474 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
2475 char __user *user_buf,
2476 size_t count, loff_t *ppos)
2478 struct iwl_trans *trans = file->private_data;
2482 ret = iwl_dump_fh(trans, &buf);
2487 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret);
2492 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
2493 DEBUGFS_READ_FILE_OPS(fh_reg);
2494 DEBUGFS_READ_FILE_OPS(rx_queue);
2495 DEBUGFS_READ_FILE_OPS(tx_queue);
2496 DEBUGFS_WRITE_FILE_OPS(csr);
2498 /* Create the debugfs files and directories */
2499 int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans)
2501 struct dentry *dir = trans->dbgfs_dir;
2503 DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
2504 DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
2505 DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
2506 DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
2507 DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
2511 IWL_ERR(trans, "failed to create the trans debugfs entry\n");
2514 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2516 static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd)
2518 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2522 for (i = 0; i < trans_pcie->max_tbs; i++)
2523 cmdlen += iwl_pcie_tfd_tb_get_len(trans, tfd, i);
2528 static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans,
2529 struct iwl_fw_error_dump_data **data,
2530 int allocated_rb_nums)
2532 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2533 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
2534 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2535 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2536 u32 i, r, j, rb_len = 0;
2538 spin_lock(&rxq->lock);
2540 r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
2542 for (i = rxq->read, j = 0;
2543 i != r && j < allocated_rb_nums;
2544 i = (i + 1) & RX_QUEUE_MASK, j++) {
2545 struct iwl_rx_mem_buffer *rxb = rxq->queue[i];
2546 struct iwl_fw_error_dump_rb *rb;
2548 dma_unmap_page(trans->dev, rxb->page_dma, max_len,
2551 rb_len += sizeof(**data) + sizeof(*rb) + max_len;
2553 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB);
2554 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len);
2555 rb = (void *)(*data)->data;
2556 rb->index = cpu_to_le32(i);
2557 memcpy(rb->data, page_address(rxb->page), max_len);
2558 /* remap the page for the free benefit */
2559 rxb->page_dma = dma_map_page(trans->dev, rxb->page, 0,
2563 *data = iwl_fw_error_next_data(*data);
2566 spin_unlock(&rxq->lock);
2570 #define IWL_CSR_TO_DUMP (0x250)
2572 static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans,
2573 struct iwl_fw_error_dump_data **data)
2575 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP;
2579 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR);
2580 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP);
2581 val = (void *)(*data)->data;
2583 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4)
2584 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2586 *data = iwl_fw_error_next_data(*data);
2591 static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans,
2592 struct iwl_fw_error_dump_data **data)
2594 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND;
2595 unsigned long flags;
2599 if (!iwl_trans_grab_nic_access(trans, &flags))
2602 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS);
2603 (*data)->len = cpu_to_le32(fh_regs_len);
2604 val = (void *)(*data)->data;
2606 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; i += sizeof(u32))
2607 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i));
2609 iwl_trans_release_nic_access(trans, &flags);
2611 *data = iwl_fw_error_next_data(*data);
2613 return sizeof(**data) + fh_regs_len;
2617 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans,
2618 struct iwl_fw_error_dump_fw_mon *fw_mon_data,
2621 u32 buf_size_in_dwords = (monitor_len >> 2);
2622 u32 *buffer = (u32 *)fw_mon_data->data;
2623 unsigned long flags;
2626 if (!iwl_trans_grab_nic_access(trans, &flags))
2629 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1);
2630 for (i = 0; i < buf_size_in_dwords; i++)
2631 buffer[i] = iwl_read_prph_no_grab(trans,
2632 MON_DMARB_RD_DATA_ADDR);
2633 iwl_write_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0);
2635 iwl_trans_release_nic_access(trans, &flags);
2641 iwl_trans_pcie_dump_monitor(struct iwl_trans *trans,
2642 struct iwl_fw_error_dump_data **data,
2645 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2648 if ((trans_pcie->fw_mon_page &&
2649 trans->cfg->device_family == IWL_DEVICE_FAMILY_7000) ||
2650 trans->dbg_dest_tlv) {
2651 struct iwl_fw_error_dump_fw_mon *fw_mon_data;
2652 u32 base, write_ptr, wrap_cnt;
2654 /* If there was a dest TLV - use the values from there */
2655 if (trans->dbg_dest_tlv) {
2657 le32_to_cpu(trans->dbg_dest_tlv->write_ptr_reg);
2658 wrap_cnt = le32_to_cpu(trans->dbg_dest_tlv->wrap_count);
2659 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2661 base = MON_BUFF_BASE_ADDR;
2662 write_ptr = MON_BUFF_WRPTR;
2663 wrap_cnt = MON_BUFF_CYCLE_CNT;
2666 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR);
2667 fw_mon_data = (void *)(*data)->data;
2668 fw_mon_data->fw_mon_wr_ptr =
2669 cpu_to_le32(iwl_read_prph(trans, write_ptr));
2670 fw_mon_data->fw_mon_cycle_cnt =
2671 cpu_to_le32(iwl_read_prph(trans, wrap_cnt));
2672 fw_mon_data->fw_mon_base_ptr =
2673 cpu_to_le32(iwl_read_prph(trans, base));
2675 len += sizeof(**data) + sizeof(*fw_mon_data);
2676 if (trans_pcie->fw_mon_page) {
2678 * The firmware is now asserted, it won't write anything
2679 * to the buffer. CPU can take ownership to fetch the
2680 * data. The buffer will be handed back to the device
2681 * before the firmware will be restarted.
2683 dma_sync_single_for_cpu(trans->dev,
2684 trans_pcie->fw_mon_phys,
2685 trans_pcie->fw_mon_size,
2687 memcpy(fw_mon_data->data,
2688 page_address(trans_pcie->fw_mon_page),
2689 trans_pcie->fw_mon_size);
2691 monitor_len = trans_pcie->fw_mon_size;
2692 } else if (trans->dbg_dest_tlv->monitor_mode == SMEM_MODE) {
2694 * Update pointers to reflect actual values after
2697 base = iwl_read_prph(trans, base) <<
2698 trans->dbg_dest_tlv->base_shift;
2699 iwl_trans_read_mem(trans, base, fw_mon_data->data,
2700 monitor_len / sizeof(u32));
2701 } else if (trans->dbg_dest_tlv->monitor_mode == MARBH_MODE) {
2703 iwl_trans_pci_dump_marbh_monitor(trans,
2707 /* Didn't match anything - output no monitor data */
2712 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data));
2718 static struct iwl_trans_dump_data
2719 *iwl_trans_pcie_dump_data(struct iwl_trans *trans,
2720 const struct iwl_fw_dbg_trigger_tlv *trigger)
2722 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2723 struct iwl_fw_error_dump_data *data;
2724 struct iwl_txq *cmdq = &trans_pcie->txq[trans_pcie->cmd_queue];
2725 struct iwl_fw_error_dump_txcmd *txcmd;
2726 struct iwl_trans_dump_data *dump_data;
2730 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) &&
2731 !trans->cfg->mq_rx_supported;
2733 /* transport dump header */
2734 len = sizeof(*dump_data);
2737 len += sizeof(*data) +
2738 cmdq->n_window * (sizeof(*txcmd) + TFD_MAX_PAYLOAD_SIZE);
2741 if (trans_pcie->fw_mon_page) {
2742 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2743 trans_pcie->fw_mon_size;
2744 monitor_len = trans_pcie->fw_mon_size;
2745 } else if (trans->dbg_dest_tlv) {
2748 base = le32_to_cpu(trans->dbg_dest_tlv->base_reg);
2749 end = le32_to_cpu(trans->dbg_dest_tlv->end_reg);
2751 base = iwl_read_prph(trans, base) <<
2752 trans->dbg_dest_tlv->base_shift;
2753 end = iwl_read_prph(trans, end) <<
2754 trans->dbg_dest_tlv->end_shift;
2756 /* Make "end" point to the actual end */
2757 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 ||
2758 trans->dbg_dest_tlv->monitor_mode == MARBH_MODE)
2759 end += (1 << trans->dbg_dest_tlv->end_shift);
2760 monitor_len = end - base;
2761 len += sizeof(*data) + sizeof(struct iwl_fw_error_dump_fw_mon) +
2767 if (trigger && (trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY)) {
2768 dump_data = vzalloc(len);
2772 data = (void *)dump_data->data;
2773 len = iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2774 dump_data->len = len;
2780 len += sizeof(*data) + IWL_CSR_TO_DUMP;
2783 len += sizeof(*data) + (FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND);
2786 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2787 struct iwl_rxq *rxq = &trans_pcie->rxq[0];
2789 num_rbs = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num))
2791 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK;
2792 len += num_rbs * (sizeof(*data) +
2793 sizeof(struct iwl_fw_error_dump_rb) +
2794 (PAGE_SIZE << trans_pcie->rx_page_order));
2797 dump_data = vzalloc(len);
2802 data = (void *)dump_data->data;
2803 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD);
2804 txcmd = (void *)data->data;
2805 spin_lock_bh(&cmdq->lock);
2806 ptr = cmdq->write_ptr;
2807 for (i = 0; i < cmdq->n_window; i++) {
2808 u8 idx = get_cmd_index(cmdq, ptr);
2811 cmdlen = iwl_trans_pcie_get_cmdlen(trans, cmdq->tfds +
2812 trans_pcie->tfd_size * ptr);
2813 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen);
2816 len += sizeof(*txcmd) + caplen;
2817 txcmd->cmdlen = cpu_to_le32(cmdlen);
2818 txcmd->caplen = cpu_to_le32(caplen);
2819 memcpy(txcmd->data, cmdq->entries[idx].cmd, caplen);
2820 txcmd = (void *)((u8 *)txcmd->data + caplen);
2823 ptr = iwl_queue_dec_wrap(ptr);
2825 spin_unlock_bh(&cmdq->lock);
2827 data->len = cpu_to_le32(len);
2828 len += sizeof(*data);
2829 data = iwl_fw_error_next_data(data);
2831 len += iwl_trans_pcie_dump_csr(trans, &data);
2832 len += iwl_trans_pcie_fh_regs_dump(trans, &data);
2834 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs);
2836 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len);
2838 dump_data->len = len;
2843 #ifdef CONFIG_PM_SLEEP
2844 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
2846 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2847 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2848 return iwl_pci_fw_enter_d0i3(trans);
2853 static void iwl_trans_pcie_resume(struct iwl_trans *trans)
2855 if (trans->runtime_pm_mode == IWL_PLAT_PM_MODE_D0I3 &&
2856 (trans->system_pm_mode == IWL_PLAT_PM_MODE_D0I3))
2857 iwl_pci_fw_exit_d0i3(trans);
2859 #endif /* CONFIG_PM_SLEEP */
2861 static const struct iwl_trans_ops trans_ops_pcie = {
2862 .start_hw = iwl_trans_pcie_start_hw,
2863 .op_mode_leave = iwl_trans_pcie_op_mode_leave,
2864 .fw_alive = iwl_trans_pcie_fw_alive,
2865 .start_fw = iwl_trans_pcie_start_fw,
2866 .stop_device = iwl_trans_pcie_stop_device,
2868 .d3_suspend = iwl_trans_pcie_d3_suspend,
2869 .d3_resume = iwl_trans_pcie_d3_resume,
2871 #ifdef CONFIG_PM_SLEEP
2872 .suspend = iwl_trans_pcie_suspend,
2873 .resume = iwl_trans_pcie_resume,
2874 #endif /* CONFIG_PM_SLEEP */
2876 .send_cmd = iwl_trans_pcie_send_hcmd,
2878 .tx = iwl_trans_pcie_tx,
2879 .reclaim = iwl_trans_pcie_reclaim,
2881 .txq_disable = iwl_trans_pcie_txq_disable,
2882 .txq_enable = iwl_trans_pcie_txq_enable,
2884 .get_txq_byte_table = iwl_trans_pcie_get_txq_byte_table,
2886 .txq_set_shared_mode = iwl_trans_pcie_txq_set_shared_mode,
2888 .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
2889 .freeze_txq_timer = iwl_trans_pcie_freeze_txq_timer,
2890 .block_txq_ptrs = iwl_trans_pcie_block_txq_ptrs,
2892 .write8 = iwl_trans_pcie_write8,
2893 .write32 = iwl_trans_pcie_write32,
2894 .read32 = iwl_trans_pcie_read32,
2895 .read_prph = iwl_trans_pcie_read_prph,
2896 .write_prph = iwl_trans_pcie_write_prph,
2897 .read_mem = iwl_trans_pcie_read_mem,
2898 .write_mem = iwl_trans_pcie_write_mem,
2899 .configure = iwl_trans_pcie_configure,
2900 .set_pmi = iwl_trans_pcie_set_pmi,
2901 .grab_nic_access = iwl_trans_pcie_grab_nic_access,
2902 .release_nic_access = iwl_trans_pcie_release_nic_access,
2903 .set_bits_mask = iwl_trans_pcie_set_bits_mask,
2905 .ref = iwl_trans_pcie_ref,
2906 .unref = iwl_trans_pcie_unref,
2908 .dump_data = iwl_trans_pcie_dump_data,
2911 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
2912 const struct pci_device_id *ent,
2913 const struct iwl_cfg *cfg)
2915 struct iwl_trans_pcie *trans_pcie;
2916 struct iwl_trans *trans;
2919 ret = pcim_enable_device(pdev);
2921 return ERR_PTR(ret);
2923 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie),
2924 &pdev->dev, cfg, &trans_ops_pcie, 0);
2926 return ERR_PTR(-ENOMEM);
2928 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2930 trans_pcie->trans = trans;
2931 spin_lock_init(&trans_pcie->irq_lock);
2932 spin_lock_init(&trans_pcie->reg_lock);
2933 mutex_init(&trans_pcie->mutex);
2934 init_waitqueue_head(&trans_pcie->ucode_write_waitq);
2935 trans_pcie->tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page);
2936 if (!trans_pcie->tso_hdr_page) {
2942 if (!cfg->base_params->pcie_l1_allowed) {
2944 * W/A - seems to solve weird behavior. We need to remove this
2945 * if we don't want to stay in L1 all the time. This wastes a
2948 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S |
2949 PCIE_LINK_STATE_L1 |
2950 PCIE_LINK_STATE_CLKPM);
2955 trans_pcie->max_tbs = IWL_TFH_NUM_TBS;
2956 trans_pcie->tfd_size = sizeof(struct iwl_tfh_tfd);
2959 trans_pcie->max_tbs = IWL_NUM_OF_TBS;
2960 trans_pcie->tfd_size = sizeof(struct iwl_tfd);
2962 trans->max_skb_frags = IWL_PCIE_MAX_FRAGS(trans_pcie);
2964 pci_set_master(pdev);
2966 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(addr_size));
2968 ret = pci_set_consistent_dma_mask(pdev,
2969 DMA_BIT_MASK(addr_size));
2971 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2973 ret = pci_set_consistent_dma_mask(pdev,
2975 /* both attempts failed: */
2977 dev_err(&pdev->dev, "No suitable DMA available\n");
2982 ret = pcim_iomap_regions_request_all(pdev, BIT(0), DRV_NAME);
2984 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n");
2988 trans_pcie->hw_base = pcim_iomap_table(pdev)[0];
2989 if (!trans_pcie->hw_base) {
2990 dev_err(&pdev->dev, "pcim_iomap_table failed\n");
2995 /* We disable the RETRY_TIMEOUT register (0x41) to keep
2996 * PCI Tx retries from interfering with C3 CPU state */
2997 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
2999 trans->dev = &pdev->dev;
3000 trans_pcie->pci_dev = pdev;
3001 iwl_disable_interrupts(trans);
3003 trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
3005 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3006 * changed, and now the revision step also includes bit 0-1 (no more
3007 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3008 * in the old format.
3010 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000) {
3011 unsigned long flags;
3013 trans->hw_rev = (trans->hw_rev & 0xfff0) |
3014 (CSR_HW_REV_STEP(trans->hw_rev << 2) << 2);
3016 ret = iwl_pcie_prepare_card_hw(trans);
3018 IWL_WARN(trans, "Exit HW not ready\n");
3023 * in-order to recognize C step driver should read chip version
3024 * id located at the AUX bus MISC address space.
3026 iwl_set_bit(trans, CSR_GP_CNTRL,
3027 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
3030 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
3031 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3032 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
3035 IWL_DEBUG_INFO(trans, "Failed to wake up the nic\n");
3039 if (iwl_trans_grab_nic_access(trans, &flags)) {
3042 hw_step = iwl_read_prph_no_grab(trans, WFPM_CTRL_REG);
3043 hw_step |= ENABLE_WFPM;
3044 iwl_write_prph_no_grab(trans, WFPM_CTRL_REG, hw_step);
3045 hw_step = iwl_read_prph_no_grab(trans, AUX_MISC_REG);
3046 hw_step = (hw_step >> HW_STEP_LOCATION_BITS) & 0xF;
3048 trans->hw_rev = (trans->hw_rev & 0xFFFFFFF3) |
3049 (SILICON_C_STEP << 2);
3050 iwl_trans_release_nic_access(trans, &flags);
3054 trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
3056 iwl_pcie_set_interrupt_capa(pdev, trans);
3057 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
3058 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
3059 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
3061 /* Initialize the wait queue for commands */
3062 init_waitqueue_head(&trans_pcie->wait_command_queue);
3064 init_waitqueue_head(&trans_pcie->d0i3_waitq);
3066 if (trans_pcie->msix_enabled) {
3067 if (iwl_pcie_init_msix_handler(pdev, trans_pcie))
3070 ret = iwl_pcie_alloc_ict(trans);
3074 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq,
3076 iwl_pcie_irq_handler,
3077 IRQF_SHARED, DRV_NAME, trans);
3079 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
3082 trans_pcie->inta_mask = CSR_INI_SET_MASK;
3085 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3086 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_D0I3;
3088 trans->runtime_pm_mode = IWL_PLAT_PM_MODE_DISABLED;
3089 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3094 iwl_pcie_free_ict(trans);
3096 free_percpu(trans_pcie->tso_hdr_page);
3097 iwl_trans_free(trans);
3098 return ERR_PTR(ret);