1 /******************************************************************************
3 * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
4 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
5 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
6 * Copyright(c) 2018 Intel Corporation
8 * Portions of this file are derived from the ipw3945 project, as well
9 * as portions of the ieee80211 subsystem header files.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of version 2 of the GNU General Public License as
13 * published by the Free Software Foundation.
15 * This program is distributed in the hope that it will be useful, but WITHOUT
16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * You should have received a copy of the GNU General Public License along with
23 * The full GNU General Public License is included in this distribution in the
24 * file called LICENSE.
26 * Contact Information:
27 * Intel Linux Wireless <linuxwifi@intel.com>
28 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
30 *****************************************************************************/
31 #include <linux/sched.h>
32 #include <linux/wait.h>
33 #include <linux/gfp.h>
38 #include "iwl-op-mode.h"
39 #include "iwl-context-info-gen3.h"
41 /******************************************************************************
45 ******************************************************************************/
48 * Rx theory of operation
50 * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
51 * each of which point to Receive Buffers to be filled by the NIC. These get
52 * used not only for Rx frames, but for any command response or notification
53 * from the NIC. The driver and NIC manage the Rx buffers by means
54 * of indexes into the circular buffer.
57 * The host/firmware share two index registers for managing the Rx buffers.
59 * The READ index maps to the first position that the firmware may be writing
60 * to -- the driver can read up to (but not including) this position and get
62 * The READ index is managed by the firmware once the card is enabled.
64 * The WRITE index maps to the last position the driver has read from -- the
65 * position preceding WRITE is the last slot the firmware can place a packet.
67 * The queue is empty (no good data) if WRITE = READ - 1, and is full if
70 * During initialization, the host sets up the READ queue position to the first
71 * INDEX position, and WRITE to the last (READ - 1 wrapped)
73 * When the firmware places a packet in a buffer, it will advance the READ index
74 * and fire the RX interrupt. The driver can then query the READ index and
75 * process as many packets as possible, moving the WRITE index forward as it
76 * resets the Rx queue buffers with new memory.
78 * The management in the driver is as follows:
79 * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
80 * When the interrupt handler is called, the request is processed.
81 * The page is either stolen - transferred to the upper layer
82 * or reused - added immediately to the iwl->rxq->rx_free list.
83 * + When the page is stolen - the driver updates the matching queue's used
84 * count, detaches the RBD and transfers it to the queue used list.
85 * When there are two used RBDs - they are transferred to the allocator empty
86 * list. Work is then scheduled for the allocator to start allocating
88 * When there are another 6 used RBDs - they are transferred to the allocator
89 * empty list and the driver tries to claim the pre-allocated buffers and
90 * add them to iwl->rxq->rx_free. If it fails - it continues to claim them
92 * When there are 8+ buffers in the free list - either from allocation or from
93 * 8 reused unstolen pages - restock is called to update the FW and indexes.
94 * + In order to make sure the allocator always has RBDs to use for allocation
95 * the allocator has initial pool in the size of num_queues*(8-2) - the
96 * maximum missing RBDs per allocation request (request posted with 2
97 * empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
98 * The queues supplies the recycle of the rest of the RBDs.
99 * + A received packet is processed and handed to the kernel network stack,
100 * detached from the iwl->rxq. The driver 'processed' index is updated.
101 * + If there are no allocated buffers in iwl->rxq->rx_free,
102 * the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
103 * If there were enough free buffers and RX_STALLED is set it is cleared.
108 * iwl_rxq_alloc() Allocates rx_free
109 * iwl_pcie_rx_replenish() Replenishes rx_free list from rx_used, and calls
110 * iwl_pcie_rxq_restock.
111 * Used only during initialization.
112 * iwl_pcie_rxq_restock() Moves available buffers from rx_free into Rx
113 * queue, updates firmware pointers, and updates
115 * iwl_pcie_rx_allocator() Background work for allocating pages.
117 * -- enable interrupts --
118 * ISR - iwl_rx() Detach iwl_rx_mem_buffers from pool up to the
119 * READ INDEX, detaching the SKB from the pool.
120 * Moves the packet buffer from queue to rx_used.
121 * Posts and claims requests to the allocator.
122 * Calls iwl_pcie_rxq_restock to refill any empty
128 * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
130 * Regular Receive interrupt:
132 * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
133 * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
135 * rxq.queue -> rxq.rx_free -> rxq.queue
141 * iwl_rxq_space - Return number of free slots available in queue.
143 static int iwl_rxq_space(const struct iwl_rxq *rxq)
145 /* Make sure rx queue size is a power of 2 */
146 WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
149 * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
150 * between empty and completely full queues.
151 * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
152 * defined for negative dividends.
154 return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
158 * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
160 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
162 return cpu_to_le32((u32)(dma_addr >> 8));
166 * iwl_pcie_rx_stop - stops the Rx DMA
168 int iwl_pcie_rx_stop(struct iwl_trans *trans)
170 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
171 /* TODO: remove this for 22560 once fw does it */
172 iwl_write_prph(trans, RFH_RXF_DMA_CFG_GEN3, 0);
173 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS_GEN3,
174 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
175 } else if (trans->cfg->mq_rx_supported) {
176 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
177 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
178 RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
180 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
181 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
182 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
188 * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
190 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
195 lockdep_assert_held(&rxq->lock);
198 * explicitly wake up the NIC if:
199 * 1. shadow registers aren't enabled
200 * 2. there is a chance that the NIC is asleep
202 if (!trans->cfg->base_params->shadow_reg_enable &&
203 test_bit(STATUS_TPOWER_PMI, &trans->status)) {
204 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
206 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
207 IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
209 iwl_set_bit(trans, CSR_GP_CNTRL,
210 BIT(trans->cfg->csr->flag_mac_access_req));
211 rxq->need_update = true;
216 rxq->write_actual = round_down(rxq->write, 8);
217 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
218 iwl_write32(trans, HBUS_TARG_WRPTR,
220 ((FIRST_RX_QUEUE + rxq->id) << 16)));
221 else if (trans->cfg->mq_rx_supported)
222 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
225 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
228 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
230 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
233 for (i = 0; i < trans->num_rx_queues; i++) {
234 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
236 if (!rxq->need_update)
238 spin_lock(&rxq->lock);
239 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
240 rxq->need_update = false;
241 spin_unlock(&rxq->lock);
245 static void iwl_pcie_restock_bd(struct iwl_trans *trans,
247 struct iwl_rx_mem_buffer *rxb)
249 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) {
250 struct iwl_rx_transfer_desc *bd = rxq->bd;
252 bd[rxq->write].type_n_size =
253 cpu_to_le32((IWL_RX_TD_TYPE & IWL_RX_TD_TYPE_MSK) |
254 ((IWL_RX_TD_SIZE_2K >> 8) & IWL_RX_TD_SIZE_MSK));
255 bd[rxq->write].addr = cpu_to_le64(rxb->page_dma);
256 bd[rxq->write].rbid = cpu_to_le16(rxb->vid);
258 __le64 *bd = rxq->bd;
260 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
265 * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
267 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
270 struct iwl_rx_mem_buffer *rxb;
273 * If the device isn't enabled - no need to try to add buffers...
274 * This can happen when we stop the device and still have an interrupt
275 * pending. We stop the APM before we sync the interrupts because we
276 * have to (see comment there). On the other hand, since the APM is
277 * stopped, we cannot access the HW (in particular not prph).
278 * So don't try to restock if the APM has been already stopped.
280 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
283 spin_lock(&rxq->lock);
284 while (rxq->free_count) {
285 /* Get next free Rx buffer, remove from free list */
286 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
288 list_del(&rxb->list);
289 rxb->invalid = false;
290 /* 12 first bits are expected to be empty */
291 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
292 /* Point to Rx buffer via next RBD in circular buffer */
293 iwl_pcie_restock_bd(trans, rxq, rxb);
294 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
297 spin_unlock(&rxq->lock);
300 * If we've added more space for the firmware to place data, tell it.
301 * Increment device's write pointer in multiples of 8.
303 if (rxq->write_actual != (rxq->write & ~0x7)) {
304 spin_lock(&rxq->lock);
305 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
306 spin_unlock(&rxq->lock);
311 * iwl_pcie_rxsq_restock - restock implementation for single queue rx
313 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
316 struct iwl_rx_mem_buffer *rxb;
319 * If the device isn't enabled - not need to try to add buffers...
320 * This can happen when we stop the device and still have an interrupt
321 * pending. We stop the APM before we sync the interrupts because we
322 * have to (see comment there). On the other hand, since the APM is
323 * stopped, we cannot access the HW (in particular not prph).
324 * So don't try to restock if the APM has been already stopped.
326 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
329 spin_lock(&rxq->lock);
330 while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
331 __le32 *bd = (__le32 *)rxq->bd;
332 /* The overwritten rxb must be a used one */
333 rxb = rxq->queue[rxq->write];
334 BUG_ON(rxb && rxb->page);
336 /* Get next free Rx buffer, remove from free list */
337 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
339 list_del(&rxb->list);
340 rxb->invalid = false;
342 /* Point to Rx buffer via next RBD in circular buffer */
343 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
344 rxq->queue[rxq->write] = rxb;
345 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
348 spin_unlock(&rxq->lock);
350 /* If we've added more space for the firmware to place data, tell it.
351 * Increment device's write pointer in multiples of 8. */
352 if (rxq->write_actual != (rxq->write & ~0x7)) {
353 spin_lock(&rxq->lock);
354 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
355 spin_unlock(&rxq->lock);
360 * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
362 * If there are slots in the RX queue that need to be restocked,
363 * and we have free pre-allocated buffers, fill the ranks as much
364 * as we can, pulling from rx_free.
366 * This moves the 'write' index forward to catch up with 'processed', and
367 * also updates the memory address in the firmware to reference the new
371 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
373 if (trans->cfg->mq_rx_supported)
374 iwl_pcie_rxmq_restock(trans, rxq);
376 iwl_pcie_rxsq_restock(trans, rxq);
380 * iwl_pcie_rx_alloc_page - allocates and returns a page.
383 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
386 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
388 gfp_t gfp_mask = priority;
390 if (trans_pcie->rx_page_order > 0)
391 gfp_mask |= __GFP_COMP;
393 /* Alloc a new receive buffer */
394 page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
397 IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
398 trans_pcie->rx_page_order);
400 * Issue an error if we don't have enough pre-allocated
403 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
405 "Failed to alloc_pages\n");
412 * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
414 * A used RBD is an Rx buffer that has been given to the stack. To use it again
415 * a page must be allocated and the RBD must point to the page. This function
416 * doesn't change the HW pointer but handles the list of pages that is used by
417 * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
420 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
423 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
424 struct iwl_rx_mem_buffer *rxb;
428 spin_lock(&rxq->lock);
429 if (list_empty(&rxq->rx_used)) {
430 spin_unlock(&rxq->lock);
433 spin_unlock(&rxq->lock);
435 /* Alloc a new receive buffer */
436 page = iwl_pcie_rx_alloc_page(trans, priority);
440 spin_lock(&rxq->lock);
442 if (list_empty(&rxq->rx_used)) {
443 spin_unlock(&rxq->lock);
444 __free_pages(page, trans_pcie->rx_page_order);
447 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
449 list_del(&rxb->list);
450 spin_unlock(&rxq->lock);
454 /* Get physical address of the RB */
456 dma_map_page(trans->dev, page, 0,
457 PAGE_SIZE << trans_pcie->rx_page_order,
459 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
461 spin_lock(&rxq->lock);
462 list_add(&rxb->list, &rxq->rx_used);
463 spin_unlock(&rxq->lock);
464 __free_pages(page, trans_pcie->rx_page_order);
468 spin_lock(&rxq->lock);
470 list_add_tail(&rxb->list, &rxq->rx_free);
473 spin_unlock(&rxq->lock);
477 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
479 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
482 for (i = 0; i < RX_POOL_SIZE; i++) {
483 if (!trans_pcie->rx_pool[i].page)
485 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
486 PAGE_SIZE << trans_pcie->rx_page_order,
488 __free_pages(trans_pcie->rx_pool[i].page,
489 trans_pcie->rx_page_order);
490 trans_pcie->rx_pool[i].page = NULL;
495 * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
497 * Allocates for each received request 8 pages
498 * Called as a scheduled work item.
500 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
502 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
503 struct iwl_rb_allocator *rba = &trans_pcie->rba;
504 struct list_head local_empty;
505 int pending = atomic_read(&rba->req_pending);
507 IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
509 /* If we were scheduled - there is at least one request */
510 spin_lock(&rba->lock);
511 /* swap out the rba->rbd_empty to a local list */
512 list_replace_init(&rba->rbd_empty, &local_empty);
513 spin_unlock(&rba->lock);
517 LIST_HEAD(local_allocated);
518 gfp_t gfp_mask = GFP_KERNEL;
520 /* Do not post a warning if there are only a few requests */
521 if (pending < RX_PENDING_WATERMARK)
522 gfp_mask |= __GFP_NOWARN;
524 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
525 struct iwl_rx_mem_buffer *rxb;
528 /* List should never be empty - each reused RBD is
529 * returned to the list, and initial pool covers any
530 * possible gap between the time the page is allocated
531 * to the time the RBD is added.
533 BUG_ON(list_empty(&local_empty));
534 /* Get the first rxb from the rbd list */
535 rxb = list_first_entry(&local_empty,
536 struct iwl_rx_mem_buffer, list);
539 /* Alloc a new receive buffer */
540 page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
545 /* Get physical address of the RB */
546 rxb->page_dma = dma_map_page(trans->dev, page, 0,
547 PAGE_SIZE << trans_pcie->rx_page_order,
549 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
551 __free_pages(page, trans_pcie->rx_page_order);
555 /* move the allocated entry to the out list */
556 list_move(&rxb->list, &local_allocated);
560 atomic_dec(&rba->req_pending);
564 pending = atomic_read(&rba->req_pending);
566 "Got more pending allocation requests = %d\n",
570 spin_lock(&rba->lock);
571 /* add the allocated rbds to the allocator allocated list */
572 list_splice_tail(&local_allocated, &rba->rbd_allocated);
573 /* get more empty RBDs for current pending requests */
574 list_splice_tail_init(&rba->rbd_empty, &local_empty);
575 spin_unlock(&rba->lock);
577 atomic_inc(&rba->req_ready);
581 spin_lock(&rba->lock);
582 /* return unused rbds to the allocator empty list */
583 list_splice_tail(&local_empty, &rba->rbd_empty);
584 spin_unlock(&rba->lock);
586 IWL_DEBUG_RX(trans, "%s, exit.\n", __func__);
590 * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
592 .* Called by queue when the queue posted allocation request and
593 * has freed 8 RBDs in order to restock itself.
594 * This function directly moves the allocated RBs to the queue's ownership
595 * and updates the relevant counters.
597 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
600 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
601 struct iwl_rb_allocator *rba = &trans_pcie->rba;
604 lockdep_assert_held(&rxq->lock);
607 * atomic_dec_if_positive returns req_ready - 1 for any scenario.
608 * If req_ready is 0 atomic_dec_if_positive will return -1 and this
609 * function will return early, as there are no ready requests.
610 * atomic_dec_if_positive will perofrm the *actual* decrement only if
611 * req_ready > 0, i.e. - there are ready requests and the function
612 * hands one request to the caller.
614 if (atomic_dec_if_positive(&rba->req_ready) < 0)
617 spin_lock(&rba->lock);
618 for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
619 /* Get next free Rx buffer, remove it from free list */
620 struct iwl_rx_mem_buffer *rxb =
621 list_first_entry(&rba->rbd_allocated,
622 struct iwl_rx_mem_buffer, list);
624 list_move(&rxb->list, &rxq->rx_free);
626 spin_unlock(&rba->lock);
628 rxq->used_count -= RX_CLAIM_REQ_ALLOC;
629 rxq->free_count += RX_CLAIM_REQ_ALLOC;
632 void iwl_pcie_rx_allocator_work(struct work_struct *data)
634 struct iwl_rb_allocator *rba_p =
635 container_of(data, struct iwl_rb_allocator, rx_alloc);
636 struct iwl_trans_pcie *trans_pcie =
637 container_of(rba_p, struct iwl_trans_pcie, rba);
639 iwl_pcie_rx_allocator(trans_pcie->trans);
642 static int iwl_pcie_free_bd_size(struct iwl_trans *trans, bool use_rx_td)
644 struct iwl_rx_transfer_desc *rx_td;
647 return sizeof(*rx_td);
649 return trans->cfg->mq_rx_supported ? sizeof(__le64) :
653 static void iwl_pcie_free_rxq_dma(struct iwl_trans *trans,
656 struct device *dev = trans->dev;
657 bool use_rx_td = (trans->cfg->device_family >=
658 IWL_DEVICE_FAMILY_22560);
659 int free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
662 dma_free_coherent(trans->dev,
663 free_size * rxq->queue_size,
664 rxq->bd, rxq->bd_dma);
669 dma_free_coherent(trans->dev,
670 use_rx_td ? sizeof(__le16) :
671 sizeof(struct iwl_rb_status),
672 rxq->rb_stts, rxq->rb_stts_dma);
673 rxq->rb_stts_dma = 0;
677 dma_free_coherent(trans->dev,
678 (use_rx_td ? sizeof(*rxq->cd) :
679 sizeof(__le32)) * rxq->queue_size,
680 rxq->used_bd, rxq->used_bd_dma);
681 rxq->used_bd_dma = 0;
684 if (trans->cfg->device_family < IWL_DEVICE_FAMILY_22560)
688 dma_free_coherent(dev, sizeof(__le16),
689 rxq->tr_tail, rxq->tr_tail_dma);
690 rxq->tr_tail_dma = 0;
694 dma_free_coherent(dev, sizeof(__le16),
695 rxq->cr_tail, rxq->cr_tail_dma);
696 rxq->cr_tail_dma = 0;
700 static int iwl_pcie_alloc_rxq_dma(struct iwl_trans *trans,
703 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
704 struct device *dev = trans->dev;
707 bool use_rx_td = (trans->cfg->device_family >=
708 IWL_DEVICE_FAMILY_22560);
710 spin_lock_init(&rxq->lock);
711 if (trans->cfg->mq_rx_supported)
712 rxq->queue_size = MQ_RX_TABLE_SIZE;
714 rxq->queue_size = RX_QUEUE_SIZE;
716 free_size = iwl_pcie_free_bd_size(trans, use_rx_td);
719 * Allocate the circular buffer of Read Buffer Descriptors
722 rxq->bd = dma_zalloc_coherent(dev,
723 free_size * rxq->queue_size,
724 &rxq->bd_dma, GFP_KERNEL);
728 if (trans->cfg->mq_rx_supported) {
729 rxq->used_bd = dma_zalloc_coherent(dev,
740 /* Allocate the driver's pointer to receive buffer status */
741 rxq->rb_stts = dma_zalloc_coherent(dev, use_rx_td ?
743 sizeof(struct iwl_rb_status),
752 /* Allocate the driver's pointer to TR tail */
753 rxq->tr_tail = dma_zalloc_coherent(dev, sizeof(__le16),
759 /* Allocate the driver's pointer to CR tail */
760 rxq->cr_tail = dma_zalloc_coherent(dev, sizeof(__le16),
766 * W/A 22560 device step Z0 must be non zero bug
767 * TODO: remove this when stop supporting Z0
769 *rxq->cr_tail = cpu_to_le16(500);
774 for (i = 0; i < trans->num_rx_queues; i++) {
775 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
777 iwl_pcie_free_rxq_dma(trans, rxq);
779 kfree(trans_pcie->rxq);
784 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
786 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
787 struct iwl_rb_allocator *rba = &trans_pcie->rba;
790 if (WARN_ON(trans_pcie->rxq))
793 trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
795 if (!trans_pcie->rxq)
798 spin_lock_init(&rba->lock);
800 for (i = 0; i < trans->num_rx_queues; i++) {
801 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
803 ret = iwl_pcie_alloc_rxq_dma(trans, rxq);
810 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
815 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
817 switch (trans_pcie->rx_buf_size) {
819 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
822 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
825 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
829 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
832 if (!iwl_trans_grab_nic_access(trans, &flags))
836 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
837 /* reset and flush pointers */
838 iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
839 iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
840 iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
842 /* Reset driver's Rx queue write index */
843 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
845 /* Tell device where to find RBD circular buffer in DRAM */
846 iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
847 (u32)(rxq->bd_dma >> 8));
849 /* Tell device where in DRAM to update its Rx status */
850 iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
851 rxq->rb_stts_dma >> 4);
854 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
855 * the credit mechanism in 5000 HW RX FIFO
856 * Direct rx interrupts to hosts
857 * Rx buffer size 4 or 8k or 12k
861 iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
862 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
863 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
864 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
866 (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
867 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
869 iwl_trans_release_nic_access(trans, &flags);
871 /* Set interrupt coalescing timer to default (2048 usecs) */
872 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
874 /* W/A for interrupt coalescing bug in 7260 and 3160 */
875 if (trans->cfg->host_interrupt_operation_mode)
876 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
879 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable)
881 if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000)
884 if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP)
887 if (!trans->cfg->integrated)
891 * Turn on the chicken-bits that cause MAC wakeup for RX-related
893 * This costs some power, but needed for W/A 9000 integrated A-step
894 * bug where shadow registers are not in the retention list and their
895 * value is lost when NIC powers down
897 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
898 CSR_MAC_SHADOW_REG_CTRL_RX_WAKE);
899 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2,
900 CSR_MAC_SHADOW_REG_CTL2_RX_WAKE);
903 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
905 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
906 u32 rb_size, enabled = 0;
910 switch (trans_pcie->rx_buf_size) {
912 rb_size = RFH_RXF_DMA_RB_SIZE_2K;
915 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
918 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
921 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
925 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
928 if (!iwl_trans_grab_nic_access(trans, &flags))
932 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
933 /* disable free amd used rx queue operation */
934 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
936 for (i = 0; i < trans->num_rx_queues; i++) {
937 /* Tell device where to find RBD free table in DRAM */
938 iwl_write_prph64_no_grab(trans,
939 RFH_Q_FRBDCB_BA_LSB(i),
940 trans_pcie->rxq[i].bd_dma);
941 /* Tell device where to find RBD used table in DRAM */
942 iwl_write_prph64_no_grab(trans,
943 RFH_Q_URBDCB_BA_LSB(i),
944 trans_pcie->rxq[i].used_bd_dma);
945 /* Tell device where in DRAM to update its Rx status */
946 iwl_write_prph64_no_grab(trans,
947 RFH_Q_URBD_STTS_WPTR_LSB(i),
948 trans_pcie->rxq[i].rb_stts_dma);
949 /* Reset device indice tables */
950 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
951 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
952 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
954 enabled |= BIT(i) | BIT(i + 16);
959 * Rx buffer size 4 or 8k or 12k
961 * Drop frames that exceed RB size
964 iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
965 RFH_DMA_EN_ENABLE_VAL | rb_size |
966 RFH_RXF_DMA_MIN_RB_4_8 |
967 RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
968 RFH_RXF_DMA_RBDCB_SIZE_512);
971 * Activate DMA snooping.
972 * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
975 iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
976 RFH_GEN_CFG_RFH_DMA_SNOOP |
977 RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
978 RFH_GEN_CFG_SERVICE_DMA_SNOOP |
979 RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
980 trans->cfg->integrated ?
981 RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
982 RFH_GEN_CFG_RB_CHUNK_SIZE_128));
983 /* Enable the relevant rx queues */
984 iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
986 iwl_trans_release_nic_access(trans, &flags);
988 /* Set interrupt coalescing timer to default (2048 usecs) */
989 iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
991 iwl_pcie_enable_rx_wake(trans, true);
994 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
996 lockdep_assert_held(&rxq->lock);
998 INIT_LIST_HEAD(&rxq->rx_free);
999 INIT_LIST_HEAD(&rxq->rx_used);
1000 rxq->free_count = 0;
1001 rxq->used_count = 0;
1004 int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
1010 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
1012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1013 struct iwl_rxq *def_rxq;
1014 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1015 int i, err, queue_size, allocator_pool_size, num_alloc;
1017 if (!trans_pcie->rxq) {
1018 err = iwl_pcie_rx_alloc(trans);
1022 def_rxq = trans_pcie->rxq;
1024 cancel_work_sync(&rba->rx_alloc);
1026 spin_lock(&rba->lock);
1027 atomic_set(&rba->req_pending, 0);
1028 atomic_set(&rba->req_ready, 0);
1029 INIT_LIST_HEAD(&rba->rbd_allocated);
1030 INIT_LIST_HEAD(&rba->rbd_empty);
1031 spin_unlock(&rba->lock);
1033 /* free all first - we might be reconfigured for a different size */
1034 iwl_pcie_free_rbs_pool(trans);
1036 for (i = 0; i < RX_QUEUE_SIZE; i++)
1037 def_rxq->queue[i] = NULL;
1039 for (i = 0; i < trans->num_rx_queues; i++) {
1040 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1044 spin_lock(&rxq->lock);
1046 * Set read write pointer to reflect that we have processed
1047 * and used all buffers, but have not restocked the Rx queue
1048 * with fresh buffers
1052 rxq->write_actual = 0;
1053 memset(rxq->rb_stts, 0,
1054 (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560) ?
1055 sizeof(__le16) : sizeof(struct iwl_rb_status));
1057 iwl_pcie_rx_init_rxb_lists(rxq);
1059 if (!rxq->napi.poll)
1060 netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
1061 iwl_pcie_dummy_napi_poll, 64);
1063 spin_unlock(&rxq->lock);
1066 /* move the pool to the default queue and allocator ownerships */
1067 queue_size = trans->cfg->mq_rx_supported ?
1068 MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
1069 allocator_pool_size = trans->num_rx_queues *
1070 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
1071 num_alloc = queue_size + allocator_pool_size;
1072 BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
1073 ARRAY_SIZE(trans_pcie->rx_pool));
1074 for (i = 0; i < num_alloc; i++) {
1075 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
1077 if (i < allocator_pool_size)
1078 list_add(&rxb->list, &rba->rbd_empty);
1080 list_add(&rxb->list, &def_rxq->rx_used);
1081 trans_pcie->global_table[i] = rxb;
1082 rxb->vid = (u16)(i + 1);
1083 rxb->invalid = true;
1086 iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
1091 int iwl_pcie_rx_init(struct iwl_trans *trans)
1093 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1094 int ret = _iwl_pcie_rx_init(trans);
1099 if (trans->cfg->mq_rx_supported)
1100 iwl_pcie_rx_mq_hw_init(trans);
1102 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
1104 iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
1106 spin_lock(&trans_pcie->rxq->lock);
1107 iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
1108 spin_unlock(&trans_pcie->rxq->lock);
1113 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
1116 * We don't configure the RFH.
1117 * Restock will be done at alive, after firmware configured the RFH.
1119 return _iwl_pcie_rx_init(trans);
1122 void iwl_pcie_rx_free(struct iwl_trans *trans)
1124 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1125 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1129 * if rxq is NULL, it means that nothing has been allocated,
1132 if (!trans_pcie->rxq) {
1133 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1137 cancel_work_sync(&rba->rx_alloc);
1139 iwl_pcie_free_rbs_pool(trans);
1141 for (i = 0; i < trans->num_rx_queues; i++) {
1142 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1144 iwl_pcie_free_rxq_dma(trans, rxq);
1147 netif_napi_del(&rxq->napi);
1149 kfree(trans_pcie->rxq);
1152 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1153 struct iwl_rb_allocator *rba)
1155 spin_lock(&rba->lock);
1156 list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1157 spin_unlock(&rba->lock);
1161 * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1163 * Called when a RBD can be reused. The RBD is transferred to the allocator.
1164 * When there are 2 empty RBDs - a request for allocation is posted
1166 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1167 struct iwl_rx_mem_buffer *rxb,
1168 struct iwl_rxq *rxq, bool emergency)
1170 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1171 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1173 /* Move the RBD to the used list, will be moved to allocator in batches
1174 * before claiming or posting a request*/
1175 list_add_tail(&rxb->list, &rxq->rx_used);
1177 if (unlikely(emergency))
1180 /* Count the allocator owned RBDs */
1183 /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1184 * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1185 * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1186 * after but we still need to post another request.
1188 if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1189 /* Move the 2 RBDs to the allocator ownership.
1190 Allocator has another 6 from pool for the request completion*/
1191 iwl_pcie_rx_move_to_allocator(rxq, rba);
1193 atomic_inc(&rba->req_pending);
1194 queue_work(rba->alloc_wq, &rba->rx_alloc);
1198 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1199 struct iwl_rxq *rxq,
1200 struct iwl_rx_mem_buffer *rxb,
1204 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1205 struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1206 bool page_stolen = false;
1207 int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1213 dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1215 while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1216 struct iwl_rx_packet *pkt;
1219 int index, cmd_index, len;
1220 struct iwl_rx_cmd_buffer rxcb = {
1222 ._rx_page_order = trans_pcie->rx_page_order,
1224 ._page_stolen = false,
1225 .truesize = max_len,
1228 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1229 rxcb.status = rxq->cd[i].status;
1231 pkt = rxb_addr(&rxcb);
1233 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1235 "Q %d: RB end marker at offset %d\n",
1240 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1241 FH_RSCSR_RXQ_POS != rxq->id,
1242 "frame on invalid queue - is on %d and indicates %d\n",
1244 (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1248 "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1250 iwl_get_cmd_string(trans,
1251 iwl_cmd_id(pkt->hdr.cmd,
1254 pkt->hdr.group_id, pkt->hdr.cmd,
1255 le16_to_cpu(pkt->hdr.sequence));
1257 len = iwl_rx_packet_len(pkt);
1258 len += sizeof(u32); /* account for status word */
1259 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1260 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1262 /* Reclaim a command buffer only if this packet is a response
1263 * to a (driver-originated) command.
1264 * If the packet (e.g. Rx frame) originated from uCode,
1265 * there is no command buffer to reclaim.
1266 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1267 * but apparently a few don't get set; catch them here. */
1268 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1269 if (reclaim && !pkt->hdr.group_id) {
1272 for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1273 if (trans_pcie->no_reclaim_cmds[i] ==
1281 sequence = le16_to_cpu(pkt->hdr.sequence);
1282 index = SEQ_TO_INDEX(sequence);
1283 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1286 iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1289 iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1293 kzfree(txq->entries[cmd_index].free_buf);
1294 txq->entries[cmd_index].free_buf = NULL;
1298 * After here, we should always check rxcb._page_stolen,
1299 * if it is true then one of the handlers took the page.
1303 /* Invoke any callbacks, transfer the buffer to caller,
1304 * and fire off the (possibly) blocking
1305 * iwl_trans_send_cmd()
1306 * as we reclaim the driver command queue */
1307 if (!rxcb._page_stolen)
1308 iwl_pcie_hcmd_complete(trans, &rxcb);
1310 IWL_WARN(trans, "Claim null rxb?\n");
1313 page_stolen |= rxcb._page_stolen;
1314 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1316 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1319 /* page was stolen from us -- free our reference */
1321 __free_pages(rxb->page, trans_pcie->rx_page_order);
1325 /* Reuse the page if possible. For notification packets and
1326 * SKBs that fail to Rx correctly, add them back into the
1327 * rx_free list for reuse later. */
1328 if (rxb->page != NULL) {
1330 dma_map_page(trans->dev, rxb->page, 0,
1331 PAGE_SIZE << trans_pcie->rx_page_order,
1333 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1335 * free the page(s) as well to not break
1336 * the invariant that the items on the used
1337 * list have no page(s)
1339 __free_pages(rxb->page, trans_pcie->rx_page_order);
1341 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1343 list_add_tail(&rxb->list, &rxq->rx_free);
1347 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1350 static struct iwl_rx_mem_buffer *iwl_pcie_get_rxb(struct iwl_trans *trans,
1351 struct iwl_rxq *rxq, int i)
1353 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1354 struct iwl_rx_mem_buffer *rxb;
1357 if (!trans->cfg->mq_rx_supported) {
1358 rxb = rxq->queue[i];
1359 rxq->queue[i] = NULL;
1363 /* used_bd is a 32/16 bit but only 12 are used to retrieve the vid */
1364 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1365 vid = le16_to_cpu(rxq->cd[i].rbid) & 0x0FFF;
1367 vid = le32_to_cpu(rxq->bd_32[i]) & 0x0FFF;
1369 if (!vid || vid > ARRAY_SIZE(trans_pcie->global_table))
1372 rxb = trans_pcie->global_table[vid - 1];
1376 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1377 rxb->size = le32_to_cpu(rxq->cd[i].size) & IWL_RX_CD_SIZE;
1379 rxb->invalid = true;
1384 WARN(1, "Invalid rxb from HW %u\n", (u32)vid);
1385 iwl_force_nmi(trans);
1390 * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1392 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1394 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1395 struct iwl_rxq *rxq;
1396 u32 r, i, count = 0;
1397 bool emergency = false;
1399 if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1402 rxq = &trans_pcie->rxq[queue];
1405 spin_lock(&rxq->lock);
1406 /* uCode's read index (stored in shared DRAM) indicates the last Rx
1407 * buffer that the driver may process (last buffer filled by ucode). */
1408 r = le16_to_cpu(iwl_get_closed_rb_stts(trans, rxq)) & 0x0FFF;
1411 /* W/A 9000 device step A0 wrap-around bug */
1412 r &= (rxq->queue_size - 1);
1414 /* Rx interrupt, but nothing sent from uCode */
1416 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1419 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1420 struct iwl_rx_mem_buffer *rxb;
1421 /* number of RBDs still waiting for page allocation */
1422 u32 rb_pending_alloc =
1423 atomic_read(&trans_pcie->rba.req_pending) *
1426 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1428 iwl_pcie_rx_move_to_allocator(rxq, rba);
1432 rxb = iwl_pcie_get_rxb(trans, rxq, i);
1436 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1437 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency, i);
1439 i = (i + 1) & (rxq->queue_size - 1);
1442 * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1443 * try to claim the pre-allocated buffers from the allocator.
1444 * If not ready - will try to reclaim next time.
1445 * There is no need to reschedule work - allocator exits only
1448 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1449 iwl_pcie_rx_allocator_get(trans, rxq);
1451 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1452 /* Add the remaining empty RBDs for allocator use */
1453 iwl_pcie_rx_move_to_allocator(rxq, rba);
1454 } else if (emergency) {
1458 if (rb_pending_alloc < rxq->queue_size / 3)
1462 spin_unlock(&rxq->lock);
1463 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1464 iwl_pcie_rxq_restock(trans, rxq);
1470 /* Backtrack one entry */
1472 /* update cr tail with the rxq read pointer */
1473 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560)
1474 *rxq->cr_tail = cpu_to_le16(r);
1475 spin_unlock(&rxq->lock);
1478 * handle a case where in emergency there are some unallocated RBDs.
1479 * those RBDs are in the used list, but are not tracked by the queue's
1480 * used_count which counts allocator owned RBDs.
1481 * unallocated emergency RBDs must be allocated on exit, otherwise
1482 * when called again the function may not be in emergency mode and
1483 * they will be handed to the allocator with no tracking in the RBD
1484 * allocator counters, which will lead to them never being claimed back
1486 * by allocating them here, they are now in the queue free list, and
1487 * will be restocked by the next call of iwl_pcie_rxq_restock.
1489 if (unlikely(emergency && count))
1490 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1493 napi_gro_flush(&rxq->napi, false);
1495 iwl_pcie_rxq_restock(trans, rxq);
1498 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1500 u8 queue = entry->entry;
1501 struct msix_entry *entries = entry - queue;
1503 return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1507 * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1508 * This interrupt handler should be used with RSS queue only.
1510 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1512 struct msix_entry *entry = dev_id;
1513 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1514 struct iwl_trans *trans = trans_pcie->trans;
1516 trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1518 if (WARN_ON(entry->entry >= trans->num_rx_queues))
1521 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1524 iwl_pcie_rx_handle(trans, entry->entry);
1527 iwl_pcie_clear_irq(trans, entry);
1529 lock_map_release(&trans->sync_cmd_lockdep_map);
1535 * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1537 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1539 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1542 /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1543 if (trans->cfg->internal_wimax_coex &&
1544 !trans->cfg->apmg_not_supported &&
1545 (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1546 APMS_CLK_VAL_MRB_FUNC_MODE) ||
1547 (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1548 APMG_PS_CTRL_VAL_RESET_REQ))) {
1549 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1550 iwl_op_mode_wimax_active(trans->op_mode);
1551 wake_up(&trans_pcie->wait_command_queue);
1555 for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1556 if (!trans_pcie->txq[i])
1558 del_timer(&trans_pcie->txq[i]->stuck_timer);
1561 /* The STATUS_FW_ERROR bit is set in this function. This must happen
1562 * before we wake up the command caller, to ensure a proper cleanup. */
1563 iwl_trans_fw_error(trans);
1565 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1566 wake_up(&trans_pcie->wait_command_queue);
1569 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1573 lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1575 trace_iwlwifi_dev_irq(trans->dev);
1577 /* Discover which interrupts are active/pending */
1578 inta = iwl_read32(trans, CSR_INT);
1580 /* the thread will service interrupts and re-enable them */
1584 /* a device (PCI-E) page is 4096 bytes long */
1585 #define ICT_SHIFT 12
1586 #define ICT_SIZE (1 << ICT_SHIFT)
1587 #define ICT_COUNT (ICT_SIZE / sizeof(u32))
1589 /* interrupt handler using ict table, with this interrupt driver will
1590 * stop using INTA register to get device's interrupt, reading this register
1591 * is expensive, device will write interrupts in ICT dram table, increment
1592 * index then will fire interrupt to driver, driver will OR all ICT table
1593 * entries from current index up to table entry with 0 value. the result is
1594 * the interrupt we need to service, driver will set the entries back to 0 and
1597 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1604 trace_iwlwifi_dev_irq(trans->dev);
1606 /* Ignore interrupt if there's nothing in NIC to service.
1607 * This may be due to IRQ shared with another device,
1608 * or due to sporadic interrupts thrown from our NIC. */
1609 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1610 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1615 * Collect all entries up to the first 0, starting from ict_index;
1616 * note we already read at ict_index.
1620 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1621 trans_pcie->ict_index, read);
1622 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1623 trans_pcie->ict_index =
1624 ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1626 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1627 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1631 /* We should not get this value, just ignore it. */
1632 if (val == 0xffffffff)
1636 * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1637 * (bit 15 before shifting it to 31) to clear when using interrupt
1638 * coalescing. fortunately, bits 18 and 19 stay set when this happens
1639 * so we use them to decide on the real state of the Rx bit.
1640 * In order words, bit 15 is set if bit 18 or bit 19 are set.
1645 inta = (0xff & val) | ((0xff00 & val) << 16);
1649 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1651 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1652 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1653 bool hw_rfkill, prev, report;
1655 mutex_lock(&trans_pcie->mutex);
1656 prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1657 hw_rfkill = iwl_is_rfkill_set(trans);
1659 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1660 set_bit(STATUS_RFKILL_HW, &trans->status);
1662 if (trans_pcie->opmode_down)
1665 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1667 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1668 hw_rfkill ? "disable radio" : "enable radio");
1670 isr_stats->rfkill++;
1673 iwl_trans_pcie_rf_kill(trans, report);
1674 mutex_unlock(&trans_pcie->mutex);
1677 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1679 IWL_DEBUG_RF_KILL(trans,
1680 "Rfkill while SYNC HCMD in flight\n");
1681 wake_up(&trans_pcie->wait_command_queue);
1683 clear_bit(STATUS_RFKILL_HW, &trans->status);
1684 if (trans_pcie->opmode_down)
1685 clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1689 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1691 struct iwl_trans *trans = dev_id;
1692 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1693 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1697 lock_map_acquire(&trans->sync_cmd_lockdep_map);
1699 spin_lock(&trans_pcie->irq_lock);
1701 /* dram interrupt table not set yet,
1702 * use legacy interrupt.
1704 if (likely(trans_pcie->use_ict))
1705 inta = iwl_pcie_int_cause_ict(trans);
1707 inta = iwl_pcie_int_cause_non_ict(trans);
1709 if (iwl_have_debug_level(IWL_DL_ISR)) {
1710 IWL_DEBUG_ISR(trans,
1711 "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1712 inta, trans_pcie->inta_mask,
1713 iwl_read32(trans, CSR_INT_MASK),
1714 iwl_read32(trans, CSR_FH_INT_STATUS));
1715 if (inta & (~trans_pcie->inta_mask))
1716 IWL_DEBUG_ISR(trans,
1717 "We got a masked interrupt (0x%08x)\n",
1718 inta & (~trans_pcie->inta_mask));
1721 inta &= trans_pcie->inta_mask;
1724 * Ignore interrupt if there's nothing in NIC to service.
1725 * This may be due to IRQ shared with another device,
1726 * or due to sporadic interrupts thrown from our NIC.
1728 if (unlikely(!inta)) {
1729 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1731 * Re-enable interrupts here since we don't
1732 * have anything to service
1734 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1735 _iwl_enable_interrupts(trans);
1736 spin_unlock(&trans_pcie->irq_lock);
1737 lock_map_release(&trans->sync_cmd_lockdep_map);
1741 if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1743 * Hardware disappeared. It might have
1744 * already raised an interrupt.
1746 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1747 spin_unlock(&trans_pcie->irq_lock);
1751 /* Ack/clear/reset pending uCode interrupts.
1752 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1754 /* There is a hardware bug in the interrupt mask function that some
1755 * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1756 * they are disabled in the CSR_INT_MASK register. Furthermore the
1757 * ICT interrupt handling mechanism has another bug that might cause
1758 * these unmasked interrupts fail to be detected. We workaround the
1759 * hardware bugs here by ACKing all the possible interrupts so that
1760 * interrupt coalescing can still be achieved.
1762 iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1764 if (iwl_have_debug_level(IWL_DL_ISR))
1765 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1766 inta, iwl_read32(trans, CSR_INT_MASK));
1768 spin_unlock(&trans_pcie->irq_lock);
1770 /* Now service all interrupt bits discovered above. */
1771 if (inta & CSR_INT_BIT_HW_ERR) {
1772 IWL_ERR(trans, "Hardware error detected. Restarting.\n");
1774 /* Tell the device to stop sending interrupts */
1775 iwl_disable_interrupts(trans);
1778 iwl_pcie_irq_handle_error(trans);
1780 handled |= CSR_INT_BIT_HW_ERR;
1785 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1786 if (inta & CSR_INT_BIT_SCD) {
1787 IWL_DEBUG_ISR(trans,
1788 "Scheduler finished to transmit the frame/frames.\n");
1792 /* Alive notification via Rx interrupt will do the real work */
1793 if (inta & CSR_INT_BIT_ALIVE) {
1794 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1796 if (trans->cfg->gen2) {
1798 * We can restock, since firmware configured
1801 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1804 handled |= CSR_INT_BIT_ALIVE;
1807 /* Safely ignore these bits for debug checks below */
1808 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1810 /* HW RF KILL switch toggled */
1811 if (inta & CSR_INT_BIT_RF_KILL) {
1812 iwl_pcie_handle_rfkill_irq(trans);
1813 handled |= CSR_INT_BIT_RF_KILL;
1816 /* Chip got too hot and stopped itself */
1817 if (inta & CSR_INT_BIT_CT_KILL) {
1818 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1819 isr_stats->ctkill++;
1820 handled |= CSR_INT_BIT_CT_KILL;
1823 /* Error detected by uCode */
1824 if (inta & CSR_INT_BIT_SW_ERR) {
1825 IWL_ERR(trans, "Microcode SW error detected. "
1826 " Restarting 0x%X.\n", inta);
1828 iwl_pcie_irq_handle_error(trans);
1829 handled |= CSR_INT_BIT_SW_ERR;
1832 /* uCode wakes up after power-down sleep */
1833 if (inta & CSR_INT_BIT_WAKEUP) {
1834 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1835 iwl_pcie_rxq_check_wrptr(trans);
1836 iwl_pcie_txq_check_wrptrs(trans);
1838 isr_stats->wakeup++;
1840 handled |= CSR_INT_BIT_WAKEUP;
1843 /* All uCode command responses, including Tx command responses,
1844 * Rx "responses" (frame-received notification), and other
1845 * notifications from uCode come through here*/
1846 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1847 CSR_INT_BIT_RX_PERIODIC)) {
1848 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1849 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1850 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1851 iwl_write32(trans, CSR_FH_INT_STATUS,
1852 CSR_FH_INT_RX_MASK);
1854 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1855 handled |= CSR_INT_BIT_RX_PERIODIC;
1857 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1859 /* Sending RX interrupt require many steps to be done in the
1861 * 1- write interrupt to current index in ICT table.
1863 * 3- update RX shared data to indicate last write index.
1864 * 4- send interrupt.
1865 * This could lead to RX race, driver could receive RX interrupt
1866 * but the shared data changes does not reflect this;
1867 * periodic interrupt will detect any dangling Rx activity.
1870 /* Disable periodic interrupt; we use it as just a one-shot. */
1871 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1872 CSR_INT_PERIODIC_DIS);
1875 * Enable periodic interrupt in 8 msec only if we received
1876 * real RX interrupt (instead of just periodic int), to catch
1877 * any dangling Rx interrupt. If it was just the periodic
1878 * interrupt, there was no dangling Rx activity, and no need
1879 * to extend the periodic interrupt; one-shot is enough.
1881 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1882 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1883 CSR_INT_PERIODIC_ENA);
1888 iwl_pcie_rx_handle(trans, 0);
1892 /* This "Tx" DMA channel is used only for loading uCode */
1893 if (inta & CSR_INT_BIT_FH_TX) {
1894 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1895 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1897 handled |= CSR_INT_BIT_FH_TX;
1898 /* Wake up uCode load routine, now that load is complete */
1899 trans_pcie->ucode_write_complete = true;
1900 wake_up(&trans_pcie->ucode_write_waitq);
1903 if (inta & ~handled) {
1904 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1905 isr_stats->unhandled++;
1908 if (inta & ~(trans_pcie->inta_mask)) {
1909 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1910 inta & ~trans_pcie->inta_mask);
1913 spin_lock(&trans_pcie->irq_lock);
1914 /* only Re-enable all interrupt if disabled by irq */
1915 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1916 _iwl_enable_interrupts(trans);
1917 /* we are loading the firmware, enable FH_TX interrupt only */
1918 else if (handled & CSR_INT_BIT_FH_TX)
1919 iwl_enable_fw_load_int(trans);
1920 /* Re-enable RF_KILL if it occurred */
1921 else if (handled & CSR_INT_BIT_RF_KILL)
1922 iwl_enable_rfkill_int(trans);
1923 /* Re-enable the ALIVE / Rx interrupt if it occurred */
1924 else if (handled & (CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX))
1925 iwl_enable_fw_load_int_ctx_info(trans);
1926 spin_unlock(&trans_pcie->irq_lock);
1929 lock_map_release(&trans->sync_cmd_lockdep_map);
1933 /******************************************************************************
1937 ******************************************************************************/
1939 /* Free dram table */
1940 void iwl_pcie_free_ict(struct iwl_trans *trans)
1942 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1944 if (trans_pcie->ict_tbl) {
1945 dma_free_coherent(trans->dev, ICT_SIZE,
1946 trans_pcie->ict_tbl,
1947 trans_pcie->ict_tbl_dma);
1948 trans_pcie->ict_tbl = NULL;
1949 trans_pcie->ict_tbl_dma = 0;
1954 * allocate dram shared table, it is an aligned memory
1955 * block of ICT_SIZE.
1956 * also reset all data related to ICT table interrupt.
1958 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1960 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1962 trans_pcie->ict_tbl =
1963 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1964 &trans_pcie->ict_tbl_dma,
1966 if (!trans_pcie->ict_tbl)
1969 /* just an API sanity check ... it is guaranteed to be aligned */
1970 if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1971 iwl_pcie_free_ict(trans);
1978 /* Device is going up inform it about using ICT interrupt table,
1979 * also we need to tell the driver to start using ICT interrupt.
1981 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1983 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1986 if (!trans_pcie->ict_tbl)
1989 spin_lock(&trans_pcie->irq_lock);
1990 _iwl_disable_interrupts(trans);
1992 memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1994 val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1996 val |= CSR_DRAM_INT_TBL_ENABLE |
1997 CSR_DRAM_INIT_TBL_WRAP_CHECK |
1998 CSR_DRAM_INIT_TBL_WRITE_POINTER;
2000 IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
2002 iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
2003 trans_pcie->use_ict = true;
2004 trans_pcie->ict_index = 0;
2005 iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
2006 _iwl_enable_interrupts(trans);
2007 spin_unlock(&trans_pcie->irq_lock);
2010 /* Device is going down disable ict interrupt usage */
2011 void iwl_pcie_disable_ict(struct iwl_trans *trans)
2013 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
2015 spin_lock(&trans_pcie->irq_lock);
2016 trans_pcie->use_ict = false;
2017 spin_unlock(&trans_pcie->irq_lock);
2020 irqreturn_t iwl_pcie_isr(int irq, void *data)
2022 struct iwl_trans *trans = data;
2027 /* Disable (but don't clear!) interrupts here to avoid
2028 * back-to-back ISRs and sporadic interrupts from our NIC.
2029 * If we have something to service, the tasklet will re-enable ints.
2030 * If we *don't* have something, we'll re-enable before leaving here.
2032 iwl_write32(trans, CSR_INT_MASK, 0x00000000);
2034 return IRQ_WAKE_THREAD;
2037 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
2039 return IRQ_WAKE_THREAD;
2042 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
2044 struct msix_entry *entry = dev_id;
2045 struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
2046 struct iwl_trans *trans = trans_pcie->trans;
2047 struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
2048 u32 inta_fh, inta_hw;
2050 lock_map_acquire(&trans->sync_cmd_lockdep_map);
2052 spin_lock(&trans_pcie->irq_lock);
2053 inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
2054 inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
2056 * Clear causes registers to avoid being handling the same cause.
2058 iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
2059 iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
2060 spin_unlock(&trans_pcie->irq_lock);
2062 trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
2064 if (unlikely(!(inta_fh | inta_hw))) {
2065 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
2066 lock_map_release(&trans->sync_cmd_lockdep_map);
2070 if (iwl_have_debug_level(IWL_DL_ISR)) {
2071 IWL_DEBUG_ISR(trans,
2072 "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2073 inta_fh, trans_pcie->fh_mask,
2074 iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
2075 if (inta_fh & ~trans_pcie->fh_mask)
2076 IWL_DEBUG_ISR(trans,
2077 "We got a masked interrupt (0x%08x)\n",
2078 inta_fh & ~trans_pcie->fh_mask);
2081 inta_fh &= trans_pcie->fh_mask;
2083 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
2084 inta_fh & MSIX_FH_INT_CAUSES_Q0) {
2086 iwl_pcie_rx_handle(trans, 0);
2090 if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
2091 inta_fh & MSIX_FH_INT_CAUSES_Q1) {
2093 iwl_pcie_rx_handle(trans, 1);
2097 /* This "Tx" DMA channel is used only for loading uCode */
2098 if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
2099 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
2102 * Wake up uCode load routine,
2103 * now that load is complete
2105 trans_pcie->ucode_write_complete = true;
2106 wake_up(&trans_pcie->ucode_write_waitq);
2109 /* Error detected by uCode */
2110 if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
2111 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR) ||
2112 (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR_V2)) {
2114 "Microcode SW error detected. Restarting 0x%X.\n",
2117 iwl_pcie_irq_handle_error(trans);
2120 /* After checking FH register check HW register */
2121 if (iwl_have_debug_level(IWL_DL_ISR)) {
2122 IWL_DEBUG_ISR(trans,
2123 "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2124 inta_hw, trans_pcie->hw_mask,
2125 iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2126 if (inta_hw & ~trans_pcie->hw_mask)
2127 IWL_DEBUG_ISR(trans,
2128 "We got a masked interrupt 0x%08x\n",
2129 inta_hw & ~trans_pcie->hw_mask);
2132 inta_hw &= trans_pcie->hw_mask;
2134 /* Alive notification via Rx interrupt will do the real work */
2135 if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2136 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2138 if (trans->cfg->gen2) {
2139 /* We can restock, since firmware configured the RFH */
2140 iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2144 if (trans->cfg->device_family >= IWL_DEVICE_FAMILY_22560 &&
2145 inta_hw & MSIX_HW_INT_CAUSES_REG_IPC) {
2146 /* Reflect IML transfer status */
2147 int res = iwl_read32(trans, CSR_IML_RESP_ADDR);
2149 IWL_DEBUG_ISR(trans, "IML transfer status: %d\n", res);
2150 if (res == IWL_IMAGE_RESP_FAIL) {
2152 iwl_pcie_irq_handle_error(trans);
2154 } else if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2155 /* uCode wakes up after power-down sleep */
2156 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2157 iwl_pcie_rxq_check_wrptr(trans);
2158 iwl_pcie_txq_check_wrptrs(trans);
2160 isr_stats->wakeup++;
2163 /* Chip got too hot and stopped itself */
2164 if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2165 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2166 isr_stats->ctkill++;
2169 /* HW RF KILL switch toggled */
2170 if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2171 iwl_pcie_handle_rfkill_irq(trans);
2173 if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2175 "Hardware error detected. Restarting.\n");
2178 iwl_pcie_irq_handle_error(trans);
2181 iwl_pcie_clear_irq(trans, entry);
2183 lock_map_release(&trans->sync_cmd_lockdep_map);