drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/sched.h>
  32 #include <linux/wait.h>
  33 #include <linux/gfp.h>
  34
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "internal.h"
  38 #include "iwl-op-mode.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
  79  *   When the interrupt handler is called, the request is processed.
  80  *   The page is either stolen - transferred to the upper layer
  81  *   or reused - added immediately to the iwl->rxq->rx_free list.
  82  * + When the page is stolen - the driver updates the matching queue's used
  83  *   count, detaches the RBD and transfers it to the queue used list.
  84  *   When there are two used RBDs - they are transferred to the allocator empty
  85  *   list. Work is then scheduled for the allocator to start allocating
  86  *   eight buffers.
  87  *   When there are another 6 used RBDs - they are transferred to the allocator
  88  *   empty list and the driver tries to claim the pre-allocated buffers and
  89  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
  90  *   until ready.
  91  *   When there are 8+ buffers in the free list - either from allocation or from
  92  *   8 reused unstolen pages - restock is called to update the FW and indexes.
  93  * + In order to make sure the allocator always has RBDs to use for allocation
  94  *   the allocator has initial pool in the size of num_queues*(8-2) - the
  95  *   maximum missing RBDs per allocation request (request posted with 2
  96  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
  97  *   The queues supplies the recycle of the rest of the RBDs.
  98  * + A received packet is processed and handed to the kernel network stack,
  99  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 100  * + If there are no allocated buffers in iwl->rxq->rx_free,
 101  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 102  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 103  *
 104  *
 105  * Driver sequence:
 106  *
 107  * iwl_rxq_alloc()            Allocates rx_free
 108  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 109  *                            iwl_pcie_rxq_restock.
 110  *                            Used only during initialization.
 111  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 112  *                            queue, updates firmware pointers, and updates
 113  *                            the WRITE index.
 114  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 115  *
 116  * -- enable interrupts --
 117  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 118  *                            READ INDEX, detaching the SKB from the pool.
 119  *                            Moves the packet buffer from queue to rx_used.
 120  *                            Posts and claims requests to the allocator.
 121  *                            Calls iwl_pcie_rxq_restock to refill any empty
 122  *                            slots.
 123  *
 124  * RBD life-cycle:
 125  *
 126  * Init:
 127  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 128  *
 129  * Regular Receive interrupt:
 130  * Page Stolen:
 131  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 132  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 133  * Page not Stolen:
 134  * rxq.queue -> rxq.rx_free -> rxq.queue
 135  * ...
 136  *
 137  */
 138
 139 /*
 140  * iwl_rxq_space - Return number of free slots available in queue.
 141  */
 142 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 143 {
 144         /* Make sure rx queue size is a power of 2 */
 145         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 146
 147         /*
 148          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 149          * between empty and completely full queues.
 150          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 151          * defined for negative dividends.
 152          */
 153         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 154 }
 155
 156 /*
 157  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 158  */
 159 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 160 {
 161         return cpu_to_le32((u32)(dma_addr >> 8));
 162 }
 163
 164 /*
 165  * iwl_pcie_rx_stop - stops the Rx DMA
 166  */
 167 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 168 {
 169         if (trans->cfg->mq_rx_supported) {
 170                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 171                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 172                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 173         } else {
 174                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 175                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 176                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 177                                            1000);
 178         }
 179 }
 180
 181 /*
 182  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 183  */
 184 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 185                                     struct iwl_rxq *rxq)
 186 {
 187         u32 reg;
 188
 189         lockdep_assert_held(&rxq->lock);
 190
 191         /*
 192          * explicitly wake up the NIC if:
 193          * 1. shadow registers aren't enabled
 194          * 2. there is a chance that the NIC is asleep
 195          */
 196         if (!trans->cfg->base_params->shadow_reg_enable &&
 197             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 198                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 199
 200                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 201                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 202                                        reg);
 203                         iwl_set_bit(trans, CSR_GP_CNTRL,
 204                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 205                         rxq->need_update = true;
 206                         return;
 207                 }
 208         }
 209
 210         rxq->write_actual = round_down(rxq->write, 8);
 211         if (trans->cfg->mq_rx_supported)
 212                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 213                             rxq->write_actual);
 214         else
 215                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 216 }
 217
 218 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 219 {
 220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 221         int i;
 222
 223         for (i = 0; i < trans->num_rx_queues; i++) {
 224                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 225
 226                 if (!rxq->need_update)
 227                         continue;
 228                 spin_lock(&rxq->lock);
 229                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 230                 rxq->need_update = false;
 231                 spin_unlock(&rxq->lock);
 232         }
 233 }
 234
 235 /*
 236  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 237  */
 238 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 239                                   struct iwl_rxq *rxq)
 240 {
 241         struct iwl_rx_mem_buffer *rxb;
 242
 243         /*
 244          * If the device isn't enabled - no need to try to add buffers...
 245          * This can happen when we stop the device and still have an interrupt
 246          * pending. We stop the APM before we sync the interrupts because we
 247          * have to (see comment there). On the other hand, since the APM is
 248          * stopped, we cannot access the HW (in particular not prph).
 249          * So don't try to restock if the APM has been already stopped.
 250          */
 251         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 252                 return;
 253
 254         spin_lock(&rxq->lock);
 255         while (rxq->free_count) {
 256                 __le64 *bd = (__le64 *)rxq->bd;
 257
 258                 /* Get next free Rx buffer, remove from free list */
 259                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 260                                        list);
 261                 list_del(&rxb->list);
 262                 rxb->invalid = false;
 263                 /* 12 first bits are expected to be empty */
 264                 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
 265                 /* Point to Rx buffer via next RBD in circular buffer */
 266                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 267                 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
 268                 rxq->free_count--;
 269         }
 270         spin_unlock(&rxq->lock);
 271
 272         /*
 273          * If we've added more space for the firmware to place data, tell it.
 274          * Increment device's write pointer in multiples of 8.
 275          */
 276         if (rxq->write_actual != (rxq->write & ~0x7)) {
 277                 spin_lock(&rxq->lock);
 278                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 279                 spin_unlock(&rxq->lock);
 280         }
 281 }
 282
 283 /*
 284  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 285  */
 286 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 287                                   struct iwl_rxq *rxq)
 288 {
 289         struct iwl_rx_mem_buffer *rxb;
 290
 291         /*
 292          * If the device isn't enabled - not need to try to add buffers...
 293          * This can happen when we stop the device and still have an interrupt
 294          * pending. We stop the APM before we sync the interrupts because we
 295          * have to (see comment there). On the other hand, since the APM is
 296          * stopped, we cannot access the HW (in particular not prph).
 297          * So don't try to restock if the APM has been already stopped.
 298          */
 299         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 300                 return;
 301
 302         spin_lock(&rxq->lock);
 303         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 304                 __le32 *bd = (__le32 *)rxq->bd;
 305                 /* The overwritten rxb must be a used one */
 306                 rxb = rxq->queue[rxq->write];
 307                 BUG_ON(rxb && rxb->page);
 308
 309                 /* Get next free Rx buffer, remove from free list */
 310                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 311                                        list);
 312                 list_del(&rxb->list);
 313                 rxb->invalid = false;
 314
 315                 /* Point to Rx buffer via next RBD in circular buffer */
 316                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 317                 rxq->queue[rxq->write] = rxb;
 318                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 319                 rxq->free_count--;
 320         }
 321         spin_unlock(&rxq->lock);
 322
 323         /* If we've added more space for the firmware to place data, tell it.
 324          * Increment device's write pointer in multiples of 8. */
 325         if (rxq->write_actual != (rxq->write & ~0x7)) {
 326                 spin_lock(&rxq->lock);
 327                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 328                 spin_unlock(&rxq->lock);
 329         }
 330 }
 331
 332 /*
 333  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 334  *
 335  * If there are slots in the RX queue that need to be restocked,
 336  * and we have free pre-allocated buffers, fill the ranks as much
 337  * as we can, pulling from rx_free.
 338  *
 339  * This moves the 'write' index forward to catch up with 'processed', and
 340  * also updates the memory address in the firmware to reference the new
 341  * target buffer.
 342  */
 343 static
 344 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 345 {
 346         if (trans->cfg->mq_rx_supported)
 347                 iwl_pcie_rxmq_restock(trans, rxq);
 348         else
 349                 iwl_pcie_rxsq_restock(trans, rxq);
 350 }
 351
 352 /*
 353  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 354  *
 355  */
 356 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 357                                            gfp_t priority)
 358 {
 359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 360         struct page *page;
 361         gfp_t gfp_mask = priority;
 362
 363         if (trans_pcie->rx_page_order > 0)
 364                 gfp_mask |= __GFP_COMP;
 365
 366         /* Alloc a new receive buffer */
 367         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 368         if (!page) {
 369                 if (net_ratelimit())
 370                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 371                                        trans_pcie->rx_page_order);
 372                 /*
 373                  * Issue an error if we don't have enough pre-allocated
 374                   * buffers.
 375 `                */
 376                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 377                         IWL_CRIT(trans,
 378                                  "Failed to alloc_pages\n");
 379                 return NULL;
 380         }
 381         return page;
 382 }
 383
 384 /*
 385  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 386  *
 387  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 388  * a page must be allocated and the RBD must point to the page. This function
 389  * doesn't change the HW pointer but handles the list of pages that is used by
 390  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 391  * allocated buffers.
 392  */
 393 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 394                                    struct iwl_rxq *rxq)
 395 {
 396         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 397         struct iwl_rx_mem_buffer *rxb;
 398         struct page *page;
 399
 400         while (1) {
 401                 spin_lock(&rxq->lock);
 402                 if (list_empty(&rxq->rx_used)) {
 403                         spin_unlock(&rxq->lock);
 404                         return;
 405                 }
 406                 spin_unlock(&rxq->lock);
 407
 408                 /* Alloc a new receive buffer */
 409                 page = iwl_pcie_rx_alloc_page(trans, priority);
 410                 if (!page)
 411                         return;
 412
 413                 spin_lock(&rxq->lock);
 414
 415                 if (list_empty(&rxq->rx_used)) {
 416                         spin_unlock(&rxq->lock);
 417                         __free_pages(page, trans_pcie->rx_page_order);
 418                         return;
 419                 }
 420                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 421                                        list);
 422                 list_del(&rxb->list);
 423                 spin_unlock(&rxq->lock);
 424
 425                 BUG_ON(rxb->page);
 426                 rxb->page = page;
 427                 /* Get physical address of the RB */
 428                 rxb->page_dma =
 429                         dma_map_page(trans->dev, page, 0,
 430                                      PAGE_SIZE << trans_pcie->rx_page_order,
 431                                      DMA_FROM_DEVICE);
 432                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 433                         rxb->page = NULL;
 434                         spin_lock(&rxq->lock);
 435                         list_add(&rxb->list, &rxq->rx_used);
 436                         spin_unlock(&rxq->lock);
 437                         __free_pages(page, trans_pcie->rx_page_order);
 438                         return;
 439                 }
 440
 441                 spin_lock(&rxq->lock);
 442
 443                 list_add_tail(&rxb->list, &rxq->rx_free);
 444                 rxq->free_count++;
 445
 446                 spin_unlock(&rxq->lock);
 447         }
 448 }
 449
 450 static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 451 {
 452         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 453         int i;
 454
 455         for (i = 0; i < RX_POOL_SIZE; i++) {
 456                 if (!trans_pcie->rx_pool[i].page)
 457                         continue;
 458                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 459                                PAGE_SIZE << trans_pcie->rx_page_order,
 460                                DMA_FROM_DEVICE);
 461                 __free_pages(trans_pcie->rx_pool[i].page,
 462                              trans_pcie->rx_page_order);
 463                 trans_pcie->rx_pool[i].page = NULL;
 464         }
 465 }
 466
 467 /*
 468  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 469  *
 470  * Allocates for each received request 8 pages
 471  * Called as a scheduled work item.
 472  */
 473 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 477         struct list_head local_empty;
 478         int pending = atomic_read(&rba->req_pending);
 479
 480         IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
 481
 482         /* If we were scheduled - there is at least one request */
 483         spin_lock(&rba->lock);
 484         /* swap out the rba->rbd_empty to a local list */
 485         list_replace_init(&rba->rbd_empty, &local_empty);
 486         spin_unlock(&rba->lock);
 487
 488         while (pending) {
 489                 int i;
 490                 LIST_HEAD(local_allocated);
 491                 gfp_t gfp_mask = GFP_KERNEL;
 492
 493                 /* Do not post a warning if there are only a few requests */
 494                 if (pending < RX_PENDING_WATERMARK)
 495                         gfp_mask |= __GFP_NOWARN;
 496
 497                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 498                         struct iwl_rx_mem_buffer *rxb;
 499                         struct page *page;
 500
 501                         /* List should never be empty - each reused RBD is
 502                          * returned to the list, and initial pool covers any
 503                          * possible gap between the time the page is allocated
 504                          * to the time the RBD is added.
 505                          */
 506                         BUG_ON(list_empty(&local_empty));
 507                         /* Get the first rxb from the rbd list */
 508                         rxb = list_first_entry(&local_empty,
 509                                                struct iwl_rx_mem_buffer, list);
 510                         BUG_ON(rxb->page);
 511
 512                         /* Alloc a new receive buffer */
 513                         page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
 514                         if (!page)
 515                                 continue;
 516                         rxb->page = page;
 517
 518                         /* Get physical address of the RB */
 519                         rxb->page_dma = dma_map_page(trans->dev, page, 0,
 520                                         PAGE_SIZE << trans_pcie->rx_page_order,
 521                                         DMA_FROM_DEVICE);
 522                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 523                                 rxb->page = NULL;
 524                                 __free_pages(page, trans_pcie->rx_page_order);
 525                                 continue;
 526                         }
 527
 528                         /* move the allocated entry to the out list */
 529                         list_move(&rxb->list, &local_allocated);
 530                         i++;
 531                 }
 532
 533                 atomic_dec(&rba->req_pending);
 534                 pending--;
 535
 536                 if (!pending) {
 537                         pending = atomic_read(&rba->req_pending);
 538                         IWL_DEBUG_RX(trans,
 539                                      "Got more pending allocation requests = %d\n",
 540                                      pending);
 541                 }
 542
 543                 spin_lock(&rba->lock);
 544                 /* add the allocated rbds to the allocator allocated list */
 545                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 546                 /* get more empty RBDs for current pending requests */
 547                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 548                 spin_unlock(&rba->lock);
 549
 550                 atomic_inc(&rba->req_ready);
 551
 552         }
 553
 554         spin_lock(&rba->lock);
 555         /* return unused rbds to the allocator empty list */
 556         list_splice_tail(&local_empty, &rba->rbd_empty);
 557         spin_unlock(&rba->lock);
 558
 559         IWL_DEBUG_RX(trans, "%s, exit.\n", __func__);
 560 }
 561
 562 /*
 563  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 564 .*
 565 .* Called by queue when the queue posted allocation request and
 566  * has freed 8 RBDs in order to restock itself.
 567  * This function directly moves the allocated RBs to the queue's ownership
 568  * and updates the relevant counters.
 569  */
 570 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 571                                       struct iwl_rxq *rxq)
 572 {
 573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 574         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 575         int i;
 576
 577         lockdep_assert_held(&rxq->lock);
 578
 579         /*
 580          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 581          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 582          * function will return early, as there are no ready requests.
 583          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 584          * req_ready > 0, i.e. - there are ready requests and the function
 585          * hands one request to the caller.
 586          */
 587         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 588                 return;
 589
 590         spin_lock(&rba->lock);
 591         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 592                 /* Get next free Rx buffer, remove it from free list */
 593                 struct iwl_rx_mem_buffer *rxb =
 594                         list_first_entry(&rba->rbd_allocated,
 595                                          struct iwl_rx_mem_buffer, list);
 596
 597                 list_move(&rxb->list, &rxq->rx_free);
 598         }
 599         spin_unlock(&rba->lock);
 600
 601         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 602         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 603 }
 604
 605 void iwl_pcie_rx_allocator_work(struct work_struct *data)
 606 {
 607         struct iwl_rb_allocator *rba_p =
 608                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 609         struct iwl_trans_pcie *trans_pcie =
 610                 container_of(rba_p, struct iwl_trans_pcie, rba);
 611
 612         iwl_pcie_rx_allocator(trans_pcie->trans);
 613 }
 614
 615 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 616 {
 617         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 618         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 619         struct device *dev = trans->dev;
 620         int i;
 621         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
 622                                                       sizeof(__le32);
 623
 624         if (WARN_ON(trans_pcie->rxq))
 625                 return -EINVAL;
 626
 627         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 628                                   GFP_KERNEL);
 629         if (!trans_pcie->rxq)
 630                 return -EINVAL;
 631
 632         spin_lock_init(&rba->lock);
 633
 634         for (i = 0; i < trans->num_rx_queues; i++) {
 635                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 636
 637                 spin_lock_init(&rxq->lock);
 638                 if (trans->cfg->mq_rx_supported)
 639                         rxq->queue_size = MQ_RX_TABLE_SIZE;
 640                 else
 641                         rxq->queue_size = RX_QUEUE_SIZE;
 642
 643                 /*
 644                  * Allocate the circular buffer of Read Buffer Descriptors
 645                  * (RBDs)
 646                  */
 647                 rxq->bd = dma_zalloc_coherent(dev,
 648                                              free_size * rxq->queue_size,
 649                                              &rxq->bd_dma, GFP_KERNEL);
 650                 if (!rxq->bd)
 651                         goto err;
 652
 653                 if (trans->cfg->mq_rx_supported) {
 654                         rxq->used_bd = dma_zalloc_coherent(dev,
 655                                                            sizeof(__le32) *
 656                                                            rxq->queue_size,
 657                                                            &rxq->used_bd_dma,
 658                                                            GFP_KERNEL);
 659                         if (!rxq->used_bd)
 660                                 goto err;
 661                 }
 662
 663                 /*Allocate the driver's pointer to receive buffer status */
 664                 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 665                                                    &rxq->rb_stts_dma,
 666                                                    GFP_KERNEL);
 667                 if (!rxq->rb_stts)
 668                         goto err;
 669         }
 670         return 0;
 671
 672 err:
 673         for (i = 0; i < trans->num_rx_queues; i++) {
 674                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 675
 676                 if (rxq->bd)
 677                         dma_free_coherent(dev, free_size * rxq->queue_size,
 678                                           rxq->bd, rxq->bd_dma);
 679                 rxq->bd_dma = 0;
 680                 rxq->bd = NULL;
 681
 682                 if (rxq->rb_stts)
 683                         dma_free_coherent(trans->dev,
 684                                           sizeof(struct iwl_rb_status),
 685                                           rxq->rb_stts, rxq->rb_stts_dma);
 686
 687                 if (rxq->used_bd)
 688                         dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size,
 689                                           rxq->used_bd, rxq->used_bd_dma);
 690                 rxq->used_bd_dma = 0;
 691                 rxq->used_bd = NULL;
 692         }
 693         kfree(trans_pcie->rxq);
 694
 695         return -ENOMEM;
 696 }
 697
 698 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 699 {
 700         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 701         u32 rb_size;
 702         unsigned long flags;
 703         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 704
 705         switch (trans_pcie->rx_buf_size) {
 706         case IWL_AMSDU_4K:
 707                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 708                 break;
 709         case IWL_AMSDU_8K:
 710                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 711                 break;
 712         case IWL_AMSDU_12K:
 713                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 714                 break;
 715         default:
 716                 WARN_ON(1);
 717                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 718         }
 719
 720         if (!iwl_trans_grab_nic_access(trans, &flags))
 721                 return;
 722
 723         /* Stop Rx DMA */
 724         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 725         /* reset and flush pointers */
 726         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 727         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 728         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 729
 730         /* Reset driver's Rx queue write index */
 731         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 732
 733         /* Tell device where to find RBD circular buffer in DRAM */
 734         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 735                     (u32)(rxq->bd_dma >> 8));
 736
 737         /* Tell device where in DRAM to update its Rx status */
 738         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 739                     rxq->rb_stts_dma >> 4);
 740
 741         /* Enable Rx DMA
 742          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 743          *      the credit mechanism in 5000 HW RX FIFO
 744          * Direct rx interrupts to hosts
 745          * Rx buffer size 4 or 8k or 12k
 746          * RB timeout 0x10
 747          * 256 RBDs
 748          */
 749         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 750                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 751                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 752                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 753                     rb_size |
 754                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 755                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 756
 757         iwl_trans_release_nic_access(trans, &flags);
 758
 759         /* Set interrupt coalescing timer to default (2048 usecs) */
 760         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 761
 762         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 763         if (trans->cfg->host_interrupt_operation_mode)
 764                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 765 }
 766
 767 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable)
 768 {
 769         if (trans->cfg->device_family != IWL_DEVICE_FAMILY_9000)
 770                 return;
 771
 772         if (CSR_HW_REV_STEP(trans->hw_rev) != SILICON_A_STEP)
 773                 return;
 774
 775         if (!trans->cfg->integrated)
 776                 return;
 777
 778         /*
 779          * Turn on the chicken-bits that cause MAC wakeup for RX-related
 780          * values.
 781          * This costs some power, but needed for W/A 9000 integrated A-step
 782          * bug where shadow registers are not in the retention list and their
 783          * value is lost when NIC powers down
 784          */
 785         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 786                     CSR_MAC_SHADOW_REG_CTRL_RX_WAKE);
 787         iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2,
 788                     CSR_MAC_SHADOW_REG_CTL2_RX_WAKE);
 789 }
 790
 791 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 792 {
 793         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 794         u32 rb_size, enabled = 0;
 795         unsigned long flags;
 796         int i;
 797
 798         switch (trans_pcie->rx_buf_size) {
 799         case IWL_AMSDU_4K:
 800                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 801                 break;
 802         case IWL_AMSDU_8K:
 803                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 804                 break;
 805         case IWL_AMSDU_12K:
 806                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 807                 break;
 808         default:
 809                 WARN_ON(1);
 810                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 811         }
 812
 813         if (!iwl_trans_grab_nic_access(trans, &flags))
 814                 return;
 815
 816         /* Stop Rx DMA */
 817         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 818         /* disable free amd used rx queue operation */
 819         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 820
 821         for (i = 0; i < trans->num_rx_queues; i++) {
 822                 /* Tell device where to find RBD free table in DRAM */
 823                 iwl_write_prph64_no_grab(trans,
 824                                          RFH_Q_FRBDCB_BA_LSB(i),
 825                                          trans_pcie->rxq[i].bd_dma);
 826                 /* Tell device where to find RBD used table in DRAM */
 827                 iwl_write_prph64_no_grab(trans,
 828                                          RFH_Q_URBDCB_BA_LSB(i),
 829                                          trans_pcie->rxq[i].used_bd_dma);
 830                 /* Tell device where in DRAM to update its Rx status */
 831                 iwl_write_prph64_no_grab(trans,
 832                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
 833                                          trans_pcie->rxq[i].rb_stts_dma);
 834                 /* Reset device indice tables */
 835                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
 836                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
 837                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 838
 839                 enabled |= BIT(i) | BIT(i + 16);
 840         }
 841
 842         /*
 843          * Enable Rx DMA
 844          * Rx buffer size 4 or 8k or 12k
 845          * Min RB size 4 or 8
 846          * Drop frames that exceed RB size
 847          * 512 RBDs
 848          */
 849         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
 850                                RFH_DMA_EN_ENABLE_VAL | rb_size |
 851                                RFH_RXF_DMA_MIN_RB_4_8 |
 852                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
 853                                RFH_RXF_DMA_RBDCB_SIZE_512);
 854
 855         /*
 856          * Activate DMA snooping.
 857          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 858          * Default queue is 0
 859          */
 860         iwl_write_prph_no_grab(trans, RFH_GEN_CFG,
 861                                RFH_GEN_CFG_RFH_DMA_SNOOP |
 862                                RFH_GEN_CFG_VAL(DEFAULT_RXQ_NUM, 0) |
 863                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
 864                                RFH_GEN_CFG_VAL(RB_CHUNK_SIZE,
 865                                                trans->cfg->integrated ?
 866                                                RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
 867                                                RFH_GEN_CFG_RB_CHUNK_SIZE_128));
 868         /* Enable the relevant rx queues */
 869         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
 870
 871         iwl_trans_release_nic_access(trans, &flags);
 872
 873         /* Set interrupt coalescing timer to default (2048 usecs) */
 874         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 875
 876         iwl_pcie_enable_rx_wake(trans, true);
 877 }
 878
 879 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 880 {
 881         lockdep_assert_held(&rxq->lock);
 882
 883         INIT_LIST_HEAD(&rxq->rx_free);
 884         INIT_LIST_HEAD(&rxq->rx_used);
 885         rxq->free_count = 0;
 886         rxq->used_count = 0;
 887 }
 888
 889 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
 890 {
 891         WARN_ON(1);
 892         return 0;
 893 }
 894
 895 static int _iwl_pcie_rx_init(struct iwl_trans *trans)
 896 {
 897         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 898         struct iwl_rxq *def_rxq;
 899         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 900         int i, err, queue_size, allocator_pool_size, num_alloc;
 901
 902         if (!trans_pcie->rxq) {
 903                 err = iwl_pcie_rx_alloc(trans);
 904                 if (err)
 905                         return err;
 906         }
 907         def_rxq = trans_pcie->rxq;
 908
 909         cancel_work_sync(&rba->rx_alloc);
 910
 911         spin_lock(&rba->lock);
 912         atomic_set(&rba->req_pending, 0);
 913         atomic_set(&rba->req_ready, 0);
 914         INIT_LIST_HEAD(&rba->rbd_allocated);
 915         INIT_LIST_HEAD(&rba->rbd_empty);
 916         spin_unlock(&rba->lock);
 917
 918         /* free all first - we might be reconfigured for a different size */
 919         iwl_pcie_free_rbs_pool(trans);
 920
 921         for (i = 0; i < RX_QUEUE_SIZE; i++)
 922                 def_rxq->queue[i] = NULL;
 923
 924         for (i = 0; i < trans->num_rx_queues; i++) {
 925                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 926
 927                 rxq->id = i;
 928
 929                 spin_lock(&rxq->lock);
 930                 /*
 931                  * Set read write pointer to reflect that we have processed
 932                  * and used all buffers, but have not restocked the Rx queue
 933                  * with fresh buffers
 934                  */
 935                 rxq->read = 0;
 936                 rxq->write = 0;
 937                 rxq->write_actual = 0;
 938                 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 939
 940                 iwl_pcie_rx_init_rxb_lists(rxq);
 941
 942                 if (!rxq->napi.poll)
 943                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
 944                                        iwl_pcie_dummy_napi_poll, 64);
 945
 946                 spin_unlock(&rxq->lock);
 947         }
 948
 949         /* move the pool to the default queue and allocator ownerships */
 950         queue_size = trans->cfg->mq_rx_supported ?
 951                      MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
 952         allocator_pool_size = trans->num_rx_queues *
 953                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
 954         num_alloc = queue_size + allocator_pool_size;
 955         BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
 956                      ARRAY_SIZE(trans_pcie->rx_pool));
 957         for (i = 0; i < num_alloc; i++) {
 958                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
 959
 960                 if (i < allocator_pool_size)
 961                         list_add(&rxb->list, &rba->rbd_empty);
 962                 else
 963                         list_add(&rxb->list, &def_rxq->rx_used);
 964                 trans_pcie->global_table[i] = rxb;
 965                 rxb->vid = (u16)(i + 1);
 966                 rxb->invalid = true;
 967         }
 968
 969         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
 970
 971         return 0;
 972 }
 973
 974 int iwl_pcie_rx_init(struct iwl_trans *trans)
 975 {
 976         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 977         int ret = _iwl_pcie_rx_init(trans);
 978
 979         if (ret)
 980                 return ret;
 981
 982         if (trans->cfg->mq_rx_supported)
 983                 iwl_pcie_rx_mq_hw_init(trans);
 984         else
 985                 iwl_pcie_rx_hw_init(trans, trans_pcie->rxq);
 986
 987         iwl_pcie_rxq_restock(trans, trans_pcie->rxq);
 988
 989         spin_lock(&trans_pcie->rxq->lock);
 990         iwl_pcie_rxq_inc_wr_ptr(trans, trans_pcie->rxq);
 991         spin_unlock(&trans_pcie->rxq->lock);
 992
 993         return 0;
 994 }
 995
 996 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans)
 997 {
 998         /*
 999          * We don't configure the RFH.
1000          * Restock will be done at alive, after firmware configured the RFH.
1001          */
1002         return _iwl_pcie_rx_init(trans);
1003 }
1004
1005 void iwl_pcie_rx_free(struct iwl_trans *trans)
1006 {
1007         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1008         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1009         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
1010                                               sizeof(__le32);
1011         int i;
1012
1013         /*
1014          * if rxq is NULL, it means that nothing has been allocated,
1015          * exit now
1016          */
1017         if (!trans_pcie->rxq) {
1018                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1019                 return;
1020         }
1021
1022         cancel_work_sync(&rba->rx_alloc);
1023
1024         iwl_pcie_free_rbs_pool(trans);
1025
1026         for (i = 0; i < trans->num_rx_queues; i++) {
1027                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1028
1029                 if (rxq->bd)
1030                         dma_free_coherent(trans->dev,
1031                                           free_size * rxq->queue_size,
1032                                           rxq->bd, rxq->bd_dma);
1033                 rxq->bd_dma = 0;
1034                 rxq->bd = NULL;
1035
1036                 if (rxq->rb_stts)
1037                         dma_free_coherent(trans->dev,
1038                                           sizeof(struct iwl_rb_status),
1039                                           rxq->rb_stts, rxq->rb_stts_dma);
1040                 else
1041                         IWL_DEBUG_INFO(trans,
1042                                        "Free rxq->rb_stts which is NULL\n");
1043
1044                 if (rxq->used_bd)
1045                         dma_free_coherent(trans->dev,
1046                                           sizeof(__le32) * rxq->queue_size,
1047                                           rxq->used_bd, rxq->used_bd_dma);
1048                 rxq->used_bd_dma = 0;
1049                 rxq->used_bd = NULL;
1050
1051                 if (rxq->napi.poll)
1052                         netif_napi_del(&rxq->napi);
1053         }
1054         kfree(trans_pcie->rxq);
1055 }
1056
1057 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1058                                           struct iwl_rb_allocator *rba)
1059 {
1060         spin_lock(&rba->lock);
1061         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1062         spin_unlock(&rba->lock);
1063 }
1064
1065 /*
1066  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1067  *
1068  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1069  * When there are 2 empty RBDs - a request for allocation is posted
1070  */
1071 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1072                                   struct iwl_rx_mem_buffer *rxb,
1073                                   struct iwl_rxq *rxq, bool emergency)
1074 {
1075         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1076         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1077
1078         /* Move the RBD to the used list, will be moved to allocator in batches
1079          * before claiming or posting a request*/
1080         list_add_tail(&rxb->list, &rxq->rx_used);
1081
1082         if (unlikely(emergency))
1083                 return;
1084
1085         /* Count the allocator owned RBDs */
1086         rxq->used_count++;
1087
1088         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1089          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1090          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1091          * after but we still need to post another request.
1092          */
1093         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1094                 /* Move the 2 RBDs to the allocator ownership.
1095                  Allocator has another 6 from pool for the request completion*/
1096                 iwl_pcie_rx_move_to_allocator(rxq, rba);
1097
1098                 atomic_inc(&rba->req_pending);
1099                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1100         }
1101 }
1102
1103 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1104                                 struct iwl_rxq *rxq,
1105                                 struct iwl_rx_mem_buffer *rxb,
1106                                 bool emergency)
1107 {
1108         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1109         struct iwl_txq *txq = trans_pcie->txq[trans_pcie->cmd_queue];
1110         bool page_stolen = false;
1111         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1112         u32 offset = 0;
1113
1114         if (WARN_ON(!rxb))
1115                 return;
1116
1117         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1118
1119         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1120                 struct iwl_rx_packet *pkt;
1121                 u16 sequence;
1122                 bool reclaim;
1123                 int index, cmd_index, len;
1124                 struct iwl_rx_cmd_buffer rxcb = {
1125                         ._offset = offset,
1126                         ._rx_page_order = trans_pcie->rx_page_order,
1127                         ._page = rxb->page,
1128                         ._page_stolen = false,
1129                         .truesize = max_len,
1130                 };
1131
1132                 pkt = rxb_addr(&rxcb);
1133
1134                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID)) {
1135                         IWL_DEBUG_RX(trans,
1136                                      "Q %d: RB end marker at offset %d\n",
1137                                      rxq->id, offset);
1138                         break;
1139                 }
1140
1141                 WARN((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1142                         FH_RSCSR_RXQ_POS != rxq->id,
1143                      "frame on invalid queue - is on %d and indicates %d\n",
1144                      rxq->id,
1145                      (le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1146                         FH_RSCSR_RXQ_POS);
1147
1148                 IWL_DEBUG_RX(trans,
1149                              "Q %d: cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1150                              rxq->id, offset,
1151                              iwl_get_cmd_string(trans,
1152                                                 iwl_cmd_id(pkt->hdr.cmd,
1153                                                            pkt->hdr.group_id,
1154                                                            0)),
1155                              pkt->hdr.group_id, pkt->hdr.cmd,
1156                              le16_to_cpu(pkt->hdr.sequence));
1157
1158                 len = iwl_rx_packet_len(pkt);
1159                 len += sizeof(u32); /* account for status word */
1160                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1161                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1162
1163                 /* Reclaim a command buffer only if this packet is a response
1164                  *   to a (driver-originated) command.
1165                  * If the packet (e.g. Rx frame) originated from uCode,
1166                  *   there is no command buffer to reclaim.
1167                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1168                  *   but apparently a few don't get set; catch them here. */
1169                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1170                 if (reclaim && !pkt->hdr.group_id) {
1171                         int i;
1172
1173                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1174                                 if (trans_pcie->no_reclaim_cmds[i] ==
1175                                                         pkt->hdr.cmd) {
1176                                         reclaim = false;
1177                                         break;
1178                                 }
1179                         }
1180                 }
1181
1182                 sequence = le16_to_cpu(pkt->hdr.sequence);
1183                 index = SEQ_TO_INDEX(sequence);
1184                 cmd_index = iwl_pcie_get_cmd_index(txq, index);
1185
1186                 if (rxq->id == 0)
1187                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1188                                        &rxcb);
1189                 else
1190                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1191                                            &rxcb, rxq->id);
1192
1193                 if (reclaim) {
1194                         kzfree(txq->entries[cmd_index].free_buf);
1195                         txq->entries[cmd_index].free_buf = NULL;
1196                 }
1197
1198                 /*
1199                  * After here, we should always check rxcb._page_stolen,
1200                  * if it is true then one of the handlers took the page.
1201                  */
1202
1203                 if (reclaim) {
1204                         /* Invoke any callbacks, transfer the buffer to caller,
1205                          * and fire off the (possibly) blocking
1206                          * iwl_trans_send_cmd()
1207                          * as we reclaim the driver command queue */
1208                         if (!rxcb._page_stolen)
1209                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1210                         else
1211                                 IWL_WARN(trans, "Claim null rxb?\n");
1212                 }
1213
1214                 page_stolen |= rxcb._page_stolen;
1215                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1216         }
1217
1218         /* page was stolen from us -- free our reference */
1219         if (page_stolen) {
1220                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1221                 rxb->page = NULL;
1222         }
1223
1224         /* Reuse the page if possible. For notification packets and
1225          * SKBs that fail to Rx correctly, add them back into the
1226          * rx_free list for reuse later. */
1227         if (rxb->page != NULL) {
1228                 rxb->page_dma =
1229                         dma_map_page(trans->dev, rxb->page, 0,
1230                                      PAGE_SIZE << trans_pcie->rx_page_order,
1231                                      DMA_FROM_DEVICE);
1232                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1233                         /*
1234                          * free the page(s) as well to not break
1235                          * the invariant that the items on the used
1236                          * list have no page(s)
1237                          */
1238                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1239                         rxb->page = NULL;
1240                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1241                 } else {
1242                         list_add_tail(&rxb->list, &rxq->rx_free);
1243                         rxq->free_count++;
1244                 }
1245         } else
1246                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1247 }
1248
1249 /*
1250  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1251  */
1252 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1253 {
1254         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1255         struct iwl_rxq *rxq;
1256         u32 r, i, count = 0;
1257         bool emergency = false;
1258
1259         if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1260                 return;
1261
1262         rxq = &trans_pcie->rxq[queue];
1263
1264 restart:
1265         spin_lock(&rxq->lock);
1266         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1267          * buffer that the driver may process (last buffer filled by ucode). */
1268         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
1269         i = rxq->read;
1270
1271         /* W/A 9000 device step A0 wrap-around bug */
1272         r &= (rxq->queue_size - 1);
1273
1274         /* Rx interrupt, but nothing sent from uCode */
1275         if (i == r)
1276                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1277
1278         while (i != r) {
1279                 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1280                 struct iwl_rx_mem_buffer *rxb;
1281                 /* number of RBDs still waiting for page allocation */
1282                 u32 rb_pending_alloc =
1283                         atomic_read(&trans_pcie->rba.req_pending) *
1284                         RX_CLAIM_REQ_ALLOC;
1285
1286                 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1287                              !emergency)) {
1288                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1289                         emergency = true;
1290                 }
1291
1292                 if (trans->cfg->mq_rx_supported) {
1293                         /*
1294                          * used_bd is a 32 bit but only 12 are used to retrieve
1295                          * the vid
1296                          */
1297                         u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF;
1298
1299                         if (WARN(!vid ||
1300                                  vid > ARRAY_SIZE(trans_pcie->global_table),
1301                                  "Invalid rxb index from HW %u\n", (u32)vid)) {
1302                                 iwl_force_nmi(trans);
1303                                 goto out;
1304                         }
1305                         rxb = trans_pcie->global_table[vid - 1];
1306                         if (WARN(rxb->invalid,
1307                                  "Invalid rxb from HW %u\n", (u32)vid)) {
1308                                 iwl_force_nmi(trans);
1309                                 goto out;
1310                         }
1311                         rxb->invalid = true;
1312                 } else {
1313                         rxb = rxq->queue[i];
1314                         rxq->queue[i] = NULL;
1315                 }
1316
1317                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1318                 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency);
1319
1320                 i = (i + 1) & (rxq->queue_size - 1);
1321
1322                 /*
1323                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1324                  * try to claim the pre-allocated buffers from the allocator.
1325                  * If not ready - will try to reclaim next time.
1326                  * There is no need to reschedule work - allocator exits only
1327                  * on success
1328                  */
1329                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1330                         iwl_pcie_rx_allocator_get(trans, rxq);
1331
1332                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1333                         /* Add the remaining empty RBDs for allocator use */
1334                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1335                 } else if (emergency) {
1336                         count++;
1337                         if (count == 8) {
1338                                 count = 0;
1339                                 if (rb_pending_alloc < rxq->queue_size / 3)
1340                                         emergency = false;
1341
1342                                 rxq->read = i;
1343                                 spin_unlock(&rxq->lock);
1344                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1345                                 iwl_pcie_rxq_restock(trans, rxq);
1346                                 goto restart;
1347                         }
1348                 }
1349         }
1350 out:
1351         /* Backtrack one entry */
1352         rxq->read = i;
1353         spin_unlock(&rxq->lock);
1354
1355         /*
1356          * handle a case where in emergency there are some unallocated RBDs.
1357          * those RBDs are in the used list, but are not tracked by the queue's
1358          * used_count which counts allocator owned RBDs.
1359          * unallocated emergency RBDs must be allocated on exit, otherwise
1360          * when called again the function may not be in emergency mode and
1361          * they will be handed to the allocator with no tracking in the RBD
1362          * allocator counters, which will lead to them never being claimed back
1363          * by the queue.
1364          * by allocating them here, they are now in the queue free list, and
1365          * will be restocked by the next call of iwl_pcie_rxq_restock.
1366          */
1367         if (unlikely(emergency && count))
1368                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1369
1370         if (rxq->napi.poll)
1371                 napi_gro_flush(&rxq->napi, false);
1372
1373         iwl_pcie_rxq_restock(trans, rxq);
1374 }
1375
1376 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1377 {
1378         u8 queue = entry->entry;
1379         struct msix_entry *entries = entry - queue;
1380
1381         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1382 }
1383
1384 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
1385                                       struct msix_entry *entry)
1386 {
1387         /*
1388          * Before sending the interrupt the HW disables it to prevent
1389          * a nested interrupt. This is done by writing 1 to the corresponding
1390          * bit in the mask register. After handling the interrupt, it should be
1391          * re-enabled by clearing this bit. This register is defined as
1392          * write 1 clear (W1C) register, meaning that it's being clear
1393          * by writing 1 to the bit.
1394          */
1395         iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
1396 }
1397
1398 /*
1399  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1400  * This interrupt handler should be used with RSS queue only.
1401  */
1402 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1403 {
1404         struct msix_entry *entry = dev_id;
1405         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1406         struct iwl_trans *trans = trans_pcie->trans;
1407
1408         trace_iwlwifi_dev_irq_msix(trans->dev, entry, false, 0, 0);
1409
1410         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1411                 return IRQ_NONE;
1412
1413         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1414
1415         local_bh_disable();
1416         iwl_pcie_rx_handle(trans, entry->entry);
1417         local_bh_enable();
1418
1419         iwl_pcie_clear_irq(trans, entry);
1420
1421         lock_map_release(&trans->sync_cmd_lockdep_map);
1422
1423         return IRQ_HANDLED;
1424 }
1425
1426 /*
1427  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1428  */
1429 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1430 {
1431         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1432         int i;
1433
1434         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1435         if (trans->cfg->internal_wimax_coex &&
1436             !trans->cfg->apmg_not_supported &&
1437             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1438                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1439              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1440                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1441                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1442                 iwl_op_mode_wimax_active(trans->op_mode);
1443                 wake_up(&trans_pcie->wait_command_queue);
1444                 return;
1445         }
1446
1447         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++) {
1448                 if (!trans_pcie->txq[i])
1449                         continue;
1450                 del_timer(&trans_pcie->txq[i]->stuck_timer);
1451         }
1452
1453         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1454          * before we wake up the command caller, to ensure a proper cleanup. */
1455         iwl_trans_fw_error(trans);
1456
1457         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1458         wake_up(&trans_pcie->wait_command_queue);
1459 }
1460
1461 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1462 {
1463         u32 inta;
1464
1465         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1466
1467         trace_iwlwifi_dev_irq(trans->dev);
1468
1469         /* Discover which interrupts are active/pending */
1470         inta = iwl_read32(trans, CSR_INT);
1471
1472         /* the thread will service interrupts and re-enable them */
1473         return inta;
1474 }
1475
1476 /* a device (PCI-E) page is 4096 bytes long */
1477 #define ICT_SHIFT       12
1478 #define ICT_SIZE        (1 << ICT_SHIFT)
1479 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1480
1481 /* interrupt handler using ict table, with this interrupt driver will
1482  * stop using INTA register to get device's interrupt, reading this register
1483  * is expensive, device will write interrupts in ICT dram table, increment
1484  * index then will fire interrupt to driver, driver will OR all ICT table
1485  * entries from current index up to table entry with 0 value. the result is
1486  * the interrupt we need to service, driver will set the entries back to 0 and
1487  * set index.
1488  */
1489 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1490 {
1491         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1492         u32 inta;
1493         u32 val = 0;
1494         u32 read;
1495
1496         trace_iwlwifi_dev_irq(trans->dev);
1497
1498         /* Ignore interrupt if there's nothing in NIC to service.
1499          * This may be due to IRQ shared with another device,
1500          * or due to sporadic interrupts thrown from our NIC. */
1501         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1502         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1503         if (!read)
1504                 return 0;
1505
1506         /*
1507          * Collect all entries up to the first 0, starting from ict_index;
1508          * note we already read at ict_index.
1509          */
1510         do {
1511                 val |= read;
1512                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1513                                 trans_pcie->ict_index, read);
1514                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1515                 trans_pcie->ict_index =
1516                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1517
1518                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1519                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1520                                            read);
1521         } while (read);
1522
1523         /* We should not get this value, just ignore it. */
1524         if (val == 0xffffffff)
1525                 val = 0;
1526
1527         /*
1528          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1529          * (bit 15 before shifting it to 31) to clear when using interrupt
1530          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1531          * so we use them to decide on the real state of the Rx bit.
1532          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1533          */
1534         if (val & 0xC0000)
1535                 val |= 0x8000;
1536
1537         inta = (0xff & val) | ((0xff00 & val) << 16);
1538         return inta;
1539 }
1540
1541 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans)
1542 {
1543         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1544         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1545         bool hw_rfkill, prev, report;
1546
1547         mutex_lock(&trans_pcie->mutex);
1548         prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1549         hw_rfkill = iwl_is_rfkill_set(trans);
1550         if (hw_rfkill) {
1551                 set_bit(STATUS_RFKILL_OPMODE, &trans->status);
1552                 set_bit(STATUS_RFKILL_HW, &trans->status);
1553         }
1554         if (trans_pcie->opmode_down)
1555                 report = hw_rfkill;
1556         else
1557                 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status);
1558
1559         IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1560                  hw_rfkill ? "disable radio" : "enable radio");
1561
1562         isr_stats->rfkill++;
1563
1564         if (prev != report)
1565                 iwl_trans_pcie_rf_kill(trans, report);
1566         mutex_unlock(&trans_pcie->mutex);
1567
1568         if (hw_rfkill) {
1569                 if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1570                                        &trans->status))
1571                         IWL_DEBUG_RF_KILL(trans,
1572                                           "Rfkill while SYNC HCMD in flight\n");
1573                 wake_up(&trans_pcie->wait_command_queue);
1574         } else {
1575                 clear_bit(STATUS_RFKILL_HW, &trans->status);
1576                 if (trans_pcie->opmode_down)
1577                         clear_bit(STATUS_RFKILL_OPMODE, &trans->status);
1578         }
1579 }
1580
1581 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1582 {
1583         struct iwl_trans *trans = dev_id;
1584         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1585         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1586         u32 inta = 0;
1587         u32 handled = 0;
1588
1589         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1590
1591         spin_lock(&trans_pcie->irq_lock);
1592
1593         /* dram interrupt table not set yet,
1594          * use legacy interrupt.
1595          */
1596         if (likely(trans_pcie->use_ict))
1597                 inta = iwl_pcie_int_cause_ict(trans);
1598         else
1599                 inta = iwl_pcie_int_cause_non_ict(trans);
1600
1601         if (iwl_have_debug_level(IWL_DL_ISR)) {
1602                 IWL_DEBUG_ISR(trans,
1603                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1604                               inta, trans_pcie->inta_mask,
1605                               iwl_read32(trans, CSR_INT_MASK),
1606                               iwl_read32(trans, CSR_FH_INT_STATUS));
1607                 if (inta & (~trans_pcie->inta_mask))
1608                         IWL_DEBUG_ISR(trans,
1609                                       "We got a masked interrupt (0x%08x)\n",
1610                                       inta & (~trans_pcie->inta_mask));
1611         }
1612
1613         inta &= trans_pcie->inta_mask;
1614
1615         /*
1616          * Ignore interrupt if there's nothing in NIC to service.
1617          * This may be due to IRQ shared with another device,
1618          * or due to sporadic interrupts thrown from our NIC.
1619          */
1620         if (unlikely(!inta)) {
1621                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1622                 /*
1623                  * Re-enable interrupts here since we don't
1624                  * have anything to service
1625                  */
1626                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1627                         _iwl_enable_interrupts(trans);
1628                 spin_unlock(&trans_pcie->irq_lock);
1629                 lock_map_release(&trans->sync_cmd_lockdep_map);
1630                 return IRQ_NONE;
1631         }
1632
1633         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1634                 /*
1635                  * Hardware disappeared. It might have
1636                  * already raised an interrupt.
1637                  */
1638                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1639                 spin_unlock(&trans_pcie->irq_lock);
1640                 goto out;
1641         }
1642
1643         /* Ack/clear/reset pending uCode interrupts.
1644          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1645          */
1646         /* There is a hardware bug in the interrupt mask function that some
1647          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1648          * they are disabled in the CSR_INT_MASK register. Furthermore the
1649          * ICT interrupt handling mechanism has another bug that might cause
1650          * these unmasked interrupts fail to be detected. We workaround the
1651          * hardware bugs here by ACKing all the possible interrupts so that
1652          * interrupt coalescing can still be achieved.
1653          */
1654         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1655
1656         if (iwl_have_debug_level(IWL_DL_ISR))
1657                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1658                               inta, iwl_read32(trans, CSR_INT_MASK));
1659
1660         spin_unlock(&trans_pcie->irq_lock);
1661
1662         /* Now service all interrupt bits discovered above. */
1663         if (inta & CSR_INT_BIT_HW_ERR) {
1664                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1665
1666                 /* Tell the device to stop sending interrupts */
1667                 iwl_disable_interrupts(trans);
1668
1669                 isr_stats->hw++;
1670                 iwl_pcie_irq_handle_error(trans);
1671
1672                 handled |= CSR_INT_BIT_HW_ERR;
1673
1674                 goto out;
1675         }
1676
1677         /* NIC fires this, but we don't use it, redundant with WAKEUP */
1678         if (inta & CSR_INT_BIT_SCD) {
1679                 IWL_DEBUG_ISR(trans,
1680                               "Scheduler finished to transmit the frame/frames.\n");
1681                 isr_stats->sch++;
1682         }
1683
1684         /* Alive notification via Rx interrupt will do the real work */
1685         if (inta & CSR_INT_BIT_ALIVE) {
1686                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1687                 isr_stats->alive++;
1688                 if (trans->cfg->gen2) {
1689                         /*
1690                          * We can restock, since firmware configured
1691                          * the RFH
1692                          */
1693                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
1694                 }
1695         }
1696
1697         /* Safely ignore these bits for debug checks below */
1698         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1699
1700         /* HW RF KILL switch toggled */
1701         if (inta & CSR_INT_BIT_RF_KILL) {
1702                 iwl_pcie_handle_rfkill_irq(trans);
1703                 handled |= CSR_INT_BIT_RF_KILL;
1704         }
1705
1706         /* Chip got too hot and stopped itself */
1707         if (inta & CSR_INT_BIT_CT_KILL) {
1708                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1709                 isr_stats->ctkill++;
1710                 handled |= CSR_INT_BIT_CT_KILL;
1711         }
1712
1713         /* Error detected by uCode */
1714         if (inta & CSR_INT_BIT_SW_ERR) {
1715                 IWL_ERR(trans, "Microcode SW error detected. "
1716                         " Restarting 0x%X.\n", inta);
1717                 isr_stats->sw++;
1718                 iwl_pcie_irq_handle_error(trans);
1719                 handled |= CSR_INT_BIT_SW_ERR;
1720         }
1721
1722         /* uCode wakes up after power-down sleep */
1723         if (inta & CSR_INT_BIT_WAKEUP) {
1724                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1725                 iwl_pcie_rxq_check_wrptr(trans);
1726                 iwl_pcie_txq_check_wrptrs(trans);
1727
1728                 isr_stats->wakeup++;
1729
1730                 handled |= CSR_INT_BIT_WAKEUP;
1731         }
1732
1733         /* All uCode command responses, including Tx command responses,
1734          * Rx "responses" (frame-received notification), and other
1735          * notifications from uCode come through here*/
1736         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1737                     CSR_INT_BIT_RX_PERIODIC)) {
1738                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1739                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1740                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1741                         iwl_write32(trans, CSR_FH_INT_STATUS,
1742                                         CSR_FH_INT_RX_MASK);
1743                 }
1744                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1745                         handled |= CSR_INT_BIT_RX_PERIODIC;
1746                         iwl_write32(trans,
1747                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1748                 }
1749                 /* Sending RX interrupt require many steps to be done in the
1750                  * the device:
1751                  * 1- write interrupt to current index in ICT table.
1752                  * 2- dma RX frame.
1753                  * 3- update RX shared data to indicate last write index.
1754                  * 4- send interrupt.
1755                  * This could lead to RX race, driver could receive RX interrupt
1756                  * but the shared data changes does not reflect this;
1757                  * periodic interrupt will detect any dangling Rx activity.
1758                  */
1759
1760                 /* Disable periodic interrupt; we use it as just a one-shot. */
1761                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1762                             CSR_INT_PERIODIC_DIS);
1763
1764                 /*
1765                  * Enable periodic interrupt in 8 msec only if we received
1766                  * real RX interrupt (instead of just periodic int), to catch
1767                  * any dangling Rx interrupt.  If it was just the periodic
1768                  * interrupt, there was no dangling Rx activity, and no need
1769                  * to extend the periodic interrupt; one-shot is enough.
1770                  */
1771                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1772                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1773                                    CSR_INT_PERIODIC_ENA);
1774
1775                 isr_stats->rx++;
1776
1777                 local_bh_disable();
1778                 iwl_pcie_rx_handle(trans, 0);
1779                 local_bh_enable();
1780         }
1781
1782         /* This "Tx" DMA channel is used only for loading uCode */
1783         if (inta & CSR_INT_BIT_FH_TX) {
1784                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1785                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1786                 isr_stats->tx++;
1787                 handled |= CSR_INT_BIT_FH_TX;
1788                 /* Wake up uCode load routine, now that load is complete */
1789                 trans_pcie->ucode_write_complete = true;
1790                 wake_up(&trans_pcie->ucode_write_waitq);
1791         }
1792
1793         if (inta & ~handled) {
1794                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1795                 isr_stats->unhandled++;
1796         }
1797
1798         if (inta & ~(trans_pcie->inta_mask)) {
1799                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1800                          inta & ~trans_pcie->inta_mask);
1801         }
1802
1803         spin_lock(&trans_pcie->irq_lock);
1804         /* only Re-enable all interrupt if disabled by irq */
1805         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1806                 _iwl_enable_interrupts(trans);
1807         /* we are loading the firmware, enable FH_TX interrupt only */
1808         else if (handled & CSR_INT_BIT_FH_TX)
1809                 iwl_enable_fw_load_int(trans);
1810         /* Re-enable RF_KILL if it occurred */
1811         else if (handled & CSR_INT_BIT_RF_KILL)
1812                 iwl_enable_rfkill_int(trans);
1813         spin_unlock(&trans_pcie->irq_lock);
1814
1815 out:
1816         lock_map_release(&trans->sync_cmd_lockdep_map);
1817         return IRQ_HANDLED;
1818 }
1819
1820 /******************************************************************************
1821  *
1822  * ICT functions
1823  *
1824  ******************************************************************************/
1825
1826 /* Free dram table */
1827 void iwl_pcie_free_ict(struct iwl_trans *trans)
1828 {
1829         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1830
1831         if (trans_pcie->ict_tbl) {
1832                 dma_free_coherent(trans->dev, ICT_SIZE,
1833                                   trans_pcie->ict_tbl,
1834                                   trans_pcie->ict_tbl_dma);
1835                 trans_pcie->ict_tbl = NULL;
1836                 trans_pcie->ict_tbl_dma = 0;
1837         }
1838 }
1839
1840 /*
1841  * allocate dram shared table, it is an aligned memory
1842  * block of ICT_SIZE.
1843  * also reset all data related to ICT table interrupt.
1844  */
1845 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1846 {
1847         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1848
1849         trans_pcie->ict_tbl =
1850                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1851                                    &trans_pcie->ict_tbl_dma,
1852                                    GFP_KERNEL);
1853         if (!trans_pcie->ict_tbl)
1854                 return -ENOMEM;
1855
1856         /* just an API sanity check ... it is guaranteed to be aligned */
1857         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1858                 iwl_pcie_free_ict(trans);
1859                 return -EINVAL;
1860         }
1861
1862         return 0;
1863 }
1864
1865 /* Device is going up inform it about using ICT interrupt table,
1866  * also we need to tell the driver to start using ICT interrupt.
1867  */
1868 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1869 {
1870         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1871         u32 val;
1872
1873         if (!trans_pcie->ict_tbl)
1874                 return;
1875
1876         spin_lock(&trans_pcie->irq_lock);
1877         _iwl_disable_interrupts(trans);
1878
1879         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1880
1881         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1882
1883         val |= CSR_DRAM_INT_TBL_ENABLE |
1884                CSR_DRAM_INIT_TBL_WRAP_CHECK |
1885                CSR_DRAM_INIT_TBL_WRITE_POINTER;
1886
1887         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1888
1889         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1890         trans_pcie->use_ict = true;
1891         trans_pcie->ict_index = 0;
1892         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1893         _iwl_enable_interrupts(trans);
1894         spin_unlock(&trans_pcie->irq_lock);
1895 }
1896
1897 /* Device is going down disable ict interrupt usage */
1898 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1899 {
1900         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1901
1902         spin_lock(&trans_pcie->irq_lock);
1903         trans_pcie->use_ict = false;
1904         spin_unlock(&trans_pcie->irq_lock);
1905 }
1906
1907 irqreturn_t iwl_pcie_isr(int irq, void *data)
1908 {
1909         struct iwl_trans *trans = data;
1910
1911         if (!trans)
1912                 return IRQ_NONE;
1913
1914         /* Disable (but don't clear!) interrupts here to avoid
1915          * back-to-back ISRs and sporadic interrupts from our NIC.
1916          * If we have something to service, the tasklet will re-enable ints.
1917          * If we *don't* have something, we'll re-enable before leaving here.
1918          */
1919         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1920
1921         return IRQ_WAKE_THREAD;
1922 }
1923
1924 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
1925 {
1926         return IRQ_WAKE_THREAD;
1927 }
1928
1929 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
1930 {
1931         struct msix_entry *entry = dev_id;
1932         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1933         struct iwl_trans *trans = trans_pcie->trans;
1934         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1935         u32 inta_fh, inta_hw;
1936
1937         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1938
1939         spin_lock(&trans_pcie->irq_lock);
1940         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
1941         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
1942         /*
1943          * Clear causes registers to avoid being handling the same cause.
1944          */
1945         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
1946         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
1947         spin_unlock(&trans_pcie->irq_lock);
1948
1949         trace_iwlwifi_dev_irq_msix(trans->dev, entry, true, inta_fh, inta_hw);
1950
1951         if (unlikely(!(inta_fh | inta_hw))) {
1952                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1953                 lock_map_release(&trans->sync_cmd_lockdep_map);
1954                 return IRQ_NONE;
1955         }
1956
1957         if (iwl_have_debug_level(IWL_DL_ISR)) {
1958                 IWL_DEBUG_ISR(trans,
1959                               "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
1960                               inta_fh, trans_pcie->fh_mask,
1961                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
1962                 if (inta_fh & ~trans_pcie->fh_mask)
1963                         IWL_DEBUG_ISR(trans,
1964                                       "We got a masked interrupt (0x%08x)\n",
1965                                       inta_fh & ~trans_pcie->fh_mask);
1966         }
1967
1968         inta_fh &= trans_pcie->fh_mask;
1969
1970         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
1971             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
1972                 local_bh_disable();
1973                 iwl_pcie_rx_handle(trans, 0);
1974                 local_bh_enable();
1975         }
1976
1977         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
1978             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
1979                 local_bh_disable();
1980                 iwl_pcie_rx_handle(trans, 1);
1981                 local_bh_enable();
1982         }
1983
1984         /* This "Tx" DMA channel is used only for loading uCode */
1985         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
1986                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1987                 isr_stats->tx++;
1988                 /*
1989                  * Wake up uCode load routine,
1990                  * now that load is complete
1991                  */
1992                 trans_pcie->ucode_write_complete = true;
1993                 wake_up(&trans_pcie->ucode_write_waitq);
1994         }
1995
1996         /* Error detected by uCode */
1997         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
1998             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
1999                 IWL_ERR(trans,
2000                         "Microcode SW error detected. Restarting 0x%X.\n",
2001                         inta_fh);
2002                 isr_stats->sw++;
2003                 iwl_pcie_irq_handle_error(trans);
2004         }
2005
2006         /* After checking FH register check HW register */
2007         if (iwl_have_debug_level(IWL_DL_ISR)) {
2008                 IWL_DEBUG_ISR(trans,
2009                               "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
2010                               inta_hw, trans_pcie->hw_mask,
2011                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
2012                 if (inta_hw & ~trans_pcie->hw_mask)
2013                         IWL_DEBUG_ISR(trans,
2014                                       "We got a masked interrupt 0x%08x\n",
2015                                       inta_hw & ~trans_pcie->hw_mask);
2016         }
2017
2018         inta_hw &= trans_pcie->hw_mask;
2019
2020         /* Alive notification via Rx interrupt will do the real work */
2021         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
2022                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
2023                 isr_stats->alive++;
2024                 if (trans->cfg->gen2) {
2025                         /* We can restock, since firmware configured the RFH */
2026                         iwl_pcie_rxmq_restock(trans, trans_pcie->rxq);
2027                 }
2028         }
2029
2030         /* uCode wakes up after power-down sleep */
2031         if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
2032                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
2033                 iwl_pcie_rxq_check_wrptr(trans);
2034                 iwl_pcie_txq_check_wrptrs(trans);
2035
2036                 isr_stats->wakeup++;
2037         }
2038
2039         /* Chip got too hot and stopped itself */
2040         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
2041                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
2042                 isr_stats->ctkill++;
2043         }
2044
2045         /* HW RF KILL switch toggled */
2046         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL)
2047                 iwl_pcie_handle_rfkill_irq(trans);
2048
2049         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2050                 IWL_ERR(trans,
2051                         "Hardware error detected. Restarting.\n");
2052
2053                 isr_stats->hw++;
2054                 iwl_pcie_irq_handle_error(trans);
2055         }
2056
2057         iwl_pcie_clear_irq(trans, entry);
2058
2059         lock_map_release(&trans->sync_cmd_lockdep_map);
2060
2061         return IRQ_HANDLED;
2062 }