drivers/net/wireless/intel/iwlwifi/pcie/rx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2014 Intel Corporation. All rights reserved.
   4  * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
   5  * Copyright(c) 2016 Intel Deutschland GmbH
   6  *
   7  * Portions of this file are derived from the ipw3945 project, as well
   8  * as portions of the ieee80211 subsystem header files.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of version 2 of the GNU General Public License as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program; if not, write to the Free Software Foundation, Inc.,
  21  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  22  *
  23  * The full GNU General Public License is included in this distribution in the
  24  * file called LICENSE.
  25  *
  26  * Contact Information:
  27  *  Intel Linux Wireless <linuxwifi@intel.com>
  28  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  29  *
  30  *****************************************************************************/
  31 #include <linux/sched.h>
  32 #include <linux/wait.h>
  33 #include <linux/gfp.h>
  34
  35 #include "iwl-prph.h"
  36 #include "iwl-io.h"
  37 #include "internal.h"
  38 #include "iwl-op-mode.h"
  39
  40 /******************************************************************************
  41  *
  42  * RX path functions
  43  *
  44  ******************************************************************************/
  45
  46 /*
  47  * Rx theory of operation
  48  *
  49  * Driver allocates a circular buffer of Receive Buffer Descriptors (RBDs),
  50  * each of which point to Receive Buffers to be filled by the NIC.  These get
  51  * used not only for Rx frames, but for any command response or notification
  52  * from the NIC.  The driver and NIC manage the Rx buffers by means
  53  * of indexes into the circular buffer.
  54  *
  55  * Rx Queue Indexes
  56  * The host/firmware share two index registers for managing the Rx buffers.
  57  *
  58  * The READ index maps to the first position that the firmware may be writing
  59  * to -- the driver can read up to (but not including) this position and get
  60  * good data.
  61  * The READ index is managed by the firmware once the card is enabled.
  62  *
  63  * The WRITE index maps to the last position the driver has read from -- the
  64  * position preceding WRITE is the last slot the firmware can place a packet.
  65  *
  66  * The queue is empty (no good data) if WRITE = READ - 1, and is full if
  67  * WRITE = READ.
  68  *
  69  * During initialization, the host sets up the READ queue position to the first
  70  * INDEX position, and WRITE to the last (READ - 1 wrapped)
  71  *
  72  * When the firmware places a packet in a buffer, it will advance the READ index
  73  * and fire the RX interrupt.  The driver can then query the READ index and
  74  * process as many packets as possible, moving the WRITE index forward as it
  75  * resets the Rx queue buffers with new memory.
  76  *
  77  * The management in the driver is as follows:
  78  * + A list of pre-allocated RBDs is stored in iwl->rxq->rx_free.
  79  *   When the interrupt handler is called, the request is processed.
  80  *   The page is either stolen - transferred to the upper layer
  81  *   or reused - added immediately to the iwl->rxq->rx_free list.
  82  * + When the page is stolen - the driver updates the matching queue's used
  83  *   count, detaches the RBD and transfers it to the queue used list.
  84  *   When there are two used RBDs - they are transferred to the allocator empty
  85  *   list. Work is then scheduled for the allocator to start allocating
  86  *   eight buffers.
  87  *   When there are another 6 used RBDs - they are transferred to the allocator
  88  *   empty list and the driver tries to claim the pre-allocated buffers and
  89  *   add them to iwl->rxq->rx_free. If it fails - it continues to claim them
  90  *   until ready.
  91  *   When there are 8+ buffers in the free list - either from allocation or from
  92  *   8 reused unstolen pages - restock is called to update the FW and indexes.
  93  * + In order to make sure the allocator always has RBDs to use for allocation
  94  *   the allocator has initial pool in the size of num_queues*(8-2) - the
  95  *   maximum missing RBDs per allocation request (request posted with 2
  96  *    empty RBDs, there is no guarantee when the other 6 RBDs are supplied).
  97  *   The queues supplies the recycle of the rest of the RBDs.
  98  * + A received packet is processed and handed to the kernel network stack,
  99  *   detached from the iwl->rxq.  The driver 'processed' index is updated.
 100  * + If there are no allocated buffers in iwl->rxq->rx_free,
 101  *   the READ INDEX is not incremented and iwl->status(RX_STALLED) is set.
 102  *   If there were enough free buffers and RX_STALLED is set it is cleared.
 103  *
 104  *
 105  * Driver sequence:
 106  *
 107  * iwl_rxq_alloc()            Allocates rx_free
 108  * iwl_pcie_rx_replenish()    Replenishes rx_free list from rx_used, and calls
 109  *                            iwl_pcie_rxq_restock.
 110  *                            Used only during initialization.
 111  * iwl_pcie_rxq_restock()     Moves available buffers from rx_free into Rx
 112  *                            queue, updates firmware pointers, and updates
 113  *                            the WRITE index.
 114  * iwl_pcie_rx_allocator()     Background work for allocating pages.
 115  *
 116  * -- enable interrupts --
 117  * ISR - iwl_rx()             Detach iwl_rx_mem_buffers from pool up to the
 118  *                            READ INDEX, detaching the SKB from the pool.
 119  *                            Moves the packet buffer from queue to rx_used.
 120  *                            Posts and claims requests to the allocator.
 121  *                            Calls iwl_pcie_rxq_restock to refill any empty
 122  *                            slots.
 123  *
 124  * RBD life-cycle:
 125  *
 126  * Init:
 127  * rxq.pool -> rxq.rx_used -> rxq.rx_free -> rxq.queue
 128  *
 129  * Regular Receive interrupt:
 130  * Page Stolen:
 131  * rxq.queue -> rxq.rx_used -> allocator.rbd_empty ->
 132  * allocator.rbd_allocated -> rxq.rx_free -> rxq.queue
 133  * Page not Stolen:
 134  * rxq.queue -> rxq.rx_free -> rxq.queue
 135  * ...
 136  *
 137  */
 138
 139 /*
 140  * iwl_rxq_space - Return number of free slots available in queue.
 141  */
 142 static int iwl_rxq_space(const struct iwl_rxq *rxq)
 143 {
 144         /* Make sure rx queue size is a power of 2 */
 145         WARN_ON(rxq->queue_size & (rxq->queue_size - 1));
 146
 147         /*
 148          * There can be up to (RX_QUEUE_SIZE - 1) free slots, to avoid ambiguity
 149          * between empty and completely full queues.
 150          * The following is equivalent to modulo by RX_QUEUE_SIZE and is well
 151          * defined for negative dividends.
 152          */
 153         return (rxq->read - rxq->write - 1) & (rxq->queue_size - 1);
 154 }
 155
 156 /*
 157  * iwl_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
 158  */
 159 static inline __le32 iwl_pcie_dma_addr2rbd_ptr(dma_addr_t dma_addr)
 160 {
 161         return cpu_to_le32((u32)(dma_addr >> 8));
 162 }
 163
 164 /*
 165  * iwl_pcie_rx_stop - stops the Rx DMA
 166  */
 167 int iwl_pcie_rx_stop(struct iwl_trans *trans)
 168 {
 169         if (trans->cfg->mq_rx_supported) {
 170                 iwl_write_prph(trans, RFH_RXF_DMA_CFG, 0);
 171                 return iwl_poll_prph_bit(trans, RFH_GEN_STATUS,
 172                                            RXF_DMA_IDLE, RXF_DMA_IDLE, 1000);
 173         } else {
 174                 iwl_write_direct32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 175                 return iwl_poll_direct_bit(trans, FH_MEM_RSSR_RX_STATUS_REG,
 176                                            FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
 177                                            1000);
 178         }
 179 }
 180
 181 /*
 182  * iwl_pcie_rxq_inc_wr_ptr - Update the write pointer for the RX queue
 183  */
 184 static void iwl_pcie_rxq_inc_wr_ptr(struct iwl_trans *trans,
 185                                     struct iwl_rxq *rxq)
 186 {
 187         u32 reg;
 188
 189         lockdep_assert_held(&rxq->lock);
 190
 191         /*
 192          * explicitly wake up the NIC if:
 193          * 1. shadow registers aren't enabled
 194          * 2. there is a chance that the NIC is asleep
 195          */
 196         if (!trans->cfg->base_params->shadow_reg_enable &&
 197             test_bit(STATUS_TPOWER_PMI, &trans->status)) {
 198                 reg = iwl_read32(trans, CSR_UCODE_DRV_GP1);
 199
 200                 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
 201                         IWL_DEBUG_INFO(trans, "Rx queue requesting wakeup, GP1 = 0x%x\n",
 202                                        reg);
 203                         iwl_set_bit(trans, CSR_GP_CNTRL,
 204                                     CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 205                         rxq->need_update = true;
 206                         return;
 207                 }
 208         }
 209
 210         rxq->write_actual = round_down(rxq->write, 8);
 211         if (trans->cfg->mq_rx_supported)
 212                 iwl_write32(trans, RFH_Q_FRBDCB_WIDX_TRG(rxq->id),
 213                             rxq->write_actual);
 214         else
 215                 iwl_write32(trans, FH_RSCSR_CHNL0_WPTR, rxq->write_actual);
 216 }
 217
 218 static void iwl_pcie_rxq_check_wrptr(struct iwl_trans *trans)
 219 {
 220         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 221         int i;
 222
 223         for (i = 0; i < trans->num_rx_queues; i++) {
 224                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 225
 226                 if (!rxq->need_update)
 227                         continue;
 228                 spin_lock(&rxq->lock);
 229                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 230                 rxq->need_update = false;
 231                 spin_unlock(&rxq->lock);
 232         }
 233 }
 234
 235 /*
 236  * iwl_pcie_rxmq_restock - restock implementation for multi-queue rx
 237  */
 238 static void iwl_pcie_rxmq_restock(struct iwl_trans *trans,
 239                                   struct iwl_rxq *rxq)
 240 {
 241         struct iwl_rx_mem_buffer *rxb;
 242
 243         /*
 244          * If the device isn't enabled - no need to try to add buffers...
 245          * This can happen when we stop the device and still have an interrupt
 246          * pending. We stop the APM before we sync the interrupts because we
 247          * have to (see comment there). On the other hand, since the APM is
 248          * stopped, we cannot access the HW (in particular not prph).
 249          * So don't try to restock if the APM has been already stopped.
 250          */
 251         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 252                 return;
 253
 254         spin_lock(&rxq->lock);
 255         while (rxq->free_count) {
 256                 __le64 *bd = (__le64 *)rxq->bd;
 257
 258                 /* Get next free Rx buffer, remove from free list */
 259                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 260                                        list);
 261                 list_del(&rxb->list);
 262                 rxb->invalid = false;
 263                 /* 12 first bits are expected to be empty */
 264                 WARN_ON(rxb->page_dma & DMA_BIT_MASK(12));
 265                 /* Point to Rx buffer via next RBD in circular buffer */
 266                 bd[rxq->write] = cpu_to_le64(rxb->page_dma | rxb->vid);
 267                 rxq->write = (rxq->write + 1) & MQ_RX_TABLE_MASK;
 268                 rxq->free_count--;
 269         }
 270         spin_unlock(&rxq->lock);
 271
 272         /*
 273          * If we've added more space for the firmware to place data, tell it.
 274          * Increment device's write pointer in multiples of 8.
 275          */
 276         if (rxq->write_actual != (rxq->write & ~0x7)) {
 277                 spin_lock(&rxq->lock);
 278                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 279                 spin_unlock(&rxq->lock);
 280         }
 281 }
 282
 283 /*
 284  * iwl_pcie_rxsq_restock - restock implementation for single queue rx
 285  */
 286 static void iwl_pcie_rxsq_restock(struct iwl_trans *trans,
 287                                   struct iwl_rxq *rxq)
 288 {
 289         struct iwl_rx_mem_buffer *rxb;
 290
 291         /*
 292          * If the device isn't enabled - not need to try to add buffers...
 293          * This can happen when we stop the device and still have an interrupt
 294          * pending. We stop the APM before we sync the interrupts because we
 295          * have to (see comment there). On the other hand, since the APM is
 296          * stopped, we cannot access the HW (in particular not prph).
 297          * So don't try to restock if the APM has been already stopped.
 298          */
 299         if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status))
 300                 return;
 301
 302         spin_lock(&rxq->lock);
 303         while ((iwl_rxq_space(rxq) > 0) && (rxq->free_count)) {
 304                 __le32 *bd = (__le32 *)rxq->bd;
 305                 /* The overwritten rxb must be a used one */
 306                 rxb = rxq->queue[rxq->write];
 307                 BUG_ON(rxb && rxb->page);
 308
 309                 /* Get next free Rx buffer, remove from free list */
 310                 rxb = list_first_entry(&rxq->rx_free, struct iwl_rx_mem_buffer,
 311                                        list);
 312                 list_del(&rxb->list);
 313                 rxb->invalid = false;
 314
 315                 /* Point to Rx buffer via next RBD in circular buffer */
 316                 bd[rxq->write] = iwl_pcie_dma_addr2rbd_ptr(rxb->page_dma);
 317                 rxq->queue[rxq->write] = rxb;
 318                 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
 319                 rxq->free_count--;
 320         }
 321         spin_unlock(&rxq->lock);
 322
 323         /* If we've added more space for the firmware to place data, tell it.
 324          * Increment device's write pointer in multiples of 8. */
 325         if (rxq->write_actual != (rxq->write & ~0x7)) {
 326                 spin_lock(&rxq->lock);
 327                 iwl_pcie_rxq_inc_wr_ptr(trans, rxq);
 328                 spin_unlock(&rxq->lock);
 329         }
 330 }
 331
 332 /*
 333  * iwl_pcie_rxq_restock - refill RX queue from pre-allocated pool
 334  *
 335  * If there are slots in the RX queue that need to be restocked,
 336  * and we have free pre-allocated buffers, fill the ranks as much
 337  * as we can, pulling from rx_free.
 338  *
 339  * This moves the 'write' index forward to catch up with 'processed', and
 340  * also updates the memory address in the firmware to reference the new
 341  * target buffer.
 342  */
 343 static
 344 void iwl_pcie_rxq_restock(struct iwl_trans *trans, struct iwl_rxq *rxq)
 345 {
 346         if (trans->cfg->mq_rx_supported)
 347                 iwl_pcie_rxmq_restock(trans, rxq);
 348         else
 349                 iwl_pcie_rxsq_restock(trans, rxq);
 350 }
 351
 352 /*
 353  * iwl_pcie_rx_alloc_page - allocates and returns a page.
 354  *
 355  */
 356 static struct page *iwl_pcie_rx_alloc_page(struct iwl_trans *trans,
 357                                            gfp_t priority)
 358 {
 359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 360         struct page *page;
 361         gfp_t gfp_mask = priority;
 362
 363         if (trans_pcie->rx_page_order > 0)
 364                 gfp_mask |= __GFP_COMP;
 365
 366         /* Alloc a new receive buffer */
 367         page = alloc_pages(gfp_mask, trans_pcie->rx_page_order);
 368         if (!page) {
 369                 if (net_ratelimit())
 370                         IWL_DEBUG_INFO(trans, "alloc_pages failed, order: %d\n",
 371                                        trans_pcie->rx_page_order);
 372                 /*
 373                  * Issue an error if we don't have enough pre-allocated
 374                   * buffers.
 375 `                */
 376                 if (!(gfp_mask & __GFP_NOWARN) && net_ratelimit())
 377                         IWL_CRIT(trans,
 378                                  "Failed to alloc_pages\n");
 379                 return NULL;
 380         }
 381         return page;
 382 }
 383
 384 /*
 385  * iwl_pcie_rxq_alloc_rbs - allocate a page for each used RBD
 386  *
 387  * A used RBD is an Rx buffer that has been given to the stack. To use it again
 388  * a page must be allocated and the RBD must point to the page. This function
 389  * doesn't change the HW pointer but handles the list of pages that is used by
 390  * iwl_pcie_rxq_restock. The latter function will update the HW to use the newly
 391  * allocated buffers.
 392  */
 393 static void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority,
 394                                    struct iwl_rxq *rxq)
 395 {
 396         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 397         struct iwl_rx_mem_buffer *rxb;
 398         struct page *page;
 399
 400         while (1) {
 401                 spin_lock(&rxq->lock);
 402                 if (list_empty(&rxq->rx_used)) {
 403                         spin_unlock(&rxq->lock);
 404                         return;
 405                 }
 406                 spin_unlock(&rxq->lock);
 407
 408                 /* Alloc a new receive buffer */
 409                 page = iwl_pcie_rx_alloc_page(trans, priority);
 410                 if (!page)
 411                         return;
 412
 413                 spin_lock(&rxq->lock);
 414
 415                 if (list_empty(&rxq->rx_used)) {
 416                         spin_unlock(&rxq->lock);
 417                         __free_pages(page, trans_pcie->rx_page_order);
 418                         return;
 419                 }
 420                 rxb = list_first_entry(&rxq->rx_used, struct iwl_rx_mem_buffer,
 421                                        list);
 422                 list_del(&rxb->list);
 423                 spin_unlock(&rxq->lock);
 424
 425                 BUG_ON(rxb->page);
 426                 rxb->page = page;
 427                 /* Get physical address of the RB */
 428                 rxb->page_dma =
 429                         dma_map_page(trans->dev, page, 0,
 430                                      PAGE_SIZE << trans_pcie->rx_page_order,
 431                                      DMA_FROM_DEVICE);
 432                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 433                         rxb->page = NULL;
 434                         spin_lock(&rxq->lock);
 435                         list_add(&rxb->list, &rxq->rx_used);
 436                         spin_unlock(&rxq->lock);
 437                         __free_pages(page, trans_pcie->rx_page_order);
 438                         return;
 439                 }
 440
 441                 spin_lock(&rxq->lock);
 442
 443                 list_add_tail(&rxb->list, &rxq->rx_free);
 444                 rxq->free_count++;
 445
 446                 spin_unlock(&rxq->lock);
 447         }
 448 }
 449
 450 static void iwl_pcie_free_rbs_pool(struct iwl_trans *trans)
 451 {
 452         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 453         int i;
 454
 455         for (i = 0; i < RX_POOL_SIZE; i++) {
 456                 if (!trans_pcie->rx_pool[i].page)
 457                         continue;
 458                 dma_unmap_page(trans->dev, trans_pcie->rx_pool[i].page_dma,
 459                                PAGE_SIZE << trans_pcie->rx_page_order,
 460                                DMA_FROM_DEVICE);
 461                 __free_pages(trans_pcie->rx_pool[i].page,
 462                              trans_pcie->rx_page_order);
 463                 trans_pcie->rx_pool[i].page = NULL;
 464         }
 465 }
 466
 467 /*
 468  * iwl_pcie_rx_allocator - Allocates pages in the background for RX queues
 469  *
 470  * Allocates for each received request 8 pages
 471  * Called as a scheduled work item.
 472  */
 473 static void iwl_pcie_rx_allocator(struct iwl_trans *trans)
 474 {
 475         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 476         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 477         struct list_head local_empty;
 478         int pending = atomic_read(&rba->req_pending);
 479
 480         IWL_DEBUG_RX(trans, "Pending allocation requests = %d\n", pending);
 481
 482         /* If we were scheduled - there is at least one request */
 483         spin_lock(&rba->lock);
 484         /* swap out the rba->rbd_empty to a local list */
 485         list_replace_init(&rba->rbd_empty, &local_empty);
 486         spin_unlock(&rba->lock);
 487
 488         while (pending) {
 489                 int i;
 490                 LIST_HEAD(local_allocated);
 491                 gfp_t gfp_mask = GFP_KERNEL;
 492
 493                 /* Do not post a warning if there are only a few requests */
 494                 if (pending < RX_PENDING_WATERMARK)
 495                         gfp_mask |= __GFP_NOWARN;
 496
 497                 for (i = 0; i < RX_CLAIM_REQ_ALLOC;) {
 498                         struct iwl_rx_mem_buffer *rxb;
 499                         struct page *page;
 500
 501                         /* List should never be empty - each reused RBD is
 502                          * returned to the list, and initial pool covers any
 503                          * possible gap between the time the page is allocated
 504                          * to the time the RBD is added.
 505                          */
 506                         BUG_ON(list_empty(&local_empty));
 507                         /* Get the first rxb from the rbd list */
 508                         rxb = list_first_entry(&local_empty,
 509                                                struct iwl_rx_mem_buffer, list);
 510                         BUG_ON(rxb->page);
 511
 512                         /* Alloc a new receive buffer */
 513                         page = iwl_pcie_rx_alloc_page(trans, gfp_mask);
 514                         if (!page)
 515                                 continue;
 516                         rxb->page = page;
 517
 518                         /* Get physical address of the RB */
 519                         rxb->page_dma = dma_map_page(trans->dev, page, 0,
 520                                         PAGE_SIZE << trans_pcie->rx_page_order,
 521                                         DMA_FROM_DEVICE);
 522                         if (dma_mapping_error(trans->dev, rxb->page_dma)) {
 523                                 rxb->page = NULL;
 524                                 __free_pages(page, trans_pcie->rx_page_order);
 525                                 continue;
 526                         }
 527
 528                         /* move the allocated entry to the out list */
 529                         list_move(&rxb->list, &local_allocated);
 530                         i++;
 531                 }
 532
 533                 atomic_dec(&rba->req_pending);
 534                 pending--;
 535
 536                 if (!pending) {
 537                         pending = atomic_read(&rba->req_pending);
 538                         IWL_DEBUG_RX(trans,
 539                                      "Got more pending allocation requests = %d\n",
 540                                      pending);
 541                 }
 542
 543                 spin_lock(&rba->lock);
 544                 /* add the allocated rbds to the allocator allocated list */
 545                 list_splice_tail(&local_allocated, &rba->rbd_allocated);
 546                 /* get more empty RBDs for current pending requests */
 547                 list_splice_tail_init(&rba->rbd_empty, &local_empty);
 548                 spin_unlock(&rba->lock);
 549
 550                 atomic_inc(&rba->req_ready);
 551
 552         }
 553
 554         spin_lock(&rba->lock);
 555         /* return unused rbds to the allocator empty list */
 556         list_splice_tail(&local_empty, &rba->rbd_empty);
 557         spin_unlock(&rba->lock);
 558
 559         IWL_DEBUG_RX(trans, "%s, exit.\n", __func__);
 560 }
 561
 562 /*
 563  * iwl_pcie_rx_allocator_get - returns the pre-allocated pages
 564 .*
 565 .* Called by queue when the queue posted allocation request and
 566  * has freed 8 RBDs in order to restock itself.
 567  * This function directly moves the allocated RBs to the queue's ownership
 568  * and updates the relevant counters.
 569  */
 570 static void iwl_pcie_rx_allocator_get(struct iwl_trans *trans,
 571                                       struct iwl_rxq *rxq)
 572 {
 573         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 574         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 575         int i;
 576
 577         lockdep_assert_held(&rxq->lock);
 578
 579         /*
 580          * atomic_dec_if_positive returns req_ready - 1 for any scenario.
 581          * If req_ready is 0 atomic_dec_if_positive will return -1 and this
 582          * function will return early, as there are no ready requests.
 583          * atomic_dec_if_positive will perofrm the *actual* decrement only if
 584          * req_ready > 0, i.e. - there are ready requests and the function
 585          * hands one request to the caller.
 586          */
 587         if (atomic_dec_if_positive(&rba->req_ready) < 0)
 588                 return;
 589
 590         spin_lock(&rba->lock);
 591         for (i = 0; i < RX_CLAIM_REQ_ALLOC; i++) {
 592                 /* Get next free Rx buffer, remove it from free list */
 593                 struct iwl_rx_mem_buffer *rxb =
 594                         list_first_entry(&rba->rbd_allocated,
 595                                          struct iwl_rx_mem_buffer, list);
 596
 597                 list_move(&rxb->list, &rxq->rx_free);
 598         }
 599         spin_unlock(&rba->lock);
 600
 601         rxq->used_count -= RX_CLAIM_REQ_ALLOC;
 602         rxq->free_count += RX_CLAIM_REQ_ALLOC;
 603 }
 604
 605 static void iwl_pcie_rx_allocator_work(struct work_struct *data)
 606 {
 607         struct iwl_rb_allocator *rba_p =
 608                 container_of(data, struct iwl_rb_allocator, rx_alloc);
 609         struct iwl_trans_pcie *trans_pcie =
 610                 container_of(rba_p, struct iwl_trans_pcie, rba);
 611
 612         iwl_pcie_rx_allocator(trans_pcie->trans);
 613 }
 614
 615 static int iwl_pcie_rx_alloc(struct iwl_trans *trans)
 616 {
 617         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 618         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 619         struct device *dev = trans->dev;
 620         int i;
 621         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
 622                                                       sizeof(__le32);
 623
 624         if (WARN_ON(trans_pcie->rxq))
 625                 return -EINVAL;
 626
 627         trans_pcie->rxq = kcalloc(trans->num_rx_queues, sizeof(struct iwl_rxq),
 628                                   GFP_KERNEL);
 629         if (!trans_pcie->rxq)
 630                 return -EINVAL;
 631
 632         spin_lock_init(&rba->lock);
 633
 634         for (i = 0; i < trans->num_rx_queues; i++) {
 635                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 636
 637                 spin_lock_init(&rxq->lock);
 638                 if (trans->cfg->mq_rx_supported)
 639                         rxq->queue_size = MQ_RX_TABLE_SIZE;
 640                 else
 641                         rxq->queue_size = RX_QUEUE_SIZE;
 642
 643                 /*
 644                  * Allocate the circular buffer of Read Buffer Descriptors
 645                  * (RBDs)
 646                  */
 647                 rxq->bd = dma_zalloc_coherent(dev,
 648                                              free_size * rxq->queue_size,
 649                                              &rxq->bd_dma, GFP_KERNEL);
 650                 if (!rxq->bd)
 651                         goto err;
 652
 653                 if (trans->cfg->mq_rx_supported) {
 654                         rxq->used_bd = dma_zalloc_coherent(dev,
 655                                                            sizeof(__le32) *
 656                                                            rxq->queue_size,
 657                                                            &rxq->used_bd_dma,
 658                                                            GFP_KERNEL);
 659                         if (!rxq->used_bd)
 660                                 goto err;
 661                 }
 662
 663                 /*Allocate the driver's pointer to receive buffer status */
 664                 rxq->rb_stts = dma_zalloc_coherent(dev, sizeof(*rxq->rb_stts),
 665                                                    &rxq->rb_stts_dma,
 666                                                    GFP_KERNEL);
 667                 if (!rxq->rb_stts)
 668                         goto err;
 669         }
 670         return 0;
 671
 672 err:
 673         for (i = 0; i < trans->num_rx_queues; i++) {
 674                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 675
 676                 if (rxq->bd)
 677                         dma_free_coherent(dev, free_size * rxq->queue_size,
 678                                           rxq->bd, rxq->bd_dma);
 679                 rxq->bd_dma = 0;
 680                 rxq->bd = NULL;
 681
 682                 if (rxq->rb_stts)
 683                         dma_free_coherent(trans->dev,
 684                                           sizeof(struct iwl_rb_status),
 685                                           rxq->rb_stts, rxq->rb_stts_dma);
 686
 687                 if (rxq->used_bd)
 688                         dma_free_coherent(dev, sizeof(__le32) * rxq->queue_size,
 689                                           rxq->used_bd, rxq->used_bd_dma);
 690                 rxq->used_bd_dma = 0;
 691                 rxq->used_bd = NULL;
 692         }
 693         kfree(trans_pcie->rxq);
 694
 695         return -ENOMEM;
 696 }
 697
 698 static void iwl_pcie_rx_hw_init(struct iwl_trans *trans, struct iwl_rxq *rxq)
 699 {
 700         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 701         u32 rb_size;
 702         unsigned long flags;
 703         const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
 704
 705         switch (trans_pcie->rx_buf_size) {
 706         case IWL_AMSDU_4K:
 707                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 708                 break;
 709         case IWL_AMSDU_8K:
 710                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 711                 break;
 712         case IWL_AMSDU_12K:
 713                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_12K;
 714                 break;
 715         default:
 716                 WARN_ON(1);
 717                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 718         }
 719
 720         if (!iwl_trans_grab_nic_access(trans, &flags))
 721                 return;
 722
 723         /* Stop Rx DMA */
 724         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 725         /* reset and flush pointers */
 726         iwl_write32(trans, FH_MEM_RCSR_CHNL0_RBDCB_WPTR, 0);
 727         iwl_write32(trans, FH_MEM_RCSR_CHNL0_FLUSH_RB_REQ, 0);
 728         iwl_write32(trans, FH_RSCSR_CHNL0_RDPTR, 0);
 729
 730         /* Reset driver's Rx queue write index */
 731         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 732
 733         /* Tell device where to find RBD circular buffer in DRAM */
 734         iwl_write32(trans, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 735                     (u32)(rxq->bd_dma >> 8));
 736
 737         /* Tell device where in DRAM to update its Rx status */
 738         iwl_write32(trans, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 739                     rxq->rb_stts_dma >> 4);
 740
 741         /* Enable Rx DMA
 742          * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
 743          *      the credit mechanism in 5000 HW RX FIFO
 744          * Direct rx interrupts to hosts
 745          * Rx buffer size 4 or 8k or 12k
 746          * RB timeout 0x10
 747          * 256 RBDs
 748          */
 749         iwl_write32(trans, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 750                     FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 751                     FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
 752                     FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 753                     rb_size |
 754                     (RX_RB_TIMEOUT << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) |
 755                     (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
 756
 757         iwl_trans_release_nic_access(trans, &flags);
 758
 759         /* Set interrupt coalescing timer to default (2048 usecs) */
 760         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 761
 762         /* W/A for interrupt coalescing bug in 7260 and 3160 */
 763         if (trans->cfg->host_interrupt_operation_mode)
 764                 iwl_set_bit(trans, CSR_INT_COALESCING, IWL_HOST_INT_OPER_MODE);
 765 }
 766
 767 void iwl_pcie_enable_rx_wake(struct iwl_trans *trans, bool enable)
 768 {
 769         /*
 770          * Turn on the chicken-bits that cause MAC wakeup for RX-related
 771          * values.
 772          * This costs some power, but needed for W/A 9000 integrated A-step
 773          * bug where shadow registers are not in the retention list and their
 774          * value is lost when NIC powers down
 775          */
 776         if (trans->cfg->integrated) {
 777                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL,
 778                             CSR_MAC_SHADOW_REG_CTRL_RX_WAKE);
 779                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTL2,
 780                             CSR_MAC_SHADOW_REG_CTL2_RX_WAKE);
 781         }
 782 }
 783
 784 static void iwl_pcie_rx_mq_hw_init(struct iwl_trans *trans)
 785 {
 786         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 787         u32 rb_size, enabled = 0;
 788         unsigned long flags;
 789         int i;
 790
 791         switch (trans_pcie->rx_buf_size) {
 792         case IWL_AMSDU_4K:
 793                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 794                 break;
 795         case IWL_AMSDU_8K:
 796                 rb_size = RFH_RXF_DMA_RB_SIZE_8K;
 797                 break;
 798         case IWL_AMSDU_12K:
 799                 rb_size = RFH_RXF_DMA_RB_SIZE_12K;
 800                 break;
 801         default:
 802                 WARN_ON(1);
 803                 rb_size = RFH_RXF_DMA_RB_SIZE_4K;
 804         }
 805
 806         if (!iwl_trans_grab_nic_access(trans, &flags))
 807                 return;
 808
 809         /* Stop Rx DMA */
 810         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG, 0);
 811         /* disable free amd used rx queue operation */
 812         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, 0);
 813
 814         for (i = 0; i < trans->num_rx_queues; i++) {
 815                 /* Tell device where to find RBD free table in DRAM */
 816                 iwl_write_prph64_no_grab(trans,
 817                                          RFH_Q_FRBDCB_BA_LSB(i),
 818                                          trans_pcie->rxq[i].bd_dma);
 819                 /* Tell device where to find RBD used table in DRAM */
 820                 iwl_write_prph64_no_grab(trans,
 821                                          RFH_Q_URBDCB_BA_LSB(i),
 822                                          trans_pcie->rxq[i].used_bd_dma);
 823                 /* Tell device where in DRAM to update its Rx status */
 824                 iwl_write_prph64_no_grab(trans,
 825                                          RFH_Q_URBD_STTS_WPTR_LSB(i),
 826                                          trans_pcie->rxq[i].rb_stts_dma);
 827                 /* Reset device indice tables */
 828                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_WIDX(i), 0);
 829                 iwl_write_prph_no_grab(trans, RFH_Q_FRBDCB_RIDX(i), 0);
 830                 iwl_write_prph_no_grab(trans, RFH_Q_URBDCB_WIDX(i), 0);
 831
 832                 enabled |= BIT(i) | BIT(i + 16);
 833         }
 834
 835         /*
 836          * Enable Rx DMA
 837          * Rx buffer size 4 or 8k or 12k
 838          * Min RB size 4 or 8
 839          * Drop frames that exceed RB size
 840          * 512 RBDs
 841          */
 842         iwl_write_prph_no_grab(trans, RFH_RXF_DMA_CFG,
 843                                RFH_DMA_EN_ENABLE_VAL | rb_size |
 844                                RFH_RXF_DMA_MIN_RB_4_8 |
 845                                RFH_RXF_DMA_DROP_TOO_LARGE_MASK |
 846                                RFH_RXF_DMA_RBDCB_SIZE_512);
 847
 848         /*
 849          * Activate DMA snooping.
 850          * Set RX DMA chunk size to 64B for IOSF and 128B for PCIe
 851          * Default queue is 0
 852          */
 853         iwl_write_prph_no_grab(trans, RFH_GEN_CFG, RFH_GEN_CFG_RFH_DMA_SNOOP |
 854                                (DEFAULT_RXQ_NUM <<
 855                                 RFH_GEN_CFG_DEFAULT_RXQ_NUM_POS) |
 856                                RFH_GEN_CFG_SERVICE_DMA_SNOOP |
 857                                (trans->cfg->integrated ?
 858                                 RFH_GEN_CFG_RB_CHUNK_SIZE_64 :
 859                                 RFH_GEN_CFG_RB_CHUNK_SIZE_128) <<
 860                                RFH_GEN_CFG_RB_CHUNK_SIZE_POS);
 861         /* Enable the relevant rx queues */
 862         iwl_write_prph_no_grab(trans, RFH_RXF_RXQ_ACTIVE, enabled);
 863
 864         iwl_trans_release_nic_access(trans, &flags);
 865
 866         /* Set interrupt coalescing timer to default (2048 usecs) */
 867         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
 868
 869         iwl_pcie_enable_rx_wake(trans, true);
 870 }
 871
 872 static void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq)
 873 {
 874         lockdep_assert_held(&rxq->lock);
 875
 876         INIT_LIST_HEAD(&rxq->rx_free);
 877         INIT_LIST_HEAD(&rxq->rx_used);
 878         rxq->free_count = 0;
 879         rxq->used_count = 0;
 880 }
 881
 882 static int iwl_pcie_dummy_napi_poll(struct napi_struct *napi, int budget)
 883 {
 884         WARN_ON(1);
 885         return 0;
 886 }
 887
 888 int iwl_pcie_rx_init(struct iwl_trans *trans)
 889 {
 890         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 891         struct iwl_rxq *def_rxq;
 892         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 893         int i, err, queue_size, allocator_pool_size, num_alloc;
 894
 895         if (!trans_pcie->rxq) {
 896                 err = iwl_pcie_rx_alloc(trans);
 897                 if (err)
 898                         return err;
 899         }
 900         def_rxq = trans_pcie->rxq;
 901         if (!rba->alloc_wq) {
 902                 rba->alloc_wq = alloc_workqueue("rb_allocator",
 903                                                 WQ_HIGHPRI | WQ_UNBOUND, 1);
 904                 if (!rba->alloc_wq)
 905                         return -ENOMEM;
 906         }
 907
 908         INIT_WORK(&rba->rx_alloc, iwl_pcie_rx_allocator_work);
 909
 910         cancel_work_sync(&rba->rx_alloc);
 911
 912         spin_lock(&rba->lock);
 913         atomic_set(&rba->req_pending, 0);
 914         atomic_set(&rba->req_ready, 0);
 915         INIT_LIST_HEAD(&rba->rbd_allocated);
 916         INIT_LIST_HEAD(&rba->rbd_empty);
 917         spin_unlock(&rba->lock);
 918
 919         /* free all first - we might be reconfigured for a different size */
 920         iwl_pcie_free_rbs_pool(trans);
 921
 922         for (i = 0; i < RX_QUEUE_SIZE; i++)
 923                 def_rxq->queue[i] = NULL;
 924
 925         for (i = 0; i < trans->num_rx_queues; i++) {
 926                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
 927
 928                 rxq->id = i;
 929
 930                 spin_lock(&rxq->lock);
 931                 /*
 932                  * Set read write pointer to reflect that we have processed
 933                  * and used all buffers, but have not restocked the Rx queue
 934                  * with fresh buffers
 935                  */
 936                 rxq->read = 0;
 937                 rxq->write = 0;
 938                 rxq->write_actual = 0;
 939                 memset(rxq->rb_stts, 0, sizeof(*rxq->rb_stts));
 940
 941                 iwl_pcie_rx_init_rxb_lists(rxq);
 942
 943                 if (!rxq->napi.poll)
 944                         netif_napi_add(&trans_pcie->napi_dev, &rxq->napi,
 945                                        iwl_pcie_dummy_napi_poll, 64);
 946
 947                 spin_unlock(&rxq->lock);
 948         }
 949
 950         /* move the pool to the default queue and allocator ownerships */
 951         queue_size = trans->cfg->mq_rx_supported ?
 952                      MQ_RX_NUM_RBDS : RX_QUEUE_SIZE;
 953         allocator_pool_size = trans->num_rx_queues *
 954                 (RX_CLAIM_REQ_ALLOC - RX_POST_REQ_ALLOC);
 955         num_alloc = queue_size + allocator_pool_size;
 956         BUILD_BUG_ON(ARRAY_SIZE(trans_pcie->global_table) !=
 957                      ARRAY_SIZE(trans_pcie->rx_pool));
 958         for (i = 0; i < num_alloc; i++) {
 959                 struct iwl_rx_mem_buffer *rxb = &trans_pcie->rx_pool[i];
 960
 961                 if (i < allocator_pool_size)
 962                         list_add(&rxb->list, &rba->rbd_empty);
 963                 else
 964                         list_add(&rxb->list, &def_rxq->rx_used);
 965                 trans_pcie->global_table[i] = rxb;
 966                 rxb->vid = (u16)(i + 1);
 967                 rxb->invalid = true;
 968         }
 969
 970         iwl_pcie_rxq_alloc_rbs(trans, GFP_KERNEL, def_rxq);
 971
 972         if (trans->cfg->mq_rx_supported)
 973                 iwl_pcie_rx_mq_hw_init(trans);
 974         else
 975                 iwl_pcie_rx_hw_init(trans, def_rxq);
 976
 977         iwl_pcie_rxq_restock(trans, def_rxq);
 978
 979         spin_lock(&def_rxq->lock);
 980         iwl_pcie_rxq_inc_wr_ptr(trans, def_rxq);
 981         spin_unlock(&def_rxq->lock);
 982
 983         return 0;
 984 }
 985
 986 void iwl_pcie_rx_free(struct iwl_trans *trans)
 987 {
 988         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 989         struct iwl_rb_allocator *rba = &trans_pcie->rba;
 990         int free_size = trans->cfg->mq_rx_supported ? sizeof(__le64) :
 991                                               sizeof(__le32);
 992         int i;
 993
 994         /*
 995          * if rxq is NULL, it means that nothing has been allocated,
 996          * exit now
 997          */
 998         if (!trans_pcie->rxq) {
 999                 IWL_DEBUG_INFO(trans, "Free NULL rx context\n");
1000                 return;
1001         }
1002
1003         cancel_work_sync(&rba->rx_alloc);
1004         if (rba->alloc_wq) {
1005                 destroy_workqueue(rba->alloc_wq);
1006                 rba->alloc_wq = NULL;
1007         }
1008
1009         iwl_pcie_free_rbs_pool(trans);
1010
1011         for (i = 0; i < trans->num_rx_queues; i++) {
1012                 struct iwl_rxq *rxq = &trans_pcie->rxq[i];
1013
1014                 if (rxq->bd)
1015                         dma_free_coherent(trans->dev,
1016                                           free_size * rxq->queue_size,
1017                                           rxq->bd, rxq->bd_dma);
1018                 rxq->bd_dma = 0;
1019                 rxq->bd = NULL;
1020
1021                 if (rxq->rb_stts)
1022                         dma_free_coherent(trans->dev,
1023                                           sizeof(struct iwl_rb_status),
1024                                           rxq->rb_stts, rxq->rb_stts_dma);
1025                 else
1026                         IWL_DEBUG_INFO(trans,
1027                                        "Free rxq->rb_stts which is NULL\n");
1028
1029                 if (rxq->used_bd)
1030                         dma_free_coherent(trans->dev,
1031                                           sizeof(__le32) * rxq->queue_size,
1032                                           rxq->used_bd, rxq->used_bd_dma);
1033                 rxq->used_bd_dma = 0;
1034                 rxq->used_bd = NULL;
1035
1036                 if (rxq->napi.poll)
1037                         netif_napi_del(&rxq->napi);
1038         }
1039         kfree(trans_pcie->rxq);
1040 }
1041
1042 static void iwl_pcie_rx_move_to_allocator(struct iwl_rxq *rxq,
1043                                           struct iwl_rb_allocator *rba)
1044 {
1045         spin_lock(&rba->lock);
1046         list_splice_tail_init(&rxq->rx_used, &rba->rbd_empty);
1047         spin_unlock(&rba->lock);
1048 }
1049
1050 /*
1051  * iwl_pcie_rx_reuse_rbd - Recycle used RBDs
1052  *
1053  * Called when a RBD can be reused. The RBD is transferred to the allocator.
1054  * When there are 2 empty RBDs - a request for allocation is posted
1055  */
1056 static void iwl_pcie_rx_reuse_rbd(struct iwl_trans *trans,
1057                                   struct iwl_rx_mem_buffer *rxb,
1058                                   struct iwl_rxq *rxq, bool emergency)
1059 {
1060         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1061         struct iwl_rb_allocator *rba = &trans_pcie->rba;
1062
1063         /* Move the RBD to the used list, will be moved to allocator in batches
1064          * before claiming or posting a request*/
1065         list_add_tail(&rxb->list, &rxq->rx_used);
1066
1067         if (unlikely(emergency))
1068                 return;
1069
1070         /* Count the allocator owned RBDs */
1071         rxq->used_count++;
1072
1073         /* If we have RX_POST_REQ_ALLOC new released rx buffers -
1074          * issue a request for allocator. Modulo RX_CLAIM_REQ_ALLOC is
1075          * used for the case we failed to claim RX_CLAIM_REQ_ALLOC,
1076          * after but we still need to post another request.
1077          */
1078         if ((rxq->used_count % RX_CLAIM_REQ_ALLOC) == RX_POST_REQ_ALLOC) {
1079                 /* Move the 2 RBDs to the allocator ownership.
1080                  Allocator has another 6 from pool for the request completion*/
1081                 iwl_pcie_rx_move_to_allocator(rxq, rba);
1082
1083                 atomic_inc(&rba->req_pending);
1084                 queue_work(rba->alloc_wq, &rba->rx_alloc);
1085         }
1086 }
1087
1088 static void iwl_pcie_rx_handle_rb(struct iwl_trans *trans,
1089                                 struct iwl_rxq *rxq,
1090                                 struct iwl_rx_mem_buffer *rxb,
1091                                 bool emergency)
1092 {
1093         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1094         struct iwl_txq *txq = &trans_pcie->txq[trans_pcie->cmd_queue];
1095         bool page_stolen = false;
1096         int max_len = PAGE_SIZE << trans_pcie->rx_page_order;
1097         u32 offset = 0;
1098
1099         if (WARN_ON(!rxb))
1100                 return;
1101
1102         dma_unmap_page(trans->dev, rxb->page_dma, max_len, DMA_FROM_DEVICE);
1103
1104         while (offset + sizeof(u32) + sizeof(struct iwl_cmd_header) < max_len) {
1105                 struct iwl_rx_packet *pkt;
1106                 u16 sequence;
1107                 bool reclaim;
1108                 int index, cmd_index, len;
1109                 struct iwl_rx_cmd_buffer rxcb = {
1110                         ._offset = offset,
1111                         ._rx_page_order = trans_pcie->rx_page_order,
1112                         ._page = rxb->page,
1113                         ._page_stolen = false,
1114                         .truesize = max_len,
1115                 };
1116
1117                 pkt = rxb_addr(&rxcb);
1118
1119                 if (pkt->len_n_flags == cpu_to_le32(FH_RSCSR_FRAME_INVALID))
1120                         break;
1121
1122                 WARN_ON((le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_RXQ_MASK) >>
1123                         FH_RSCSR_RXQ_POS != rxq->id);
1124
1125                 IWL_DEBUG_RX(trans,
1126                              "cmd at offset %d: %s (%.2x.%2x, seq 0x%x)\n",
1127                              rxcb._offset,
1128                              iwl_get_cmd_string(trans,
1129                                                 iwl_cmd_id(pkt->hdr.cmd,
1130                                                            pkt->hdr.group_id,
1131                                                            0)),
1132                              pkt->hdr.group_id, pkt->hdr.cmd,
1133                              le16_to_cpu(pkt->hdr.sequence));
1134
1135                 len = iwl_rx_packet_len(pkt);
1136                 len += sizeof(u32); /* account for status word */
1137                 trace_iwlwifi_dev_rx(trans->dev, trans, pkt, len);
1138                 trace_iwlwifi_dev_rx_data(trans->dev, trans, pkt, len);
1139
1140                 /* Reclaim a command buffer only if this packet is a response
1141                  *   to a (driver-originated) command.
1142                  * If the packet (e.g. Rx frame) originated from uCode,
1143                  *   there is no command buffer to reclaim.
1144                  * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
1145                  *   but apparently a few don't get set; catch them here. */
1146                 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME);
1147                 if (reclaim) {
1148                         int i;
1149
1150                         for (i = 0; i < trans_pcie->n_no_reclaim_cmds; i++) {
1151                                 if (trans_pcie->no_reclaim_cmds[i] ==
1152                                                         pkt->hdr.cmd) {
1153                                         reclaim = false;
1154                                         break;
1155                                 }
1156                         }
1157                 }
1158
1159                 sequence = le16_to_cpu(pkt->hdr.sequence);
1160                 index = SEQ_TO_INDEX(sequence);
1161                 cmd_index = get_cmd_index(txq, index);
1162
1163                 if (rxq->id == 0)
1164                         iwl_op_mode_rx(trans->op_mode, &rxq->napi,
1165                                        &rxcb);
1166                 else
1167                         iwl_op_mode_rx_rss(trans->op_mode, &rxq->napi,
1168                                            &rxcb, rxq->id);
1169
1170                 if (reclaim) {
1171                         kzfree(txq->entries[cmd_index].free_buf);
1172                         txq->entries[cmd_index].free_buf = NULL;
1173                 }
1174
1175                 /*
1176                  * After here, we should always check rxcb._page_stolen,
1177                  * if it is true then one of the handlers took the page.
1178                  */
1179
1180                 if (reclaim) {
1181                         /* Invoke any callbacks, transfer the buffer to caller,
1182                          * and fire off the (possibly) blocking
1183                          * iwl_trans_send_cmd()
1184                          * as we reclaim the driver command queue */
1185                         if (!rxcb._page_stolen)
1186                                 iwl_pcie_hcmd_complete(trans, &rxcb);
1187                         else
1188                                 IWL_WARN(trans, "Claim null rxb?\n");
1189                 }
1190
1191                 page_stolen |= rxcb._page_stolen;
1192                 offset += ALIGN(len, FH_RSCSR_FRAME_ALIGN);
1193         }
1194
1195         /* page was stolen from us -- free our reference */
1196         if (page_stolen) {
1197                 __free_pages(rxb->page, trans_pcie->rx_page_order);
1198                 rxb->page = NULL;
1199         }
1200
1201         /* Reuse the page if possible. For notification packets and
1202          * SKBs that fail to Rx correctly, add them back into the
1203          * rx_free list for reuse later. */
1204         if (rxb->page != NULL) {
1205                 rxb->page_dma =
1206                         dma_map_page(trans->dev, rxb->page, 0,
1207                                      PAGE_SIZE << trans_pcie->rx_page_order,
1208                                      DMA_FROM_DEVICE);
1209                 if (dma_mapping_error(trans->dev, rxb->page_dma)) {
1210                         /*
1211                          * free the page(s) as well to not break
1212                          * the invariant that the items on the used
1213                          * list have no page(s)
1214                          */
1215                         __free_pages(rxb->page, trans_pcie->rx_page_order);
1216                         rxb->page = NULL;
1217                         iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1218                 } else {
1219                         list_add_tail(&rxb->list, &rxq->rx_free);
1220                         rxq->free_count++;
1221                 }
1222         } else
1223                 iwl_pcie_rx_reuse_rbd(trans, rxb, rxq, emergency);
1224 }
1225
1226 /*
1227  * iwl_pcie_rx_handle - Main entry function for receiving responses from fw
1228  */
1229 static void iwl_pcie_rx_handle(struct iwl_trans *trans, int queue)
1230 {
1231         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1232         struct iwl_rxq *rxq;
1233         u32 r, i, count = 0;
1234         bool emergency = false;
1235
1236         if (WARN_ON_ONCE(!trans_pcie->rxq || !trans_pcie->rxq[queue].bd))
1237                 return;
1238
1239         rxq = &trans_pcie->rxq[queue];
1240
1241 restart:
1242         spin_lock(&rxq->lock);
1243         /* uCode's read index (stored in shared DRAM) indicates the last Rx
1244          * buffer that the driver may process (last buffer filled by ucode). */
1245         r = le16_to_cpu(ACCESS_ONCE(rxq->rb_stts->closed_rb_num)) & 0x0FFF;
1246         i = rxq->read;
1247
1248         /* W/A 9000 device step A0 wrap-around bug */
1249         r &= (rxq->queue_size - 1);
1250
1251         /* Rx interrupt, but nothing sent from uCode */
1252         if (i == r)
1253                 IWL_DEBUG_RX(trans, "Q %d: HW = SW = %d\n", rxq->id, r);
1254
1255         while (i != r) {
1256                 struct iwl_rb_allocator *rba = &trans_pcie->rba;
1257                 struct iwl_rx_mem_buffer *rxb;
1258                 /* number of RBDs still waiting for page allocation */
1259                 u32 rb_pending_alloc =
1260                         atomic_read(&trans_pcie->rba.req_pending) *
1261                         RX_CLAIM_REQ_ALLOC;
1262
1263                 if (unlikely(rb_pending_alloc >= rxq->queue_size / 2 &&
1264                              !emergency)) {
1265                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1266                         emergency = true;
1267                 }
1268
1269                 if (trans->cfg->mq_rx_supported) {
1270                         /*
1271                          * used_bd is a 32 bit but only 12 are used to retrieve
1272                          * the vid
1273                          */
1274                         u16 vid = le32_to_cpu(rxq->used_bd[i]) & 0x0FFF;
1275
1276                         if (WARN(!vid ||
1277                                  vid > ARRAY_SIZE(trans_pcie->global_table),
1278                                  "Invalid rxb index from HW %u\n", (u32)vid)) {
1279                                 iwl_force_nmi(trans);
1280                                 goto out;
1281                         }
1282                         rxb = trans_pcie->global_table[vid - 1];
1283                         if (WARN(rxb->invalid,
1284                                  "Invalid rxb from HW %u\n", (u32)vid)) {
1285                                 iwl_force_nmi(trans);
1286                                 goto out;
1287                         }
1288                         rxb->invalid = true;
1289                 } else {
1290                         rxb = rxq->queue[i];
1291                         rxq->queue[i] = NULL;
1292                 }
1293
1294                 IWL_DEBUG_RX(trans, "Q %d: HW = %d, SW = %d\n", rxq->id, r, i);
1295                 iwl_pcie_rx_handle_rb(trans, rxq, rxb, emergency);
1296
1297                 i = (i + 1) & (rxq->queue_size - 1);
1298
1299                 /*
1300                  * If we have RX_CLAIM_REQ_ALLOC released rx buffers -
1301                  * try to claim the pre-allocated buffers from the allocator.
1302                  * If not ready - will try to reclaim next time.
1303                  * There is no need to reschedule work - allocator exits only
1304                  * on success
1305                  */
1306                 if (rxq->used_count >= RX_CLAIM_REQ_ALLOC)
1307                         iwl_pcie_rx_allocator_get(trans, rxq);
1308
1309                 if (rxq->used_count % RX_CLAIM_REQ_ALLOC == 0 && !emergency) {
1310                         /* Add the remaining empty RBDs for allocator use */
1311                         iwl_pcie_rx_move_to_allocator(rxq, rba);
1312                 } else if (emergency) {
1313                         count++;
1314                         if (count == 8) {
1315                                 count = 0;
1316                                 if (rb_pending_alloc < rxq->queue_size / 3)
1317                                         emergency = false;
1318
1319                                 rxq->read = i;
1320                                 spin_unlock(&rxq->lock);
1321                                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1322                                 iwl_pcie_rxq_restock(trans, rxq);
1323                                 goto restart;
1324                         }
1325                 }
1326         }
1327 out:
1328         /* Backtrack one entry */
1329         rxq->read = i;
1330         spin_unlock(&rxq->lock);
1331
1332         /*
1333          * handle a case where in emergency there are some unallocated RBDs.
1334          * those RBDs are in the used list, but are not tracked by the queue's
1335          * used_count which counts allocator owned RBDs.
1336          * unallocated emergency RBDs must be allocated on exit, otherwise
1337          * when called again the function may not be in emergency mode and
1338          * they will be handed to the allocator with no tracking in the RBD
1339          * allocator counters, which will lead to them never being claimed back
1340          * by the queue.
1341          * by allocating them here, they are now in the queue free list, and
1342          * will be restocked by the next call of iwl_pcie_rxq_restock.
1343          */
1344         if (unlikely(emergency && count))
1345                 iwl_pcie_rxq_alloc_rbs(trans, GFP_ATOMIC, rxq);
1346
1347         if (rxq->napi.poll)
1348                 napi_gro_flush(&rxq->napi, false);
1349
1350         iwl_pcie_rxq_restock(trans, rxq);
1351 }
1352
1353 static struct iwl_trans_pcie *iwl_pcie_get_trans_pcie(struct msix_entry *entry)
1354 {
1355         u8 queue = entry->entry;
1356         struct msix_entry *entries = entry - queue;
1357
1358         return container_of(entries, struct iwl_trans_pcie, msix_entries[0]);
1359 }
1360
1361 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans,
1362                                       struct msix_entry *entry)
1363 {
1364         /*
1365          * Before sending the interrupt the HW disables it to prevent
1366          * a nested interrupt. This is done by writing 1 to the corresponding
1367          * bit in the mask register. After handling the interrupt, it should be
1368          * re-enabled by clearing this bit. This register is defined as
1369          * write 1 clear (W1C) register, meaning that it's being clear
1370          * by writing 1 to the bit.
1371          */
1372         iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(entry->entry));
1373 }
1374
1375 /*
1376  * iwl_pcie_rx_msix_handle - Main entry function for receiving responses from fw
1377  * This interrupt handler should be used with RSS queue only.
1378  */
1379 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id)
1380 {
1381         struct msix_entry *entry = dev_id;
1382         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1383         struct iwl_trans *trans = trans_pcie->trans;
1384
1385         if (WARN_ON(entry->entry >= trans->num_rx_queues))
1386                 return IRQ_NONE;
1387
1388         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1389
1390         local_bh_disable();
1391         iwl_pcie_rx_handle(trans, entry->entry);
1392         local_bh_enable();
1393
1394         iwl_pcie_clear_irq(trans, entry);
1395
1396         lock_map_release(&trans->sync_cmd_lockdep_map);
1397
1398         return IRQ_HANDLED;
1399 }
1400
1401 /*
1402  * iwl_pcie_irq_handle_error - called for HW or SW error interrupt from card
1403  */
1404 static void iwl_pcie_irq_handle_error(struct iwl_trans *trans)
1405 {
1406         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1407         int i;
1408
1409         /* W/A for WiFi/WiMAX coex and WiMAX own the RF */
1410         if (trans->cfg->internal_wimax_coex &&
1411             !trans->cfg->apmg_not_supported &&
1412             (!(iwl_read_prph(trans, APMG_CLK_CTRL_REG) &
1413                              APMS_CLK_VAL_MRB_FUNC_MODE) ||
1414              (iwl_read_prph(trans, APMG_PS_CTRL_REG) &
1415                             APMG_PS_CTRL_VAL_RESET_REQ))) {
1416                 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1417                 iwl_op_mode_wimax_active(trans->op_mode);
1418                 wake_up(&trans_pcie->wait_command_queue);
1419                 return;
1420         }
1421
1422         iwl_pcie_dump_csr(trans);
1423         iwl_dump_fh(trans, NULL);
1424
1425         local_bh_disable();
1426         /* The STATUS_FW_ERROR bit is set in this function. This must happen
1427          * before we wake up the command caller, to ensure a proper cleanup. */
1428         iwl_trans_fw_error(trans);
1429         local_bh_enable();
1430
1431         for (i = 0; i < trans->cfg->base_params->num_of_queues; i++)
1432                 del_timer(&trans_pcie->txq[i].stuck_timer);
1433
1434         clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status);
1435         wake_up(&trans_pcie->wait_command_queue);
1436 }
1437
1438 static u32 iwl_pcie_int_cause_non_ict(struct iwl_trans *trans)
1439 {
1440         u32 inta;
1441
1442         lockdep_assert_held(&IWL_TRANS_GET_PCIE_TRANS(trans)->irq_lock);
1443
1444         trace_iwlwifi_dev_irq(trans->dev);
1445
1446         /* Discover which interrupts are active/pending */
1447         inta = iwl_read32(trans, CSR_INT);
1448
1449         /* the thread will service interrupts and re-enable them */
1450         return inta;
1451 }
1452
1453 /* a device (PCI-E) page is 4096 bytes long */
1454 #define ICT_SHIFT       12
1455 #define ICT_SIZE        (1 << ICT_SHIFT)
1456 #define ICT_COUNT       (ICT_SIZE / sizeof(u32))
1457
1458 /* interrupt handler using ict table, with this interrupt driver will
1459  * stop using INTA register to get device's interrupt, reading this register
1460  * is expensive, device will write interrupts in ICT dram table, increment
1461  * index then will fire interrupt to driver, driver will OR all ICT table
1462  * entries from current index up to table entry with 0 value. the result is
1463  * the interrupt we need to service, driver will set the entries back to 0 and
1464  * set index.
1465  */
1466 static u32 iwl_pcie_int_cause_ict(struct iwl_trans *trans)
1467 {
1468         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1469         u32 inta;
1470         u32 val = 0;
1471         u32 read;
1472
1473         trace_iwlwifi_dev_irq(trans->dev);
1474
1475         /* Ignore interrupt if there's nothing in NIC to service.
1476          * This may be due to IRQ shared with another device,
1477          * or due to sporadic interrupts thrown from our NIC. */
1478         read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1479         trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index, read);
1480         if (!read)
1481                 return 0;
1482
1483         /*
1484          * Collect all entries up to the first 0, starting from ict_index;
1485          * note we already read at ict_index.
1486          */
1487         do {
1488                 val |= read;
1489                 IWL_DEBUG_ISR(trans, "ICT index %d value 0x%08X\n",
1490                                 trans_pcie->ict_index, read);
1491                 trans_pcie->ict_tbl[trans_pcie->ict_index] = 0;
1492                 trans_pcie->ict_index =
1493                         ((trans_pcie->ict_index + 1) & (ICT_COUNT - 1));
1494
1495                 read = le32_to_cpu(trans_pcie->ict_tbl[trans_pcie->ict_index]);
1496                 trace_iwlwifi_dev_ict_read(trans->dev, trans_pcie->ict_index,
1497                                            read);
1498         } while (read);
1499
1500         /* We should not get this value, just ignore it. */
1501         if (val == 0xffffffff)
1502                 val = 0;
1503
1504         /*
1505          * this is a w/a for a h/w bug. the h/w bug may cause the Rx bit
1506          * (bit 15 before shifting it to 31) to clear when using interrupt
1507          * coalescing. fortunately, bits 18 and 19 stay set when this happens
1508          * so we use them to decide on the real state of the Rx bit.
1509          * In order words, bit 15 is set if bit 18 or bit 19 are set.
1510          */
1511         if (val & 0xC0000)
1512                 val |= 0x8000;
1513
1514         inta = (0xff & val) | ((0xff00 & val) << 16);
1515         return inta;
1516 }
1517
1518 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id)
1519 {
1520         struct iwl_trans *trans = dev_id;
1521         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1522         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1523         u32 inta = 0;
1524         u32 handled = 0;
1525
1526         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1527
1528         spin_lock(&trans_pcie->irq_lock);
1529
1530         /* dram interrupt table not set yet,
1531          * use legacy interrupt.
1532          */
1533         if (likely(trans_pcie->use_ict))
1534                 inta = iwl_pcie_int_cause_ict(trans);
1535         else
1536                 inta = iwl_pcie_int_cause_non_ict(trans);
1537
1538         if (iwl_have_debug_level(IWL_DL_ISR)) {
1539                 IWL_DEBUG_ISR(trans,
1540                               "ISR inta 0x%08x, enabled 0x%08x(sw), enabled(hw) 0x%08x, fh 0x%08x\n",
1541                               inta, trans_pcie->inta_mask,
1542                               iwl_read32(trans, CSR_INT_MASK),
1543                               iwl_read32(trans, CSR_FH_INT_STATUS));
1544                 if (inta & (~trans_pcie->inta_mask))
1545                         IWL_DEBUG_ISR(trans,
1546                                       "We got a masked interrupt (0x%08x)\n",
1547                                       inta & (~trans_pcie->inta_mask));
1548         }
1549
1550         inta &= trans_pcie->inta_mask;
1551
1552         /*
1553          * Ignore interrupt if there's nothing in NIC to service.
1554          * This may be due to IRQ shared with another device,
1555          * or due to sporadic interrupts thrown from our NIC.
1556          */
1557         if (unlikely(!inta)) {
1558                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1559                 /*
1560                  * Re-enable interrupts here since we don't
1561                  * have anything to service
1562                  */
1563                 if (test_bit(STATUS_INT_ENABLED, &trans->status))
1564                         _iwl_enable_interrupts(trans);
1565                 spin_unlock(&trans_pcie->irq_lock);
1566                 lock_map_release(&trans->sync_cmd_lockdep_map);
1567                 return IRQ_NONE;
1568         }
1569
1570         if (unlikely(inta == 0xFFFFFFFF || (inta & 0xFFFFFFF0) == 0xa5a5a5a0)) {
1571                 /*
1572                  * Hardware disappeared. It might have
1573                  * already raised an interrupt.
1574                  */
1575                 IWL_WARN(trans, "HARDWARE GONE?? INTA == 0x%08x\n", inta);
1576                 spin_unlock(&trans_pcie->irq_lock);
1577                 goto out;
1578         }
1579
1580         /* Ack/clear/reset pending uCode interrupts.
1581          * Note:  Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1582          */
1583         /* There is a hardware bug in the interrupt mask function that some
1584          * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
1585          * they are disabled in the CSR_INT_MASK register. Furthermore the
1586          * ICT interrupt handling mechanism has another bug that might cause
1587          * these unmasked interrupts fail to be detected. We workaround the
1588          * hardware bugs here by ACKing all the possible interrupts so that
1589          * interrupt coalescing can still be achieved.
1590          */
1591         iwl_write32(trans, CSR_INT, inta | ~trans_pcie->inta_mask);
1592
1593         if (iwl_have_debug_level(IWL_DL_ISR))
1594                 IWL_DEBUG_ISR(trans, "inta 0x%08x, enabled 0x%08x\n",
1595                               inta, iwl_read32(trans, CSR_INT_MASK));
1596
1597         spin_unlock(&trans_pcie->irq_lock);
1598
1599         /* Now service all interrupt bits discovered above. */
1600         if (inta & CSR_INT_BIT_HW_ERR) {
1601                 IWL_ERR(trans, "Hardware error detected.  Restarting.\n");
1602
1603                 /* Tell the device to stop sending interrupts */
1604                 iwl_disable_interrupts(trans);
1605
1606                 isr_stats->hw++;
1607                 iwl_pcie_irq_handle_error(trans);
1608
1609                 handled |= CSR_INT_BIT_HW_ERR;
1610
1611                 goto out;
1612         }
1613
1614         if (iwl_have_debug_level(IWL_DL_ISR)) {
1615                 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1616                 if (inta & CSR_INT_BIT_SCD) {
1617                         IWL_DEBUG_ISR(trans,
1618                                       "Scheduler finished to transmit the frame/frames.\n");
1619                         isr_stats->sch++;
1620                 }
1621
1622                 /* Alive notification via Rx interrupt will do the real work */
1623                 if (inta & CSR_INT_BIT_ALIVE) {
1624                         IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1625                         isr_stats->alive++;
1626                 }
1627         }
1628
1629         /* Safely ignore these bits for debug checks below */
1630         inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1631
1632         /* HW RF KILL switch toggled */
1633         if (inta & CSR_INT_BIT_RF_KILL) {
1634                 bool hw_rfkill;
1635
1636                 hw_rfkill = iwl_is_rfkill_set(trans);
1637                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1638                          hw_rfkill ? "disable radio" : "enable radio");
1639
1640                 isr_stats->rfkill++;
1641
1642                 mutex_lock(&trans_pcie->mutex);
1643                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
1644                 mutex_unlock(&trans_pcie->mutex);
1645                 if (hw_rfkill) {
1646                         set_bit(STATUS_RFKILL, &trans->status);
1647                         if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
1648                                                &trans->status))
1649                                 IWL_DEBUG_RF_KILL(trans,
1650                                                   "Rfkill while SYNC HCMD in flight\n");
1651                         wake_up(&trans_pcie->wait_command_queue);
1652                 } else {
1653                         clear_bit(STATUS_RFKILL, &trans->status);
1654                 }
1655
1656                 handled |= CSR_INT_BIT_RF_KILL;
1657         }
1658
1659         /* Chip got too hot and stopped itself */
1660         if (inta & CSR_INT_BIT_CT_KILL) {
1661                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1662                 isr_stats->ctkill++;
1663                 handled |= CSR_INT_BIT_CT_KILL;
1664         }
1665
1666         /* Error detected by uCode */
1667         if (inta & CSR_INT_BIT_SW_ERR) {
1668                 IWL_ERR(trans, "Microcode SW error detected. "
1669                         " Restarting 0x%X.\n", inta);
1670                 isr_stats->sw++;
1671                 iwl_pcie_irq_handle_error(trans);
1672                 handled |= CSR_INT_BIT_SW_ERR;
1673         }
1674
1675         /* uCode wakes up after power-down sleep */
1676         if (inta & CSR_INT_BIT_WAKEUP) {
1677                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1678                 iwl_pcie_rxq_check_wrptr(trans);
1679                 iwl_pcie_txq_check_wrptrs(trans);
1680
1681                 isr_stats->wakeup++;
1682
1683                 handled |= CSR_INT_BIT_WAKEUP;
1684         }
1685
1686         /* All uCode command responses, including Tx command responses,
1687          * Rx "responses" (frame-received notification), and other
1688          * notifications from uCode come through here*/
1689         if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1690                     CSR_INT_BIT_RX_PERIODIC)) {
1691                 IWL_DEBUG_ISR(trans, "Rx interrupt\n");
1692                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1693                         handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1694                         iwl_write32(trans, CSR_FH_INT_STATUS,
1695                                         CSR_FH_INT_RX_MASK);
1696                 }
1697                 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1698                         handled |= CSR_INT_BIT_RX_PERIODIC;
1699                         iwl_write32(trans,
1700                                 CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1701                 }
1702                 /* Sending RX interrupt require many steps to be done in the
1703                  * the device:
1704                  * 1- write interrupt to current index in ICT table.
1705                  * 2- dma RX frame.
1706                  * 3- update RX shared data to indicate last write index.
1707                  * 4- send interrupt.
1708                  * This could lead to RX race, driver could receive RX interrupt
1709                  * but the shared data changes does not reflect this;
1710                  * periodic interrupt will detect any dangling Rx activity.
1711                  */
1712
1713                 /* Disable periodic interrupt; we use it as just a one-shot. */
1714                 iwl_write8(trans, CSR_INT_PERIODIC_REG,
1715                             CSR_INT_PERIODIC_DIS);
1716
1717                 /*
1718                  * Enable periodic interrupt in 8 msec only if we received
1719                  * real RX interrupt (instead of just periodic int), to catch
1720                  * any dangling Rx interrupt.  If it was just the periodic
1721                  * interrupt, there was no dangling Rx activity, and no need
1722                  * to extend the periodic interrupt; one-shot is enough.
1723                  */
1724                 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1725                         iwl_write8(trans, CSR_INT_PERIODIC_REG,
1726                                    CSR_INT_PERIODIC_ENA);
1727
1728                 isr_stats->rx++;
1729
1730                 local_bh_disable();
1731                 iwl_pcie_rx_handle(trans, 0);
1732                 local_bh_enable();
1733         }
1734
1735         /* This "Tx" DMA channel is used only for loading uCode */
1736         if (inta & CSR_INT_BIT_FH_TX) {
1737                 iwl_write32(trans, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
1738                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1739                 isr_stats->tx++;
1740                 handled |= CSR_INT_BIT_FH_TX;
1741                 /* Wake up uCode load routine, now that load is complete */
1742                 trans_pcie->ucode_write_complete = true;
1743                 wake_up(&trans_pcie->ucode_write_waitq);
1744         }
1745
1746         if (inta & ~handled) {
1747                 IWL_ERR(trans, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1748                 isr_stats->unhandled++;
1749         }
1750
1751         if (inta & ~(trans_pcie->inta_mask)) {
1752                 IWL_WARN(trans, "Disabled INTA bits 0x%08x were pending\n",
1753                          inta & ~trans_pcie->inta_mask);
1754         }
1755
1756         spin_lock(&trans_pcie->irq_lock);
1757         /* only Re-enable all interrupt if disabled by irq */
1758         if (test_bit(STATUS_INT_ENABLED, &trans->status))
1759                 _iwl_enable_interrupts(trans);
1760         /* we are loading the firmware, enable FH_TX interrupt only */
1761         else if (handled & CSR_INT_BIT_FH_TX)
1762                 iwl_enable_fw_load_int(trans);
1763         /* Re-enable RF_KILL if it occurred */
1764         else if (handled & CSR_INT_BIT_RF_KILL)
1765                 iwl_enable_rfkill_int(trans);
1766         spin_unlock(&trans_pcie->irq_lock);
1767
1768 out:
1769         lock_map_release(&trans->sync_cmd_lockdep_map);
1770         return IRQ_HANDLED;
1771 }
1772
1773 /******************************************************************************
1774  *
1775  * ICT functions
1776  *
1777  ******************************************************************************/
1778
1779 /* Free dram table */
1780 void iwl_pcie_free_ict(struct iwl_trans *trans)
1781 {
1782         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1783
1784         if (trans_pcie->ict_tbl) {
1785                 dma_free_coherent(trans->dev, ICT_SIZE,
1786                                   trans_pcie->ict_tbl,
1787                                   trans_pcie->ict_tbl_dma);
1788                 trans_pcie->ict_tbl = NULL;
1789                 trans_pcie->ict_tbl_dma = 0;
1790         }
1791 }
1792
1793 /*
1794  * allocate dram shared table, it is an aligned memory
1795  * block of ICT_SIZE.
1796  * also reset all data related to ICT table interrupt.
1797  */
1798 int iwl_pcie_alloc_ict(struct iwl_trans *trans)
1799 {
1800         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1801
1802         trans_pcie->ict_tbl =
1803                 dma_zalloc_coherent(trans->dev, ICT_SIZE,
1804                                    &trans_pcie->ict_tbl_dma,
1805                                    GFP_KERNEL);
1806         if (!trans_pcie->ict_tbl)
1807                 return -ENOMEM;
1808
1809         /* just an API sanity check ... it is guaranteed to be aligned */
1810         if (WARN_ON(trans_pcie->ict_tbl_dma & (ICT_SIZE - 1))) {
1811                 iwl_pcie_free_ict(trans);
1812                 return -EINVAL;
1813         }
1814
1815         return 0;
1816 }
1817
1818 /* Device is going up inform it about using ICT interrupt table,
1819  * also we need to tell the driver to start using ICT interrupt.
1820  */
1821 void iwl_pcie_reset_ict(struct iwl_trans *trans)
1822 {
1823         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1824         u32 val;
1825
1826         if (!trans_pcie->ict_tbl)
1827                 return;
1828
1829         spin_lock(&trans_pcie->irq_lock);
1830         _iwl_disable_interrupts(trans);
1831
1832         memset(trans_pcie->ict_tbl, 0, ICT_SIZE);
1833
1834         val = trans_pcie->ict_tbl_dma >> ICT_SHIFT;
1835
1836         val |= CSR_DRAM_INT_TBL_ENABLE |
1837                CSR_DRAM_INIT_TBL_WRAP_CHECK |
1838                CSR_DRAM_INIT_TBL_WRITE_POINTER;
1839
1840         IWL_DEBUG_ISR(trans, "CSR_DRAM_INT_TBL_REG =0x%x\n", val);
1841
1842         iwl_write32(trans, CSR_DRAM_INT_TBL_REG, val);
1843         trans_pcie->use_ict = true;
1844         trans_pcie->ict_index = 0;
1845         iwl_write32(trans, CSR_INT, trans_pcie->inta_mask);
1846         _iwl_enable_interrupts(trans);
1847         spin_unlock(&trans_pcie->irq_lock);
1848 }
1849
1850 /* Device is going down disable ict interrupt usage */
1851 void iwl_pcie_disable_ict(struct iwl_trans *trans)
1852 {
1853         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1854
1855         spin_lock(&trans_pcie->irq_lock);
1856         trans_pcie->use_ict = false;
1857         spin_unlock(&trans_pcie->irq_lock);
1858 }
1859
1860 irqreturn_t iwl_pcie_isr(int irq, void *data)
1861 {
1862         struct iwl_trans *trans = data;
1863
1864         if (!trans)
1865                 return IRQ_NONE;
1866
1867         /* Disable (but don't clear!) interrupts here to avoid
1868          * back-to-back ISRs and sporadic interrupts from our NIC.
1869          * If we have something to service, the tasklet will re-enable ints.
1870          * If we *don't* have something, we'll re-enable before leaving here.
1871          */
1872         iwl_write32(trans, CSR_INT_MASK, 0x00000000);
1873
1874         return IRQ_WAKE_THREAD;
1875 }
1876
1877 irqreturn_t iwl_pcie_msix_isr(int irq, void *data)
1878 {
1879         return IRQ_WAKE_THREAD;
1880 }
1881
1882 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id)
1883 {
1884         struct msix_entry *entry = dev_id;
1885         struct iwl_trans_pcie *trans_pcie = iwl_pcie_get_trans_pcie(entry);
1886         struct iwl_trans *trans = trans_pcie->trans;
1887         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1888         u32 inta_fh, inta_hw;
1889
1890         lock_map_acquire(&trans->sync_cmd_lockdep_map);
1891
1892         spin_lock(&trans_pcie->irq_lock);
1893         inta_fh = iwl_read32(trans, CSR_MSIX_FH_INT_CAUSES_AD);
1894         inta_hw = iwl_read32(trans, CSR_MSIX_HW_INT_CAUSES_AD);
1895         /*
1896          * Clear causes registers to avoid being handling the same cause.
1897          */
1898         iwl_write32(trans, CSR_MSIX_FH_INT_CAUSES_AD, inta_fh);
1899         iwl_write32(trans, CSR_MSIX_HW_INT_CAUSES_AD, inta_hw);
1900         spin_unlock(&trans_pcie->irq_lock);
1901
1902         if (unlikely(!(inta_fh | inta_hw))) {
1903                 IWL_DEBUG_ISR(trans, "Ignore interrupt, inta == 0\n");
1904                 lock_map_release(&trans->sync_cmd_lockdep_map);
1905                 return IRQ_NONE;
1906         }
1907
1908         if (iwl_have_debug_level(IWL_DL_ISR)) {
1909                 IWL_DEBUG_ISR(trans,
1910                               "ISR inta_fh 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
1911                               inta_fh, trans_pcie->fh_mask,
1912                               iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD));
1913                 if (inta_fh & ~trans_pcie->fh_mask)
1914                         IWL_DEBUG_ISR(trans,
1915                                       "We got a masked interrupt (0x%08x)\n",
1916                                       inta_fh & ~trans_pcie->fh_mask);
1917         }
1918
1919         inta_fh &= trans_pcie->fh_mask;
1920
1921         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) &&
1922             inta_fh & MSIX_FH_INT_CAUSES_Q0) {
1923                 local_bh_disable();
1924                 iwl_pcie_rx_handle(trans, 0);
1925                 local_bh_enable();
1926         }
1927
1928         if ((trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) &&
1929             inta_fh & MSIX_FH_INT_CAUSES_Q1) {
1930                 local_bh_disable();
1931                 iwl_pcie_rx_handle(trans, 1);
1932                 local_bh_enable();
1933         }
1934
1935         /* This "Tx" DMA channel is used only for loading uCode */
1936         if (inta_fh & MSIX_FH_INT_CAUSES_D2S_CH0_NUM) {
1937                 IWL_DEBUG_ISR(trans, "uCode load interrupt\n");
1938                 isr_stats->tx++;
1939                 /*
1940                  * Wake up uCode load routine,
1941                  * now that load is complete
1942                  */
1943                 trans_pcie->ucode_write_complete = true;
1944                 wake_up(&trans_pcie->ucode_write_waitq);
1945         }
1946
1947         /* Error detected by uCode */
1948         if ((inta_fh & MSIX_FH_INT_CAUSES_FH_ERR) ||
1949             (inta_hw & MSIX_HW_INT_CAUSES_REG_SW_ERR)) {
1950                 IWL_ERR(trans,
1951                         "Microcode SW error detected. Restarting 0x%X.\n",
1952                         inta_fh);
1953                 isr_stats->sw++;
1954                 iwl_pcie_irq_handle_error(trans);
1955         }
1956
1957         /* After checking FH register check HW register */
1958         if (iwl_have_debug_level(IWL_DL_ISR)) {
1959                 IWL_DEBUG_ISR(trans,
1960                               "ISR inta_hw 0x%08x, enabled (sw) 0x%08x (hw) 0x%08x\n",
1961                               inta_hw, trans_pcie->hw_mask,
1962                               iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD));
1963                 if (inta_hw & ~trans_pcie->hw_mask)
1964                         IWL_DEBUG_ISR(trans,
1965                                       "We got a masked interrupt 0x%08x\n",
1966                                       inta_hw & ~trans_pcie->hw_mask);
1967         }
1968
1969         inta_hw &= trans_pcie->hw_mask;
1970
1971         /* Alive notification via Rx interrupt will do the real work */
1972         if (inta_hw & MSIX_HW_INT_CAUSES_REG_ALIVE) {
1973                 IWL_DEBUG_ISR(trans, "Alive interrupt\n");
1974                 isr_stats->alive++;
1975         }
1976
1977         /* uCode wakes up after power-down sleep */
1978         if (inta_hw & MSIX_HW_INT_CAUSES_REG_WAKEUP) {
1979                 IWL_DEBUG_ISR(trans, "Wakeup interrupt\n");
1980                 iwl_pcie_rxq_check_wrptr(trans);
1981                 iwl_pcie_txq_check_wrptrs(trans);
1982
1983                 isr_stats->wakeup++;
1984         }
1985
1986         /* Chip got too hot and stopped itself */
1987         if (inta_hw & MSIX_HW_INT_CAUSES_REG_CT_KILL) {
1988                 IWL_ERR(trans, "Microcode CT kill error detected.\n");
1989                 isr_stats->ctkill++;
1990         }
1991
1992         /* HW RF KILL switch toggled */
1993         if (inta_hw & MSIX_HW_INT_CAUSES_REG_RF_KILL) {
1994                 bool hw_rfkill;
1995
1996                 hw_rfkill = iwl_is_rfkill_set(trans);
1997                 IWL_WARN(trans, "RF_KILL bit toggled to %s.\n",
1998                          hw_rfkill ? "disable radio" : "enable radio");
1999
2000                 isr_stats->rfkill++;
2001
2002                 mutex_lock(&trans_pcie->mutex);
2003                 iwl_trans_pcie_rf_kill(trans, hw_rfkill);
2004                 mutex_unlock(&trans_pcie->mutex);
2005                 if (hw_rfkill) {
2006                         set_bit(STATUS_RFKILL, &trans->status);
2007                         if (test_and_clear_bit(STATUS_SYNC_HCMD_ACTIVE,
2008                                                &trans->status))
2009                                 IWL_DEBUG_RF_KILL(trans,
2010                                                   "Rfkill while SYNC HCMD in flight\n");
2011                         wake_up(&trans_pcie->wait_command_queue);
2012                 } else {
2013                         clear_bit(STATUS_RFKILL, &trans->status);
2014                 }
2015         }
2016
2017         if (inta_hw & MSIX_HW_INT_CAUSES_REG_HW_ERR) {
2018                 IWL_ERR(trans,
2019                         "Hardware error detected. Restarting.\n");
2020
2021                 isr_stats->hw++;
2022                 iwl_pcie_irq_handle_error(trans);
2023         }
2024
2025         iwl_pcie_clear_irq(trans, entry);
2026
2027         lock_map_release(&trans->sync_cmd_lockdep_map);
2028
2029         return IRQ_HANDLED;
2030 }