1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 Intel Corporation
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31 * Copyright(c) 2012 - 2014 Intel Corporation. All rights reserved.
32 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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65 #ifndef __iwl_fw_api_rx_h__
66 #define __iwl_fw_api_rx_h__
68 /* API for pre-9000 hardware */
70 #define IWL_RX_INFO_PHY_CNT 8
71 #define IWL_RX_INFO_ENERGY_ANT_ABC_IDX 1
72 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
73 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
74 #define IWL_RX_INFO_ENERGY_ANT_C_MSK 0x00ff0000
75 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
76 #define IWL_RX_INFO_ENERGY_ANT_B_POS 8
77 #define IWL_RX_INFO_ENERGY_ANT_C_POS 16
79 enum iwl_mac_context_info {
80 MAC_CONTEXT_INFO_NONE,
81 MAC_CONTEXT_INFO_GSCAN,
85 * struct iwl_rx_phy_info - phy info
86 * (REPLY_RX_PHY_CMD = 0xc0)
87 * @non_cfg_phy_cnt: non configurable DSP phy data byte count
88 * @cfg_phy_cnt: configurable DSP phy data byte count
89 * @stat_id: configurable DSP phy data set ID
90 * @reserved1: reserved
91 * @system_timestamp: GP2 at on air rise
92 * @timestamp: TSF at on air rise
93 * @beacon_time_stamp: beacon at on-air rise
94 * @phy_flags: general phy flags: band, modulation, ...
95 * @channel: channel number
96 * @non_cfg_phy: for various implementations of non_cfg_phy
97 * @rate_n_flags: RATE_MCS_*
98 * @byte_count: frame's byte-count
99 * @frame_time: frame's time on the air, based on byte count and frame rate
101 * @mac_active_msk: what MACs were active when the frame was received
102 * @mac_context_info: additional info on the context in which the frame was
103 * received as defined in &enum iwl_mac_context_info
105 * Before each Rx, the device sends this data. It contains PHY information
106 * about the reception of the packet.
108 struct iwl_rx_phy_info {
113 __le32 system_timestamp;
115 __le32 beacon_time_stamp;
118 __le32 non_cfg_phy[IWL_RX_INFO_PHY_CNT];
127 * TCP offload Rx assist info
129 * bits 0:3 - reserved
130 * bits 4:7 - MIC CRC length
131 * bits 8:12 - MAC header length
132 * bit 13 - Padding indication
133 * bit 14 - A-AMSDU indication
134 * bit 15 - Offload enabled
136 enum iwl_csum_rx_assist_info {
137 CSUM_RXA_RESERVED_MASK = 0x000f,
138 CSUM_RXA_MICSIZE_MASK = 0x00f0,
139 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
140 CSUM_RXA_PADD = BIT(13),
141 CSUM_RXA_AMSDU = BIT(14),
142 CSUM_RXA_ENA = BIT(15)
146 * struct iwl_rx_mpdu_res_start - phy info
147 * @byte_count: byte count of the frame
148 * @assist: see &enum iwl_csum_rx_assist_info
150 struct iwl_rx_mpdu_res_start {
153 } __packed; /* _RX_MPDU_RES_START_API_S_VER_2 */
156 * enum iwl_rx_phy_flags - to parse %iwl_rx_phy_info phy_flags
157 * @RX_RES_PHY_FLAGS_BAND_24: true if the packet was received on 2.4 band
158 * @RX_RES_PHY_FLAGS_MOD_CCK: modulation is CCK
159 * @RX_RES_PHY_FLAGS_SHORT_PREAMBLE: true if packet's preamble was short
160 * @RX_RES_PHY_FLAGS_NARROW_BAND: narrow band (<20 MHz) receive
161 * @RX_RES_PHY_FLAGS_ANTENNA: antenna on which the packet was received
162 * @RX_RES_PHY_FLAGS_ANTENNA_POS: antenna bit position
163 * @RX_RES_PHY_FLAGS_AGG: set if the packet was part of an A-MPDU
164 * @RX_RES_PHY_FLAGS_OFDM_HT: The frame was an HT frame
165 * @RX_RES_PHY_FLAGS_OFDM_GF: The frame used GF preamble
166 * @RX_RES_PHY_FLAGS_OFDM_VHT: The frame was a VHT frame
168 enum iwl_rx_phy_flags {
169 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
170 RX_RES_PHY_FLAGS_MOD_CCK = BIT(1),
171 RX_RES_PHY_FLAGS_SHORT_PREAMBLE = BIT(2),
172 RX_RES_PHY_FLAGS_NARROW_BAND = BIT(3),
173 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
174 RX_RES_PHY_FLAGS_ANTENNA_POS = 4,
175 RX_RES_PHY_FLAGS_AGG = BIT(7),
176 RX_RES_PHY_FLAGS_OFDM_HT = BIT(8),
177 RX_RES_PHY_FLAGS_OFDM_GF = BIT(9),
178 RX_RES_PHY_FLAGS_OFDM_VHT = BIT(10),
182 * enum iwl_mvm_rx_status - written by fw for each Rx packet
183 * @RX_MPDU_RES_STATUS_CRC_OK: CRC is fine
184 * @RX_MPDU_RES_STATUS_OVERRUN_OK: there was no RXE overflow
185 * @RX_MPDU_RES_STATUS_SRC_STA_FOUND: station was found
186 * @RX_MPDU_RES_STATUS_KEY_VALID: key was valid
187 * @RX_MPDU_RES_STATUS_KEY_PARAM_OK: key parameters were usable
188 * @RX_MPDU_RES_STATUS_ICV_OK: ICV is fine, if not, the packet is destroyed
189 * @RX_MPDU_RES_STATUS_MIC_OK: used for CCM alg only. TKIP MIC is checked
191 * @RX_MPDU_RES_STATUS_TTAK_OK: TTAK is fine
192 * @RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR: valid for alg = CCM_CMAC or
193 * alg = CCM only. Checks replay attack for 11w frames. Relevant only if
194 * %RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME is set.
195 * @RX_MPDU_RES_STATUS_SEC_NO_ENC: this frame is not encrypted
196 * @RX_MPDU_RES_STATUS_SEC_WEP_ENC: this frame is encrypted using WEP
197 * @RX_MPDU_RES_STATUS_SEC_CCM_ENC: this frame is encrypted using CCM
198 * @RX_MPDU_RES_STATUS_SEC_TKIP_ENC: this frame is encrypted using TKIP
199 * @RX_MPDU_RES_STATUS_SEC_EXT_ENC: this frame is encrypted using extension
201 * @RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC: this frame is encrypted using CCM_CMAC
202 * @RX_MPDU_RES_STATUS_SEC_ENC_ERR: this frame couldn't be decrypted
203 * @RX_MPDU_RES_STATUS_SEC_ENC_MSK: bitmask of the encryption algorithm
204 * @RX_MPDU_RES_STATUS_DEC_DONE: this frame has been successfully decrypted
205 * @RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP: extended IV (set with TKIP)
206 * @RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT: key ID comparison done
207 * @RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME: this frame is an 11w management frame
208 * @RX_MPDU_RES_STATUS_CSUM_DONE: checksum was done by the hw
209 * @RX_MPDU_RES_STATUS_CSUM_OK: checksum found no errors
210 * @RX_MPDU_RES_STATUS_STA_ID_MSK: station ID mask
211 * @RX_MDPU_RES_STATUS_STA_ID_SHIFT: station ID bit shift
212 * @RX_MPDU_RES_STATUS_FILTERING_MSK: filter status
213 * @RX_MPDU_RES_STATUS2_FILTERING_MSK: filter status 2
215 enum iwl_mvm_rx_status {
216 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
217 RX_MPDU_RES_STATUS_OVERRUN_OK = BIT(1),
218 RX_MPDU_RES_STATUS_SRC_STA_FOUND = BIT(2),
219 RX_MPDU_RES_STATUS_KEY_VALID = BIT(3),
220 RX_MPDU_RES_STATUS_KEY_PARAM_OK = BIT(4),
221 RX_MPDU_RES_STATUS_ICV_OK = BIT(5),
222 RX_MPDU_RES_STATUS_MIC_OK = BIT(6),
223 RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
224 RX_MPDU_RES_STATUS_MNG_FRAME_REPLAY_ERR = BIT(7),
225 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
226 RX_MPDU_RES_STATUS_SEC_WEP_ENC = (1 << 8),
227 RX_MPDU_RES_STATUS_SEC_CCM_ENC = (2 << 8),
228 RX_MPDU_RES_STATUS_SEC_TKIP_ENC = (3 << 8),
229 RX_MPDU_RES_STATUS_SEC_EXT_ENC = (4 << 8),
230 RX_MPDU_RES_STATUS_SEC_CCM_CMAC_ENC = (6 << 8),
231 RX_MPDU_RES_STATUS_SEC_ENC_ERR = (7 << 8),
232 RX_MPDU_RES_STATUS_SEC_ENC_MSK = (7 << 8),
233 RX_MPDU_RES_STATUS_DEC_DONE = BIT(11),
234 RX_MPDU_RES_STATUS_EXT_IV_BIT_CMP = BIT(13),
235 RX_MPDU_RES_STATUS_KEY_ID_CMP_BIT = BIT(14),
236 RX_MPDU_RES_STATUS_ROBUST_MNG_FRAME = BIT(15),
237 RX_MPDU_RES_STATUS_CSUM_DONE = BIT(16),
238 RX_MPDU_RES_STATUS_CSUM_OK = BIT(17),
239 RX_MDPU_RES_STATUS_STA_ID_SHIFT = 24,
240 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
241 RX_MPDU_RES_STATUS_FILTERING_MSK = (0xc00000),
242 RX_MPDU_RES_STATUS2_FILTERING_MSK = (0xc0000000),
245 /* 9000 series API */
246 enum iwl_rx_mpdu_mac_flags1 {
247 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03,
248 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0,
249 /* shift should be 4, but the length is measured in 2-byte
250 * words, so shifting only by 3 gives a byte result
252 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_SHIFT = 3,
255 enum iwl_rx_mpdu_mac_flags2 {
256 /* in 2-byte words */
257 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f,
258 IWL_RX_MPDU_MFLG2_PAD = 0x20,
259 IWL_RX_MPDU_MFLG2_AMSDU = 0x40,
262 enum iwl_rx_mpdu_amsdu_info {
263 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f,
264 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80,
267 enum iwl_rx_l3_proto_values {
270 IWL_RX_L3_TYPE_IPV4_FRAG,
271 IWL_RX_L3_TYPE_IPV6_FRAG,
273 IWL_RX_L3_TYPE_IPV6_IN_IPV4,
275 IWL_RX_L3_TYPE_EAPOL,
278 #define IWL_RX_L3_PROTO_POS 4
280 enum iwl_rx_l3l4_flags {
281 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0),
282 IWL_RX_L3L4_TCP_UDP_CSUM_OK = BIT(1),
283 IWL_RX_L3L4_TCP_FIN_SYN_RST_PSH = BIT(2),
284 IWL_RX_L3L4_TCP_ACK = BIT(3),
285 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS,
286 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8,
287 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12,
290 enum iwl_rx_mpdu_status {
291 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0),
292 IWL_RX_MPDU_STATUS_OVERRUN_OK = BIT(1),
293 IWL_RX_MPDU_STATUS_SRC_STA_FOUND = BIT(2),
294 IWL_RX_MPDU_STATUS_KEY_VALID = BIT(3),
295 IWL_RX_MPDU_STATUS_KEY_PARAM_OK = BIT(4),
296 IWL_RX_MPDU_STATUS_ICV_OK = BIT(5),
297 IWL_RX_MPDU_STATUS_MIC_OK = BIT(6),
298 IWL_RX_MPDU_RES_STATUS_TTAK_OK = BIT(7),
299 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8,
300 IWL_RX_MPDU_STATUS_SEC_UNKNOWN = IWL_RX_MPDU_STATUS_SEC_MASK,
301 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8,
302 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8,
303 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8,
304 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8,
305 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8,
306 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8,
307 IWL_RX_MPDU_STATUS_DECRYPTED = BIT(11),
308 IWL_RX_MPDU_STATUS_WEP_MATCH = BIT(12),
309 IWL_RX_MPDU_STATUS_EXT_IV_MATCH = BIT(13),
310 IWL_RX_MPDU_STATUS_KEY_ID_MATCH = BIT(14),
311 IWL_RX_MPDU_STATUS_ROBUST_MNG_FRAME = BIT(15),
314 enum iwl_rx_mpdu_hash_filter {
315 IWL_RX_MPDU_HF_A1_HASH_MASK = 0x3f,
316 IWL_RX_MPDU_HF_FILTER_STATUS_MASK = 0xc0,
319 enum iwl_rx_mpdu_sta_id_flags {
320 IWL_RX_MPDU_SIF_STA_ID_MASK = 0x1f,
321 IWL_RX_MPDU_SIF_RRF_ABORT = 0x20,
322 IWL_RX_MPDU_SIF_FILTER_STATUS_MASK = 0xc0,
325 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
327 enum iwl_rx_mpdu_reorder_data {
328 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff,
329 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000,
330 IWL_RX_MPDU_REORDER_SN_SHIFT = 12,
331 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000,
332 IWL_RX_MPDU_REORDER_BAID_SHIFT = 24,
333 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000,
336 enum iwl_rx_mpdu_phy_info {
337 IWL_RX_MPDU_PHY_AMPDU = BIT(5),
338 IWL_RX_MPDU_PHY_AMPDU_TOGGLE = BIT(6),
339 IWL_RX_MPDU_PHY_SHORT_PREAMBLE = BIT(7),
340 IWL_RX_MPDU_PHY_TSF_OVERLOAD = BIT(8),
343 enum iwl_rx_mpdu_mac_info {
344 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f,
345 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0,
349 * enum iwl_rx_he_phy - HE PHY data
352 IWL_RX_HE_PHY_BEAM_CHNG = BIT(0),
353 IWL_RX_HE_PHY_UPLINK = BIT(1),
354 IWL_RX_HE_PHY_BSS_COLOR_MASK = 0xfc,
355 IWL_RX_HE_PHY_SPATIAL_REUSE_MASK = 0xf00,
356 IWL_RX_HE_PHY_SU_EXT_BW10 = BIT(12),
357 IWL_RX_HE_PHY_TXOP_DUR_MASK = 0xfe000,
358 IWL_RX_HE_PHY_LDPC_EXT_SYM = BIT(20),
359 IWL_RX_HE_PHY_PRE_FEC_PAD_MASK = 0x600000,
360 IWL_RX_HE_PHY_PE_DISAMBIG = BIT(23),
361 IWL_RX_HE_PHY_DOPPLER = BIT(24),
362 /* 6 bits reserved */
363 IWL_RX_HE_PHY_DELIM_EOF = BIT(31),
365 /* second dword - MU data */
366 IWL_RX_HE_PHY_SIGB_COMPRESSION = BIT_ULL(32 + 0),
367 IWL_RX_HE_PHY_SIBG_SYM_OR_USER_NUM_MASK = 0x1e00000000ULL,
368 IWL_RX_HE_PHY_HE_LTF_NUM_MASK = 0xe000000000ULL,
369 IWL_RX_HE_PHY_RU_ALLOC_SEC80 = BIT_ULL(32 + 8),
370 /* trigger encoded */
371 IWL_RX_HE_PHY_RU_ALLOC_MASK = 0xfe0000000000ULL,
372 IWL_RX_HE_PHY_SIGB_MCS_MASK = 0xf000000000000ULL,
374 IWL_RX_HE_PHY_SIGB_DCM = BIT_ULL(32 + 21),
375 IWL_RX_HE_PHY_PREAMBLE_PUNC_TYPE_MASK = 0xc0000000000000ULL,
376 /* 8 bits reserved */
380 * struct iwl_rx_mpdu_desc_v1 - RX MPDU descriptor
382 struct iwl_rx_mpdu_desc_v1 {
383 /* DW7 - carries rss_hash only when rpa_en == 1 */
385 * @rss_hash: RSS hash value
388 /* DW8 - carries filter_match only when rpa_en == 1 */
390 * @filter_match: filter match value
395 * @rate_n_flags: RX rate/flags encoding
400 * @energy_a: energy chain A
404 * @energy_b: energy chain B
408 * @channel: channel number
412 * @mac_context: MAC context mask
417 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
419 __le32 gp2_on_air_rise;
424 * TSF value on air rise (INA), only valid if
425 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
427 __le64 tsf_on_air_rise;
430 * HE PHY data, see &enum iwl_rx_he_phy, valid
431 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set
438 * struct iwl_rx_mpdu_desc_v3 - RX MPDU descriptor
440 struct iwl_rx_mpdu_desc_v3 {
441 /* DW7 - carries filter_match only when rpa_en == 1 */
443 * @filter_match: filter match value
446 /* DW8 - carries rss_hash only when rpa_en == 1 */
448 * @rss_hash: RSS hash value
453 * @partial_hash: 31:0 ip/tcp header hash
454 * w/o some fields (such as IP SRC addr)
459 * @raw_xsum: raw xsum value
464 * @rate_n_flags: RX rate/flags encoding
469 * @energy_a: energy chain A
473 * @energy_b: energy chain B
477 * @channel: channel number
481 * @mac_context: MAC context mask
486 * @gp2_on_air_rise: GP2 timer value on air rise (INA)
488 __le32 gp2_on_air_rise;
493 * TSF value on air rise (INA), only valid if
494 * %IWL_RX_MPDU_PHY_TSF_OVERLOAD isn't set
496 __le64 tsf_on_air_rise;
499 * HE PHY data, see &enum iwl_rx_he_phy, valid
500 * only if %IWL_RX_MPDU_PHY_TSF_OVERLOAD is set
506 * @reserved: reserved
509 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
512 * struct iwl_rx_mpdu_desc - RX MPDU descriptor
514 struct iwl_rx_mpdu_desc {
517 * @mpdu_len: MPDU length
521 * @mac_flags1: &enum iwl_rx_mpdu_mac_flags1
525 * @mac_flags2: &enum iwl_rx_mpdu_mac_flags2
530 * @amsdu_info: &enum iwl_rx_mpdu_amsdu_info
534 * @phy_info: &enum iwl_rx_mpdu_phy_info
538 * @mac_phy_idx: MAC/PHY index
541 /* DW4 - carries csum data only when rpa_en == 1 */
543 * @raw_csum: raw checksum (alledgedly unreliable)
547 * @l3l4_flags: &enum iwl_rx_l3l4_flags
552 * @status: &enum iwl_rx_mpdu_status
556 * @hash_filter: hash filter value
560 * @sta_id_flags: &enum iwl_rx_mpdu_sta_id_flags
565 * @reorder_data: &enum iwl_rx_mpdu_reorder_data
570 struct iwl_rx_mpdu_desc_v1 v1;
571 struct iwl_rx_mpdu_desc_v3 v3;
573 } __packed; /* RX_MPDU_RES_START_API_S_VER_3 */
575 #define IWL_RX_DESC_SIZE_V1 offsetofend(struct iwl_rx_mpdu_desc, v1)
577 #define IWL_CD_STTS_OPTIMIZED_POS 0
578 #define IWL_CD_STTS_OPTIMIZED_MSK 0x01
579 #define IWL_CD_STTS_TRANSFER_STATUS_POS 1
580 #define IWL_CD_STTS_TRANSFER_STATUS_MSK 0x0E
581 #define IWL_CD_STTS_WIFI_STATUS_POS 4
582 #define IWL_CD_STTS_WIFI_STATUS_MSK 0xF0
585 * enum iwl_completion_desc_transfer_status - transfer status (bits 1-3)
586 * @IWL_CD_STTS_UNUSED: unused
587 * @IWL_CD_STTS_UNUSED_2: unused
588 * @IWL_CD_STTS_END_TRANSFER: successful transfer complete.
589 * In sniffer mode, when split is used, set in last CD completion. (RX)
590 * @IWL_CD_STTS_OVERFLOW: In sniffer mode, when using split - used for
591 * all CD completion. (RX)
592 * @IWL_CD_STTS_ABORTED: CR abort / close flow. (RX)
593 * @IWL_CD_STTS_ERROR: general error (RX)
595 enum iwl_completion_desc_transfer_status {
597 IWL_CD_STTS_UNUSED_2,
598 IWL_CD_STTS_END_TRANSFER,
599 IWL_CD_STTS_OVERFLOW,
605 * enum iwl_completion_desc_wifi_status - wifi status (bits 4-7)
606 * @IWL_CD_STTS_VALID: the packet is valid (RX)
607 * @IWL_CD_STTS_FCS_ERR: frame check sequence error (RX)
608 * @IWL_CD_STTS_SEC_KEY_ERR: error handling the security key of rx (RX)
609 * @IWL_CD_STTS_DECRYPTION_ERR: error decrypting the frame (RX)
610 * @IWL_CD_STTS_DUP: duplicate packet (RX)
611 * @IWL_CD_STTS_ICV_MIC_ERR: MIC error (RX)
612 * @IWL_CD_STTS_INTERNAL_SNAP_ERR: problems removing the snap (RX)
613 * @IWL_CD_STTS_SEC_PORT_FAIL: security port fail (RX)
614 * @IWL_CD_STTS_BA_OLD_SN: block ack received old SN (RX)
615 * @IWL_CD_STTS_QOS_NULL: QoS null packet (RX)
616 * @IWL_CD_STTS_MAC_HDR_ERR: MAC header conversion error (RX)
617 * @IWL_CD_STTS_MAX_RETRANS: reached max number of retransmissions (TX)
618 * @IWL_CD_STTS_EX_LIFETIME: exceeded lifetime (TX)
619 * @IWL_CD_STTS_NOT_USED: completed but not used (RX)
620 * @IWL_CD_STTS_REPLAY_ERR: pn check failed, replay error (RX)
622 enum iwl_completion_desc_wifi_status {
625 IWL_CD_STTS_SEC_KEY_ERR,
626 IWL_CD_STTS_DECRYPTION_ERR,
628 IWL_CD_STTS_ICV_MIC_ERR,
629 IWL_CD_STTS_INTERNAL_SNAP_ERR,
630 IWL_CD_STTS_SEC_PORT_FAIL,
631 IWL_CD_STTS_BA_OLD_SN,
632 IWL_CD_STTS_QOS_NULL,
633 IWL_CD_STTS_MAC_HDR_ERR,
634 IWL_CD_STTS_MAX_RETRANS,
635 IWL_CD_STTS_EX_LIFETIME,
636 IWL_CD_STTS_NOT_USED,
637 IWL_CD_STTS_REPLAY_ERR,
640 struct iwl_frame_release {
646 enum iwl_rss_hash_func_en {
647 IWL_RSS_HASH_TYPE_IPV4_TCP,
648 IWL_RSS_HASH_TYPE_IPV4_UDP,
649 IWL_RSS_HASH_TYPE_IPV4_PAYLOAD,
650 IWL_RSS_HASH_TYPE_IPV6_TCP,
651 IWL_RSS_HASH_TYPE_IPV6_UDP,
652 IWL_RSS_HASH_TYPE_IPV6_PAYLOAD,
655 #define IWL_RSS_HASH_KEY_CNT 10
656 #define IWL_RSS_INDIRECTION_TABLE_SIZE 128
657 #define IWL_RSS_ENABLE 1
660 * struct iwl_rss_config_cmd - RSS (Receive Side Scaling) configuration
662 * @flags: 1 - enable, 0 - disable
663 * @hash_mask: Type of RSS to use. Values are from %iwl_rss_hash_func_en
664 * @reserved: reserved
665 * @secret_key: 320 bit input of random key configuration from driver
666 * @indirection_table: indirection table
668 struct iwl_rss_config_cmd {
672 __le32 secret_key[IWL_RSS_HASH_KEY_CNT];
673 u8 indirection_table[IWL_RSS_INDIRECTION_TABLE_SIZE];
674 } __packed; /* RSS_CONFIG_CMD_API_S_VER_1 */
676 #define IWL_MULTI_QUEUE_SYNC_MSG_MAX_SIZE 128
677 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
678 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
681 * struct iwl_rxq_sync_cmd - RXQ notification trigger
683 * @flags: flags of the notification. bit 0:3 are the sender queue
684 * @rxq_mask: rx queues to send the notification on
685 * @count: number of bytes in payload, should be DWORD aligned
686 * @payload: data to send to rx queues
688 struct iwl_rxq_sync_cmd {
693 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
696 * struct iwl_rxq_sync_notification - Notification triggered by RXQ
699 * @count: number of bytes in payload
700 * @payload: data to send to rx queues
702 struct iwl_rxq_sync_notification {
705 } __packed; /* MULTI_QUEUE_DRV_SYNC_HDR_CMD_API_S_VER_1 */
708 * enum iwl_mvm_rxq_notif_type - Internal message identifier
710 * @IWL_MVM_RXQ_EMPTY: empty sync notification
711 * @IWL_MVM_RXQ_NOTIF_DEL_BA: notify RSS queues of delBA
713 enum iwl_mvm_rxq_notif_type {
715 IWL_MVM_RXQ_NOTIF_DEL_BA,
719 * struct iwl_mvm_internal_rxq_notif - Internal representation of the data sent
720 * in &iwl_rxq_sync_cmd. Should be DWORD aligned.
721 * FW is agnostic to the payload, so there are no endianity requirements.
723 * @type: value from &iwl_mvm_rxq_notif_type
724 * @sync: ctrl path is waiting for all notifications to be received
725 * @cookie: internal cookie to identify old notifications
728 struct iwl_mvm_internal_rxq_notif {
736 * enum iwl_mvm_pm_event - type of station PM event
737 * @IWL_MVM_PM_EVENT_AWAKE: station woke up
738 * @IWL_MVM_PM_EVENT_ASLEEP: station went to sleep
739 * @IWL_MVM_PM_EVENT_UAPSD: station sent uAPSD trigger
740 * @IWL_MVM_PM_EVENT_PS_POLL: station sent PS-Poll
742 enum iwl_mvm_pm_event {
743 IWL_MVM_PM_EVENT_AWAKE,
744 IWL_MVM_PM_EVENT_ASLEEP,
745 IWL_MVM_PM_EVENT_UAPSD,
746 IWL_MVM_PM_EVENT_PS_POLL,
747 }; /* PEER_PM_NTFY_API_E_VER_1 */
750 * struct iwl_mvm_pm_state_notification - station PM state notification
751 * @sta_id: station ID of the station changing state
752 * @type: the new powersave state, see &enum iwl_mvm_pm_event
754 struct iwl_mvm_pm_state_notification {
759 } __packed; /* PEER_PM_NTFY_API_S_VER_1 */
761 #define BA_WINDOW_STREAMS_MAX 16
762 #define BA_WINDOW_STATUS_TID_MSK 0x000F
763 #define BA_WINDOW_STATUS_STA_ID_POS 4
764 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0
765 #define BA_WINDOW_STATUS_VALID_MSK BIT(9)
768 * struct iwl_ba_window_status_notif - reordering window's status notification
769 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
770 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid
771 * @start_seq_num: the start sequence number of the bitmap
772 * @mpdu_rx_count: the number of received MPDUs since entering D0i3
774 struct iwl_ba_window_status_notif {
775 __le64 bitmap[BA_WINDOW_STREAMS_MAX];
776 __le16 ra_tid[BA_WINDOW_STREAMS_MAX];
777 __le32 start_seq_num[BA_WINDOW_STREAMS_MAX];
778 __le16 mpdu_rx_count[BA_WINDOW_STREAMS_MAX];
779 } __packed; /* BA_WINDOW_STATUS_NTFY_API_S_VER_1 */
782 * struct iwl_rfh_queue_config - RX queue configuration
784 * @enable: enable queue
785 * @reserved: alignment
786 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr
787 * @fr_bd_cb: DMA address of freeRB table
788 * @ur_bd_cb: DMA address of used RB table
789 * @fr_bd_wid: Initial index of the free table
791 struct iwl_rfh_queue_data {
795 __le64 urbd_stts_wrptr;
799 } __packed; /* RFH_QUEUE_CONFIG_S_VER_1 */
802 * struct iwl_rfh_queue_config - RX queue configuration
803 * @num_queues: number of queues configured
804 * @reserved: alignment
805 * @data: DMA addresses per-queue
807 struct iwl_rfh_queue_config {
810 struct iwl_rfh_queue_data data[];
811 } __packed; /* RFH_QUEUE_CONFIG_API_S_VER_1 */
813 #endif /* __iwl_fw_api_rx_h__ */