2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 #include <linux/kernel.h>
17 #include <linux/delay.h>
18 #include <linux/bitops.h>
20 #include <brcm_hw_ids.h>
21 #include <chipcommon.h>
27 #include "phy_radio.h"
31 #define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || \
32 (radioid == BCM2056_ID) || \
33 (radioid == BCM2057_ID))
35 #define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
37 #define VALID_RADIO(pi, radioid) ( \
38 (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
39 (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
41 /* basic mux operation - can be optimized on several architectures */
42 #define MUX(pred, true, false) ((pred) ? (true) : (false))
44 /* modulo inc/dec - assumes x E [0, bound - 1] */
45 #define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
47 /* modulo inc/dec, bound = 2^k */
48 #define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
49 #define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
51 struct chan_info_basic {
56 static const struct chan_info_basic chan_info_all[] = {
115 static const u8 ofdm_rate_lookup[] = {
127 #define PHY_WREG_LIMIT 24
129 void wlc_phyreg_enter(struct brcms_phy_pub *pih)
131 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
132 wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
135 void wlc_phyreg_exit(struct brcms_phy_pub *pih)
137 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
138 wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
141 void wlc_radioreg_enter(struct brcms_phy_pub *pih)
143 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
144 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
149 void wlc_radioreg_exit(struct brcms_phy_pub *pih)
151 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
153 (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
155 wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
158 u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
162 if (addr == RADIO_IDCODE)
165 switch (pi->pubpi.phy_type) {
167 if (!CONF_HAS(PHYTYPE, PHY_TYPE_N))
169 if (NREV_GE(pi->pubpi.phy_rev, 7))
170 addr |= RADIO_2057_READ_OFF;
172 addr |= RADIO_2055_READ_OFF;
176 if (!CONF_HAS(PHYTYPE, PHY_TYPE_LCN))
178 addr |= RADIO_2064_READ_OFF;
185 if ((D11REV_GE(pi->sh->corerev, 24)) ||
186 (D11REV_IS(pi->sh->corerev, 22)
187 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
188 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
189 data = bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
191 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
192 data = bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
199 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
201 if ((D11REV_GE(pi->sh->corerev, 24)) ||
202 (D11REV_IS(pi->sh->corerev, 22)
203 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
205 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
206 bcma_write16(pi->d11core, D11REGOFFS(radioregdata), val);
208 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
209 bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
212 if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
213 (++pi->phy_wreg >= pi->phy_wreg_limit)) {
214 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
219 static u32 read_radio_id(struct brcms_phy *pi)
223 if (D11REV_GE(pi->sh->corerev, 24)) {
226 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 0);
227 b0 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
228 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 1);
229 b1 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
230 bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 2);
231 b2 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
233 id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
236 bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), RADIO_IDCODE);
237 id = (u32) bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
238 id |= (u32) bcma_read16(pi->d11core,
239 D11REGOFFS(phy4wdatahi)) << 16;
245 void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
249 rval = read_radio_reg(pi, addr);
250 write_radio_reg(pi, addr, (rval & val));
253 void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
257 rval = read_radio_reg(pi, addr);
258 write_radio_reg(pi, addr, (rval | val));
261 void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask)
265 rval = read_radio_reg(pi, addr);
266 write_radio_reg(pi, addr, (rval ^ mask));
269 void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
273 rval = read_radio_reg(pi, addr);
274 write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
277 void write_phy_channel_reg(struct brcms_phy *pi, uint val)
279 bcma_write16(pi->d11core, D11REGOFFS(phychannel), val);
282 u16 read_phy_reg(struct brcms_phy *pi, u16 addr)
284 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
287 return bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
290 void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
292 #ifdef CONFIG_BCM47XX
293 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
294 bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val);
296 (void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
298 bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
299 if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
300 (++pi->phy_wreg >= pi->phy_wreg_limit)) {
302 (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
307 void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
309 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
310 bcma_mask16(pi->d11core, D11REGOFFS(phyregdata), val);
314 void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
316 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
317 bcma_set16(pi->d11core, D11REGOFFS(phyregdata), val);
321 void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
324 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
325 bcma_maskset16(pi->d11core, D11REGOFFS(phyregdata), ~mask, val);
329 static void wlc_set_phy_uninitted(struct brcms_phy *pi)
333 pi->initialized = false;
336 pi->nrssi_table_delta = 0x7fffffff;
338 pi->mintxbias = 0xffff;
341 pi->phy_spuravoid = SPURAVOID_DISABLE;
343 if (NREV_GE(pi->pubpi.phy_rev, 3)
344 && NREV_LT(pi->pubpi.phy_rev, 7))
345 pi->phy_spuravoid = SPURAVOID_AUTO;
347 pi->nphy_papd_skip = 0;
348 pi->nphy_papd_epsilon_offset[0] = 0xf588;
349 pi->nphy_papd_epsilon_offset[1] = 0xf588;
350 pi->nphy_txpwr_idx[0] = 128;
351 pi->nphy_txpwr_idx[1] = 128;
352 pi->nphy_txpwrindex[0].index_internal = 40;
353 pi->nphy_txpwrindex[1].index_internal = 40;
356 pi->phy_spuravoid = SPURAVOID_AUTO;
358 pi->radiopwr = 0xffff;
359 for (i = 0; i < STATIC_NUM_RF; i++) {
360 for (j = 0; j < STATIC_NUM_BB; j++)
361 pi->stats_11b_txpower[i][j] = -1;
365 struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
367 struct shared_phy *sh;
369 sh = kzalloc(sizeof(struct shared_phy), GFP_ATOMIC);
373 sh->physhim = shp->physhim;
374 sh->unit = shp->unit;
375 sh->corerev = shp->corerev;
379 sh->chip = shp->chip;
380 sh->chiprev = shp->chiprev;
381 sh->chippkg = shp->chippkg;
382 sh->sromrev = shp->sromrev;
383 sh->boardtype = shp->boardtype;
384 sh->boardrev = shp->boardrev;
385 sh->boardflags = shp->boardflags;
386 sh->boardflags2 = shp->boardflags2;
388 sh->fast_timer = PHY_SW_TIMER_FAST;
389 sh->slow_timer = PHY_SW_TIMER_SLOW;
390 sh->glacial_timer = PHY_SW_TIMER_GLACIAL;
392 sh->rssi_mode = RSSI_ANT_MERGE_MAX;
397 static void wlc_phy_timercb_phycal(struct brcms_phy *pi)
401 if (PHY_PERICAL_MPHASE_PENDING(pi)) {
403 wlc_phy_cal_perical_mphase_reset(pi);
407 if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
410 wlc_phy_cal_perical_mphase_restart(pi);
412 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
413 wlapi_add_timer(pi->phycal_timer, delay, 0);
419 static u32 wlc_phy_get_radio_ver(struct brcms_phy *pi)
423 ver = read_radio_id(pi);
428 struct brcms_phy_pub *
429 wlc_phy_attach(struct shared_phy *sh, struct bcma_device *d11core,
430 int bandtype, struct wiphy *wiphy)
432 struct brcms_phy *pi;
438 if (D11REV_IS(sh->corerev, 4))
439 sflags = SISF_2G_PHY | SISF_5G_PHY;
441 sflags = bcma_aread32(d11core, BCMA_IOST);
443 if (bandtype == BRCM_BAND_5G) {
444 if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0)
449 if ((sflags & SISF_DB_PHY) && pi) {
450 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
452 return &pi->pubpi_ro;
455 pi = kzalloc(sizeof(struct brcms_phy), GFP_ATOMIC);
459 pi->d11core = d11core;
461 pi->phy_init_por = true;
462 pi->phy_wreg_limit = PHY_WREG_LIMIT;
464 pi->txpwr_percent = 100;
466 pi->do_initcal = true;
468 pi->phycal_tempdelta = 0;
470 if (bandtype == BRCM_BAND_2G && (sflags & SISF_2G_PHY))
471 pi->pubpi.coreflags = SICF_GMODE;
473 wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
474 phyversion = bcma_read16(pi->d11core, D11REGOFFS(phyversion));
476 pi->pubpi.phy_type = PHY_TYPE(phyversion);
477 pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
479 if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
480 pi->pubpi.phy_type = PHY_TYPE_N;
481 pi->pubpi.phy_rev += LCNXN_BASEREV;
483 pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
484 pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
486 if (pi->pubpi.phy_type != PHY_TYPE_N &&
487 pi->pubpi.phy_type != PHY_TYPE_LCN)
490 if (bandtype == BRCM_BAND_5G) {
493 } else if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
497 wlc_phy_anacore((struct brcms_phy_pub *) pi, ON);
499 idcode = wlc_phy_get_radio_ver(pi);
501 (idcode & IDCODE_ID_MASK) >> IDCODE_ID_SHIFT;
503 (idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
505 (idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
506 if (!VALID_RADIO(pi, pi->pubpi.radioid))
509 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, OFF);
511 wlc_set_phy_uninitted(pi);
513 pi->bw = WL_CHANSPEC_BW_20;
514 pi->radio_chanspec = (bandtype == BRCM_BAND_2G) ?
515 ch20mhz_chspec(1) : ch20mhz_chspec(36);
517 pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
518 pi->rxiq_antsel = ANT_RX_DIV_DEF;
520 pi->watchdog_override = true;
522 pi->cal_type_override = PHY_PERICAL_AUTO;
524 pi->nphy_saved_noisevars.bufcount = 0;
527 pi->min_txpower = PHY_TXPWR_MIN_NPHY;
529 pi->min_txpower = PHY_TXPWR_MIN;
531 pi->sh->phyrxchain = 0x3;
533 pi->rx2tx_biasentry = -1;
535 pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
536 pi->phy_txcore_enable_temp =
537 PHY_CHAIN_TX_DISABLE_TEMP - PHY_HYSTERESIS_DELTATEMP;
538 pi->phy_tempsense_offset = 0;
539 pi->phy_txcore_heatedup = false;
541 pi->nphy_lastcal_temp = -50;
543 pi->phynoise_polling = true;
544 if (ISNPHY(pi) || ISLCNPHY(pi))
545 pi->phynoise_polling = false;
547 for (i = 0; i < TXP_NUM_RATES; i++) {
548 pi->txpwr_limit[i] = BRCMS_TXPWR_MAX;
549 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
550 pi->tx_user_target[i] = BRCMS_TXPWR_MAX;
553 pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
555 pi->user_txpwr_at_rfport = false;
559 pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
560 wlc_phy_timercb_phycal,
562 if (!pi->phycal_timer)
565 if (!wlc_phy_attach_nphy(pi))
568 } else if (ISLCNPHY(pi)) {
569 if (!wlc_phy_attach_lcnphy(pi))
575 pi->next = pi->sh->phy_head;
578 memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(struct brcms_phy_pub));
580 return &pi->pubpi_ro;
587 void wlc_phy_detach(struct brcms_phy_pub *pih)
589 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
595 if (pi->phycal_timer) {
596 wlapi_free_timer(pi->phycal_timer);
597 pi->phycal_timer = NULL;
600 if (pi->sh->phy_head == pi)
601 pi->sh->phy_head = pi->next;
602 else if (pi->sh->phy_head->next == pi)
603 pi->sh->phy_head->next = NULL;
605 if (pi->pi_fptr.detach)
606 (pi->pi_fptr.detach)(pi);
613 wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype, u16 *phyrev,
614 u16 *radioid, u16 *radiover)
616 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
617 *phytype = (u16) pi->pubpi.phy_type;
618 *phyrev = (u16) pi->pubpi.phy_rev;
619 *radioid = pi->pubpi.radioid;
620 *radiover = pi->pubpi.radiorev;
625 bool wlc_phy_get_encore(struct brcms_phy_pub *pih)
627 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
628 return pi->pubpi.abgphy_encore;
631 u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih)
633 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
634 return pi->pubpi.coreflags;
637 void wlc_phy_anacore(struct brcms_phy_pub *pih, bool on)
639 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
643 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
644 write_phy_reg(pi, 0xa6, 0x0d);
645 write_phy_reg(pi, 0x8f, 0x0);
646 write_phy_reg(pi, 0xa7, 0x0d);
647 write_phy_reg(pi, 0xa5, 0x0);
649 write_phy_reg(pi, 0xa5, 0x0);
652 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
653 write_phy_reg(pi, 0x8f, 0x07ff);
654 write_phy_reg(pi, 0xa6, 0x0fd);
655 write_phy_reg(pi, 0xa5, 0x07ff);
656 write_phy_reg(pi, 0xa7, 0x0fd);
658 write_phy_reg(pi, 0xa5, 0x7fff);
661 } else if (ISLCNPHY(pi)) {
663 and_phy_reg(pi, 0x43b,
664 ~((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
666 or_phy_reg(pi, 0x43c,
667 (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
668 or_phy_reg(pi, 0x43b,
669 (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
674 u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih)
676 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
678 u32 phy_bw_clkbits = 0;
680 if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
682 case WL_CHANSPEC_BW_10:
683 phy_bw_clkbits = SICF_BW10;
685 case WL_CHANSPEC_BW_20:
686 phy_bw_clkbits = SICF_BW20;
688 case WL_CHANSPEC_BW_40:
689 phy_bw_clkbits = SICF_BW40;
696 return phy_bw_clkbits;
699 void wlc_phy_por_inform(struct brcms_phy_pub *ppi)
701 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
703 pi->phy_init_por = true;
706 void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock)
708 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
710 pi->edcrs_threshold_lock = lock;
712 write_phy_reg(pi, 0x22c, 0x46b);
713 write_phy_reg(pi, 0x22d, 0x46b);
714 write_phy_reg(pi, 0x22e, 0x3c0);
715 write_phy_reg(pi, 0x22f, 0x3c0);
718 void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal)
720 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
722 pi->do_initcal = initcal;
725 void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *pih, bool newstate)
727 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
732 pi->sh->clk = newstate;
735 void wlc_phy_hw_state_upd(struct brcms_phy_pub *pih, bool newstate)
737 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
742 pi->sh->up = newstate;
745 void wlc_phy_init(struct brcms_phy_pub *pih, u16 chanspec)
748 void (*phy_init)(struct brcms_phy *) = NULL;
749 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
751 if (pi->init_in_progress)
754 pi->init_in_progress = true;
756 pi->radio_chanspec = chanspec;
758 mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
759 if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
762 if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
763 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
765 if (WARN(!(bcma_aread32(pi->d11core, BCMA_IOST) & SISF_FCLKA),
766 "HW error SISF_FCLKA\n"))
769 phy_init = pi->pi_fptr.init;
771 if (phy_init == NULL)
774 wlc_phy_anacore(pih, ON);
776 if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
777 wlapi_bmac_bw_set(pi->sh->physhim,
778 CHSPEC_BW(pi->radio_chanspec));
780 pi->nphy_gain_boost = true;
782 wlc_phy_switch_radio((struct brcms_phy_pub *) pi, ON);
786 pi->phy_init_por = false;
788 if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
789 wlc_phy_do_dummy_tx(pi, true, OFF);
792 wlc_phy_txpower_update_shm(pi);
794 wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi, pi->sh->rx_antdiv);
796 pi->init_in_progress = false;
799 void wlc_phy_cal_init(struct brcms_phy_pub *pih)
801 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
802 void (*cal_init)(struct brcms_phy *) = NULL;
804 if (WARN((bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
805 MCTL_EN_MAC) != 0, "HW error: MAC enabled during phy cal\n"))
808 if (!pi->initialized) {
809 cal_init = pi->pi_fptr.calinit;
813 pi->initialized = true;
817 int wlc_phy_down(struct brcms_phy_pub *pih)
819 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
823 && !wlapi_del_timer(pi->phycal_timer))
826 pi->nphy_iqcal_chanspec_2G = 0;
827 pi->nphy_iqcal_chanspec_5G = 0;
833 wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
834 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
836 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
838 pi->tbl_data_hi = tblDataHi;
839 pi->tbl_data_lo = tblDataLo;
841 if (pi->sh->chip == BCMA_CHIP_ID_BCM43224 &&
842 pi->sh->chiprev == 1) {
843 pi->tbl_addr = tblAddr;
844 pi->tbl_save_id = tbl_id;
845 pi->tbl_save_offset = tbl_offset;
849 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
851 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
852 (pi->sh->chiprev == 1) &&
853 (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
854 read_phy_reg(pi, pi->tbl_data_lo);
856 write_phy_reg(pi, pi->tbl_addr,
857 (pi->tbl_save_id << 10) | pi->tbl_save_offset);
858 pi->tbl_save_offset++;
862 write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
863 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
865 write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
870 wlc_phy_write_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
871 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
874 uint tbl_id = ptbl_info->tbl_id;
875 uint tbl_offset = ptbl_info->tbl_offset;
876 uint tbl_width = ptbl_info->tbl_width;
877 const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
878 const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
879 const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
881 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
883 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
885 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
886 (pi->sh->chiprev == 1) &&
887 (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
888 read_phy_reg(pi, tblDataLo);
890 write_phy_reg(pi, tblAddr,
891 (tbl_id << 10) | (tbl_offset + idx));
894 if (tbl_width == 32) {
895 write_phy_reg(pi, tblDataHi,
896 (u16) (ptbl_32b[idx] >> 16));
897 write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
898 } else if (tbl_width == 16) {
899 write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
901 write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
907 wlc_phy_read_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
908 u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
911 uint tbl_id = ptbl_info->tbl_id;
912 uint tbl_offset = ptbl_info->tbl_offset;
913 uint tbl_width = ptbl_info->tbl_width;
914 u8 *ptbl_8b = (u8 *)ptbl_info->tbl_ptr;
915 u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
916 u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
918 write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
920 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
922 if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
923 (pi->sh->chiprev == 1)) {
924 (void)read_phy_reg(pi, tblDataLo);
926 write_phy_reg(pi, tblAddr,
927 (tbl_id << 10) | (tbl_offset + idx));
930 if (tbl_width == 32) {
931 ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
932 ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
933 } else if (tbl_width == 16) {
934 ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
936 ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
942 wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
943 struct radio_20xx_regs *radioregs)
948 if (radioregs[i].do_init)
949 write_radio_reg(pi, radioregs[i].address,
950 (u16) radioregs[i].init);
953 } while (radioregs[i].address != 0xffff);
959 wlc_phy_init_radio_regs(struct brcms_phy *pi,
960 const struct radio_regs *radioregs,
967 if (CHSPEC_IS5G(pi->radio_chanspec)) {
968 if (radioregs[i].do_init_a) {
971 address | core_offset,
972 (u16) radioregs[i].init_a);
973 if (ISNPHY(pi) && (++count % 4 == 0))
974 BRCMS_PHY_WAR_PR51571(pi);
977 if (radioregs[i].do_init_g) {
980 address | core_offset,
981 (u16) radioregs[i].init_g);
982 if (ISNPHY(pi) && (++count % 4 == 0))
983 BRCMS_PHY_WAR_PR51571(pi);
988 } while (radioregs[i].address != 0xffff);
993 void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on)
995 #define DUMMY_PKT_LEN 20
996 struct bcma_device *core = pi->d11core;
998 u8 ofdmpkt[DUMMY_PKT_LEN] = {
999 0xcc, 0x01, 0x02, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
1000 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
1002 u8 cckpkt[DUMMY_PKT_LEN] = {
1003 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
1004 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
1008 dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
1009 wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
1012 bcma_write16(core, D11REGOFFS(xmtsel), 0);
1014 if (D11REV_GE(pi->sh->corerev, 11))
1015 bcma_write16(core, D11REGOFFS(wepctl), 0x100);
1017 bcma_write16(core, D11REGOFFS(wepctl), 0);
1019 bcma_write16(core, D11REGOFFS(txe_phyctl),
1020 (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
1021 if (ISNPHY(pi) || ISLCNPHY(pi))
1022 bcma_write16(core, D11REGOFFS(txe_phyctl1), 0x1A02);
1024 bcma_write16(core, D11REGOFFS(txe_wm_0), 0);
1025 bcma_write16(core, D11REGOFFS(txe_wm_1), 0);
1027 bcma_write16(core, D11REGOFFS(xmttplatetxptr), 0);
1028 bcma_write16(core, D11REGOFFS(xmttxcnt), DUMMY_PKT_LEN);
1030 bcma_write16(core, D11REGOFFS(xmtsel),
1031 ((8 << 8) | (1 << 5) | (1 << 2) | 2));
1033 bcma_write16(core, D11REGOFFS(txe_ctl), 0);
1037 wlc_phy_pa_override_nphy(pi, OFF);
1040 if (ISNPHY(pi) || ISLCNPHY(pi))
1041 bcma_write16(core, D11REGOFFS(txe_aux), 0xD0);
1043 bcma_write16(core, D11REGOFFS(txe_aux), ((1 << 5) | (1 << 4)));
1045 (void)bcma_read16(core, D11REGOFFS(txe_aux));
1048 count = ofdm ? 30 : 250;
1049 while ((i++ < count)
1050 && (bcma_read16(core, D11REGOFFS(txe_status)) & (1 << 7)))
1055 while ((i++ < 10) &&
1056 ((bcma_read16(core, D11REGOFFS(txe_status)) & (1 << 10)) == 0))
1061 while ((i++ < 10) &&
1062 ((bcma_read16(core, D11REGOFFS(ifsstat)) & (1 << 8))))
1067 wlc_phy_pa_override_nphy(pi, ON);
1071 void wlc_phy_hold_upd(struct brcms_phy_pub *pih, u32 id, bool set)
1073 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1076 mboolset(pi->measure_hold, id);
1078 mboolclr(pi->measure_hold, id);
1083 void wlc_phy_mute_upd(struct brcms_phy_pub *pih, bool mute, u32 flags)
1085 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1088 mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1090 mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
1092 if (!mute && (flags & PHY_MUTE_FOR_PREISM))
1093 pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
1097 void wlc_phy_clear_tssi(struct brcms_phy_pub *pih)
1099 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1104 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
1105 wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
1106 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
1107 wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
1111 static bool wlc_phy_cal_txpower_recalc_sw(struct brcms_phy *pi)
1116 void wlc_phy_switch_radio(struct brcms_phy_pub *pih, bool on)
1118 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1119 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
1122 wlc_phy_switch_radio_nphy(pi, on);
1123 } else if (ISLCNPHY(pi)) {
1125 and_phy_reg(pi, 0x44c,
1128 (0x1 << 10) | (0x1 << 11) | (0x1 << 12)));
1129 and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
1130 and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
1132 and_phy_reg(pi, 0x44d,
1135 (0x1 << 12) | (0x1 << 13) | (0x1 << 14)));
1136 or_phy_reg(pi, 0x44c,
1139 (0x1 << 10) | (0x1 << 11) | (0x1 << 12));
1141 and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
1142 and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
1143 or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
1144 and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
1145 or_phy_reg(pi, 0x4f9, (0x1 << 3));
1150 u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi)
1152 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1157 void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw)
1159 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1164 void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch)
1166 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1167 pi->radio_chanspec = newch;
1171 u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi)
1173 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1175 return pi->radio_chanspec;
1178 void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec)
1180 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1182 void (*chanspec_set)(struct brcms_phy *, u16) = NULL;
1183 m_cur_channel = CHSPEC_CHANNEL(chanspec);
1184 if (CHSPEC_IS5G(chanspec))
1185 m_cur_channel |= D11_CURCHANNEL_5G;
1186 if (CHSPEC_IS40(chanspec))
1187 m_cur_channel |= D11_CURCHANNEL_40;
1188 wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
1190 chanspec_set = pi->pi_fptr.chanset;
1192 (*chanspec_set)(pi, chanspec);
1196 int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq)
1201 range = WL_CHAN_FREQ_RANGE_2G;
1202 else if (freq <= 5320)
1203 range = WL_CHAN_FREQ_RANGE_5GL;
1204 else if (freq <= 5700)
1205 range = WL_CHAN_FREQ_RANGE_5GM;
1207 range = WL_CHAN_FREQ_RANGE_5GH;
1212 int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi, u16 chanspec)
1215 uint channel = CHSPEC_CHANNEL(chanspec);
1216 uint freq = wlc_phy_channel2freq(channel);
1219 range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
1220 else if (ISLCNPHY(pi))
1221 range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
1226 void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
1229 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1231 pi->channel_14_wide_filter = wide_filter;
1235 int wlc_phy_channel2freq(uint channel)
1239 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++)
1240 if (chan_info_all[i].chan == channel)
1241 return chan_info_all[i].freq;
1246 wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
1247 struct brcms_chanvec *channels)
1249 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1253 memset(channels, 0, sizeof(struct brcms_chanvec));
1255 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1256 channel = chan_info_all[i].chan;
1258 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1259 && (channel <= LAST_REF5_CHANNUM))
1262 if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
1263 (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
1264 setbit(channels->vec, channel);
1268 u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi, uint band)
1270 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1275 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1276 channel = chan_info_all[i].chan;
1278 if (ISNPHY(pi) && pi->bw == WL_CHANSPEC_BW_40) {
1281 for (j = 0; j < ARRAY_SIZE(chan_info_all); j++) {
1282 if (chan_info_all[j].chan ==
1283 channel + CH_10MHZ_APART)
1287 if (j == ARRAY_SIZE(chan_info_all))
1290 channel = upper_20_sb(channel);
1291 chspec = channel | WL_CHANSPEC_BW_40 |
1292 WL_CHANSPEC_CTL_SB_LOWER;
1293 if (band == BRCM_BAND_2G)
1294 chspec |= WL_CHANSPEC_BAND_2G;
1296 chspec |= WL_CHANSPEC_BAND_5G;
1298 chspec = ch20mhz_chspec(channel);
1300 if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
1301 && (channel <= LAST_REF5_CHANNUM))
1304 if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
1305 (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
1309 return (u16) INVCHANSPEC;
1312 int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override)
1314 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1316 *qdbm = pi->tx_user_target[0];
1317 if (override != NULL)
1318 *override = pi->txpwroverride;
1322 void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
1323 struct txpwr_limits *txpwr)
1325 bool mac_enabled = false;
1326 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1328 memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
1329 &txpwr->cck[0], BRCMS_NUM_RATES_CCK);
1331 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
1332 &txpwr->ofdm[0], BRCMS_NUM_RATES_OFDM);
1333 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
1334 &txpwr->ofdm_cdd[0], BRCMS_NUM_RATES_OFDM);
1336 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
1337 &txpwr->ofdm_40_siso[0], BRCMS_NUM_RATES_OFDM);
1338 memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
1339 &txpwr->ofdm_40_cdd[0], BRCMS_NUM_RATES_OFDM);
1341 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
1342 &txpwr->mcs_20_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1343 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
1344 &txpwr->mcs_20_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1345 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
1346 &txpwr->mcs_20_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1347 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
1348 &txpwr->mcs_20_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
1350 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
1351 &txpwr->mcs_40_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1352 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
1353 &txpwr->mcs_40_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1354 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
1355 &txpwr->mcs_40_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
1356 memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
1357 &txpwr->mcs_40_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
1359 if (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
1363 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1365 wlc_phy_txpower_recalc_target(pi);
1366 wlc_phy_cal_txpower_recalc_sw(pi);
1369 wlapi_enable_mac(pi->sh->physhim);
1372 int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override)
1374 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1380 for (i = 0; i < TXP_NUM_RATES; i++)
1381 pi->tx_user_target[i] = (u8) qdbm;
1383 pi->txpwroverride = false;
1386 if (!SCAN_INPROG_PHY(pi)) {
1389 suspend = (0 == (bcma_read32(pi->d11core,
1390 D11REGOFFS(maccontrol)) &
1394 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1396 wlc_phy_txpower_recalc_target(pi);
1397 wlc_phy_cal_txpower_recalc_sw(pi);
1400 wlapi_enable_mac(pi->sh->physhim);
1407 wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint channel, u8 *min_pwr,
1408 u8 *max_pwr, int txp_rate_idx)
1410 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1413 *min_pwr = pi->min_txpower * BRCMS_TXPWR_DB_FACTOR;
1416 if (txp_rate_idx < 0)
1417 txp_rate_idx = TXP_FIRST_CCK;
1418 wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
1421 } else if ((channel <= CH_MAX_2G_CHANNEL)) {
1422 if (txp_rate_idx < 0)
1423 txp_rate_idx = TXP_FIRST_CCK;
1424 *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
1427 *max_pwr = BRCMS_TXPWR_MAX;
1429 if (txp_rate_idx < 0)
1430 txp_rate_idx = TXP_FIRST_OFDM;
1432 for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
1433 if (channel == chan_info_all[i].chan)
1438 *max_pwr = pi->hwtxpwr[i];
1441 if ((i >= FIRST_MID_5G_CHAN) && (i <= LAST_MID_5G_CHAN))
1443 pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
1444 if ((i >= FIRST_HIGH_5G_CHAN)
1445 && (i <= LAST_HIGH_5G_CHAN))
1447 pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
1448 if ((i >= FIRST_LOW_5G_CHAN) && (i <= LAST_LOW_5G_CHAN))
1450 pi->tx_srom_max_rate_5g_low[txp_rate_idx];
1456 wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi, uint chan,
1457 u8 *max_txpwr, u8 *min_txpwr)
1459 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1461 u8 tx_pwr_min = 255;
1463 u8 maxtxpwr, mintxpwr, rate, pactrl;
1467 max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
1468 ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 +
1469 1) : (TXP_LAST_OFDM + 1);
1471 for (rate = 0; rate < max_num_rate; rate++) {
1473 wlc_phy_txpower_sromlimit(ppi, chan, &mintxpwr, &maxtxpwr,
1476 maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
1478 maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
1480 tx_pwr_max = max(tx_pwr_max, maxtxpwr);
1481 tx_pwr_min = min(tx_pwr_min, maxtxpwr);
1483 *max_txpwr = tx_pwr_max;
1484 *min_txpwr = tx_pwr_min;
1488 wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi, uint bandunit,
1489 s32 *max_pwr, s32 *min_pwr, u32 *step_pwr)
1494 u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi)
1496 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1498 return pi->tx_power_min;
1501 u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi)
1503 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1505 return pi->tx_power_max;
1508 static s8 wlc_phy_env_measure_vbat(struct brcms_phy *pi)
1511 return wlc_lcnphy_vbatsense(pi, 0);
1516 static s8 wlc_phy_env_measure_temperature(struct brcms_phy *pi)
1519 return wlc_lcnphy_tempsense_degree(pi, 0);
1524 static void wlc_phy_upd_env_txpwr_rate_limits(struct brcms_phy *pi, u32 band)
1529 for (i = 0; i < TXP_NUM_RATES; i++)
1530 pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
1532 vbat = wlc_phy_env_measure_vbat(pi);
1533 temp = wlc_phy_env_measure_temperature(pi);
1538 wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi, uint chan, u32 band,
1544 void wlc_phy_txpower_recalc_target(struct brcms_phy *pi)
1546 u8 maxtxpwr, mintxpwr, rate, pactrl;
1548 u8 tx_pwr_target[TXP_NUM_RATES];
1550 u8 tx_pwr_min = 255;
1551 u8 tx_pwr_max_rate_ind = 0;
1555 u32 band = CHSPEC2BAND(pi->radio_chanspec);
1556 void (*txpwr_recalc_fn)(struct brcms_phy *) = NULL;
1558 chspec = pi->radio_chanspec;
1559 if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE)
1560 target_chan = CHSPEC_CHANNEL(chspec);
1561 else if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
1562 target_chan = upper_20_sb(CHSPEC_CHANNEL(chspec));
1564 target_chan = lower_20_sb(CHSPEC_CHANNEL(chspec));
1570 if (CHSPEC_IS40(pi->radio_chanspec)) {
1571 offset_mcs = pi->mcs40_po;
1572 for (i = TXP_FIRST_SISO_MCS_20;
1573 i <= TXP_LAST_SISO_MCS_20; i++) {
1574 pi->tx_srom_max_rate_2g[i - 8] =
1575 pi->tx_srom_max_2g -
1576 ((offset_mcs & 0xf) * 2);
1580 offset_mcs = pi->mcs20_po;
1581 for (i = TXP_FIRST_SISO_MCS_20;
1582 i <= TXP_LAST_SISO_MCS_20; i++) {
1583 pi->tx_srom_max_rate_2g[i - 8] =
1584 pi->tx_srom_max_2g -
1585 ((offset_mcs & 0xf) * 2);
1591 max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
1593 (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1)));
1595 wlc_phy_upd_env_txpwr_rate_limits(pi, band);
1597 for (rate = start_rate; rate < max_num_rate; rate++) {
1599 tx_pwr_target[rate] = pi->tx_user_target[rate];
1601 if (pi->user_txpwr_at_rfport)
1602 tx_pwr_target[rate] +=
1603 wlc_user_txpwr_antport_to_rfport(pi,
1608 wlc_phy_txpower_sromlimit((struct brcms_phy_pub *) pi,
1610 &mintxpwr, &maxtxpwr, rate);
1612 maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
1614 maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
1616 maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
1618 maxtxpwr = min(maxtxpwr, tx_pwr_target[rate]);
1620 if (pi->txpwr_percent <= 100)
1621 maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
1623 tx_pwr_target[rate] = max(maxtxpwr, mintxpwr);
1625 tx_pwr_target[rate] =
1626 min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
1628 if (tx_pwr_target[rate] > tx_pwr_max)
1629 tx_pwr_max_rate_ind = rate;
1631 tx_pwr_max = max(tx_pwr_max, tx_pwr_target[rate]);
1632 tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
1635 memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
1636 pi->tx_power_max = tx_pwr_max;
1637 pi->tx_power_min = tx_pwr_min;
1638 pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
1639 for (rate = 0; rate < max_num_rate; rate++) {
1641 pi->tx_power_target[rate] = tx_pwr_target[rate];
1643 if (!pi->hwpwrctrl || ISNPHY(pi))
1644 pi->tx_power_offset[rate] =
1645 pi->tx_power_max - pi->tx_power_target[rate];
1647 pi->tx_power_offset[rate] =
1648 pi->tx_power_target[rate] - pi->tx_power_min;
1651 txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
1652 if (txpwr_recalc_fn)
1653 (*txpwr_recalc_fn)(pi);
1657 wlc_phy_txpower_reg_limit_calc(struct brcms_phy *pi, struct txpwr_limits *txpwr,
1660 u8 tmp_txpwr_limit[2 * BRCMS_NUM_RATES_OFDM];
1661 u8 *txpwr_ptr1 = NULL, *txpwr_ptr2 = NULL;
1662 int rate_start_index = 0, rate1, rate2, k;
1664 for (rate1 = WL_TX_POWER_CCK_FIRST, rate2 = 0;
1665 rate2 < WL_TX_POWER_CCK_NUM; rate1++, rate2++)
1666 pi->txpwr_limit[rate1] = txpwr->cck[rate2];
1668 for (rate1 = WL_TX_POWER_OFDM_FIRST, rate2 = 0;
1669 rate2 < WL_TX_POWER_OFDM_NUM; rate1++, rate2++)
1670 pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
1674 for (k = 0; k < 4; k++) {
1678 txpwr_ptr1 = txpwr->mcs_20_siso;
1679 txpwr_ptr2 = txpwr->ofdm;
1680 rate_start_index = WL_TX_POWER_OFDM_FIRST;
1684 txpwr_ptr1 = txpwr->mcs_20_cdd;
1685 txpwr_ptr2 = txpwr->ofdm_cdd;
1686 rate_start_index = WL_TX_POWER_OFDM20_CDD_FIRST;
1690 txpwr_ptr1 = txpwr->mcs_40_siso;
1691 txpwr_ptr2 = txpwr->ofdm_40_siso;
1693 WL_TX_POWER_OFDM40_SISO_FIRST;
1697 txpwr_ptr1 = txpwr->mcs_40_cdd;
1698 txpwr_ptr2 = txpwr->ofdm_40_cdd;
1699 rate_start_index = WL_TX_POWER_OFDM40_CDD_FIRST;
1703 for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
1705 tmp_txpwr_limit[rate2] = 0;
1706 tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
1709 wlc_phy_mcs_to_ofdm_powers_nphy(
1711 BRCMS_NUM_RATES_OFDM -
1712 1, BRCMS_NUM_RATES_OFDM);
1713 for (rate1 = rate_start_index, rate2 = 0;
1714 rate2 < BRCMS_NUM_RATES_OFDM; rate1++, rate2++)
1715 pi->txpwr_limit[rate1] =
1716 min(txpwr_ptr2[rate2],
1717 tmp_txpwr_limit[rate2]);
1720 for (k = 0; k < 4; k++) {
1724 txpwr_ptr1 = txpwr->ofdm;
1725 txpwr_ptr2 = txpwr->mcs_20_siso;
1726 rate_start_index = WL_TX_POWER_MCS20_SISO_FIRST;
1730 txpwr_ptr1 = txpwr->ofdm_cdd;
1731 txpwr_ptr2 = txpwr->mcs_20_cdd;
1732 rate_start_index = WL_TX_POWER_MCS20_CDD_FIRST;
1736 txpwr_ptr1 = txpwr->ofdm_40_siso;
1737 txpwr_ptr2 = txpwr->mcs_40_siso;
1738 rate_start_index = WL_TX_POWER_MCS40_SISO_FIRST;
1742 txpwr_ptr1 = txpwr->ofdm_40_cdd;
1743 txpwr_ptr2 = txpwr->mcs_40_cdd;
1744 rate_start_index = WL_TX_POWER_MCS40_CDD_FIRST;
1747 for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
1749 tmp_txpwr_limit[rate2] = 0;
1750 tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
1753 wlc_phy_ofdm_to_mcs_powers_nphy(
1755 BRCMS_NUM_RATES_OFDM -
1756 1, BRCMS_NUM_RATES_OFDM);
1757 for (rate1 = rate_start_index, rate2 = 0;
1758 rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
1760 pi->txpwr_limit[rate1] =
1761 min(txpwr_ptr2[rate2],
1762 tmp_txpwr_limit[rate2]);
1765 for (k = 0; k < 2; k++) {
1769 rate_start_index = WL_TX_POWER_MCS20_STBC_FIRST;
1770 txpwr_ptr1 = txpwr->mcs_20_stbc;
1774 rate_start_index = WL_TX_POWER_MCS40_STBC_FIRST;
1775 txpwr_ptr1 = txpwr->mcs_40_stbc;
1778 for (rate1 = rate_start_index, rate2 = 0;
1779 rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
1781 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1784 for (k = 0; k < 2; k++) {
1788 rate_start_index = WL_TX_POWER_MCS20_SDM_FIRST;
1789 txpwr_ptr1 = txpwr->mcs_20_mimo;
1793 rate_start_index = WL_TX_POWER_MCS40_SDM_FIRST;
1794 txpwr_ptr1 = txpwr->mcs_40_mimo;
1797 for (rate1 = rate_start_index, rate2 = 0;
1798 rate2 < BRCMS_NUM_RATES_MCS_2_STREAM;
1800 pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
1803 pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
1805 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
1806 min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
1807 pi->txpwr_limit[WL_TX_POWER_MCS_32]);
1808 pi->txpwr_limit[WL_TX_POWER_MCS_32] =
1809 pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
1813 void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi, u8 txpwr_percent)
1815 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1817 pi->txpwr_percent = txpwr_percent;
1820 void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap)
1822 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1824 pi->sh->machwcap = machwcap;
1827 void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end)
1829 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1833 if (start_end == ON) {
1837 if (NREV_IS(pi->pubpi.phy_rev, 3)
1838 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1839 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
1841 bcma_set16(pi->d11core, D11REGOFFS(phyregdata),
1845 if (NREV_IS(pi->pubpi.phy_rev, 3)
1846 || NREV_IS(pi->pubpi.phy_rev, 4)) {
1847 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
1849 bcma_write16(pi->d11core, D11REGOFFS(phyregdata), rxc);
1852 wlc_phy_por_inform(ppi);
1857 wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *txpwr,
1860 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1862 wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
1866 for (i = TXP_FIRST_OFDM_20_CDD, j = 0;
1867 j < BRCMS_NUM_RATES_MCS_1_STREAM; i++, j++) {
1868 if (txpwr->mcs_20_siso[j])
1869 pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
1871 pi->txpwr_limit[i] = txpwr->ofdm[j];
1875 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1877 wlc_phy_txpower_recalc_target(pi);
1878 wlc_phy_cal_txpower_recalc_sw(pi);
1879 wlapi_enable_mac(pi->sh->physhim);
1882 void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war)
1884 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1886 pi->ofdm_rateset_war = war;
1889 void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt)
1891 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
1893 pi->bf_preempt_4306 = bf_preempt;
1896 void wlc_phy_txpower_update_shm(struct brcms_phy *pi)
1905 if (pi->hwpwrctrl) {
1908 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
1909 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
1910 1 << NUM_TSSI_FRAMES);
1912 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
1913 pi->tx_power_min << NUM_TSSI_FRAMES);
1915 wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
1918 for (j = TXP_FIRST_OFDM; j <= TXP_LAST_OFDM; j++) {
1919 static const u8 ucode_ofdm_rates[] = {
1920 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c
1922 offset = wlapi_bmac_rate_shm_offset(
1924 ucode_ofdm_rates[j - TXP_FIRST_OFDM]);
1925 wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
1926 pi->tx_power_offset[j]);
1927 wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
1928 -(pi->tx_power_offset[j] / 2));
1931 wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
1932 MHF2_HWPWRCTL, BRCM_BAND_ALL);
1936 for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++)
1937 pi->tx_power_offset[i] =
1938 (u8) roundup(pi->tx_power_offset[i], 8);
1939 wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
1941 ((pi->tx_power_offset[TXP_FIRST_OFDM]
1946 bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi)
1948 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1951 return pi->nphy_txpwrctrl;
1953 return pi->hwpwrctrl;
1956 void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi, bool hwpwrctrl)
1958 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
1961 if (!pi->hwpwrctrl_capable)
1964 pi->hwpwrctrl = hwpwrctrl;
1965 pi->nphy_txpwrctrl = hwpwrctrl;
1966 pi->txpwrctrl = hwpwrctrl;
1969 suspend = (0 == (bcma_read32(pi->d11core,
1970 D11REGOFFS(maccontrol)) &
1973 wlapi_suspend_mac_and_wait(pi->sh->physhim);
1975 wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
1976 if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
1977 wlc_phy_txpwr_fixpower_nphy(pi);
1979 mod_phy_reg(pi, 0x1e7, (0x7f << 0),
1980 pi->saved_txpwr_idx);
1983 wlapi_enable_mac(pi->sh->physhim);
1987 void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi)
1990 if (NREV_GE(pi->pubpi.phy_rev, 3)) {
1991 pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
1992 pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
1994 pi->ipa2g_on = false;
1995 pi->ipa5g_on = false;
1999 static u32 wlc_phy_txpower_est_power_nphy(struct brcms_phy *pi)
2001 s16 tx0_status, tx1_status;
2002 u16 estPower1, estPower2;
2003 u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
2006 estPower1 = read_phy_reg(pi, 0x118);
2007 estPower2 = read_phy_reg(pi, 0x119);
2009 if ((estPower1 & (0x1 << 8)) == (0x1 << 8))
2010 pwr0 = (u8) (estPower1 & (0xff << 0)) >> 0;
2014 if ((estPower2 & (0x1 << 8)) == (0x1 << 8))
2015 pwr1 = (u8) (estPower2 & (0xff << 0)) >> 0;
2019 tx0_status = read_phy_reg(pi, 0x1ed);
2020 tx1_status = read_phy_reg(pi, 0x1ee);
2022 if ((tx0_status & (0x1 << 15)) == (0x1 << 15))
2023 adj_pwr0 = (u8) (tx0_status & (0xff << 0)) >> 0;
2026 if ((tx1_status & (0x1 << 15)) == (0x1 << 15))
2027 adj_pwr1 = (u8) (tx1_status & (0xff << 0)) >> 0;
2031 est_pwr = (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) |
2038 wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi, struct tx_power *power,
2041 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2042 uint rate, num_rates;
2043 u8 min_pwr, max_pwr;
2045 #if WL_TX_POWER_RATES != TXP_NUM_RATES
2046 #error "struct tx_power out of sync with this fn"
2050 power->rf_cores = 2;
2051 power->flags |= (WL_TX_POWER_F_MIMO);
2052 if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
2054 (WL_TX_POWER_F_ENABLED | WL_TX_POWER_F_HW);
2055 } else if (ISLCNPHY(pi)) {
2056 power->rf_cores = 1;
2057 power->flags |= (WL_TX_POWER_F_SISO);
2058 if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
2059 power->flags |= WL_TX_POWER_F_ENABLED;
2061 power->flags |= WL_TX_POWER_F_HW;
2064 num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
2066 (TXP_LAST_OFDM_20_CDD + 1) : (TXP_LAST_OFDM + 1)));
2068 for (rate = 0; rate < num_rates; rate++) {
2069 power->user_limit[rate] = pi->tx_user_target[rate];
2070 wlc_phy_txpower_sromlimit(ppi, channel, &min_pwr, &max_pwr,
2072 power->board_limit[rate] = (u8) max_pwr;
2073 power->target[rate] = pi->tx_power_target[rate];
2079 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2080 wlc_phyreg_enter((struct brcms_phy_pub *) pi);
2081 est_pout = wlc_phy_txpower_est_power_nphy(pi);
2082 wlc_phyreg_exit((struct brcms_phy_pub *) pi);
2083 wlapi_enable_mac(pi->sh->physhim);
2085 power->est_Pout[0] = (est_pout >> 8) & 0xff;
2086 power->est_Pout[1] = est_pout & 0xff;
2088 power->est_Pout_act[0] = est_pout >> 24;
2089 power->est_Pout_act[1] = (est_pout >> 16) & 0xff;
2091 if (power->est_Pout[0] == 0x80)
2092 power->est_Pout[0] = 0;
2093 if (power->est_Pout[1] == 0x80)
2094 power->est_Pout[1] = 0;
2096 if (power->est_Pout_act[0] == 0x80)
2097 power->est_Pout_act[0] = 0;
2098 if (power->est_Pout_act[1] == 0x80)
2099 power->est_Pout_act[1] = 0;
2101 power->est_Pout_cck = 0;
2103 power->tx_power_max[0] = pi->tx_power_max;
2104 power->tx_power_max[1] = pi->tx_power_max;
2106 power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
2107 power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
2108 } else if (pi->hwpwrctrl && pi->sh->up) {
2110 wlc_phyreg_enter(ppi);
2113 power->tx_power_max[0] = pi->tx_power_max;
2114 power->tx_power_max[1] = pi->tx_power_max;
2116 power->tx_power_max_rate_ind[0] =
2117 pi->tx_power_max_rate_ind;
2118 power->tx_power_max_rate_ind[1] =
2119 pi->tx_power_max_rate_ind;
2121 if (wlc_phy_tpc_isenabled_lcnphy(pi))
2124 WL_TX_POWER_F_ENABLED);
2127 ~(WL_TX_POWER_F_HW |
2128 WL_TX_POWER_F_ENABLED);
2130 wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
2131 (s8 *) &power->est_Pout_cck);
2133 wlc_phyreg_exit(ppi);
2137 void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type)
2139 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2141 pi->antsel_type = antsel_type;
2144 bool wlc_phy_test_ison(struct brcms_phy_pub *ppi)
2146 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2148 return pi->phytest_on;
2151 void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val)
2153 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2156 pi->sh->rx_antdiv = val;
2158 if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
2159 if (val > ANT_RX_DIV_FORCE_1)
2160 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
2161 MHF1_ANTDIV, BRCM_BAND_ALL);
2163 wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
2173 suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
2176 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2179 if (val > ANT_RX_DIV_FORCE_1) {
2180 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
2181 mod_phy_reg(pi, 0x410,
2183 ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0);
2185 mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
2186 mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
2191 wlapi_enable_mac(pi->sh->physhim);
2197 wlc_phy_noise_calc_phy(struct brcms_phy *pi, u32 *cmplx_pwr, s8 *pwr_ant)
2199 s8 cmplx_pwr_dbm[PHY_CORE_MAX];
2202 memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
2203 wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
2205 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2206 if (NREV_GE(pi->pubpi.phy_rev, 3))
2207 cmplx_pwr_dbm[i] += (s8) PHY_NOISE_OFFSETFACT_4322;
2210 cmplx_pwr_dbm[i] += (s8) (16 - (15) * 3 - 70);
2213 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2214 pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
2215 pwr_ant[i] = cmplx_pwr_dbm[i];
2217 pi->nphy_noise_index =
2218 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2222 static void wlc_phy_noise_cb(struct brcms_phy *pi, u8 channel, s8 noise_dbm)
2224 if (!pi->phynoise_state)
2227 if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
2228 if (pi->phynoise_chan_watchdog == channel) {
2229 pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
2231 pi->sh->phy_noise_index =
2232 MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
2234 pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
2237 if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL)
2238 pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
2242 static s8 wlc_phy_noise_read_shmem(struct brcms_phy *pi)
2244 u32 cmplx_pwr[PHY_CORE_MAX];
2245 s8 noise_dbm_ant[PHY_CORE_MAX];
2247 u32 cmplx_pwr_tot = 0;
2248 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2251 memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
2252 memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
2254 for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2,
2256 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
2257 hi = wlapi_bmac_read_shm(pi->sh->physhim,
2258 M_PWRIND_MAP(idx + 1));
2259 cmplx_pwr[core] = (hi << 16) + lo;
2260 cmplx_pwr_tot += cmplx_pwr[core];
2261 if (cmplx_pwr[core] == 0)
2262 noise_dbm_ant[core] = PHY_NOISE_FIXED_VAL_NPHY;
2264 cmplx_pwr[core] >>= PHY_NOISE_SAMPLE_LOG_NUM_UCODE;
2267 if (cmplx_pwr_tot != 0)
2268 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2270 for (core = 0; core < pi->pubpi.phy_corenum; core++) {
2271 pi->nphy_noise_win[core][pi->nphy_noise_index] =
2272 noise_dbm_ant[core];
2274 if (noise_dbm_ant[core] > noise_dbm)
2275 noise_dbm = noise_dbm_ant[core];
2277 pi->nphy_noise_index =
2278 MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
2284 void wlc_phy_noise_sample_intr(struct brcms_phy_pub *pih)
2286 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2289 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2292 u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
2294 s32 pwr_offset_dB, gain_dB;
2295 u16 status_0, status_1;
2297 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2298 channel = jssi_aux & D11_CURCHANNEL_MAX;
2300 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
2301 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
2302 cmplx_pwr0 = (hi << 16) + lo;
2304 lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
2305 hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
2306 cmplx_pwr1 = (hi << 16) + lo;
2307 cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6;
2310 status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
2311 if ((cmplx_pwr > 0 && cmplx_pwr < 500)
2312 && ((status_1 & 0xc000) == 0x4000)) {
2314 wlc_phy_compute_dB(&cmplx_pwr, &noise_dbm,
2315 pi->pubpi.phy_corenum);
2316 pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
2317 if (pwr_offset_dB > 127)
2318 pwr_offset_dB -= 256;
2320 noise_dbm += (s8) (pwr_offset_dB - 30);
2322 gain_dB = (status_0 & 0x1ff);
2323 noise_dbm -= (s8) (gain_dB);
2325 noise_dbm = PHY_NOISE_FIXED_VAL_LCNPHY;
2327 } else if (ISNPHY(pi)) {
2329 jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
2330 channel = jssi_aux & D11_CURCHANNEL_MAX;
2332 noise_dbm = wlc_phy_noise_read_shmem(pi);
2335 wlc_phy_noise_cb(pi, channel, noise_dbm);
2340 wlc_phy_noise_sample_request(struct brcms_phy_pub *pih, u8 reason, u8 ch)
2342 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2343 s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2344 bool sampling_in_progress = (pi->phynoise_state != 0);
2345 bool wait_for_intr = true;
2348 case PHY_NOISE_SAMPLE_MON:
2349 pi->phynoise_chan_watchdog = ch;
2350 pi->phynoise_state |= PHY_NOISE_STATE_MON;
2353 case PHY_NOISE_SAMPLE_EXTERNAL:
2354 pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
2361 if (sampling_in_progress)
2364 pi->phynoise_now = pi->sh->now;
2366 if (pi->phy_fixed_noise) {
2368 pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
2369 PHY_NOISE_FIXED_VAL_NPHY;
2370 pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
2371 PHY_NOISE_FIXED_VAL_NPHY;
2372 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2373 PHY_NOISE_WINDOW_SZ);
2374 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
2376 noise_dbm = PHY_NOISE_FIXED_VAL;
2379 wait_for_intr = false;
2384 if (!pi->phynoise_polling
2385 || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
2386 wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
2387 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2388 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2389 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2390 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2392 bcma_set32(pi->d11core, D11REGOFFS(maccommand),
2395 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2396 wlc_lcnphy_deaf_mode(pi, (bool) 0);
2397 noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
2398 wlc_lcnphy_deaf_mode(pi, (bool) 1);
2399 wlapi_enable_mac(pi->sh->physhim);
2400 wait_for_intr = false;
2402 } else if (ISNPHY(pi)) {
2403 if (!pi->phynoise_polling
2404 || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
2406 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
2407 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
2408 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
2409 wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
2411 bcma_set32(pi->d11core, D11REGOFFS(maccommand),
2414 struct phy_iq_est est[PHY_CORE_MAX];
2415 u32 cmplx_pwr[PHY_CORE_MAX];
2416 s8 noise_dbm_ant[PHY_CORE_MAX];
2417 u16 log_num_samps, num_samps, classif_state = 0;
2422 memset((u8 *) est, 0, sizeof(est));
2423 memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
2424 memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
2426 log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
2427 num_samps = 1 << log_num_samps;
2429 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2430 classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
2431 wlc_phy_classifier_nphy(pi, 3, 0);
2432 wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
2434 wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
2435 wlapi_enable_mac(pi->sh->physhim);
2437 for (i = 0; i < pi->pubpi.phy_corenum; i++)
2438 cmplx_pwr[i] = (est[i].i_pwr + est[i].q_pwr) >>
2441 wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
2443 for (i = 0; i < pi->pubpi.phy_corenum; i++) {
2444 pi->nphy_noise_win[i][pi->nphy_noise_index] =
2447 if (noise_dbm_ant[i] > noise_dbm)
2448 noise_dbm = noise_dbm_ant[i];
2450 pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
2451 PHY_NOISE_WINDOW_SZ);
2453 wait_for_intr = false;
2460 wlc_phy_noise_cb(pi, ch, noise_dbm);
2464 void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *pih)
2468 channel = CHSPEC_CHANNEL(wlc_phy_chanspec_get(pih));
2470 wlc_phy_noise_sample_request(pih, PHY_NOISE_SAMPLE_EXTERNAL, channel);
2473 static const s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
2514 void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
2516 u8 msb, secondmsb, i;
2519 for (i = 0; i < core; i++) {
2524 secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
2525 p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
2529 int wlc_phy_rssi_compute(struct brcms_phy_pub *pih,
2530 struct d11rxhdr *rxh)
2532 int rssi = rxh->PhyRxStatus_1 & PRXS1_JSSI_MASK;
2533 uint radioid = pih->radioid;
2534 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2536 if ((pi->sh->corerev >= 11)
2537 && !(rxh->RxStatus2 & RXS_PHYRXST_VALID)) {
2538 rssi = BRCMS_RSSI_INVALID;
2543 u8 gidx = (rxh->PhyRxStatus_2 & 0xFC00) >> 10;
2544 struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
2549 rssi = rssi + lcnphy_gain_index_offset_for_pkt_rssi[gidx];
2550 if ((rssi > -46) && (gidx > 18))
2553 rssi = rssi + pi_lcn->lcnphy_pkteng_rssi_slope;
2562 } else if (radioid == BCM2055_ID || radioid == BCM2056_ID
2563 || radioid == BCM2057_ID) {
2564 rssi = wlc_phy_rssi_compute_nphy(pi, rxh);
2571 void wlc_phy_freqtrack_start(struct brcms_phy_pub *pih)
2576 void wlc_phy_freqtrack_end(struct brcms_phy_pub *pih)
2581 void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag)
2583 struct brcms_phy *pi;
2584 pi = (struct brcms_phy *) ppi;
2587 wlc_lcnphy_deaf_mode(pi, true);
2588 else if (ISNPHY(pi))
2589 wlc_nphy_deaf_mode(pi, true);
2592 void wlc_phy_watchdog(struct brcms_phy_pub *pih)
2594 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2595 bool delay_phy_cal = false;
2598 if (!pi->watchdog_override)
2601 if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)))
2602 wlc_phy_noise_sample_request((struct brcms_phy_pub *) pi,
2603 PHY_NOISE_SAMPLE_MON,
2607 if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5)
2608 pi->phynoise_state = 0;
2610 if ((!pi->phycal_txpower) ||
2611 ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
2613 if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi))
2614 pi->phycal_txpower = pi->sh->now;
2617 if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2618 || ASSOC_INPROG_PHY(pi)))
2621 if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
2623 if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
2624 (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
2625 ((pi->sh->now - pi->nphy_perical_last) >=
2626 pi->sh->glacial_timer))
2627 wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
2628 PHY_PERICAL_WATCHDOG);
2630 wlc_phy_txpwr_papd_cal_nphy(pi);
2634 if (pi->phy_forcecal ||
2635 ((pi->sh->now - pi->phy_lastcal) >=
2636 pi->sh->glacial_timer)) {
2637 if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
2638 wlc_lcnphy_calib_modes(
2640 LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
2642 (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
2643 || ASSOC_INPROG_PHY(pi)
2644 || pi->carrier_suppr_disable
2645 || pi->disable_percal))
2646 wlc_lcnphy_calib_modes(pi,
2647 PHY_PERICAL_WATCHDOG);
2652 void wlc_phy_BSSinit(struct brcms_phy_pub *pih, bool bonlyap, int rssi)
2654 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2658 for (i = 0; i < MA_WINDOW_SZ; i++)
2659 pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
2661 for (i = 0; i < MA_WINDOW_SZ; i++)
2662 pi->sh->phy_noise_window[i] =
2663 PHY_NOISE_FIXED_VAL_LCNPHY;
2665 pi->sh->phy_noise_index = 0;
2667 for (i = 0; i < PHY_NOISE_WINDOW_SZ; i++) {
2668 for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++)
2669 pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
2671 pi->nphy_noise_index = 0;
2675 wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag)
2677 *eps_imag = (epsilon >> 13);
2678 if (*eps_imag > 0xfff)
2679 *eps_imag -= 0x2000;
2681 *eps_real = (epsilon & 0x1fff);
2682 if (*eps_real > 0xfff)
2683 *eps_real -= 0x2000;
2686 void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi)
2688 wlapi_del_timer(pi->phycal_timer);
2690 pi->cal_type_override = PHY_PERICAL_AUTO;
2691 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
2692 pi->mphase_txcal_cmdidx = 0;
2696 wlc_phy_cal_perical_mphase_schedule(struct brcms_phy *pi, uint delay)
2699 if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
2700 (pi->nphy_perical != PHY_PERICAL_MANUAL))
2703 wlapi_del_timer(pi->phycal_timer);
2705 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2706 wlapi_add_timer(pi->phycal_timer, delay, 0);
2709 void wlc_phy_cal_perical(struct brcms_phy_pub *pih, u8 reason)
2711 s16 nphy_currtemp = 0;
2713 bool do_periodic_cal = true;
2714 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2719 if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
2720 (pi->nphy_perical == PHY_PERICAL_MANUAL))
2724 case PHY_PERICAL_DRIVERUP:
2727 case PHY_PERICAL_PHYINIT:
2728 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2729 if (PHY_PERICAL_MPHASE_PENDING(pi))
2730 wlc_phy_cal_perical_mphase_reset(pi);
2732 wlc_phy_cal_perical_mphase_schedule(
2734 PHY_PERICAL_INIT_DELAY);
2738 case PHY_PERICAL_JOIN_BSS:
2739 case PHY_PERICAL_START_IBSS:
2740 case PHY_PERICAL_UP_BSS:
2741 if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
2742 PHY_PERICAL_MPHASE_PENDING(pi))
2743 wlc_phy_cal_perical_mphase_reset(pi);
2745 pi->first_cal_after_assoc = true;
2747 pi->cal_type_override = PHY_PERICAL_FULL;
2749 if (pi->phycal_tempdelta)
2750 pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
2752 wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
2755 case PHY_PERICAL_WATCHDOG:
2756 if (pi->phycal_tempdelta) {
2757 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2759 (nphy_currtemp > pi->nphy_lastcal_temp) ?
2760 nphy_currtemp - pi->nphy_lastcal_temp :
2761 pi->nphy_lastcal_temp - nphy_currtemp;
2763 if ((delta_temp < (s16) pi->phycal_tempdelta) &&
2764 (pi->nphy_txiqlocal_chanspec ==
2765 pi->radio_chanspec))
2766 do_periodic_cal = false;
2768 pi->nphy_lastcal_temp = nphy_currtemp;
2771 if (do_periodic_cal) {
2772 if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
2773 if (!PHY_PERICAL_MPHASE_PENDING(pi))
2774 wlc_phy_cal_perical_mphase_schedule(
2776 PHY_PERICAL_WDOG_DELAY);
2777 } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
2778 wlc_phy_cal_perical_nphy_run(pi,
2787 void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi)
2789 pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
2790 pi->mphase_txcal_cmdidx = 0;
2793 u8 wlc_phy_nbits(s32 value)
2798 abs_val = abs(value);
2799 while ((abs_val >> nbits) > 0)
2805 void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
2807 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2809 pi->sh->hw_phytxchain = txchain;
2810 pi->sh->hw_phyrxchain = rxchain;
2811 pi->sh->phytxchain = txchain;
2812 pi->sh->phyrxchain = rxchain;
2813 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2816 void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
2818 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2820 pi->sh->phytxchain = txchain;
2823 wlc_phy_rxcore_setstate_nphy(pih, rxchain);
2825 pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
2828 void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain, u8 *rxchain)
2830 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2832 *txchain = pi->sh->phytxchain;
2833 *rxchain = pi->sh->phyrxchain;
2836 u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih)
2840 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2842 active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
2844 if (!pi->watchdog_override)
2845 return active_bitmap;
2847 if (NREV_GE(pi->pubpi.phy_rev, 6)) {
2848 wlapi_suspend_mac_and_wait(pi->sh->physhim);
2849 nphy_currtemp = wlc_phy_tempsense_nphy(pi);
2850 wlapi_enable_mac(pi->sh->physhim);
2852 if (!pi->phy_txcore_heatedup) {
2853 if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
2854 active_bitmap &= 0xFD;
2855 pi->phy_txcore_heatedup = true;
2858 if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
2859 active_bitmap |= 0x2;
2860 pi->phy_txcore_heatedup = false;
2865 return active_bitmap;
2868 s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih, u16 chanspec)
2870 struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
2871 u8 siso_mcs_id, cdd_mcs_id;
2874 (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_SISO :
2875 TXP_FIRST_MCS_20_SISO;
2877 (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_CDD :
2878 TXP_FIRST_MCS_20_CDD;
2880 if (pi->tx_power_target[siso_mcs_id] >
2881 (pi->tx_power_target[cdd_mcs_id] + 12))
2882 return PHY_TXC1_MODE_SISO;
2884 return PHY_TXC1_MODE_CDD;
2887 const u8 *wlc_phy_get_ofdm_rate_lookup(void)
2889 return ofdm_rate_lookup;
2892 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
2894 if ((pi->sh->chip == BCMA_CHIP_ID_BCM4313) &&
2895 (pi->sh->boardflags & BFL_FEM)) {
2898 txant = wlapi_bmac_get_txant(pi->sh->physhim);
2900 mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
2902 mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
2906 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
2908 bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
2910 bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
2913 mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
2915 mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
2917 bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
2919 bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
2921 bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
2927 void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool ldpc)
2933 wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, s8 *ofdmoffset)
2939 s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec)
2945 bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *ppi)
2947 struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
2950 return wlc_phy_n_txpower_ipa_ison(pi);