2 * Copyright (c) 2010 Broadcom Corporation
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/types.h>
18 #include <linux/atomic.h>
19 #include <linux/kernel.h>
20 #include <linux/kthread.h>
21 #include <linux/printk.h>
22 #include <linux/pci_ids.h>
23 #include <linux/netdevice.h>
24 #include <linux/interrupt.h>
25 #include <linux/sched.h>
26 #include <linux/mmc/sdio.h>
27 #include <linux/mmc/sdio_ids.h>
28 #include <linux/mmc/sdio_func.h>
29 #include <linux/mmc/card.h>
30 #include <linux/semaphore.h>
31 #include <linux/firmware.h>
32 #include <linux/module.h>
33 #include <linux/bcma/bcma.h>
34 #include <linux/debugfs.h>
35 #include <linux/vmalloc.h>
36 #include <asm/unaligned.h>
38 #include <brcmu_wifi.h>
39 #include <brcmu_utils.h>
40 #include <brcm_hw_ids.h>
48 #define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500)
49 #define CTL_DONE_TIMEOUT msecs_to_jiffies(2500)
53 #define BRCMF_TRAP_INFO_SIZE 80
55 #define CBUF_LEN (128)
57 /* Device console log buffer state */
58 #define CONSOLE_BUFFER_MAX 2024
61 __le32 buf; /* Can't be pointer on (64-bit) hosts */
64 char *_buf_compat; /* Redundant pointer for backward compat. */
69 * When there is no UART (e.g. Quickturn),
70 * the host should write a complete
71 * input line directly into cbuf and then write
72 * the length into vcons_in.
73 * This may also be used when there is a real UART
74 * (at risk of conflicting with
75 * the real UART). vcons_out is currently unused.
80 /* Output (logging) buffer
81 * Console output is written to a ring buffer log_buf at index log_idx.
82 * The host may read the output when it sees log_idx advance.
83 * Output will be lost if the output wraps around faster than the host
86 struct rte_log_le log_le;
88 /* Console input line buffer
89 * Characters are read one at a time into cbuf
90 * until <CR> is received, then
91 * the buffer is processed as a command line.
92 * Also used for virtual UART.
99 #include <chipcommon.h>
103 #include "tracepoint.h"
105 #define TXQLEN 2048 /* bulk tx queue length */
106 #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
107 #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
110 #define TXRETRIES 2 /* # of retries for tx frames */
112 #define BRCMF_RXBOUND 50 /* Default for max rx frames in
115 #define BRCMF_TXBOUND 20 /* Default for max tx frames in
118 #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
120 #define MEMBLOCK 2048 /* Block size used for downloading
122 #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
123 biggest possible glom */
125 #define BRCMF_FIRSTREAD (1 << 6)
127 #define BRCMF_CONSOLE 10 /* watchdog interval to poll console */
129 /* SBSDIO_DEVICE_CTL */
131 /* 1: device will assert busy signal when receiving CMD53 */
132 #define SBSDIO_DEVCTL_SETBUSY 0x01
133 /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
134 #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
135 /* 1: mask all interrupts to host except the chipActive (rev 8) */
136 #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
137 /* 1: isolate internal sdio signals, put external pads in tri-state; requires
138 * sdio bus power cycle to clear (rev 9) */
139 #define SBSDIO_DEVCTL_PADS_ISO 0x08
140 /* Force SD->SB reset mapping (rev 11) */
141 #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
142 /* Determined by CoreControl bit */
143 #define SBSDIO_DEVCTL_RST_CORECTL 0x00
144 /* Force backplane reset */
145 #define SBSDIO_DEVCTL_RST_BPRESET 0x10
146 /* Force no backplane reset */
147 #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
149 /* direct(mapped) cis space */
151 /* MAPPED common CIS address */
152 #define SBSDIO_CIS_BASE_COMMON 0x1000
153 /* maximum bytes in one CIS */
154 #define SBSDIO_CIS_SIZE_LIMIT 0x200
155 /* cis offset addr is < 17 bits */
156 #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
158 /* manfid tuple length, include tuple, link bytes */
159 #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
161 #define CORE_BUS_REG(base, field) \
162 (base + offsetof(struct sdpcmd_regs, field))
164 /* SDIO function 1 register CHIPCLKCSR */
165 /* Force ALP request to backplane */
166 #define SBSDIO_FORCE_ALP 0x01
167 /* Force HT request to backplane */
168 #define SBSDIO_FORCE_HT 0x02
169 /* Force ILP request to backplane */
170 #define SBSDIO_FORCE_ILP 0x04
171 /* Make ALP ready (power up xtal) */
172 #define SBSDIO_ALP_AVAIL_REQ 0x08
173 /* Make HT ready (power up PLL) */
174 #define SBSDIO_HT_AVAIL_REQ 0x10
175 /* Squelch clock requests from HW */
176 #define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20
177 /* Status: ALP is ready */
178 #define SBSDIO_ALP_AVAIL 0x40
179 /* Status: HT is ready */
180 #define SBSDIO_HT_AVAIL 0x80
181 #define SBSDIO_CSR_MASK 0x1F
182 #define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL)
183 #define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS)
184 #define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS)
185 #define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval))
186 #define SBSDIO_CLKAV(regval, alponly) \
187 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval)))
190 #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
191 #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
192 #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
193 #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
194 #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
195 #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
196 #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
197 #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
198 #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
199 #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
200 #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
201 #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
202 #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
203 #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
204 #define I_PC (1 << 10) /* descriptor error */
205 #define I_PD (1 << 11) /* data error */
206 #define I_DE (1 << 12) /* Descriptor protocol Error */
207 #define I_RU (1 << 13) /* Receive descriptor Underflow */
208 #define I_RO (1 << 14) /* Receive fifo Overflow */
209 #define I_XU (1 << 15) /* Transmit fifo Underflow */
210 #define I_RI (1 << 16) /* Receive Interrupt */
211 #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
212 #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
213 #define I_XI (1 << 24) /* Transmit Interrupt */
214 #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
215 #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
216 #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
217 #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
218 #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
219 #define I_SRESET (1 << 30) /* CCCR RES interrupt */
220 #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
221 #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
222 #define I_DMA (I_RI | I_XI | I_ERRORS)
225 #define CC_CISRDY (1 << 0) /* CIS Ready */
226 #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
227 #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
228 #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
229 #define CC_XMTDATAAVAIL_MODE (1 << 4)
230 #define CC_XMTDATAAVAIL_CTRL (1 << 5)
233 #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
234 #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
235 #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
236 #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
239 * Software allocation of To SB Mailbox resources
242 /* tosbmailbox bits corresponding to intstatus bits */
243 #define SMB_NAK (1 << 0) /* Frame NAK */
244 #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
245 #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
246 #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
248 /* tosbmailboxdata */
249 #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
252 * Software allocation of To Host Mailbox resources
256 #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
257 #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
258 #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
259 #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
261 /* tohostmailboxdata */
262 #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
263 #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
264 #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
265 #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
267 #define HMB_DATA_FCDATA_MASK 0xff000000
268 #define HMB_DATA_FCDATA_SHIFT 24
270 #define HMB_DATA_VERSION_MASK 0x00ff0000
271 #define HMB_DATA_VERSION_SHIFT 16
274 * Software-defined protocol header
277 /* Current protocol version */
278 #define SDPCM_PROT_VERSION 4
281 * Shared structure between dongle and the host.
282 * The structure contains pointers to trap or assert information.
284 #define SDPCM_SHARED_VERSION 0x0003
285 #define SDPCM_SHARED_VERSION_MASK 0x00FF
286 #define SDPCM_SHARED_ASSERT_BUILT 0x0100
287 #define SDPCM_SHARED_ASSERT 0x0200
288 #define SDPCM_SHARED_TRAP 0x0400
290 /* Space for header read, limit for data packets */
291 #define MAX_HDR_READ (1 << 6)
292 #define MAX_RX_DATASZ 2048
294 /* Bump up limit on waiting for HT to account for first startup;
295 * if the image is doing a CRC calculation before programming the PMU
296 * for HT availability, it could take a couple hundred ms more, so
297 * max out at a 1 second (1000000us).
299 #undef PMU_MAX_TRANSITION_DLY
300 #define PMU_MAX_TRANSITION_DLY 1000000
302 /* Value for ChipClockCSR during initial setup */
303 #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
304 SBSDIO_ALP_AVAIL_REQ)
306 /* Flags for SDH calls */
307 #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
309 #define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change
312 #define BRCMF_IDLE_INTERVAL 1
314 #define KSO_WAIT_US 50
315 #define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US)
316 #define BRCMF_SDIO_MAX_ACCESS_ERRORS 5
319 * Conversion of 802.1D priority to precedence level
321 static uint prio2prec(u32 prio)
323 return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
328 /* Device console log buffer state */
329 struct brcmf_console {
330 uint count; /* Poll interval msec counter */
331 uint log_addr; /* Log struct address (fixed) */
332 struct rte_log_le log_le; /* Log struct (host copy) */
333 uint bufsize; /* Size of log buffer */
334 u8 *buf; /* Log buffer (host copy) */
335 uint last; /* Last buffer read index */
338 struct brcmf_trap_info {
352 __le32 r9; /* sb/v6 */
353 __le32 r10; /* sl/v7 */
354 __le32 r11; /* fp/v8 */
362 struct sdpcm_shared {
366 u32 assert_file_addr;
368 u32 console_addr; /* Address of struct rte_console */
374 struct sdpcm_shared_le {
377 __le32 assert_exp_addr;
378 __le32 assert_file_addr;
380 __le32 console_addr; /* Address of struct rte_console */
381 __le32 msgtrace_addr;
386 /* dongle SDIO bus specific header info */
387 struct brcmf_sdio_hdrinfo {
399 * hold counter variables
401 struct brcmf_sdio_count {
402 uint intrcount; /* Count of device interrupt callbacks */
403 uint lastintrs; /* Count as of last watchdog timer */
404 uint pollcnt; /* Count of active polls */
405 uint regfails; /* Count of R_REG failures */
406 uint tx_sderrs; /* Count of tx attempts with sd errors */
407 uint fcqueued; /* Tx packets that got queued */
408 uint rxrtx; /* Count of rtx requests (NAK to dongle) */
409 uint rx_toolong; /* Receive frames too long to receive */
410 uint rxc_errors; /* SDIO errors when reading control frames */
411 uint rx_hdrfail; /* SDIO errors on header reads */
412 uint rx_badhdr; /* Bad received headers (roosync?) */
413 uint rx_badseq; /* Mismatched rx sequence number */
414 uint fc_rcvd; /* Number of flow-control events received */
415 uint fc_xoff; /* Number which turned on flow-control */
416 uint fc_xon; /* Number which turned off flow-control */
417 uint rxglomfail; /* Failed deglom attempts */
418 uint rxglomframes; /* Number of glom frames (superframes) */
419 uint rxglompkts; /* Number of packets from glom frames */
420 uint f2rxhdrs; /* Number of header reads */
421 uint f2rxdata; /* Number of frame data reads */
422 uint f2txdata; /* Number of f2 frame writes */
423 uint f1regdata; /* Number of f1 register accesses */
424 uint tickcnt; /* Number of watchdog been schedule */
425 ulong tx_ctlerrs; /* Err of sending ctrl frames */
426 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */
427 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */
428 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */
429 ulong rx_readahead_cnt; /* packets where header read-ahead was used */
432 /* misc chip info needed by some of the routines */
433 /* Private data for SDIO bus interaction */
435 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
436 struct brcmf_chip *ci; /* Chip info struct */
438 u32 hostintmask; /* Copy of Host Interrupt Mask */
439 atomic_t intstatus; /* Intstatus bits (events) pending */
440 atomic_t fcstate; /* State of dongle flow-control */
442 uint blocksize; /* Block size of SDIO transfers */
443 uint roundup; /* Max roundup limit */
445 struct pktq txq; /* Queue length used for flow-control */
446 u8 flowcontrol; /* per prio flow control bitmask */
447 u8 tx_seq; /* Transmit sequence number (next) */
448 u8 tx_max; /* Maximum transmit sequence allowed */
450 u8 *hdrbuf; /* buffer for handling rx frame */
451 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
452 u8 rx_seq; /* Receive sequence number (expected) */
453 struct brcmf_sdio_hdrinfo cur_read;
454 /* info of current read frame */
455 bool rxskip; /* Skip receive (awaiting NAK ACK) */
456 bool rxpending; /* Data frame pending in dongle */
458 uint rxbound; /* Rx frames to read before resched */
459 uint txbound; /* Tx frames to send before resched */
462 struct sk_buff *glomd; /* Packet containing glomming descriptor */
463 struct sk_buff_head glom; /* Packet list for glommed superframe */
465 u8 *rxbuf; /* Buffer for receiving control packets */
466 uint rxblen; /* Allocated length of rxbuf */
467 u8 *rxctl; /* Aligned pointer into rxbuf */
468 u8 *rxctl_orig; /* pointer for freeing rxctl */
469 uint rxlen; /* Length of valid data in buffer */
470 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */
472 u8 sdpcm_ver; /* Bus protocol reported by dongle */
474 bool intr; /* Use interrupts */
475 bool poll; /* Use polling */
476 atomic_t ipend; /* Device interrupt is pending */
477 uint spurious; /* Count of spurious interrupts */
478 uint pollrate; /* Ticks between device polls */
479 uint polltick; /* Tick counter */
482 uint console_interval;
483 struct brcmf_console console; /* Console output polling support */
484 uint console_addr; /* Console address from shared struct */
487 uint clkstate; /* State of sd and backplane clock(s) */
488 s32 idletime; /* Control for activity timeout */
489 s32 idlecount; /* Activity timeout counter */
490 s32 idleclock; /* How to set bus driver when idle */
491 bool rxflow_mode; /* Rx flow control mode */
492 bool rxflow; /* Is rx flow control on */
493 bool alp_only; /* Don't use HT clock (ALP only) */
497 bool ctrl_frame_stat;
500 spinlock_t txq_lock; /* protect bus->txq */
501 wait_queue_head_t ctrl_wait;
502 wait_queue_head_t dcmd_resp_wait;
504 struct timer_list timer;
505 struct completion watchdog_wait;
506 struct task_struct *watchdog_tsk;
509 struct workqueue_struct *brcmf_wq;
510 struct work_struct datawork;
514 bool txoff; /* Transmit flow-controlled */
515 struct brcmf_sdio_count sdcnt;
516 bool sr_enabled; /* SaveRestore enabled */
519 u8 tx_hdrlen; /* sdio bus header length for tx packet */
520 bool txglom; /* host tx glomming enable flag */
521 u16 head_align; /* buffer pointer alignment */
522 u16 sgentry_align; /* scatter-gather buffer alignment */
528 #define CLK_PENDING 2
532 static int qcount[NUMPRIO];
535 #define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */
537 #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
539 /* Limit on rounding up frames */
540 static const uint max_roundup = 512;
544 enum brcmf_sdio_frmtype {
545 BRCMF_SDIO_FT_NORMAL,
550 #define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu))
552 /* SDIO Pad drive strength to select value mappings */
553 struct sdiod_drive_str {
554 u8 strength; /* Pad Drive Strength in mA */
555 u8 sel; /* Chip-specific select value */
558 /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */
559 static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = {
570 /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */
571 static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = {
581 /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */
582 static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = {
588 /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */
589 static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = {
596 BRCMF_FW_NVRAM_DEF(43143, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
597 BRCMF_FW_NVRAM_DEF(43241B0, "/*(DEBLOBBED)*/",
599 BRCMF_FW_NVRAM_DEF(43241B4, "/*(DEBLOBBED)*/",
601 BRCMF_FW_NVRAM_DEF(43241B5, "/*(DEBLOBBED)*/",
603 BRCMF_FW_NVRAM_DEF(4329, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
604 BRCMF_FW_NVRAM_DEF(4330, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
605 BRCMF_FW_NVRAM_DEF(4334, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
606 BRCMF_FW_NVRAM_DEF(43340, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
607 BRCMF_FW_NVRAM_DEF(4335, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
608 BRCMF_FW_NVRAM_DEF(43362, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
609 BRCMF_FW_NVRAM_DEF(4339, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
610 BRCMF_FW_NVRAM_DEF(43430, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
611 BRCMF_FW_NVRAM_DEF(43455, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
612 BRCMF_FW_NVRAM_DEF(4354, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
613 BRCMF_FW_NVRAM_DEF(4356, "/*(DEBLOBBED)*/", "/*(DEBLOBBED)*/");
615 static struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = {
616 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143),
617 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0),
618 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4),
619 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5),
620 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329),
621 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330),
622 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334),
623 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340),
624 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335),
625 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362),
626 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339),
627 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFF, 43430),
628 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFFC0, 43455),
629 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354),
630 BRCMF_FW_NVRAM_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356)
633 static void pkt_align(struct sk_buff *p, int len, int align)
636 datalign = (unsigned long)(p->data);
637 datalign = roundup(datalign, (align)) - datalign;
639 skb_pull(p, datalign);
643 /* To check if there's window offered */
644 static bool data_ok(struct brcmf_sdio *bus)
646 return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
647 ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
651 * Reads a register in the SDIO hardware block. This block occupies a series of
652 * adresses on the 32 bit backplane bus.
654 static int r_sdreg32(struct brcmf_sdio *bus, u32 *regvar, u32 offset)
656 struct brcmf_core *core;
659 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
660 *regvar = brcmf_sdiod_regrl(bus->sdiodev, core->base + offset, &ret);
665 static int w_sdreg32(struct brcmf_sdio *bus, u32 regval, u32 reg_offset)
667 struct brcmf_core *core;
670 core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
671 brcmf_sdiod_regwl(bus->sdiodev, core->base + reg_offset, regval, &ret);
677 brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on)
679 u8 wr_val = 0, rd_val, cmp_val, bmask;
684 brcmf_dbg(TRACE, "Enter: on=%d\n", on);
686 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
687 /* 1st KSO write goes to AOS wake up core if device is asleep */
688 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
692 /* device WAKEUP through KSO:
693 * write bit 0 & read back until
694 * both bits 0 (kso bit) & 1 (dev on status) are set
696 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK |
697 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK;
699 usleep_range(2000, 3000);
701 /* Put device to sleep, turn off KSO */
703 /* only check for bit0, bit1(dev on status) may not
704 * get cleared right away
706 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK;
710 /* reliable KSO bit set/clr:
711 * the sdiod sleep write access is synced to PMU 32khz clk
712 * just one write attempt may fail,
713 * read it back until it matches written value
715 rd_val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
718 if ((rd_val & bmask) == cmp_val)
722 /* bail out upon subsequent access errors */
723 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS))
726 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
728 } while (try_cnt++ < MAX_KSO_ATTEMPTS);
731 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt,
734 if (try_cnt > MAX_KSO_ATTEMPTS)
735 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err);
740 #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
742 /* Turn backplane clock on or off */
743 static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok)
746 u8 clkctl, clkreq, devctl;
747 unsigned long timeout;
749 brcmf_dbg(SDIO, "Enter\n");
753 if (bus->sr_enabled) {
754 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY);
759 /* Request HT Avail */
761 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
763 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
766 brcmf_err("HT Avail request error: %d\n", err);
770 /* Check current status */
771 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
772 SBSDIO_FUNC1_CHIPCLKCSR, &err);
774 brcmf_err("HT Avail read error: %d\n", err);
778 /* Go to pending and await interrupt if appropriate */
779 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
780 /* Allow only clock-available interrupt */
781 devctl = brcmf_sdiod_regrb(bus->sdiodev,
782 SBSDIO_DEVICE_CTL, &err);
784 brcmf_err("Devctl error setting CA: %d\n",
789 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
790 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
792 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n");
793 bus->clkstate = CLK_PENDING;
796 } else if (bus->clkstate == CLK_PENDING) {
797 /* Cancel CA-only interrupt filter */
798 devctl = brcmf_sdiod_regrb(bus->sdiodev,
799 SBSDIO_DEVICE_CTL, &err);
800 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
801 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
805 /* Otherwise, wait here (polling) for HT Avail */
807 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
808 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
809 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
810 SBSDIO_FUNC1_CHIPCLKCSR,
812 if (time_after(jiffies, timeout))
815 usleep_range(5000, 10000);
818 brcmf_err("HT Avail request error: %d\n", err);
821 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
822 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n",
823 PMU_MAX_TRANSITION_DLY, clkctl);
827 /* Mark clock available */
828 bus->clkstate = CLK_AVAIL;
829 brcmf_dbg(SDIO, "CLKCTL: turned ON\n");
832 if (!bus->alp_only) {
833 if (SBSDIO_ALPONLY(clkctl))
834 brcmf_err("HT Clock should be on\n");
836 #endif /* defined (DEBUG) */
841 if (bus->clkstate == CLK_PENDING) {
842 /* Cancel CA-only interrupt filter */
843 devctl = brcmf_sdiod_regrb(bus->sdiodev,
844 SBSDIO_DEVICE_CTL, &err);
845 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
846 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
850 bus->clkstate = CLK_SDONLY;
851 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
853 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n");
855 brcmf_err("Failed access turning clock off: %d\n",
863 /* Change idle/active SD state */
864 static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on)
866 brcmf_dbg(SDIO, "Enter\n");
869 bus->clkstate = CLK_SDONLY;
871 bus->clkstate = CLK_NONE;
876 /* Transition SD and backplane clock readiness */
877 static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok)
880 uint oldstate = bus->clkstate;
883 brcmf_dbg(SDIO, "Enter\n");
885 /* Early exit if we're already there */
886 if (bus->clkstate == target)
891 /* Make sure SD clock is available */
892 if (bus->clkstate == CLK_NONE)
893 brcmf_sdio_sdclk(bus, true);
894 /* Now request HT Avail on the backplane */
895 brcmf_sdio_htclk(bus, true, pendok);
899 /* Remove HT request, or bring up SD clock */
900 if (bus->clkstate == CLK_NONE)
901 brcmf_sdio_sdclk(bus, true);
902 else if (bus->clkstate == CLK_AVAIL)
903 brcmf_sdio_htclk(bus, false, false);
905 brcmf_err("request for %d -> %d\n",
906 bus->clkstate, target);
910 /* Make sure to remove HT request */
911 if (bus->clkstate == CLK_AVAIL)
912 brcmf_sdio_htclk(bus, false, false);
913 /* Now remove the SD clock */
914 brcmf_sdio_sdclk(bus, false);
918 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate);
925 brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok)
930 brcmf_dbg(SDIO, "Enter: request %s currently %s\n",
931 (sleep ? "SLEEP" : "WAKE"),
932 (bus->sleeping ? "SLEEP" : "WAKE"));
934 /* If SR is enabled control bus state with KSO */
935 if (bus->sr_enabled) {
936 /* Done if we're already in the requested state */
937 if (sleep == bus->sleeping)
942 clkcsr = brcmf_sdiod_regrb(bus->sdiodev,
943 SBSDIO_FUNC1_CHIPCLKCSR,
945 if ((clkcsr & SBSDIO_CSR_MASK) == 0) {
946 brcmf_dbg(SDIO, "no clock, set ALP\n");
947 brcmf_sdiod_regwb(bus->sdiodev,
948 SBSDIO_FUNC1_CHIPCLKCSR,
949 SBSDIO_ALP_AVAIL_REQ, &err);
951 err = brcmf_sdio_kso_control(bus, false);
953 err = brcmf_sdio_kso_control(bus, true);
956 brcmf_err("error while changing bus sleep state %d\n",
965 if (!bus->sr_enabled)
966 brcmf_sdio_clkctl(bus, CLK_NONE, pendok);
968 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok);
969 brcmf_sdio_wd_timer(bus, true);
971 bus->sleeping = sleep;
972 brcmf_dbg(SDIO, "new state %s\n",
973 (sleep ? "SLEEP" : "WAKE"));
975 brcmf_dbg(SDIO, "Exit: err=%d\n", err);
981 static inline bool brcmf_sdio_valid_shared_address(u32 addr)
983 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff));
986 static int brcmf_sdio_readshared(struct brcmf_sdio *bus,
987 struct sdpcm_shared *sh)
992 struct sdpcm_shared_le sh_le;
995 sdio_claim_host(bus->sdiodev->func[1]);
996 brcmf_sdio_bus_sleep(bus, false, false);
999 * Read last word in socram to determine
1000 * address of sdpcm_shared structure
1002 shaddr = bus->ci->rambase + bus->ci->ramsize - 4;
1003 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci))
1004 shaddr -= bus->ci->srsize;
1005 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr,
1011 * Check if addr is valid.
1012 * NVRAM length at the end of memory should have been overwritten.
1014 addr = le32_to_cpu(addr_le);
1015 if (!brcmf_sdio_valid_shared_address(addr)) {
1016 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr);
1021 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr);
1023 /* Read hndrte_shared structure */
1024 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le,
1025 sizeof(struct sdpcm_shared_le));
1029 sdio_release_host(bus->sdiodev->func[1]);
1032 sh->flags = le32_to_cpu(sh_le.flags);
1033 sh->trap_addr = le32_to_cpu(sh_le.trap_addr);
1034 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr);
1035 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr);
1036 sh->assert_line = le32_to_cpu(sh_le.assert_line);
1037 sh->console_addr = le32_to_cpu(sh_le.console_addr);
1038 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr);
1040 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) {
1041 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n",
1042 SDPCM_SHARED_VERSION,
1043 sh->flags & SDPCM_SHARED_VERSION_MASK);
1049 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n",
1051 sdio_release_host(bus->sdiodev->func[1]);
1055 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1057 struct sdpcm_shared sh;
1059 if (brcmf_sdio_readshared(bus, &sh) == 0)
1060 bus->console_addr = sh.console_addr;
1063 static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus)
1068 static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus)
1075 brcmf_dbg(SDIO, "Enter\n");
1077 /* Read mailbox data and ack that we did so */
1078 ret = r_sdreg32(bus, &hmb_data,
1079 offsetof(struct sdpcmd_regs, tohostmailboxdata));
1082 w_sdreg32(bus, SMB_INT_ACK,
1083 offsetof(struct sdpcmd_regs, tosbmailbox));
1084 bus->sdcnt.f1regdata += 2;
1086 /* Dongle recomposed rx frames, accept them again */
1087 if (hmb_data & HMB_DATA_NAKHANDLED) {
1088 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n",
1091 brcmf_err("unexpected NAKHANDLED!\n");
1093 bus->rxskip = false;
1094 intstatus |= I_HMB_FRAME_IND;
1098 * DEVREADY does not occur with gSPI.
1100 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
1102 (hmb_data & HMB_DATA_VERSION_MASK) >>
1103 HMB_DATA_VERSION_SHIFT;
1104 if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
1105 brcmf_err("Version mismatch, dongle reports %d, "
1107 bus->sdpcm_ver, SDPCM_PROT_VERSION);
1109 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n",
1113 * Retrieve console state address now that firmware should have
1116 brcmf_sdio_get_console_addr(bus);
1120 * Flow Control has been moved into the RX headers and this out of band
1121 * method isn't used any more.
1122 * remaining backward compatible with older dongles.
1124 if (hmb_data & HMB_DATA_FC) {
1125 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
1126 HMB_DATA_FCDATA_SHIFT;
1128 if (fcbits & ~bus->flowcontrol)
1129 bus->sdcnt.fc_xoff++;
1131 if (bus->flowcontrol & ~fcbits)
1132 bus->sdcnt.fc_xon++;
1134 bus->sdcnt.fc_rcvd++;
1135 bus->flowcontrol = fcbits;
1138 /* Shouldn't be any others */
1139 if (hmb_data & ~(HMB_DATA_DEVREADY |
1140 HMB_DATA_NAKHANDLED |
1143 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
1144 brcmf_err("Unknown mailbox data content: 0x%02x\n",
1150 static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx)
1157 brcmf_err("%sterminate frame%s\n",
1158 abort ? "abort command, " : "",
1159 rtx ? ", send NAK" : "");
1162 brcmf_sdiod_abort(bus->sdiodev, SDIO_FUNC_2);
1164 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL,
1166 bus->sdcnt.f1regdata++;
1168 /* Wait until the packet has been flushed (device/FIFO stable) */
1169 for (lastrbc = retries = 0xffff; retries > 0; retries--) {
1170 hi = brcmf_sdiod_regrb(bus->sdiodev,
1171 SBSDIO_FUNC1_RFRAMEBCHI, &err);
1172 lo = brcmf_sdiod_regrb(bus->sdiodev,
1173 SBSDIO_FUNC1_RFRAMEBCLO, &err);
1174 bus->sdcnt.f1regdata += 2;
1176 if ((hi == 0) && (lo == 0))
1179 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
1180 brcmf_err("count growing: last 0x%04x now 0x%04x\n",
1181 lastrbc, (hi << 8) + lo);
1183 lastrbc = (hi << 8) + lo;
1187 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc);
1189 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries);
1193 err = w_sdreg32(bus, SMB_NAK,
1194 offsetof(struct sdpcmd_regs, tosbmailbox));
1196 bus->sdcnt.f1regdata++;
1201 /* Clear partial in any case */
1202 bus->cur_read.len = 0;
1205 static void brcmf_sdio_txfail(struct brcmf_sdio *bus)
1207 struct brcmf_sdio_dev *sdiodev = bus->sdiodev;
1210 /* On failure, abort the command and terminate the frame */
1211 brcmf_err("sdio error, abort command and terminate frame\n");
1212 bus->sdcnt.tx_sderrs++;
1214 brcmf_sdiod_abort(sdiodev, SDIO_FUNC_2);
1215 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL);
1216 bus->sdcnt.f1regdata++;
1218 for (i = 0; i < 3; i++) {
1219 hi = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL);
1220 lo = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL);
1221 bus->sdcnt.f1regdata += 2;
1222 if ((hi == 0) && (lo == 0))
1227 /* return total length of buffer chain */
1228 static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus)
1234 skb_queue_walk(&bus->glom, p)
1239 static void brcmf_sdio_free_glom(struct brcmf_sdio *bus)
1241 struct sk_buff *cur, *next;
1243 skb_queue_walk_safe(&bus->glom, cur, next) {
1244 skb_unlink(cur, &bus->glom);
1245 brcmu_pkt_buf_free_skb(cur);
1250 * brcmfmac sdio bus specific header
1251 * This is the lowest layer header wrapped on the packets transmitted between
1252 * host and WiFi dongle which contains information needed for SDIO core and
1255 * It consists of 3 parts: hardware header, hardware extension header and
1257 * hardware header (frame tag) - 4 bytes
1258 * Byte 0~1: Frame length
1259 * Byte 2~3: Checksum, bit-wise inverse of frame length
1260 * hardware extension header - 8 bytes
1261 * Tx glom mode only, N/A for Rx or normal Tx
1262 * Byte 0~1: Packet length excluding hw frame tag
1264 * Byte 3: Frame flags, bit 0: last frame indication
1265 * Byte 4~5: Reserved
1266 * Byte 6~7: Tail padding length
1267 * software header - 8 bytes
1268 * Byte 0: Rx/Tx sequence number
1269 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag
1270 * Byte 2: Length of next data frame, reserved for Tx
1271 * Byte 3: Data offset
1272 * Byte 4: Flow control bits, reserved for Tx
1273 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet
1274 * Byte 6~7: Reserved
1276 #define SDPCM_HWHDR_LEN 4
1277 #define SDPCM_HWEXT_LEN 8
1278 #define SDPCM_SWHDR_LEN 8
1279 #define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN)
1280 /* software header */
1281 #define SDPCM_SEQ_MASK 0x000000ff
1282 #define SDPCM_SEQ_WRAP 256
1283 #define SDPCM_CHANNEL_MASK 0x00000f00
1284 #define SDPCM_CHANNEL_SHIFT 8
1285 #define SDPCM_CONTROL_CHANNEL 0 /* Control */
1286 #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */
1287 #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */
1288 #define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */
1289 #define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */
1290 #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
1291 #define SDPCM_NEXTLEN_MASK 0x00ff0000
1292 #define SDPCM_NEXTLEN_SHIFT 16
1293 #define SDPCM_DOFFSET_MASK 0xff000000
1294 #define SDPCM_DOFFSET_SHIFT 24
1295 #define SDPCM_FCMASK_MASK 0x000000ff
1296 #define SDPCM_WINDOW_MASK 0x0000ff00
1297 #define SDPCM_WINDOW_SHIFT 8
1299 static inline u8 brcmf_sdio_getdatoffset(u8 *swheader)
1302 hdrvalue = *(u32 *)swheader;
1303 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT);
1306 static inline bool brcmf_sdio_fromevntchan(u8 *swheader)
1311 hdrvalue = *(u32 *)swheader;
1312 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT);
1314 return (ret == SDPCM_EVENT_CHANNEL);
1317 static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header,
1318 struct brcmf_sdio_hdrinfo *rd,
1319 enum brcmf_sdio_frmtype type)
1322 u8 rx_seq, fc, tx_seq_max;
1325 trace_brcmf_sdpcm_hdr(SDPCM_RX, header);
1328 len = get_unaligned_le16(header);
1329 checksum = get_unaligned_le16(header + sizeof(u16));
1330 /* All zero means no more to read */
1331 if (!(len | checksum)) {
1332 bus->rxpending = false;
1335 if ((u16)(~(len ^ checksum))) {
1336 brcmf_err("HW header checksum error\n");
1337 bus->sdcnt.rx_badhdr++;
1338 brcmf_sdio_rxfail(bus, false, false);
1341 if (len < SDPCM_HDRLEN) {
1342 brcmf_err("HW header length error\n");
1345 if (type == BRCMF_SDIO_FT_SUPER &&
1346 (roundup(len, bus->blocksize) != rd->len)) {
1347 brcmf_err("HW superframe header length error\n");
1350 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) {
1351 brcmf_err("HW subframe header length error\n");
1356 /* software header */
1357 header += SDPCM_HWHDR_LEN;
1358 swheader = le32_to_cpu(*(__le32 *)header);
1359 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) {
1360 brcmf_err("Glom descriptor found in superframe head\n");
1364 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK);
1365 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT;
1366 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL &&
1367 type != BRCMF_SDIO_FT_SUPER) {
1368 brcmf_err("HW header length too long\n");
1369 bus->sdcnt.rx_toolong++;
1370 brcmf_sdio_rxfail(bus, false, false);
1374 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) {
1375 brcmf_err("Wrong channel for superframe\n");
1379 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL &&
1380 rd->channel != SDPCM_EVENT_CHANNEL) {
1381 brcmf_err("Wrong channel for subframe\n");
1385 rd->dat_offset = brcmf_sdio_getdatoffset(header);
1386 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) {
1387 brcmf_err("seq %d: bad data offset\n", rx_seq);
1388 bus->sdcnt.rx_badhdr++;
1389 brcmf_sdio_rxfail(bus, false, false);
1393 if (rd->seq_num != rx_seq) {
1394 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num);
1395 bus->sdcnt.rx_badseq++;
1396 rd->seq_num = rx_seq;
1398 /* no need to check the reset for subframe */
1399 if (type == BRCMF_SDIO_FT_SUB)
1401 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT;
1402 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) {
1403 /* only warm for NON glom packet */
1404 if (rd->channel != SDPCM_GLOM_CHANNEL)
1405 brcmf_err("seq %d: next length error\n", rx_seq);
1408 swheader = le32_to_cpu(*(__le32 *)(header + 4));
1409 fc = swheader & SDPCM_FCMASK_MASK;
1410 if (bus->flowcontrol != fc) {
1411 if (~bus->flowcontrol & fc)
1412 bus->sdcnt.fc_xoff++;
1413 if (bus->flowcontrol & ~fc)
1414 bus->sdcnt.fc_xon++;
1415 bus->sdcnt.fc_rcvd++;
1416 bus->flowcontrol = fc;
1418 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT;
1419 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) {
1420 brcmf_err("seq %d: max tx seq number error\n", rx_seq);
1421 tx_seq_max = bus->tx_seq + 2;
1423 bus->tx_max = tx_seq_max;
1428 static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length)
1430 *(__le16 *)header = cpu_to_le16(frm_length);
1431 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length);
1434 static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header,
1435 struct brcmf_sdio_hdrinfo *hd_info)
1440 brcmf_sdio_update_hwhdr(header, hd_info->len);
1441 hdr_offset = SDPCM_HWHDR_LEN;
1444 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24);
1445 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1446 hdrval = (u16)hd_info->tail_pad << 16;
1447 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval);
1448 hdr_offset += SDPCM_HWEXT_LEN;
1451 hdrval = hd_info->seq_num;
1452 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) &
1454 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) &
1456 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval);
1457 *(((__le32 *)(header + hdr_offset)) + 1) = 0;
1458 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header);
1461 static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq)
1466 struct sk_buff *pfirst, *pnext;
1471 struct brcmf_sdio_hdrinfo rd_new;
1473 /* If packets, issue read(s) and send up packet chain */
1474 /* Return sequence numbers consumed? */
1476 brcmf_dbg(SDIO, "start: glomd %p glom %p\n",
1477 bus->glomd, skb_peek(&bus->glom));
1479 /* If there's a descriptor, generate the packet chain */
1481 pfirst = pnext = NULL;
1482 dlen = (u16) (bus->glomd->len);
1483 dptr = bus->glomd->data;
1484 if (!dlen || (dlen & 1)) {
1485 brcmf_err("bad glomd len(%d), ignore descriptor\n",
1490 for (totlen = num = 0; dlen; num++) {
1491 /* Get (and move past) next length */
1492 sublen = get_unaligned_le16(dptr);
1493 dlen -= sizeof(u16);
1494 dptr += sizeof(u16);
1495 if ((sublen < SDPCM_HDRLEN) ||
1496 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
1497 brcmf_err("descriptor len %d bad: %d\n",
1502 if (sublen % bus->sgentry_align) {
1503 brcmf_err("sublen %d not multiple of %d\n",
1504 sublen, bus->sgentry_align);
1508 /* For last frame, adjust read len so total
1509 is a block multiple */
1512 (roundup(totlen, bus->blocksize) - totlen);
1513 totlen = roundup(totlen, bus->blocksize);
1516 /* Allocate/chain packet for next subframe */
1517 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align);
1518 if (pnext == NULL) {
1519 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n",
1523 skb_queue_tail(&bus->glom, pnext);
1525 /* Adhere to start alignment requirements */
1526 pkt_align(pnext, sublen, bus->sgentry_align);
1529 /* If all allocations succeeded, save packet chain
1532 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
1534 if (BRCMF_GLOM_ON() && bus->cur_read.len &&
1535 totlen != bus->cur_read.len) {
1536 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
1537 bus->cur_read.len, totlen, rxseq);
1539 pfirst = pnext = NULL;
1541 brcmf_sdio_free_glom(bus);
1545 /* Done with descriptor packet */
1546 brcmu_pkt_buf_free_skb(bus->glomd);
1548 bus->cur_read.len = 0;
1551 /* Ok -- either we just generated a packet chain,
1552 or had one from before */
1553 if (!skb_queue_empty(&bus->glom)) {
1554 if (BRCMF_GLOM_ON()) {
1555 brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
1556 skb_queue_walk(&bus->glom, pnext) {
1557 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
1558 pnext, (u8 *) (pnext->data),
1559 pnext->len, pnext->len);
1563 pfirst = skb_peek(&bus->glom);
1564 dlen = (u16) brcmf_sdio_glom_len(bus);
1566 /* Do an SDIO read for the superframe. Configurable iovar to
1567 * read directly into the chained packet, or allocate a large
1568 * packet and and copy into the chain.
1570 sdio_claim_host(bus->sdiodev->func[1]);
1571 errcode = brcmf_sdiod_recv_chain(bus->sdiodev,
1573 sdio_release_host(bus->sdiodev->func[1]);
1574 bus->sdcnt.f2rxdata++;
1576 /* On failure, kill the superframe */
1578 brcmf_err("glom read of %d bytes failed: %d\n",
1581 sdio_claim_host(bus->sdiodev->func[1]);
1582 brcmf_sdio_rxfail(bus, true, false);
1583 bus->sdcnt.rxglomfail++;
1584 brcmf_sdio_free_glom(bus);
1585 sdio_release_host(bus->sdiodev->func[1]);
1589 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1590 pfirst->data, min_t(int, pfirst->len, 48),
1593 rd_new.seq_num = rxseq;
1595 sdio_claim_host(bus->sdiodev->func[1]);
1596 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new,
1597 BRCMF_SDIO_FT_SUPER);
1598 sdio_release_host(bus->sdiodev->func[1]);
1599 bus->cur_read.len = rd_new.len_nxtfrm << 4;
1601 /* Remove superframe header, remember offset */
1602 skb_pull(pfirst, rd_new.dat_offset);
1603 sfdoff = rd_new.dat_offset;
1606 /* Validate all the subframe headers */
1607 skb_queue_walk(&bus->glom, pnext) {
1608 /* leave when invalid subframe is found */
1612 rd_new.len = pnext->len;
1613 rd_new.seq_num = rxseq++;
1614 sdio_claim_host(bus->sdiodev->func[1]);
1615 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new,
1617 sdio_release_host(bus->sdiodev->func[1]);
1618 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1619 pnext->data, 32, "subframe:\n");
1625 /* Terminate frame on error */
1626 sdio_claim_host(bus->sdiodev->func[1]);
1627 brcmf_sdio_rxfail(bus, true, false);
1628 bus->sdcnt.rxglomfail++;
1629 brcmf_sdio_free_glom(bus);
1630 sdio_release_host(bus->sdiodev->func[1]);
1631 bus->cur_read.len = 0;
1635 /* Basic SD framing looks ok - process each packet (header) */
1637 skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
1638 dptr = (u8 *) (pfirst->data);
1639 sublen = get_unaligned_le16(dptr);
1640 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]);
1642 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1644 "Rx Subframe Data:\n");
1646 __skb_trim(pfirst, sublen);
1647 skb_pull(pfirst, doff);
1649 if (pfirst->len == 0) {
1650 skb_unlink(pfirst, &bus->glom);
1651 brcmu_pkt_buf_free_skb(pfirst);
1655 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1657 min_t(int, pfirst->len, 32),
1658 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
1659 bus->glom.qlen, pfirst, pfirst->data,
1660 pfirst->len, pfirst->next,
1662 skb_unlink(pfirst, &bus->glom);
1663 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN]))
1664 brcmf_rx_event(bus->sdiodev->dev, pfirst);
1666 brcmf_rx_frame(bus->sdiodev->dev, pfirst,
1668 bus->sdcnt.rxglompkts++;
1671 bus->sdcnt.rxglomframes++;
1676 static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition,
1679 DECLARE_WAITQUEUE(wait, current);
1680 int timeout = DCMD_RESP_TIMEOUT;
1682 /* Wait until control frame is available */
1683 add_wait_queue(&bus->dcmd_resp_wait, &wait);
1684 set_current_state(TASK_INTERRUPTIBLE);
1686 while (!(*condition) && (!signal_pending(current) && timeout))
1687 timeout = schedule_timeout(timeout);
1689 if (signal_pending(current))
1692 set_current_state(TASK_RUNNING);
1693 remove_wait_queue(&bus->dcmd_resp_wait, &wait);
1698 static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus)
1700 wake_up_interruptible(&bus->dcmd_resp_wait);
1705 brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff)
1708 u8 *buf = NULL, *rbuf;
1711 brcmf_dbg(TRACE, "Enter\n");
1714 buf = vzalloc(bus->rxblen);
1719 pad = ((unsigned long)rbuf % bus->head_align);
1721 rbuf += (bus->head_align - pad);
1723 /* Copy the already-read portion over */
1724 memcpy(buf, hdr, BRCMF_FIRSTREAD);
1725 if (len <= BRCMF_FIRSTREAD)
1728 /* Raise rdlen to next SDIO block to avoid tail command */
1729 rdlen = len - BRCMF_FIRSTREAD;
1730 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
1731 pad = bus->blocksize - (rdlen % bus->blocksize);
1732 if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
1733 ((len + pad) < bus->sdiodev->bus_if->maxctl))
1735 } else if (rdlen % bus->head_align) {
1736 rdlen += bus->head_align - (rdlen % bus->head_align);
1739 /* Drop if the read is too big or it exceeds our maximum */
1740 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) {
1741 brcmf_err("%d-byte control read exceeds %d-byte buffer\n",
1742 rdlen, bus->sdiodev->bus_if->maxctl);
1743 brcmf_sdio_rxfail(bus, false, false);
1747 if ((len - doff) > bus->sdiodev->bus_if->maxctl) {
1748 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
1749 len, len - doff, bus->sdiodev->bus_if->maxctl);
1750 bus->sdcnt.rx_toolong++;
1751 brcmf_sdio_rxfail(bus, false, false);
1755 /* Read remain of frame body */
1756 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen);
1757 bus->sdcnt.f2rxdata++;
1759 /* Control frame failures need retransmission */
1761 brcmf_err("read %d control bytes failed: %d\n",
1763 bus->sdcnt.rxc_errors++;
1764 brcmf_sdio_rxfail(bus, true, true);
1767 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen);
1771 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
1772 buf, len, "RxCtrl:\n");
1774 /* Point to valid data and indicate its length */
1775 spin_lock_bh(&bus->rxctl_lock);
1777 brcmf_err("last control frame is being processed.\n");
1778 spin_unlock_bh(&bus->rxctl_lock);
1782 bus->rxctl = buf + doff;
1783 bus->rxctl_orig = buf;
1784 bus->rxlen = len - doff;
1785 spin_unlock_bh(&bus->rxctl_lock);
1788 /* Awake any waiters */
1789 brcmf_sdio_dcmd_resp_wake(bus);
1792 /* Pad read to blocksize for efficiency */
1793 static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen)
1795 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
1796 *pad = bus->blocksize - (*rdlen % bus->blocksize);
1797 if (*pad <= bus->roundup && *pad < bus->blocksize &&
1798 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
1800 } else if (*rdlen % bus->head_align) {
1801 *rdlen += bus->head_align - (*rdlen % bus->head_align);
1805 static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes)
1807 struct sk_buff *pkt; /* Packet for event or data frames */
1808 u16 pad; /* Number of pad bytes to read */
1809 uint rxleft = 0; /* Remaining number of frames allowed */
1810 int ret; /* Return code from calls */
1811 uint rxcount = 0; /* Total frames read */
1812 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new;
1815 brcmf_dbg(TRACE, "Enter\n");
1817 /* Not finished unless we encounter no more frames indication */
1818 bus->rxpending = true;
1820 for (rd->seq_num = bus->rx_seq, rxleft = maxframes;
1821 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA;
1822 rd->seq_num++, rxleft--) {
1824 /* Handle glomming separately */
1825 if (bus->glomd || !skb_queue_empty(&bus->glom)) {
1827 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
1828 bus->glomd, skb_peek(&bus->glom));
1829 cnt = brcmf_sdio_rxglom(bus, rd->seq_num);
1830 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
1831 rd->seq_num += cnt - 1;
1832 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
1836 rd->len_left = rd->len;
1837 /* read header first for unknow frame length */
1838 sdio_claim_host(bus->sdiodev->func[1]);
1840 ret = brcmf_sdiod_recv_buf(bus->sdiodev,
1841 bus->rxhdr, BRCMF_FIRSTREAD);
1842 bus->sdcnt.f2rxhdrs++;
1844 brcmf_err("RXHEADER FAILED: %d\n",
1846 bus->sdcnt.rx_hdrfail++;
1847 brcmf_sdio_rxfail(bus, true, true);
1848 sdio_release_host(bus->sdiodev->func[1]);
1852 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(),
1853 bus->rxhdr, SDPCM_HDRLEN,
1856 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd,
1857 BRCMF_SDIO_FT_NORMAL)) {
1858 sdio_release_host(bus->sdiodev->func[1]);
1859 if (!bus->rxpending)
1865 if (rd->channel == SDPCM_CONTROL_CHANNEL) {
1866 brcmf_sdio_read_control(bus, bus->rxhdr,
1869 /* prepare the descriptor for the next read */
1870 rd->len = rd->len_nxtfrm << 4;
1872 /* treat all packet as event if we don't know */
1873 rd->channel = SDPCM_EVENT_CHANNEL;
1874 sdio_release_host(bus->sdiodev->func[1]);
1877 rd->len_left = rd->len > BRCMF_FIRSTREAD ?
1878 rd->len - BRCMF_FIRSTREAD : 0;
1879 head_read = BRCMF_FIRSTREAD;
1882 brcmf_sdio_pad(bus, &pad, &rd->len_left);
1884 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read +
1887 /* Give up on data, request rtx of events */
1888 brcmf_err("brcmu_pkt_buf_get_skb failed\n");
1889 brcmf_sdio_rxfail(bus, false,
1890 RETRYCHAN(rd->channel));
1891 sdio_release_host(bus->sdiodev->func[1]);
1894 skb_pull(pkt, head_read);
1895 pkt_align(pkt, rd->len_left, bus->head_align);
1897 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt);
1898 bus->sdcnt.f2rxdata++;
1899 sdio_release_host(bus->sdiodev->func[1]);
1902 brcmf_err("read %d bytes from channel %d failed: %d\n",
1903 rd->len, rd->channel, ret);
1904 brcmu_pkt_buf_free_skb(pkt);
1905 sdio_claim_host(bus->sdiodev->func[1]);
1906 brcmf_sdio_rxfail(bus, true,
1907 RETRYCHAN(rd->channel));
1908 sdio_release_host(bus->sdiodev->func[1]);
1913 skb_push(pkt, head_read);
1914 memcpy(pkt->data, bus->rxhdr, head_read);
1917 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN);
1918 rd_new.seq_num = rd->seq_num;
1919 sdio_claim_host(bus->sdiodev->func[1]);
1920 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new,
1921 BRCMF_SDIO_FT_NORMAL)) {
1923 brcmu_pkt_buf_free_skb(pkt);
1926 bus->sdcnt.rx_readahead_cnt++;
1927 if (rd->len != roundup(rd_new.len, 16)) {
1928 brcmf_err("frame length mismatch:read %d, should be %d\n",
1930 roundup(rd_new.len, 16) >> 4);
1932 brcmf_sdio_rxfail(bus, true, true);
1933 sdio_release_host(bus->sdiodev->func[1]);
1934 brcmu_pkt_buf_free_skb(pkt);
1937 sdio_release_host(bus->sdiodev->func[1]);
1938 rd->len_nxtfrm = rd_new.len_nxtfrm;
1939 rd->channel = rd_new.channel;
1940 rd->dat_offset = rd_new.dat_offset;
1942 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() &&
1945 bus->rxhdr, SDPCM_HDRLEN,
1948 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) {
1949 brcmf_err("readahead on control packet %d?\n",
1951 /* Force retry w/normal header read */
1953 sdio_claim_host(bus->sdiodev->func[1]);
1954 brcmf_sdio_rxfail(bus, false, true);
1955 sdio_release_host(bus->sdiodev->func[1]);
1956 brcmu_pkt_buf_free_skb(pkt);
1961 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(),
1962 pkt->data, rd->len, "Rx Data:\n");
1964 /* Save superframe descriptor and allocate packet frame */
1965 if (rd->channel == SDPCM_GLOM_CHANNEL) {
1966 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) {
1967 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
1969 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(),
1972 __skb_trim(pkt, rd->len);
1973 skb_pull(pkt, SDPCM_HDRLEN);
1976 brcmf_err("%s: glom superframe w/o "
1977 "descriptor!\n", __func__);
1978 sdio_claim_host(bus->sdiodev->func[1]);
1979 brcmf_sdio_rxfail(bus, false, false);
1980 sdio_release_host(bus->sdiodev->func[1]);
1982 /* prepare the descriptor for the next read */
1983 rd->len = rd->len_nxtfrm << 4;
1985 /* treat all packet as event if we don't know */
1986 rd->channel = SDPCM_EVENT_CHANNEL;
1990 /* Fill in packet len and prio, deliver upward */
1991 __skb_trim(pkt, rd->len);
1992 skb_pull(pkt, rd->dat_offset);
1995 brcmu_pkt_buf_free_skb(pkt);
1996 else if (rd->channel == SDPCM_EVENT_CHANNEL)
1997 brcmf_rx_event(bus->sdiodev->dev, pkt);
1999 brcmf_rx_frame(bus->sdiodev->dev, pkt,
2002 /* prepare the descriptor for the next read */
2003 rd->len = rd->len_nxtfrm << 4;
2005 /* treat all packet as event if we don't know */
2006 rd->channel = SDPCM_EVENT_CHANNEL;
2009 rxcount = maxframes - rxleft;
2010 /* Message if we hit the limit */
2012 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes);
2014 brcmf_dbg(DATA, "processed %d frames\n", rxcount);
2015 /* Back off rxseq if awaiting rtx, update rx_seq */
2018 bus->rx_seq = rd->seq_num;
2024 brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus)
2026 wake_up_interruptible(&bus->ctrl_wait);
2030 static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt)
2035 dat_buf = (u8 *)(pkt->data);
2037 /* Check head padding */
2038 head_pad = ((unsigned long)dat_buf % bus->head_align);
2040 if (skb_headroom(pkt) < head_pad) {
2041 bus->sdiodev->bus_if->tx_realloc++;
2043 if (skb_cow(pkt, head_pad))
2046 skb_push(pkt, head_pad);
2047 dat_buf = (u8 *)(pkt->data);
2048 memset(dat_buf, 0, head_pad + bus->tx_hdrlen);
2054 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for
2057 /* flag marking a dummy skb added for DMA alignment requirement */
2058 #define ALIGN_SKB_FLAG 0x8000
2059 /* bit mask of data length chopped from the previous packet */
2060 #define ALIGN_SKB_CHOP_LEN_MASK 0x7fff
2062 static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus,
2063 struct sk_buff_head *pktq,
2064 struct sk_buff *pkt, u16 total_len)
2066 struct brcmf_sdio_dev *sdiodev;
2067 struct sk_buff *pkt_pad;
2068 u16 tail_pad, tail_chop, chain_pad;
2069 unsigned int blksize;
2073 sdiodev = bus->sdiodev;
2074 blksize = sdiodev->func[SDIO_FUNC_2]->cur_blksize;
2075 /* sg entry alignment should be a divisor of block size */
2076 WARN_ON(blksize % bus->sgentry_align);
2078 /* Check tail padding */
2079 lastfrm = skb_queue_is_last(pktq, pkt);
2081 tail_chop = pkt->len % bus->sgentry_align;
2083 tail_pad = bus->sgentry_align - tail_chop;
2084 chain_pad = (total_len + tail_pad) % blksize;
2085 if (lastfrm && chain_pad)
2086 tail_pad += blksize - chain_pad;
2087 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) {
2088 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop +
2090 if (pkt_pad == NULL)
2092 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad);
2093 if (unlikely(ret < 0)) {
2097 memcpy(pkt_pad->data,
2098 pkt->data + pkt->len - tail_chop,
2100 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop;
2101 skb_trim(pkt, pkt->len - tail_chop);
2102 skb_trim(pkt_pad, tail_pad + tail_chop);
2103 __skb_queue_after(pktq, pkt, pkt_pad);
2105 ntail = pkt->data_len + tail_pad -
2106 (pkt->end - pkt->tail);
2107 if (skb_cloned(pkt) || ntail > 0)
2108 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC))
2110 if (skb_linearize(pkt))
2112 __skb_put(pkt, tail_pad);
2119 * brcmf_sdio_txpkt_prep - packet preparation for transmit
2120 * @bus: brcmf_sdio structure pointer
2121 * @pktq: packet list pointer
2122 * @chan: virtual channel to transmit the packet
2124 * Processes to be applied to the packet
2125 * - Align data buffer pointer
2126 * - Align data buffer length
2128 * Return: negative value if there is error
2131 brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2134 u16 head_pad, total_len;
2135 struct sk_buff *pkt_next;
2138 struct brcmf_sdio_hdrinfo hd_info = {0};
2140 txseq = bus->tx_seq;
2142 skb_queue_walk(pktq, pkt_next) {
2143 /* alignment packet inserted in previous
2144 * loop cycle can be skipped as it is
2145 * already properly aligned and does not
2146 * need an sdpcm header.
2148 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG)
2151 /* align packet data pointer */
2152 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next);
2155 head_pad = (u16)ret;
2157 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad);
2159 total_len += pkt_next->len;
2161 hd_info.len = pkt_next->len;
2162 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next);
2163 if (bus->txglom && pktq->qlen > 1) {
2164 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq,
2165 pkt_next, total_len);
2168 hd_info.tail_pad = (u16)ret;
2169 total_len += (u16)ret;
2172 hd_info.channel = chan;
2173 hd_info.dat_offset = head_pad + bus->tx_hdrlen;
2174 hd_info.seq_num = txseq++;
2176 /* Now fill the header */
2177 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info);
2179 if (BRCMF_BYTES_ON() &&
2180 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) ||
2181 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL)))
2182 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len,
2184 else if (BRCMF_HDRS_ON())
2185 brcmf_dbg_hex_dump(true, pkt_next->data,
2186 head_pad + bus->tx_hdrlen,
2189 /* Hardware length tag of the first packet should be total
2190 * length of the chain (including padding)
2193 brcmf_sdio_update_hwhdr(pktq->next->data, total_len);
2198 * brcmf_sdio_txpkt_postp - packet post processing for transmit
2199 * @bus: brcmf_sdio structure pointer
2200 * @pktq: packet list pointer
2202 * Processes to be applied to the packet
2203 * - Remove head padding
2204 * - Remove tail padding
2207 brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq)
2212 u16 dummy_flags, chop_len;
2213 struct sk_buff *pkt_next, *tmp, *pkt_prev;
2215 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2216 dummy_flags = *(u16 *)(pkt_next->cb);
2217 if (dummy_flags & ALIGN_SKB_FLAG) {
2218 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK;
2220 pkt_prev = pkt_next->prev;
2221 skb_put(pkt_prev, chop_len);
2223 __skb_unlink(pkt_next, pktq);
2224 brcmu_pkt_buf_free_skb(pkt_next);
2226 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN;
2227 dat_offset = le32_to_cpu(*(__le32 *)hdr);
2228 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >>
2229 SDPCM_DOFFSET_SHIFT;
2230 skb_pull(pkt_next, dat_offset);
2232 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2));
2233 skb_trim(pkt_next, pkt_next->len - tail_pad);
2239 /* Writes a HW/SW header into the packet and sends it. */
2240 /* Assumes: (a) header space already there, (b) caller holds lock */
2241 static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq,
2245 struct sk_buff *pkt_next, *tmp;
2247 brcmf_dbg(TRACE, "Enter\n");
2249 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan);
2253 sdio_claim_host(bus->sdiodev->func[1]);
2254 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq);
2255 bus->sdcnt.f2txdata++;
2258 brcmf_sdio_txfail(bus);
2260 sdio_release_host(bus->sdiodev->func[1]);
2263 brcmf_sdio_txpkt_postp(bus, pktq);
2265 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP;
2266 skb_queue_walk_safe(pktq, pkt_next, tmp) {
2267 __skb_unlink(pkt_next, pktq);
2268 brcmf_txcomplete(bus->sdiodev->dev, pkt_next, ret == 0);
2273 static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes)
2275 struct sk_buff *pkt;
2276 struct sk_buff_head pktq;
2278 int ret = 0, prec_out, i;
2280 u8 tx_prec_map, pkt_num;
2282 brcmf_dbg(TRACE, "Enter\n");
2284 tx_prec_map = ~bus->flowcontrol;
2286 /* Send frames until the limit or some other event */
2287 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) {
2290 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq,
2291 bus->sdiodev->txglomsz);
2292 pkt_num = min_t(u32, pkt_num,
2293 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol));
2294 __skb_queue_head_init(&pktq);
2295 spin_lock_bh(&bus->txq_lock);
2296 for (i = 0; i < pkt_num; i++) {
2297 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map,
2301 __skb_queue_tail(&pktq, pkt);
2303 spin_unlock_bh(&bus->txq_lock);
2307 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL);
2311 /* In poll mode, need to check for other events */
2313 /* Check device status, signal pending interrupt */
2314 sdio_claim_host(bus->sdiodev->func[1]);
2315 ret = r_sdreg32(bus, &intstatus,
2316 offsetof(struct sdpcmd_regs,
2318 sdio_release_host(bus->sdiodev->func[1]);
2319 bus->sdcnt.f2txdata++;
2322 if (intstatus & bus->hostintmask)
2323 atomic_set(&bus->ipend, 1);
2327 /* Deflow-control stack if needed */
2328 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) &&
2329 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) {
2331 brcmf_txflowblock(bus->sdiodev->dev, false);
2337 static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len)
2342 struct brcmf_sdio_hdrinfo hd_info = {0};
2345 brcmf_dbg(TRACE, "Enter\n");
2347 /* Back the pointer to make room for bus header */
2348 frame -= bus->tx_hdrlen;
2349 len += bus->tx_hdrlen;
2351 /* Add alignment padding (optional for ctl frames) */
2352 doff = ((unsigned long)frame % bus->head_align);
2356 memset(frame + bus->tx_hdrlen, 0, doff);
2359 /* Round send length to next SDIO block */
2361 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
2362 pad = bus->blocksize - (len % bus->blocksize);
2363 if ((pad > bus->roundup) || (pad >= bus->blocksize))
2365 } else if (len % bus->head_align) {
2366 pad = bus->head_align - (len % bus->head_align);
2370 hd_info.len = len - pad;
2371 hd_info.channel = SDPCM_CONTROL_CHANNEL;
2372 hd_info.dat_offset = doff + bus->tx_hdrlen;
2373 hd_info.seq_num = bus->tx_seq;
2374 hd_info.lastfrm = true;
2375 hd_info.tail_pad = pad;
2376 brcmf_sdio_hdpack(bus, frame, &hd_info);
2379 brcmf_sdio_update_hwhdr(frame, len);
2381 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(),
2382 frame, len, "Tx Frame:\n");
2383 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) &&
2385 frame, min_t(u16, len, 16), "TxHdr:\n");
2388 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len);
2391 brcmf_sdio_txfail(bus);
2393 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP;
2394 } while (ret < 0 && retries++ < TXRETRIES);
2399 static void brcmf_sdio_bus_stop(struct device *dev)
2401 u32 local_hostintmask;
2404 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2405 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2406 struct brcmf_sdio *bus = sdiodev->bus;
2408 brcmf_dbg(TRACE, "Enter\n");
2410 if (bus->watchdog_tsk) {
2411 send_sig(SIGTERM, bus->watchdog_tsk, 1);
2412 kthread_stop(bus->watchdog_tsk);
2413 bus->watchdog_tsk = NULL;
2416 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
2417 sdio_claim_host(sdiodev->func[1]);
2419 /* Enable clock for device interrupts */
2420 brcmf_sdio_bus_sleep(bus, false, false);
2422 /* Disable and clear interrupts at the chip level also */
2423 w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask));
2424 local_hostintmask = bus->hostintmask;
2425 bus->hostintmask = 0;
2427 /* Force backplane clocks to assure F2 interrupt propagates */
2428 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2431 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
2432 (saveclk | SBSDIO_FORCE_HT), &err);
2434 brcmf_err("Failed to force clock for F2: err %d\n",
2437 /* Turn off the bus (F2), free any pending packets */
2438 brcmf_dbg(INTR, "disable SDIO interrupts\n");
2439 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
2441 /* Clear any pending interrupts now that F2 is disabled */
2442 w_sdreg32(bus, local_hostintmask,
2443 offsetof(struct sdpcmd_regs, intstatus));
2445 sdio_release_host(sdiodev->func[1]);
2447 /* Clear the data packet queues */
2448 brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
2450 /* Clear any held glomming stuff */
2451 brcmu_pkt_buf_free_skb(bus->glomd);
2452 brcmf_sdio_free_glom(bus);
2454 /* Clear rx control and wake any waiters */
2455 spin_lock_bh(&bus->rxctl_lock);
2457 spin_unlock_bh(&bus->rxctl_lock);
2458 brcmf_sdio_dcmd_resp_wake(bus);
2460 /* Reset some F2 state stuff */
2461 bus->rxskip = false;
2462 bus->tx_seq = bus->rx_seq = 0;
2465 static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus)
2467 struct brcmf_sdio_dev *sdiodev;
2468 unsigned long flags;
2470 sdiodev = bus->sdiodev;
2471 if (sdiodev->oob_irq_requested) {
2472 spin_lock_irqsave(&sdiodev->irq_en_lock, flags);
2473 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) {
2474 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr);
2475 sdiodev->irq_en = true;
2477 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags);
2481 static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus)
2483 struct brcmf_core *buscore;
2488 buscore = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV);
2489 addr = buscore->base + offsetof(struct sdpcmd_regs, intstatus);
2491 val = brcmf_sdiod_regrl(bus->sdiodev, addr, &ret);
2492 bus->sdcnt.f1regdata++;
2496 val &= bus->hostintmask;
2497 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE));
2499 /* Clear interrupts */
2501 brcmf_sdiod_regwl(bus->sdiodev, addr, val, &ret);
2502 bus->sdcnt.f1regdata++;
2503 atomic_or(val, &bus->intstatus);
2509 static void brcmf_sdio_dpc(struct brcmf_sdio *bus)
2512 unsigned long intstatus;
2513 uint txlimit = bus->txbound; /* Tx frames to send before resched */
2514 uint framecnt; /* Temporary counter of tx/rx frames */
2517 brcmf_dbg(TRACE, "Enter\n");
2519 sdio_claim_host(bus->sdiodev->func[1]);
2521 /* If waiting for HTAVAIL, check status */
2522 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) {
2523 u8 clkctl, devctl = 0;
2526 /* Check for inconsistent device control */
2527 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2528 SBSDIO_DEVICE_CTL, &err);
2531 /* Read CSR, if clock on switch to AVAIL, else ignore */
2532 clkctl = brcmf_sdiod_regrb(bus->sdiodev,
2533 SBSDIO_FUNC1_CHIPCLKCSR, &err);
2535 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
2538 if (SBSDIO_HTAV(clkctl)) {
2539 devctl = brcmf_sdiod_regrb(bus->sdiodev,
2540 SBSDIO_DEVICE_CTL, &err);
2541 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
2542 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_DEVICE_CTL,
2544 bus->clkstate = CLK_AVAIL;
2548 /* Make sure backplane clock is on */
2549 brcmf_sdio_bus_sleep(bus, false, true);
2551 /* Pending interrupt indicates new device status */
2552 if (atomic_read(&bus->ipend) > 0) {
2553 atomic_set(&bus->ipend, 0);
2554 err = brcmf_sdio_intr_rstatus(bus);
2557 /* Start with leftover status bits */
2558 intstatus = atomic_xchg(&bus->intstatus, 0);
2560 /* Handle flow-control change: read new state in case our ack
2561 * crossed another change interrupt. If change still set, assume
2562 * FC ON for safety, let next loop through do the debounce.
2564 if (intstatus & I_HMB_FC_CHANGE) {
2565 intstatus &= ~I_HMB_FC_CHANGE;
2566 err = w_sdreg32(bus, I_HMB_FC_CHANGE,
2567 offsetof(struct sdpcmd_regs, intstatus));
2569 err = r_sdreg32(bus, &newstatus,
2570 offsetof(struct sdpcmd_regs, intstatus));
2571 bus->sdcnt.f1regdata += 2;
2572 atomic_set(&bus->fcstate,
2573 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE)));
2574 intstatus |= (newstatus & bus->hostintmask);
2577 /* Handle host mailbox indication */
2578 if (intstatus & I_HMB_HOST_INT) {
2579 intstatus &= ~I_HMB_HOST_INT;
2580 intstatus |= brcmf_sdio_hostmail(bus);
2583 sdio_release_host(bus->sdiodev->func[1]);
2585 /* Generally don't ask for these, can get CRC errors... */
2586 if (intstatus & I_WR_OOSYNC) {
2587 brcmf_err("Dongle reports WR_OOSYNC\n");
2588 intstatus &= ~I_WR_OOSYNC;
2591 if (intstatus & I_RD_OOSYNC) {
2592 brcmf_err("Dongle reports RD_OOSYNC\n");
2593 intstatus &= ~I_RD_OOSYNC;
2596 if (intstatus & I_SBINT) {
2597 brcmf_err("Dongle reports SBINT\n");
2598 intstatus &= ~I_SBINT;
2601 /* Would be active due to wake-wlan in gSPI */
2602 if (intstatus & I_CHIPACTIVE) {
2603 brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
2604 intstatus &= ~I_CHIPACTIVE;
2607 /* Ignore frame indications if rxskip is set */
2609 intstatus &= ~I_HMB_FRAME_IND;
2611 /* On frame indication, read available frames */
2612 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) {
2613 brcmf_sdio_readframes(bus, bus->rxbound);
2614 if (!bus->rxpending)
2615 intstatus &= ~I_HMB_FRAME_IND;
2618 /* Keep still-pending events for next scheduling */
2620 atomic_or(intstatus, &bus->intstatus);
2622 brcmf_sdio_clrintr(bus);
2624 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) &&
2626 sdio_claim_host(bus->sdiodev->func[1]);
2627 if (bus->ctrl_frame_stat) {
2628 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf,
2629 bus->ctrl_frame_len);
2630 bus->ctrl_frame_err = err;
2632 bus->ctrl_frame_stat = false;
2634 sdio_release_host(bus->sdiodev->func[1]);
2635 brcmf_sdio_wait_event_wakeup(bus);
2637 /* Send queued frames (limit 1 if rx may still be pending) */
2638 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) &&
2639 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit &&
2641 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) :
2643 brcmf_sdio_sendfromq(bus, framecnt);
2646 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) {
2647 brcmf_err("failed backplane access over SDIO, halting operation\n");
2648 atomic_set(&bus->intstatus, 0);
2649 if (bus->ctrl_frame_stat) {
2650 sdio_claim_host(bus->sdiodev->func[1]);
2651 if (bus->ctrl_frame_stat) {
2652 bus->ctrl_frame_err = -ENODEV;
2654 bus->ctrl_frame_stat = false;
2655 brcmf_sdio_wait_event_wakeup(bus);
2657 sdio_release_host(bus->sdiodev->func[1]);
2659 } else if (atomic_read(&bus->intstatus) ||
2660 atomic_read(&bus->ipend) > 0 ||
2661 (!atomic_read(&bus->fcstate) &&
2662 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
2664 bus->dpc_triggered = true;
2668 static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev)
2670 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2671 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2672 struct brcmf_sdio *bus = sdiodev->bus;
2677 static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec)
2680 int eprec = -1; /* precedence to evict from */
2682 /* Fast case, precedence queue is not full and we are also not
2683 * exceeding total queue length
2685 if (!pktq_pfull(q, prec) && !pktq_full(q)) {
2686 brcmu_pktq_penq(q, prec, pkt);
2690 /* Determine precedence from which to evict packet, if any */
2691 if (pktq_pfull(q, prec)) {
2693 } else if (pktq_full(q)) {
2694 p = brcmu_pktq_peek_tail(q, &eprec);
2699 /* Evict if needed */
2701 /* Detect queueing to unconfigured precedence */
2703 return false; /* refuse newer (incoming) packet */
2704 /* Evict packet according to discard policy */
2705 p = brcmu_pktq_pdeq_tail(q, eprec);
2707 brcmf_err("brcmu_pktq_pdeq_tail() failed\n");
2708 brcmu_pkt_buf_free_skb(p);
2712 p = brcmu_pktq_penq(q, prec, pkt);
2714 brcmf_err("brcmu_pktq_penq() failed\n");
2719 static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt)
2723 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2724 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2725 struct brcmf_sdio *bus = sdiodev->bus;
2727 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len);
2728 if (sdiodev->state != BRCMF_SDIOD_DATA)
2731 /* Add space for the header */
2732 skb_push(pkt, bus->tx_hdrlen);
2733 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
2735 prec = prio2prec((pkt->priority & PRIOMASK));
2737 /* Check for existing queue, current flow-control,
2738 pending event, or pending clock */
2739 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
2740 bus->sdcnt.fcqueued++;
2742 /* Priority based enq */
2743 spin_lock_bh(&bus->txq_lock);
2744 /* reset bus_flags in packet cb */
2745 *(u16 *)(pkt->cb) = 0;
2746 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) {
2747 skb_pull(pkt, bus->tx_hdrlen);
2748 brcmf_err("out of bus->txq !!!\n");
2754 if (pktq_len(&bus->txq) >= TXHI) {
2756 brcmf_txflowblock(dev, true);
2758 spin_unlock_bh(&bus->txq_lock);
2761 if (pktq_plen(&bus->txq, prec) > qcount[prec])
2762 qcount[prec] = pktq_plen(&bus->txq, prec);
2765 brcmf_sdio_trigger_dpc(bus);
2770 #define CONSOLE_LINE_MAX 192
2772 static int brcmf_sdio_readconsole(struct brcmf_sdio *bus)
2774 struct brcmf_console *c = &bus->console;
2775 u8 line[CONSOLE_LINE_MAX], ch;
2779 /* Don't do anything until FWREADY updates console address */
2780 if (bus->console_addr == 0)
2783 /* Read console log struct */
2784 addr = bus->console_addr + offsetof(struct rte_console, log_le);
2785 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le,
2790 /* Allocate console buffer (one time only) */
2791 if (c->buf == NULL) {
2792 c->bufsize = le32_to_cpu(c->log_le.buf_size);
2793 c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
2798 idx = le32_to_cpu(c->log_le.idx);
2800 /* Protect against corrupt value */
2801 if (idx > c->bufsize)
2804 /* Skip reading the console buffer if the index pointer
2809 /* Read the console buffer */
2810 addr = le32_to_cpu(c->log_le.buf);
2811 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize);
2815 while (c->last != idx) {
2816 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
2817 if (c->last == idx) {
2818 /* This would output a partial line.
2820 * the buffer pointer and output this
2821 * line next time around.
2826 c->last = c->bufsize - n;
2829 ch = c->buf[c->last];
2830 c->last = (c->last + 1) % c->bufsize;
2837 if (line[n - 1] == '\r')
2840 pr_debug("CONSOLE: %s\n", line);
2850 brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen)
2852 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2853 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
2854 struct brcmf_sdio *bus = sdiodev->bus;
2857 brcmf_dbg(TRACE, "Enter\n");
2858 if (sdiodev->state != BRCMF_SDIOD_DATA)
2862 bus->ctrl_frame_buf = msg;
2863 bus->ctrl_frame_len = msglen;
2865 bus->ctrl_frame_stat = true;
2867 brcmf_sdio_trigger_dpc(bus);
2868 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat,
2871 if (bus->ctrl_frame_stat) {
2872 sdio_claim_host(bus->sdiodev->func[1]);
2873 if (bus->ctrl_frame_stat) {
2874 brcmf_dbg(SDIO, "ctrl_frame timeout\n");
2875 bus->ctrl_frame_stat = false;
2878 sdio_release_host(bus->sdiodev->func[1]);
2881 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n",
2882 bus->ctrl_frame_err);
2884 ret = bus->ctrl_frame_err;
2888 bus->sdcnt.tx_ctlerrs++;
2890 bus->sdcnt.tx_ctlpkts++;
2896 static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus,
2897 struct sdpcm_shared *sh)
2899 u32 addr, console_ptr, console_size, console_index;
2900 char *conbuf = NULL;
2904 /* obtain console information from device memory */
2905 addr = sh->console_addr + offsetof(struct rte_console, log_le);
2906 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2907 (u8 *)&sh_val, sizeof(u32));
2910 console_ptr = le32_to_cpu(sh_val);
2912 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size);
2913 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2914 (u8 *)&sh_val, sizeof(u32));
2917 console_size = le32_to_cpu(sh_val);
2919 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx);
2920 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr,
2921 (u8 *)&sh_val, sizeof(u32));
2924 console_index = le32_to_cpu(sh_val);
2926 /* allocate buffer for console data */
2927 if (console_size <= CONSOLE_BUFFER_MAX)
2928 conbuf = vzalloc(console_size+1);
2933 /* obtain the console data from device */
2934 conbuf[console_size] = '\0';
2935 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf,
2940 rv = seq_write(seq, conbuf + console_index,
2941 console_size - console_index);
2945 if (console_index > 0)
2946 rv = seq_write(seq, conbuf, console_index - 1);
2953 static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus,
2954 struct sdpcm_shared *sh)
2957 struct brcmf_trap_info tr;
2959 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) {
2960 brcmf_dbg(INFO, "no trap in firmware\n");
2964 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr,
2965 sizeof(struct brcmf_trap_info));
2970 "dongle trap info: type 0x%x @ epc 0x%08x\n"
2971 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n"
2972 " lr 0x%08x pc 0x%08x offset 0x%x\n"
2973 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n"
2974 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n",
2975 le32_to_cpu(tr.type), le32_to_cpu(tr.epc),
2976 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr),
2977 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14),
2978 le32_to_cpu(tr.pc), sh->trap_addr,
2979 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1),
2980 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3),
2981 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5),
2982 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7));
2987 static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus,
2988 struct sdpcm_shared *sh)
2991 char file[80] = "?";
2992 char expr[80] = "<???>";
2994 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) {
2995 brcmf_dbg(INFO, "firmware not built with -assert\n");
2997 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) {
2998 brcmf_dbg(INFO, "no assert in dongle\n");
3002 sdio_claim_host(bus->sdiodev->func[1]);
3003 if (sh->assert_file_addr != 0) {
3004 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3005 sh->assert_file_addr, (u8 *)file, 80);
3009 if (sh->assert_exp_addr != 0) {
3010 error = brcmf_sdiod_ramrw(bus->sdiodev, false,
3011 sh->assert_exp_addr, (u8 *)expr, 80);
3015 sdio_release_host(bus->sdiodev->func[1]);
3017 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n",
3018 file, sh->assert_line, expr);
3022 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3025 struct sdpcm_shared sh;
3027 error = brcmf_sdio_readshared(bus, &sh);
3032 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0)
3033 brcmf_dbg(INFO, "firmware not built with -assert\n");
3034 else if (sh.flags & SDPCM_SHARED_ASSERT)
3035 brcmf_err("assertion in dongle\n");
3037 if (sh.flags & SDPCM_SHARED_TRAP)
3038 brcmf_err("firmware trap in dongle\n");
3043 static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus)
3046 struct sdpcm_shared sh;
3048 error = brcmf_sdio_readshared(bus, &sh);
3052 error = brcmf_sdio_assert_info(seq, bus, &sh);
3056 error = brcmf_sdio_trap_info(seq, bus, &sh);
3060 error = brcmf_sdio_dump_console(seq, bus, &sh);
3066 static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data)
3068 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3069 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus;
3071 return brcmf_sdio_died_dump(seq, bus);
3074 static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data)
3076 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private);
3077 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3078 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt;
3081 "intrcount: %u\nlastintrs: %u\n"
3082 "pollcnt: %u\nregfails: %u\n"
3083 "tx_sderrs: %u\nfcqueued: %u\n"
3084 "rxrtx: %u\nrx_toolong: %u\n"
3085 "rxc_errors: %u\nrx_hdrfail: %u\n"
3086 "rx_badhdr: %u\nrx_badseq: %u\n"
3087 "fc_rcvd: %u\nfc_xoff: %u\n"
3088 "fc_xon: %u\nrxglomfail: %u\n"
3089 "rxglomframes: %u\nrxglompkts: %u\n"
3090 "f2rxhdrs: %u\nf2rxdata: %u\n"
3091 "f2txdata: %u\nf1regdata: %u\n"
3092 "tickcnt: %u\ntx_ctlerrs: %lu\n"
3093 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n"
3094 "rx_ctlpkts: %lu\nrx_readahead: %lu\n",
3095 sdcnt->intrcount, sdcnt->lastintrs,
3096 sdcnt->pollcnt, sdcnt->regfails,
3097 sdcnt->tx_sderrs, sdcnt->fcqueued,
3098 sdcnt->rxrtx, sdcnt->rx_toolong,
3099 sdcnt->rxc_errors, sdcnt->rx_hdrfail,
3100 sdcnt->rx_badhdr, sdcnt->rx_badseq,
3101 sdcnt->fc_rcvd, sdcnt->fc_xoff,
3102 sdcnt->fc_xon, sdcnt->rxglomfail,
3103 sdcnt->rxglomframes, sdcnt->rxglompkts,
3104 sdcnt->f2rxhdrs, sdcnt->f2rxdata,
3105 sdcnt->f2txdata, sdcnt->f1regdata,
3106 sdcnt->tickcnt, sdcnt->tx_ctlerrs,
3107 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs,
3108 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt);
3113 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3115 struct brcmf_pub *drvr = bus->sdiodev->bus_if->drvr;
3116 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
3118 if (IS_ERR_OR_NULL(dentry))
3121 bus->console_interval = BRCMF_CONSOLE;
3123 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read);
3124 brcmf_debugfs_add_entry(drvr, "counters",
3125 brcmf_debugfs_sdio_count_read);
3126 debugfs_create_u32("console_interval", 0644, dentry,
3127 &bus->console_interval);
3130 static int brcmf_sdio_checkdied(struct brcmf_sdio *bus)
3135 static void brcmf_sdio_debugfs_create(struct brcmf_sdio *bus)
3141 brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen)
3147 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3148 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3149 struct brcmf_sdio *bus = sdiodev->bus;
3151 brcmf_dbg(TRACE, "Enter\n");
3152 if (sdiodev->state != BRCMF_SDIOD_DATA)
3155 /* Wait until control frame is available */
3156 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending);
3158 spin_lock_bh(&bus->rxctl_lock);
3160 memcpy(msg, bus->rxctl, min(msglen, rxlen));
3162 buf = bus->rxctl_orig;
3163 bus->rxctl_orig = NULL;
3165 spin_unlock_bh(&bus->rxctl_lock);
3169 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
3171 } else if (timeleft == 0) {
3172 brcmf_err("resumed on timeout\n");
3173 brcmf_sdio_checkdied(bus);
3174 } else if (pending) {
3175 brcmf_dbg(CTL, "cancelled\n");
3176 return -ERESTARTSYS;
3178 brcmf_dbg(CTL, "resumed for unknown reason?\n");
3179 brcmf_sdio_checkdied(bus);
3183 bus->sdcnt.rx_ctlpkts++;
3185 bus->sdcnt.rx_ctlerrs++;
3187 return rxlen ? (int)rxlen : -ETIMEDOUT;
3192 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3193 u8 *ram_data, uint ram_sz)
3202 /* read back and verify */
3203 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr,
3205 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL);
3206 /* do not proceed while no memory but */
3212 while (offset < ram_sz) {
3213 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK :
3215 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len);
3217 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3221 } else if (memcmp(ram_cmp, &ram_data[offset], len)) {
3222 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n",
3237 brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr,
3238 u8 *ram_data, uint ram_sz)
3244 static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus,
3245 const struct firmware *fw)
3249 brcmf_dbg(TRACE, "Enter\n");
3251 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase,
3252 (u8 *)fw->data, fw->size);
3254 brcmf_err("error %d on writing %d membytes at 0x%08x\n",
3255 err, (int)fw->size, bus->ci->rambase);
3256 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase,
3257 (u8 *)fw->data, fw->size))
3263 static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus,
3264 void *vars, u32 varsz)
3269 brcmf_dbg(TRACE, "Enter\n");
3271 address = bus->ci->ramsize - varsz + bus->ci->rambase;
3272 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz);
3274 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n",
3275 err, varsz, address);
3276 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz))
3282 static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus,
3283 const struct firmware *fw,
3284 void *nvram, u32 nvlen)
3289 sdio_claim_host(bus->sdiodev->func[1]);
3290 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
3292 rstvec = get_unaligned_le32(fw->data);
3293 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec);
3295 bcmerror = brcmf_sdio_download_code_file(bus, fw);
3296 release_firmware(fw);
3298 brcmf_err("dongle image file download failed\n");
3299 brcmf_fw_nvram_free(nvram);
3303 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen);
3304 brcmf_fw_nvram_free(nvram);
3306 brcmf_err("dongle nvram file download failed\n");
3310 /* Take arm out of reset */
3311 if (!brcmf_chip_set_active(bus->ci, rstvec)) {
3312 brcmf_err("error getting out of ARM core reset\n");
3317 brcmf_sdio_clkctl(bus, CLK_SDONLY, false);
3318 sdio_release_host(bus->sdiodev->func[1]);
3322 static void brcmf_sdio_sr_init(struct brcmf_sdio *bus)
3327 brcmf_dbg(TRACE, "Enter\n");
3329 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err);
3331 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n");
3335 val |= 1 << SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT;
3336 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err);
3338 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n");
3342 /* Add CMD14 Support */
3343 brcmf_sdiod_regwb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP,
3344 (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT |
3345 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT),
3348 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n");
3352 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3353 SBSDIO_FORCE_HT, &err);
3355 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n");
3360 bus->sr_enabled = true;
3361 brcmf_dbg(INFO, "SR enabled\n");
3364 /* enable KSO bit */
3365 static int brcmf_sdio_kso_init(struct brcmf_sdio *bus)
3370 brcmf_dbg(TRACE, "Enter\n");
3372 /* KSO bit added in SDIO core rev 12 */
3373 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12)
3376 val = brcmf_sdiod_regrb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err);
3378 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n");
3382 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) {
3383 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN <<
3384 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT);
3385 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR,
3388 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n");
3397 static int brcmf_sdio_bus_preinit(struct device *dev)
3399 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3400 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3401 struct brcmf_sdio *bus = sdiodev->bus;
3406 /* the commands below use the terms tx and rx from
3407 * a device perspective, ie. bus:txglom affects the
3408 * bus transfers from device to host.
3410 if (brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV)->rev < 12) {
3411 /* for sdio core rev < 12, disable txgloming */
3413 err = brcmf_iovar_data_set(dev, "bus:txglom", &value,
3416 /* otherwise, set txglomalign */
3417 value = sdiodev->settings->bus.sdio.sd_sgentry_align;
3418 /* SDIO ADMA requires at least 32 bit alignment */
3419 value = max_t(u32, value, 4);
3420 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &value,
3427 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
3428 if (sdiodev->sg_support) {
3429 bus->txglom = false;
3431 pad_size = bus->sdiodev->func[2]->cur_blksize << 1;
3432 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom",
3433 &value, sizeof(u32));
3435 /* bus:rxglom is allowed to fail */
3439 bus->tx_hdrlen += SDPCM_HWEXT_LEN;
3442 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen);
3448 static size_t brcmf_sdio_bus_get_ramsize(struct device *dev)
3450 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3451 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3452 struct brcmf_sdio *bus = sdiodev->bus;
3454 return bus->ci->ramsize - bus->ci->srsize;
3457 static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data,
3460 struct brcmf_bus *bus_if = dev_get_drvdata(dev);
3461 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio;
3462 struct brcmf_sdio *bus = sdiodev->bus;
3468 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase,
3471 address = bus->ci->rambase;
3473 sdio_claim_host(sdiodev->func[1]);
3474 while (offset < mem_size) {
3475 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK :
3477 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len);
3479 brcmf_err("error %d on reading %d membytes at 0x%08x\n",
3489 sdio_release_host(sdiodev->func[1]);
3493 void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus)
3495 if (!bus->dpc_triggered) {
3496 bus->dpc_triggered = true;
3497 queue_work(bus->brcmf_wq, &bus->datawork);
3501 void brcmf_sdio_isr(struct brcmf_sdio *bus)
3503 brcmf_dbg(TRACE, "Enter\n");
3506 brcmf_err("bus is null pointer, exiting\n");
3510 /* Count the interrupt call */
3511 bus->sdcnt.intrcount++;
3513 atomic_set(&bus->ipend, 1);
3515 if (brcmf_sdio_intr_rstatus(bus)) {
3516 brcmf_err("failed backplane access\n");
3519 /* Disable additional interrupts (is this needed now)? */
3521 brcmf_err("isr w/o interrupt configured!\n");
3523 bus->dpc_triggered = true;
3524 queue_work(bus->brcmf_wq, &bus->datawork);
3527 static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus)
3529 brcmf_dbg(TIMER, "Enter\n");
3531 /* Poll period: check device if appropriate. */
3532 if (!bus->sr_enabled &&
3533 bus->poll && (++bus->polltick >= bus->pollrate)) {
3536 /* Reset poll tick */
3539 /* Check device if no interrupts */
3541 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) {
3543 if (!bus->dpc_triggered) {
3546 sdio_claim_host(bus->sdiodev->func[1]);
3547 devpend = brcmf_sdiod_regrb(bus->sdiodev,
3550 sdio_release_host(bus->sdiodev->func[1]);
3551 intstatus = devpend & (INTR_STATUS_FUNC1 |
3555 /* If there is something, make like the ISR and
3558 bus->sdcnt.pollcnt++;
3559 atomic_set(&bus->ipend, 1);
3561 bus->dpc_triggered = true;
3562 queue_work(bus->brcmf_wq, &bus->datawork);
3566 /* Update interrupt tracking */
3567 bus->sdcnt.lastintrs = bus->sdcnt.intrcount;
3570 /* Poll for console output periodically */
3571 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() &&
3572 bus->console_interval != 0) {
3573 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL);
3574 if (bus->console.count >= bus->console_interval) {
3575 bus->console.count -= bus->console_interval;
3576 sdio_claim_host(bus->sdiodev->func[1]);
3577 /* Make sure backplane clock is on */
3578 brcmf_sdio_bus_sleep(bus, false, false);
3579 if (brcmf_sdio_readconsole(bus) < 0)
3581 bus->console_interval = 0;
3582 sdio_release_host(bus->sdiodev->func[1]);
3587 /* On idle timeout clear activity flag and/or turn off clock */
3588 if (!bus->dpc_triggered) {
3590 if ((!bus->dpc_running) && (bus->idletime > 0) &&
3591 (bus->clkstate == CLK_AVAIL)) {
3593 if (bus->idlecount > bus->idletime) {
3594 brcmf_dbg(SDIO, "idle\n");
3595 sdio_claim_host(bus->sdiodev->func[1]);
3596 brcmf_sdio_wd_timer(bus, false);
3598 brcmf_sdio_bus_sleep(bus, true, false);
3599 sdio_release_host(bus->sdiodev->func[1]);
3609 static void brcmf_sdio_dataworker(struct work_struct *work)
3611 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio,
3614 bus->dpc_running = true;
3616 while (ACCESS_ONCE(bus->dpc_triggered)) {
3617 bus->dpc_triggered = false;
3618 brcmf_sdio_dpc(bus);
3621 bus->dpc_running = false;
3622 if (brcmf_sdiod_freezing(bus->sdiodev)) {
3623 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN);
3624 brcmf_sdiod_try_freeze(bus->sdiodev);
3625 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
3630 brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev,
3631 struct brcmf_chip *ci, u32 drivestrength)
3633 const struct sdiod_drive_str *str_tab = NULL;
3637 u32 drivestrength_sel = 0;
3641 if (!(ci->cc_caps & CC_CAP_PMU))
3644 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) {
3645 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12):
3646 str_tab = sdiod_drvstr_tab1_1v8;
3647 str_mask = 0x00003800;
3650 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17):
3651 str_tab = sdiod_drvstr_tab6_1v8;
3652 str_mask = 0x00001800;
3655 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17):
3656 /* note: 43143 does not support tristate */
3657 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1;
3658 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) {
3659 str_tab = sdiod_drvstr_tab2_3v3;
3660 str_mask = 0x00000007;
3663 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n",
3664 ci->name, drivestrength);
3666 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13):
3667 str_tab = sdiod_drive_strength_tab5_1v8;
3668 str_mask = 0x00003800;
3672 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n",
3673 ci->name, ci->chiprev, ci->pmurev);
3677 if (str_tab != NULL) {
3678 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci);
3680 for (i = 0; str_tab[i].strength != 0; i++) {
3681 if (drivestrength >= str_tab[i].strength) {
3682 drivestrength_sel = str_tab[i].sel;
3686 addr = CORE_CC_REG(pmu->base, chipcontrol_addr);
3687 brcmf_sdiod_regwl(sdiodev, addr, 1, NULL);
3688 cc_data_temp = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3689 cc_data_temp &= ~str_mask;
3690 drivestrength_sel <<= str_shift;
3691 cc_data_temp |= drivestrength_sel;
3692 brcmf_sdiod_regwl(sdiodev, addr, cc_data_temp, NULL);
3694 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n",
3695 str_tab[i].strength, drivestrength, cc_data_temp);
3699 static int brcmf_sdio_buscoreprep(void *ctx)
3701 struct brcmf_sdio_dev *sdiodev = ctx;
3705 /* Try forcing SDIO core to do ALPAvail request only */
3706 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
3707 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3709 brcmf_err("error writing for HT off\n");
3713 /* If register supported, wait for ALPAvail and then force ALP */
3714 /* This may take up to 15 milliseconds */
3715 clkval = brcmf_sdiod_regrb(sdiodev,
3716 SBSDIO_FUNC1_CHIPCLKCSR, NULL);
3718 if ((clkval & ~SBSDIO_AVBITS) != clkset) {
3719 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
3724 SPINWAIT(((clkval = brcmf_sdiod_regrb(sdiodev,
3725 SBSDIO_FUNC1_CHIPCLKCSR, NULL)),
3726 !SBSDIO_ALPAV(clkval)),
3727 PMU_MAX_TRANSITION_DLY);
3728 if (!SBSDIO_ALPAV(clkval)) {
3729 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n",
3734 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP;
3735 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err);
3738 /* Also, disable the extra SDIO pull-ups */
3739 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL);
3744 static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip,
3747 struct brcmf_sdio_dev *sdiodev = ctx;
3748 struct brcmf_core *core;
3751 /* clear all interrupts */
3752 core = brcmf_chip_get_core(chip, BCMA_CORE_SDIO_DEV);
3753 reg_addr = core->base + offsetof(struct sdpcmd_regs, intstatus);
3754 brcmf_sdiod_regwl(sdiodev, reg_addr, 0xFFFFFFFF, NULL);
3757 /* Write reset vector to address 0 */
3758 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec,
3762 static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr)
3764 struct brcmf_sdio_dev *sdiodev = ctx;
3767 val = brcmf_sdiod_regrl(sdiodev, addr, NULL);
3768 if ((sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4335_4339 ||
3769 sdiodev->func[0]->device == SDIO_DEVICE_ID_BROADCOM_4339) &&
3770 addr == CORE_CC_REG(SI_ENUM_BASE, chipid)) {
3771 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT;
3773 val &= ~CID_ID_MASK;
3774 val |= BRCM_CC_4339_CHIP_ID;
3780 static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val)
3782 struct brcmf_sdio_dev *sdiodev = ctx;
3784 brcmf_sdiod_regwl(sdiodev, addr, val, NULL);
3787 static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = {
3788 .prepare = brcmf_sdio_buscoreprep,
3789 .activate = brcmf_sdio_buscore_activate,
3790 .read32 = brcmf_sdio_buscore_read32,
3791 .write32 = brcmf_sdio_buscore_write32,
3795 brcmf_sdio_probe_attach(struct brcmf_sdio *bus)
3797 struct brcmf_sdio_dev *sdiodev;
3804 sdiodev = bus->sdiodev;
3805 sdio_claim_host(sdiodev->func[1]);
3807 pr_debug("F1 signature read @0x18000000=0x%4x\n",
3808 brcmf_sdiod_regrl(sdiodev, SI_ENUM_BASE, NULL));
3811 * Force PLL off until brcmf_chip_attach()
3812 * programs PLL control regs
3815 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
3816 BRCMF_INIT_CLKCTL1, &err);
3818 clkctl = brcmf_sdiod_regrb(sdiodev,
3819 SBSDIO_FUNC1_CHIPCLKCSR, &err);
3821 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
3822 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
3823 err, BRCMF_INIT_CLKCTL1, clkctl);
3827 bus->ci = brcmf_chip_attach(sdiodev, &brcmf_sdio_buscore_ops);
3828 if (IS_ERR(bus->ci)) {
3829 brcmf_err("brcmf_chip_attach failed!\n");
3833 sdiodev->settings = brcmf_get_module_param(sdiodev->dev,
3837 if (!sdiodev->settings) {
3838 brcmf_err("Failed to get device parameters\n");
3841 /* platform specific configuration:
3842 * alignments must be at least 4 bytes for ADMA
3844 bus->head_align = ALIGNMENT;
3845 bus->sgentry_align = ALIGNMENT;
3846 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT)
3847 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align;
3848 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT)
3849 bus->sgentry_align =
3850 sdiodev->settings->bus.sdio.sd_sgentry_align;
3852 /* allocate scatter-gather table. sg support
3853 * will be disabled upon allocation failure.
3855 brcmf_sdiod_sgtable_alloc(sdiodev);
3857 #ifdef CONFIG_PM_SLEEP
3858 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ
3859 * is true or when platform data OOB irq is true).
3861 if ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_KEEP_POWER) &&
3862 ((sdio_get_host_pm_caps(sdiodev->func[1]) & MMC_PM_WAKE_SDIO_IRQ) ||
3863 (sdiodev->settings->bus.sdio.oob_irq_supported)))
3864 sdiodev->bus_if->wowl_supported = true;
3867 if (brcmf_sdio_kso_init(bus)) {
3868 brcmf_err("error enabling KSO\n");
3872 if (sdiodev->settings->bus.sdio.drive_strength)
3873 drivestrength = sdiodev->settings->bus.sdio.drive_strength;
3875 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH;
3876 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength);
3878 /* Set card control so an SDIO card reset does a WLAN backplane reset */
3879 reg_val = brcmf_sdiod_regrb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err);
3883 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET;
3885 brcmf_sdiod_regwb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err);
3889 /* set PMUControl so a backplane reset does PMU state reload */
3890 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol);
3891 reg_val = brcmf_sdiod_regrl(sdiodev, reg_addr, &err);
3895 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT);
3897 brcmf_sdiod_regwl(sdiodev, reg_addr, reg_val, &err);
3901 sdio_release_host(sdiodev->func[1]);
3903 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
3905 /* allocate header buffer */
3906 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL);
3909 /* Locate an appropriately-aligned portion of hdrbuf */
3910 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
3913 /* Set the poll and/or interrupt flags */
3922 sdio_release_host(sdiodev->func[1]);
3927 brcmf_sdio_watchdog_thread(void *data)
3929 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3932 allow_signal(SIGTERM);
3933 /* Run until signal received */
3934 brcmf_sdiod_freezer_count(bus->sdiodev);
3936 if (kthread_should_stop())
3938 brcmf_sdiod_freezer_uncount(bus->sdiodev);
3939 wait = wait_for_completion_interruptible(&bus->watchdog_wait);
3940 brcmf_sdiod_freezer_count(bus->sdiodev);
3941 brcmf_sdiod_try_freeze(bus->sdiodev);
3943 brcmf_sdio_bus_watchdog(bus);
3944 /* Count the tick for reference */
3945 bus->sdcnt.tickcnt++;
3946 reinit_completion(&bus->watchdog_wait);
3954 brcmf_sdio_watchdog(unsigned long data)
3956 struct brcmf_sdio *bus = (struct brcmf_sdio *)data;
3958 if (bus->watchdog_tsk) {
3959 complete(&bus->watchdog_wait);
3960 /* Reschedule the watchdog */
3962 mod_timer(&bus->timer,
3963 jiffies + BRCMF_WD_POLL);
3967 static const struct brcmf_bus_ops brcmf_sdio_bus_ops = {
3968 .stop = brcmf_sdio_bus_stop,
3969 .preinit = brcmf_sdio_bus_preinit,
3970 .txdata = brcmf_sdio_bus_txdata,
3971 .txctl = brcmf_sdio_bus_txctl,
3972 .rxctl = brcmf_sdio_bus_rxctl,
3973 .gettxq = brcmf_sdio_bus_gettxq,
3974 .wowl_config = brcmf_sdio_wowl_config,
3975 .get_ramsize = brcmf_sdio_bus_get_ramsize,
3976 .get_memdump = brcmf_sdio_bus_get_memdump,
3979 static void brcmf_sdio_firmware_callback(struct device *dev, int err,
3980 const struct firmware *code,
3981 void *nvram, u32 nvram_len)
3983 struct brcmf_bus *bus_if;
3984 struct brcmf_sdio_dev *sdiodev;
3985 struct brcmf_sdio *bus;
3988 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err);
3989 bus_if = dev_get_drvdata(dev);
3990 sdiodev = bus_if->bus_priv.sdio;
3999 /* try to download image and nvram to the dongle */
4000 bus->alp_only = true;
4001 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len);
4004 bus->alp_only = false;
4006 /* Start the watchdog timer */
4007 bus->sdcnt.tickcnt = 0;
4008 brcmf_sdio_wd_timer(bus, true);
4010 sdio_claim_host(sdiodev->func[1]);
4012 /* Make sure backplane clock is on, needed to generate F2 interrupt */
4013 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4014 if (bus->clkstate != CLK_AVAIL)
4017 /* Force clocks on backplane to be sure F2 interrupt propagates */
4018 saveclk = brcmf_sdiod_regrb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, &err);
4020 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4021 (saveclk | SBSDIO_FORCE_HT), &err);
4024 brcmf_err("Failed to force clock for F2: err %d\n", err);
4028 /* Enable function 2 (frame transfers) */
4029 w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
4030 offsetof(struct sdpcmd_regs, tosbmailboxdata));
4031 err = sdio_enable_func(sdiodev->func[SDIO_FUNC_2]);
4034 brcmf_dbg(INFO, "enable F2: err=%d\n", err);
4036 /* If F2 successfully enabled, set core and enable interrupts */
4038 /* Set up the interrupt mask and enable interrupts */
4039 bus->hostintmask = HOSTINTMASK;
4040 w_sdreg32(bus, bus->hostintmask,
4041 offsetof(struct sdpcmd_regs, hostintmask));
4043 brcmf_sdiod_regwb(sdiodev, SBSDIO_WATERMARK, 8, &err);
4045 /* Disable F2 again */
4046 sdio_disable_func(sdiodev->func[SDIO_FUNC_2]);
4050 if (brcmf_chip_sr_capable(bus->ci)) {
4051 brcmf_sdio_sr_init(bus);
4053 /* Restore previous clock setting */
4054 brcmf_sdiod_regwb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR,
4059 /* Allow full data communication using DPC from now on. */
4060 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA);
4062 err = brcmf_sdiod_intr_register(sdiodev);
4064 brcmf_err("intr register failed:%d\n", err);
4067 /* If we didn't come up, turn off backplane clock */
4069 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4071 sdio_release_host(sdiodev->func[1]);
4073 err = brcmf_bus_start(dev);
4075 brcmf_err("dongle is not responding\n");
4081 sdio_release_host(sdiodev->func[1]);
4083 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err);
4084 device_release_driver(&sdiodev->func[2]->dev);
4085 device_release_driver(dev);
4088 struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev)
4091 struct brcmf_sdio *bus;
4092 struct workqueue_struct *wq;
4094 brcmf_dbg(TRACE, "Enter\n");
4096 /* Allocate private bus interface state */
4097 bus = kzalloc(sizeof(struct brcmf_sdio), GFP_ATOMIC);
4101 bus->sdiodev = sdiodev;
4103 skb_queue_head_init(&bus->glom);
4104 bus->txbound = BRCMF_TXBOUND;
4105 bus->rxbound = BRCMF_RXBOUND;
4106 bus->txminmax = BRCMF_TXMINMAX;
4107 bus->tx_seq = SDPCM_SEQ_WRAP - 1;
4109 /* single-threaded workqueue */
4110 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM,
4111 dev_name(&sdiodev->func[1]->dev));
4113 brcmf_err("insufficient memory to create txworkqueue\n");
4116 brcmf_sdiod_freezer_count(sdiodev);
4117 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker);
4120 /* attempt to attach to the dongle */
4121 if (!(brcmf_sdio_probe_attach(bus))) {
4122 brcmf_err("brcmf_sdio_probe_attach failed\n");
4126 spin_lock_init(&bus->rxctl_lock);
4127 spin_lock_init(&bus->txq_lock);
4128 init_waitqueue_head(&bus->ctrl_wait);
4129 init_waitqueue_head(&bus->dcmd_resp_wait);
4131 /* Set up the watchdog timer */
4132 init_timer(&bus->timer);
4133 bus->timer.data = (unsigned long)bus;
4134 bus->timer.function = brcmf_sdio_watchdog;
4136 /* Initialize watchdog thread */
4137 init_completion(&bus->watchdog_wait);
4138 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread,
4139 bus, "brcmf_wdog/%s",
4140 dev_name(&sdiodev->func[1]->dev));
4141 if (IS_ERR(bus->watchdog_tsk)) {
4142 pr_warn("brcmf_watchdog thread failed to start\n");
4143 bus->watchdog_tsk = NULL;
4145 /* Initialize DPC thread */
4146 bus->dpc_triggered = false;
4147 bus->dpc_running = false;
4149 /* Assign bus interface call back */
4150 bus->sdiodev->bus_if->dev = bus->sdiodev->dev;
4151 bus->sdiodev->bus_if->ops = &brcmf_sdio_bus_ops;
4152 bus->sdiodev->bus_if->chip = bus->ci->chip;
4153 bus->sdiodev->bus_if->chiprev = bus->ci->chiprev;
4155 /* default sdio bus header length for tx packet */
4156 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN;
4158 /* Attach to the common layer, reserve hdr space */
4159 ret = brcmf_attach(bus->sdiodev->dev, bus->sdiodev->settings);
4161 brcmf_err("brcmf_attach failed\n");
4165 /* Query the F2 block size, set roundup accordingly */
4166 bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
4167 bus->roundup = min(max_roundup, bus->blocksize);
4169 /* Allocate buffers */
4170 if (bus->sdiodev->bus_if->maxctl) {
4171 bus->sdiodev->bus_if->maxctl += bus->roundup;
4173 roundup((bus->sdiodev->bus_if->maxctl + SDPCM_HDRLEN),
4174 ALIGNMENT) + bus->head_align;
4175 bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
4176 if (!(bus->rxbuf)) {
4177 brcmf_err("rxbuf allocation failed\n");
4182 sdio_claim_host(bus->sdiodev->func[1]);
4184 /* Disable F2 to clear any intermediate frame state on the dongle */
4185 sdio_disable_func(bus->sdiodev->func[SDIO_FUNC_2]);
4187 bus->rxflow = false;
4189 /* Done with backplane-dependent accesses, can drop clock... */
4190 brcmf_sdiod_regwb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
4192 sdio_release_host(bus->sdiodev->func[1]);
4194 /* ...and initialize clock/power states */
4195 bus->clkstate = CLK_SDONLY;
4196 bus->idletime = BRCMF_IDLE_INTERVAL;
4197 bus->idleclock = BRCMF_IDLE_ACTIVE;
4200 bus->sr_enabled = false;
4202 brcmf_sdio_debugfs_create(bus);
4203 brcmf_dbg(INFO, "completed!!\n");
4205 ret = brcmf_fw_map_chip_to_name(bus->ci->chip, bus->ci->chiprev,
4207 ARRAY_SIZE(brcmf_sdio_fwnames),
4208 sdiodev->fw_name, sdiodev->nvram_name);
4212 ret = brcmf_fw_get_firmwares(sdiodev->dev, BRCMF_FW_REQUEST_NVRAM,
4213 sdiodev->fw_name, sdiodev->nvram_name,
4214 brcmf_sdio_firmware_callback);
4216 brcmf_err("async firmware request failed: %d\n", ret);
4223 brcmf_sdio_remove(bus);
4227 /* Detach and free everything */
4228 void brcmf_sdio_remove(struct brcmf_sdio *bus)
4230 brcmf_dbg(TRACE, "Enter\n");
4233 /* Stop watchdog task */
4234 if (bus->watchdog_tsk) {
4235 send_sig(SIGTERM, bus->watchdog_tsk, 1);
4236 kthread_stop(bus->watchdog_tsk);
4237 bus->watchdog_tsk = NULL;
4240 /* De-register interrupt handler */
4241 brcmf_sdiod_intr_unregister(bus->sdiodev);
4243 brcmf_detach(bus->sdiodev->dev);
4245 cancel_work_sync(&bus->datawork);
4247 destroy_workqueue(bus->brcmf_wq);
4250 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) {
4251 sdio_claim_host(bus->sdiodev->func[1]);
4252 brcmf_sdio_wd_timer(bus, false);
4253 brcmf_sdio_clkctl(bus, CLK_AVAIL, false);
4254 /* Leave the device in state where it is
4255 * 'passive'. This is done by resetting all
4259 brcmf_chip_set_passive(bus->ci);
4260 brcmf_sdio_clkctl(bus, CLK_NONE, false);
4261 sdio_release_host(bus->sdiodev->func[1]);
4263 brcmf_chip_detach(bus->ci);
4265 if (bus->sdiodev->settings)
4266 brcmf_release_module_param(bus->sdiodev->settings);
4273 brcmf_dbg(TRACE, "Disconnected\n");
4276 void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active)
4278 /* Totally stop the timer */
4279 if (!active && bus->wd_active) {
4280 del_timer_sync(&bus->timer);
4281 bus->wd_active = false;
4285 /* don't start the wd until fw is loaded */
4286 if (bus->sdiodev->state != BRCMF_SDIOD_DATA)
4290 if (!bus->wd_active) {
4291 /* Create timer again when watchdog period is
4292 dynamically changed or in the first instance
4294 bus->timer.expires = jiffies + BRCMF_WD_POLL;
4295 add_timer(&bus->timer);
4296 bus->wd_active = true;
4298 /* Re arm the timer, at last watchdog period */
4299 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL);
4304 int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep)
4308 sdio_claim_host(bus->sdiodev->func[1]);
4309 ret = brcmf_sdio_bus_sleep(bus, sleep, false);
4310 sdio_release_host(bus->sdiodev->func[1]);
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